[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap1 / mcbsp.c

/*
 * linux/arch/arm/mach-omap1/mcbsp.c
 *
 * Copyright (C) 2008 Instituto Nokia de Tecnologia
 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Multichannel mode not supported.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <mach/irqs.h>
#include <plat/dma.h>
#include <plat/mux.h>
#include <plat/cpu.h>
#include <plat/mcbsp.h>
#include <plat/dsp_common.h>

#define DPS_RSTCT2_PER_EN	(1 << 0)
#define DSP_RSTCT2_WD_PER_EN	(1 << 1)

static int dsp_use;
static struct clk *api_clk;
static struct clk *dsp_clk;

static void omap1_mcbsp_request(unsigned int id)
{
	/*
	 * On 1510, 1610 and 1710, McBSP1 and McBSP3
	 * are DSP public peripherals.
	 */
	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
		if (dsp_use++ == 0) {
			api_clk = clk_get(NULL, "api_ck");
			dsp_clk = clk_get(NULL, "dsp_ck");
			if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
				clk_enable(api_clk);
				clk_enable(dsp_clk);

				omap_dsp_request_mem();
				/*
				 * DSP external peripheral reset
				 * FIXME: This should be moved to dsp code
				 */
				__raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
						DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
			}
		}
	}
}

static void omap1_mcbsp_free(unsigned int id)
{
	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
		if (--dsp_use == 0) {
			omap_dsp_release_mem();
			if (!IS_ERR(api_clk)) {
				clk_disable(api_clk);
				clk_put(api_clk);
			}
			if (!IS_ERR(dsp_clk)) {
				clk_disable(dsp_clk);
				clk_put(dsp_clk);
			}
		}
	}
}

static struct omap_mcbsp_ops omap1_mcbsp_ops = {
	.request	= omap1_mcbsp_request,
	.free		= omap1_mcbsp_free,
};

#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP7XX_MCBSP1_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,
		.rx_irq		= INT_7XX_McBSP1RX,
		.tx_irq		= INT_7XX_McBSP1TX,
		.ops		= &omap1_mcbsp_ops,
	},
	{
		.phys_base	= OMAP7XX_MCBSP2_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,
		.rx_irq		= INT_7XX_McBSP2RX,
		.tx_irq		= INT_7XX_McBSP2TX,
		.ops		= &omap1_mcbsp_ops,
	},
};
#define OMAP7XX_MCBSP_PDATA_SZ		ARRAY_SIZE(omap7xx_mcbsp_pdata)
#define OMAP7XX_MCBSP_REG_NUM		(OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#else
#define omap7xx_mcbsp_pdata		NULL
#define OMAP7XX_MCBSP_PDATA_SZ		0
#define OMAP7XX_MCBSP_REG_NUM		0
#endif

#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP1510_MCBSP1_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,
		.rx_irq		= INT_McBSP1RX,
		.tx_irq		= INT_McBSP1TX,
		.ops		= &omap1_mcbsp_ops,
	},
	{
		.phys_base	= OMAP1510_MCBSP2_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP2_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP2_TX,
		.rx_irq		= INT_1510_SPI_RX,
		.tx_irq		= INT_1510_SPI_TX,
		.ops		= &omap1_mcbsp_ops,
	},
	{
		.phys_base	= OMAP1510_MCBSP3_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,
		.rx_irq		= INT_McBSP3RX,
		.tx_irq		= INT_McBSP3TX,
		.ops		= &omap1_mcbsp_ops,
	},
};
#define OMAP15XX_MCBSP_PDATA_SZ		ARRAY_SIZE(omap15xx_mcbsp_pdata)
#define OMAP15XX_MCBSP_REG_NUM		(OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#else
#define omap15xx_mcbsp_pdata		NULL
#define OMAP15XX_MCBSP_PDATA_SZ		0
#define OMAP15XX_MCBSP_REG_NUM		0
#endif

#ifdef CONFIG_ARCH_OMAP16XX
static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
	{
		.phys_base	= OMAP1610_MCBSP1_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP1_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP1_TX,
		.rx_irq		= INT_McBSP1RX,
		.tx_irq		= INT_McBSP1TX,
		.ops		= &omap1_mcbsp_ops,
	},
	{
		.phys_base	= OMAP1610_MCBSP2_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP2_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP2_TX,
		.rx_irq		= INT_1610_McBSP2_RX,
		.tx_irq		= INT_1610_McBSP2_TX,
		.ops		= &omap1_mcbsp_ops,
	},
	{
		.phys_base	= OMAP1610_MCBSP3_BASE,
		.dma_rx_sync	= OMAP_DMA_MCBSP3_RX,
		.dma_tx_sync	= OMAP_DMA_MCBSP3_TX,
		.rx_irq		= INT_McBSP3RX,
		.tx_irq		= INT_McBSP3TX,
		.ops		= &omap1_mcbsp_ops,
	},
};
#define OMAP16XX_MCBSP_PDATA_SZ		ARRAY_SIZE(omap16xx_mcbsp_pdata)
#define OMAP16XX_MCBSP_REG_NUM		(OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
#else
#define omap16xx_mcbsp_pdata		NULL
#define OMAP16XX_MCBSP_PDATA_SZ		0
#define OMAP16XX_MCBSP_REG_NUM		0
#endif

int __init omap1_mcbsp_init(void)
{
	if (cpu_is_omap7xx()) {
		omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
	} else if (cpu_is_omap15xx()) {
		omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
	} else if (cpu_is_omap16xx()) {
		omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
		omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
	}

	mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
								GFP_KERNEL);
	if (!mcbsp_ptr)
		return -ENOMEM;

	if (cpu_is_omap7xx())
		omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
						OMAP7XX_MCBSP_PDATA_SZ);

	if (cpu_is_omap15xx())
		omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
						OMAP15XX_MCBSP_PDATA_SZ);

	if (cpu_is_omap16xx())
		omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
						OMAP16XX_MCBSP_PDATA_SZ);

	return omap_mcbsp_init();
}

arch_initcall(omap1_mcbsp_init);
Commit	Line	Data
44ec9a33 EV	1	/*
	2	* linux/arch/arm/mach-omap1/mcbsp.c
	3	*
	4	* Copyright (C) 2008 Instituto Nokia de Tecnologia
	5	* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* Multichannel mode not supported.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/platform_device.h>
5a0e3ad6	19	#include <linux/slab.h>
44ec9a33	20
dd7667aa	21	#include <mach/irqs.h>
ce491cf8 TL	22	#include <plat/dma.h>
	23	#include <plat/mux.h>
	24	#include <plat/cpu.h>
	25	#include <plat/mcbsp.h>
	26	#include <plat/dsp_common.h>
44ec9a33 EV	27
	28	#define DPS_RSTCT2_PER_EN (1 << 0)
	29	#define DSP_RSTCT2_WD_PER_EN (1 << 1)
	30
b820ce4e RK	31	static int dsp_use;
	32	static struct clk *api_clk;
	33	static struct clk *dsp_clk;
44ec9a33	34
44ec9a33 EV	35	static void omap1_mcbsp_request(unsigned int id)
	36	{
	37	/*
	38	* On 1510, 1610 and 1710, McBSP1 and McBSP3
	39	* are DSP public peripherals.
	40	*/
	41	if (id == OMAP_MCBSP1 \|\| id == OMAP_MCBSP3) {
b820ce4e	42	if (dsp_use++ == 0) {
d53eb737 AK	43	api_clk = clk_get(NULL, "api_ck");
d53eb737 AK	44	dsp_clk = clk_get(NULL, "dsp_ck");
b820ce4e RK	45	if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
	46	clk_enable(api_clk);
	47	clk_enable(dsp_clk);
	48
	49	omap_dsp_request_mem();
	50	/*
	51	* DSP external peripheral reset
	52	* FIXME: This should be moved to dsp code
	53	*/
	54	__raw_writew(__raw_readw(DSP_RSTCT2) \| DPS_RSTCT2_PER_EN \|
	55	DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
	56	}
	57	}
44ec9a33 EV	58	}
	59	}
	60
	61	static void omap1_mcbsp_free(unsigned int id)
	62	{
b820ce4e RK	63	if (id == OMAP_MCBSP1 \|\| id == OMAP_MCBSP3) {
	64	if (--dsp_use == 0) {
	65	omap_dsp_release_mem();
	66	if (!IS_ERR(api_clk)) {
	67	clk_disable(api_clk);
	68	clk_put(api_clk);
	69	}
	70	if (!IS_ERR(dsp_clk)) {
	71	clk_disable(dsp_clk);
	72	clk_put(dsp_clk);
	73	}
	74	}
	75	}
44ec9a33 EV	76	}
	77
	78	static struct omap_mcbsp_ops omap1_mcbsp_ops = {
44ec9a33 EV	79	.request = omap1_mcbsp_request,
	80	.free = omap1_mcbsp_free,
	81	};
	82
bf1cb7eb	83	#if defined(CONFIG_ARCH_OMAP730) \|\| defined(CONFIG_ARCH_OMAP850)
7c006926	84	static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
44ec9a33	85	{
7c006926	86	.phys_base = OMAP7XX_MCBSP1_BASE,
44ec9a33 EV	87	.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
44ec9a33 EV	88	.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
372b1c32 AB	89	.rx_irq = INT_7XX_McBSP1RX,
372b1c32 AB	90	.tx_irq = INT_7XX_McBSP1TX,
44ec9a33 EV	91	.ops = &omap1_mcbsp_ops,
	92	},
	93	{
7c006926	94	.phys_base = OMAP7XX_MCBSP2_BASE,
44ec9a33 EV	95	.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
44ec9a33 EV	96	.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
372b1c32 AB	97	.rx_irq = INT_7XX_McBSP2RX,
372b1c32 AB	98	.tx_irq = INT_7XX_McBSP2TX,
44ec9a33 EV	99	.ops = &omap1_mcbsp_ops,
	100	},
	101	};
7c006926	102	#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata)
c8c99699	103	#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
44ec9a33	104	#else
7c006926 AB	105	#define omap7xx_mcbsp_pdata NULL
7c006926 AB	106	#define OMAP7XX_MCBSP_PDATA_SZ 0
c8c99699	107	#define OMAP7XX_MCBSP_REG_NUM 0
44ec9a33 EV	108	#endif
	109
	110	#ifdef CONFIG_ARCH_OMAP15XX
	111	static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
	112	{
65846909	113	.phys_base = OMAP1510_MCBSP1_BASE,
44ec9a33 EV	114	.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
	115	.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
	116	.rx_irq = INT_McBSP1RX,
	117	.tx_irq = INT_McBSP1TX,
	118	.ops = &omap1_mcbsp_ops,
06151158	119	},
44ec9a33	120	{
65846909	121	.phys_base = OMAP1510_MCBSP2_BASE,
44ec9a33 EV	122	.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
	123	.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
	124	.rx_irq = INT_1510_SPI_RX,
	125	.tx_irq = INT_1510_SPI_TX,
	126	.ops = &omap1_mcbsp_ops,
	127	},
	128	{
65846909	129	.phys_base = OMAP1510_MCBSP3_BASE,
44ec9a33 EV	130	.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
	131	.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
	132	.rx_irq = INT_McBSP3RX,
	133	.tx_irq = INT_McBSP3TX,
	134	.ops = &omap1_mcbsp_ops,
44ec9a33 EV	135	},
	136	};
	137	#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
c8c99699	138	#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
44ec9a33 EV	139	#else
	140	#define omap15xx_mcbsp_pdata NULL
	141	#define OMAP15XX_MCBSP_PDATA_SZ 0
c8c99699	142	#define OMAP15XX_MCBSP_REG_NUM 0
44ec9a33 EV	143	#endif
	144
	145	#ifdef CONFIG_ARCH_OMAP16XX
	146	static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
	147	{
65846909	148	.phys_base = OMAP1610_MCBSP1_BASE,
44ec9a33 EV	149	.dma_rx_sync = OMAP_DMA_MCBSP1_RX,
	150	.dma_tx_sync = OMAP_DMA_MCBSP1_TX,
	151	.rx_irq = INT_McBSP1RX,
	152	.tx_irq = INT_McBSP1TX,
	153	.ops = &omap1_mcbsp_ops,
44ec9a33 EV	154	},
44ec9a33 EV	155	{
65846909	156	.phys_base = OMAP1610_MCBSP2_BASE,
44ec9a33 EV	157	.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
	158	.dma_tx_sync = OMAP_DMA_MCBSP2_TX,
	159	.rx_irq = INT_1610_McBSP2_RX,
	160	.tx_irq = INT_1610_McBSP2_TX,
	161	.ops = &omap1_mcbsp_ops,
	162	},
	163	{
65846909	164	.phys_base = OMAP1610_MCBSP3_BASE,
44ec9a33 EV	165	.dma_rx_sync = OMAP_DMA_MCBSP3_RX,
	166	.dma_tx_sync = OMAP_DMA_MCBSP3_TX,
	167	.rx_irq = INT_McBSP3RX,
	168	.tx_irq = INT_McBSP3TX,
	169	.ops = &omap1_mcbsp_ops,
44ec9a33 EV	170	},
	171	};
	172	#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
c8c99699	173	#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
44ec9a33 EV	174	#else
	175	#define omap16xx_mcbsp_pdata NULL
	176	#define OMAP16XX_MCBSP_PDATA_SZ 0
c8c99699	177	#define OMAP16XX_MCBSP_REG_NUM 0
44ec9a33 EV	178	#endif
	179
	180	int __init omap1_mcbsp_init(void)
	181	{
c8c99699	182	if (cpu_is_omap7xx()) {
7c006926	183	omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
c8c99699 JK	184	omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
c8c99699 JK	185	} else if (cpu_is_omap15xx()) {
b4b58f58	186	omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
c8c99699 JK	187	omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
c8c99699 JK	188	} else if (cpu_is_omap16xx()) {
b4b58f58	189	omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
c8c99699 JK	190	omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
c8c99699 JK	191	}
b4b58f58 CS	192
	193	mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
	194	GFP_KERNEL);
	195	if (!mcbsp_ptr)
	196	return -ENOMEM;
	197
bf1cb7eb	198	if (cpu_is_omap7xx())
7c006926 AB	199	omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
7c006926 AB	200	OMAP7XX_MCBSP_PDATA_SZ);
44ec9a33 EV	201
	202	if (cpu_is_omap15xx())
	203	omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
	204	OMAP15XX_MCBSP_PDATA_SZ);
	205
	206	if (cpu_is_omap16xx())
	207	omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
	208	OMAP16XX_MCBSP_PDATA_SZ);
	209
	210	return omap_mcbsp_init();
	211	}
	212
	213	arch_initcall(omap1_mcbsp_init);