[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap1 / sram.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * linux/arch/arm/plat-omap/sram-fn.S
 *
 * Functions that need to be run in internal SRAM
 */

#include <linux/linkage.h>

#include <asm/assembler.h>

#include <mach/hardware.h>

#include "iomap.h"

	.text

/*
 * Reprograms ULPD and CKCTL.
 */
	.align	3
ENTRY(omap1_sram_reprogram_clock)
	stmfd	sp!, {r0 - r12, lr}		@ save registers on stack

	mov	r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
	orr	r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
	orr	r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00

	mov	r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
	orr	r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
	orr	r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00

	tst	r0, #1 << 4			@ want lock mode?
	beq	newck				@ nope
	bic	r0, r0, #1 << 4			@ else clear lock bit
	strh	r0, [r2]			@ set dpll into bypass mode
	orr	r0, r0, #1 << 4			@ set lock bit again

newck:
	strh	r1, [r3]			@ write new ckctl value
	strh	r0, [r2]			@ write new dpll value

	mov	r4, #0x0700			@ let the clocks settle
	orr	r4, r4, #0x00ff
delay:	sub	r4, r4, #1
	cmp	r4, #0
	bne	delay

lock:	ldrh	r4, [r2], #0			@ read back dpll value
	tst	r0, #1 << 4			@ want lock mode?
	beq	out				@ nope
	tst	r4, #1 << 0			@ dpll rate locked?
	beq	lock				@ try again

out:
	ldmfd	sp!, {r0 - r12, pc}		@ restore regs and return
ENTRY(omap1_sram_reprogram_clock_sz)
	.word	. - omap1_sram_reprogram_clock
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
92105bb7	2	/*
f30c2269	3	* linux/arch/arm/plat-omap/sram-fn.S
92105bb7 TL	4	*
92105bb7 TL	5	* Functions that need to be run in internal SRAM
92105bb7 TL	6	*/
92105bb7 TL	7
92105bb7	8	#include <linux/linkage.h>
2e3ee9f4	9
92105bb7	10	#include <asm/assembler.h>
2e3ee9f4	11
a09e64fb	12	#include <mach/hardware.h>
92105bb7	13
2e3ee9f4 TL	14	#include "iomap.h"
2e3ee9f4 TL	15
92105bb7 TL	16	.text
	17
	18	/*
	19	* Reprograms ULPD and CKCTL.
	20	*/
b6338bdc	21	.align 3
c2d43e39	22	ENTRY(omap1_sram_reprogram_clock)
92105bb7 TL	23	stmfd sp!, {r0 - r12, lr} @ save registers on stack
92105bb7 TL	24
94113260 TL	25	mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
	26	orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
	27	orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
92105bb7	28
94113260 TL	29	mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
	30	orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
	31	orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
92105bb7 TL	32
	33	tst r0, #1 << 4 @ want lock mode?
	34	beq newck @ nope
	35	bic r0, r0, #1 << 4 @ else clear lock bit
	36	strh r0, [r2] @ set dpll into bypass mode
	37	orr r0, r0, #1 << 4 @ set lock bit again
	38
	39	newck:
	40	strh r1, [r3] @ write new ckctl value
	41	strh r0, [r2] @ write new dpll value
	42
	43	mov r4, #0x0700 @ let the clocks settle
	44	orr r4, r4, #0x00ff
	45	delay: sub r4, r4, #1
	46	cmp r4, #0
	47	bne delay
	48
	49	lock: ldrh r4, [r2], #0 @ read back dpll value
	50	tst r0, #1 << 4 @ want lock mode?
	51	beq out @ nope
	52	tst r4, #1 << 0 @ dpll rate locked?
	53	beq lock @ try again
	54
	55	out:
	56	ldmfd sp!, {r0 - r12, pc} @ restore regs and return
c2d43e39 TL	57	ENTRY(omap1_sram_reprogram_clock_sz)
c2d43e39 TL	58	.word . - omap1_sram_reprogram_clock