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ffe7f95b 1/*
9312fffb 2 * linux/arch/arm/mach-omap2/board-rx51-peripherals.c
ffe7f95b
LL
3 *
4 * Copyright (C) 2008-2009 Nokia
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/input.h>
6135434a 15#include <linux/input/matrix_keypad.h>
ffe7f95b 16#include <linux/spi/spi.h>
c1f9a095 17#include <linux/wl12xx.h>
3dad5356 18#include <linux/spi/tsc2005.h>
ffe7f95b 19#include <linux/i2c.h>
ebeb53e1 20#include <linux/i2c/twl.h>
ffe7f95b
LL
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/regulator/machine.h>
24#include <linux/gpio.h>
f014ee32 25#include <linux/gpio_keys.h>
5e763d29 26#include <linux/mmc/host.h>
10299e2e 27#include <linux/power/isp1704_charger.h>
2203747c
AB
28#include <linux/platform_data/spi-omap2-mcspi.h>
29#include <linux/platform_data/mtd-onenand-omap2.h>
30
9f97da78 31#include <asm/system_info.h>
ffe7f95b 32
4e65331c 33#include "common.h"
ce491cf8
TL
34#include <plat/dma.h>
35#include <plat/gpmc.h>
322c183c 36#include <plat/omap-pm.h>
60628152 37#include "gpmc-smc91x.h"
ffe7f95b 38
0a6f98c9 39#include "board-rx51.h"
04aeae77 40
87581fd4 41#include <sound/tlv320aic3x.h>
64d06691 42#include <sound/tpa6130a2-plat.h>
589541c0
JN
43#include <media/radio-si4713.h>
44#include <media/si4713.h>
eeada9e8 45#include <linux/leds-lp5523.h>
87581fd4 46
70b5d737 47#include <../drivers/staging/iio/light/tsl2563.h>
3b511201 48#include <linux/lis3lv02d.h>
70b5d737 49
322c183c
TK
50#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
51#include <media/ir-rx51.h>
52#endif
53
4896e394 54#include "mux.h"
d02a900b 55#include "hsmmc.h"
fbd8071c 56#include "common-board-devices.h"
ffe7f95b 57
f52eeee8
AH
58#define SYSTEM_REV_B_USES_VAUX3 0x1699
59#define SYSTEM_REV_S_USES_VAUX3 0x8
60
a24e61a9
KV
61#define RX51_WL1251_POWER_GPIO 87
62#define RX51_WL1251_IRQ_GPIO 42
589541c0
JN
63#define RX51_FMTX_RESET_GPIO 163
64#define RX51_FMTX_IRQ 53
eeada9e8 65#define RX51_LP5523_CHIP_EN_GPIO 41
a24e61a9 66
10299e2e
KJ
67#define RX51_USB_TRANSCEIVER_RST_GPIO 67
68
3dad5356
AK
69#define RX51_TSC2005_RESET_GPIO 104
70#define RX51_TSC2005_IRQ_GPIO 100
71
3b511201
AP
72#define LIS302_IRQ1_GPIO 181
73#define LIS302_IRQ2_GPIO 180 /* Not yet in use */
74
a24e61a9
KV
75/* list all spi devices here */
76enum {
77 RX51_SPI_WL1251,
03e11104 78 RX51_SPI_MIPID, /* LCD panel */
6996e7ff 79 RX51_SPI_TSC2005, /* Touch Controller */
a24e61a9
KV
80};
81
82static struct wl12xx_platform_data wl1251_pdata;
3dad5356 83static struct tsc2005_platform_data tsc2005_pdata;
a24e61a9 84
3b511201
AP
85#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
86static int lis302_setup(void)
87{
88 int err;
89 int irq1 = LIS302_IRQ1_GPIO;
90 int irq2 = LIS302_IRQ2_GPIO;
91
92 /* gpio for interrupt pin 1 */
93 err = gpio_request(irq1, "lis3lv02dl_irq1");
94 if (err) {
95 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
96 goto out;
97 }
98
99 /* gpio for interrupt pin 2 */
100 err = gpio_request(irq2, "lis3lv02dl_irq2");
101 if (err) {
102 gpio_free(irq1);
103 printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
104 goto out;
105 }
106
107 gpio_direction_input(irq1);
108 gpio_direction_input(irq2);
109
110out:
111 return err;
112}
113
114static int lis302_release(void)
115{
116 gpio_free(LIS302_IRQ1_GPIO);
117 gpio_free(LIS302_IRQ2_GPIO);
118
119 return 0;
120}
121
122static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
123 .click_flags = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
124 LIS3_CLICK_SINGLE_Z,
125 /* Limits are 0.5g * value */
126 .click_thresh_x = 8,
127 .click_thresh_y = 8,
128 .click_thresh_z = 10,
129 /* Click must be longer than time limit */
130 .click_time_limit = 9,
131 /* Kind of debounce filter */
132 .click_latency = 50,
133
134 /* Limits for all axis. millig-value / 18 to get HW values */
135 .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
136 .wakeup_thresh = 800 / 18,
137 .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
138 .wakeup_thresh2 = 900 / 18,
139
140 .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
141
142 /* Interrupt line 2 for click detection, line 1 for thresholds */
143 .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
144
145 .axis_x = LIS3_DEV_X,
146 .axis_y = LIS3_INV_DEV_Y,
147 .axis_z = LIS3_INV_DEV_Z,
148 .setup_resources = lis302_setup,
149 .release_resources = lis302_release,
150 .st_min_limits = {-32, 3, 3},
151 .st_max_limits = {-3, 32, 32},
3b511201
AP
152};
153#endif
154
70b5d737
MN
155#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
156static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
157 .cover_comp_gain = 16,
158};
159#endif
160
eeada9e8
AP
161#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
162static struct lp5523_led_config rx51_lp5523_led_config[] = {
163 {
164 .chan_nr = 0,
165 .led_current = 50,
166 }, {
167 .chan_nr = 1,
168 .led_current = 50,
169 }, {
170 .chan_nr = 2,
171 .led_current = 50,
172 }, {
173 .chan_nr = 3,
174 .led_current = 50,
175 }, {
176 .chan_nr = 4,
177 .led_current = 50,
178 }, {
179 .chan_nr = 5,
180 .led_current = 50,
181 }, {
182 .chan_nr = 6,
183 .led_current = 50,
184 }, {
185 .chan_nr = 7,
186 .led_current = 50,
187 }, {
188 .chan_nr = 8,
189 .led_current = 50,
190 }
191};
192
193static int rx51_lp5523_setup(void)
194{
195 return gpio_request_one(RX51_LP5523_CHIP_EN_GPIO, GPIOF_DIR_OUT,
196 "lp5523_enable");
197}
198
199static void rx51_lp5523_release(void)
200{
201 gpio_free(RX51_LP5523_CHIP_EN_GPIO);
202}
203
204static void rx51_lp5523_enable(bool state)
205{
206 gpio_set_value(RX51_LP5523_CHIP_EN_GPIO, !!state);
207}
208
209static struct lp5523_platform_data rx51_lp5523_platform_data = {
210 .led_config = rx51_lp5523_led_config,
211 .num_channels = ARRAY_SIZE(rx51_lp5523_led_config),
212 .clock_mode = LP5523_CLOCK_AUTO,
213 .setup_resources = rx51_lp5523_setup,
214 .release_resources = rx51_lp5523_release,
215 .enable = rx51_lp5523_enable,
216};
217#endif
218
a24e61a9
KV
219static struct omap2_mcspi_device_config wl1251_mcspi_config = {
220 .turbo_mode = 0,
a24e61a9
KV
221};
222
03e11104
RQ
223static struct omap2_mcspi_device_config mipid_mcspi_config = {
224 .turbo_mode = 0,
03e11104
RQ
225};
226
6996e7ff
RQ
227static struct omap2_mcspi_device_config tsc2005_mcspi_config = {
228 .turbo_mode = 0,
6996e7ff
RQ
229};
230
a24e61a9
KV
231static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
232 [RX51_SPI_WL1251] = {
233 .modalias = "wl1251",
234 .bus_num = 4,
235 .chip_select = 0,
236 .max_speed_hz = 48000000,
860fc976 237 .mode = SPI_MODE_3,
a24e61a9
KV
238 .controller_data = &wl1251_mcspi_config,
239 .platform_data = &wl1251_pdata,
240 },
03e11104
RQ
241 [RX51_SPI_MIPID] = {
242 .modalias = "acx565akm",
243 .bus_num = 1,
244 .chip_select = 2,
245 .max_speed_hz = 6000000,
246 .controller_data = &mipid_mcspi_config,
247 },
6996e7ff
RQ
248 [RX51_SPI_TSC2005] = {
249 .modalias = "tsc2005",
250 .bus_num = 1,
251 .chip_select = 0,
6996e7ff
RQ
252 .max_speed_hz = 6000000,
253 .controller_data = &tsc2005_mcspi_config,
3dad5356 254 .platform_data = &tsc2005_pdata,
6996e7ff 255 },
a24e61a9
KV
256};
257
10299e2e
KJ
258static void rx51_charger_set_power(bool on)
259{
260 gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
261}
262
263static struct isp1704_charger_data rx51_charger_data = {
264 .set_power = rx51_charger_set_power,
265};
266
fd0964c5 267static struct platform_device rx51_charger_device = {
10299e2e
KJ
268 .name = "isp1704_charger",
269 .dev = {
270 .platform_data = &rx51_charger_data,
271 },
fd0964c5
HK
272};
273
10299e2e
KJ
274static void __init rx51_charger_init(void)
275{
276 WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
e5fe29c7 277 GPIOF_OUT_INIT_HIGH, "isp1704_reset"));
10299e2e
KJ
278
279 platform_device_register(&rx51_charger_device);
280}
281
f014ee32
JN
282#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
283
284#define RX51_GPIO_CAMERA_LENS_COVER 110
285#define RX51_GPIO_CAMERA_FOCUS 68
286#define RX51_GPIO_CAMERA_CAPTURE 69
287#define RX51_GPIO_KEYPAD_SLIDE 71
288#define RX51_GPIO_LOCK_BUTTON 113
289#define RX51_GPIO_PROXIMITY 89
290
291#define RX51_GPIO_DEBOUNCE_TIMEOUT 10
292
293static struct gpio_keys_button rx51_gpio_keys[] = {
294 {
295 .desc = "Camera Lens Cover",
296 .type = EV_SW,
297 .code = SW_CAMERA_LENS_COVER,
298 .gpio = RX51_GPIO_CAMERA_LENS_COVER,
299 .active_low = 1,
300 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
301 }, {
302 .desc = "Camera Focus",
303 .type = EV_KEY,
304 .code = KEY_CAMERA_FOCUS,
305 .gpio = RX51_GPIO_CAMERA_FOCUS,
306 .active_low = 1,
307 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
308 }, {
309 .desc = "Camera Capture",
310 .type = EV_KEY,
311 .code = KEY_CAMERA,
312 .gpio = RX51_GPIO_CAMERA_CAPTURE,
313 .active_low = 1,
314 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
315 }, {
316 .desc = "Lock Button",
317 .type = EV_KEY,
318 .code = KEY_SCREENLOCK,
319 .gpio = RX51_GPIO_LOCK_BUTTON,
320 .active_low = 1,
321 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
322 }, {
323 .desc = "Keypad Slide",
324 .type = EV_SW,
325 .code = SW_KEYPAD_SLIDE,
326 .gpio = RX51_GPIO_KEYPAD_SLIDE,
327 .active_low = 1,
328 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
329 }, {
330 .desc = "Proximity Sensor",
331 .type = EV_SW,
332 .code = SW_FRONT_PROXIMITY,
333 .gpio = RX51_GPIO_PROXIMITY,
334 .active_low = 0,
335 .debounce_interval = RX51_GPIO_DEBOUNCE_TIMEOUT,
336 }
337};
338
339static struct gpio_keys_platform_data rx51_gpio_keys_data = {
340 .buttons = rx51_gpio_keys,
341 .nbuttons = ARRAY_SIZE(rx51_gpio_keys),
342};
343
344static struct platform_device rx51_gpio_keys_device = {
345 .name = "gpio-keys",
346 .id = -1,
347 .dev = {
348 .platform_data = &rx51_gpio_keys_data,
349 },
350};
351
352static void __init rx51_add_gpio_keys(void)
353{
354 platform_device_register(&rx51_gpio_keys_device);
355}
356#else
357static void __init rx51_add_gpio_keys(void)
358{
359}
360#endif /* CONFIG_KEYBOARD_GPIO || CONFIG_KEYBOARD_GPIO_MODULE */
361
bead4375 362static uint32_t board_keymap[] = {
3fea6026
DT
363 /*
364 * Note that KEY(x, 8, KEY_XXX) entries represent "entrire row
365 * connected to the ground" matrix state.
366 */
ffe7f95b 367 KEY(0, 0, KEY_Q),
acf442dc
AK
368 KEY(0, 1, KEY_O),
369 KEY(0, 2, KEY_P),
370 KEY(0, 3, KEY_COMMA),
371 KEY(0, 4, KEY_BACKSPACE),
372 KEY(0, 6, KEY_A),
373 KEY(0, 7, KEY_S),
3fea6026 374
acf442dc 375 KEY(1, 0, KEY_W),
ffe7f95b 376 KEY(1, 1, KEY_D),
acf442dc
AK
377 KEY(1, 2, KEY_F),
378 KEY(1, 3, KEY_G),
379 KEY(1, 4, KEY_H),
380 KEY(1, 5, KEY_J),
381 KEY(1, 6, KEY_K),
382 KEY(1, 7, KEY_L),
3fea6026 383
acf442dc
AK
384 KEY(2, 0, KEY_E),
385 KEY(2, 1, KEY_DOT),
ffe7f95b 386 KEY(2, 2, KEY_UP),
acf442dc
AK
387 KEY(2, 3, KEY_ENTER),
388 KEY(2, 5, KEY_Z),
389 KEY(2, 6, KEY_X),
390 KEY(2, 7, KEY_C),
3fea6026
DT
391 KEY(2, 8, KEY_F9),
392
acf442dc
AK
393 KEY(3, 0, KEY_R),
394 KEY(3, 1, KEY_V),
395 KEY(3, 2, KEY_B),
ffe7f95b 396 KEY(3, 3, KEY_N),
acf442dc
AK
397 KEY(3, 4, KEY_M),
398 KEY(3, 5, KEY_SPACE),
399 KEY(3, 6, KEY_SPACE),
400 KEY(3, 7, KEY_LEFT),
3fea6026 401
acf442dc
AK
402 KEY(4, 0, KEY_T),
403 KEY(4, 1, KEY_DOWN),
404 KEY(4, 2, KEY_RIGHT),
ffe7f95b 405 KEY(4, 4, KEY_LEFTCTRL),
acf442dc
AK
406 KEY(4, 5, KEY_RIGHTALT),
407 KEY(4, 6, KEY_LEFTSHIFT),
2e65a207 408 KEY(4, 8, KEY_F10),
3fea6026 409
acf442dc 410 KEY(5, 0, KEY_Y),
2e65a207 411 KEY(5, 8, KEY_F11),
3fea6026 412
acf442dc 413 KEY(6, 0, KEY_U),
3fea6026 414
acf442dc
AK
415 KEY(7, 0, KEY_I),
416 KEY(7, 1, KEY_F7),
417 KEY(7, 2, KEY_F8),
ffe7f95b
LL
418};
419
4f543332
TL
420static struct matrix_keymap_data board_map_data = {
421 .keymap = board_keymap,
422 .keymap_size = ARRAY_SIZE(board_keymap),
423};
424
ffe7f95b 425static struct twl4030_keypad_data rx51_kp_data = {
4f543332 426 .keymap_data = &board_map_data,
ffe7f95b
LL
427 .rows = 8,
428 .cols = 8,
ffe7f95b
LL
429 .rep = 1,
430};
431
ce6f0016
AH
432/* Enable input logic and pull all lines up when eMMC is on. */
433static struct omap_board_mux rx51_mmc2_on_mux[] = {
434 OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
435 OMAP3_MUX(SDMMC2_DAT0, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
436 OMAP3_MUX(SDMMC2_DAT1, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
437 OMAP3_MUX(SDMMC2_DAT2, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
438 OMAP3_MUX(SDMMC2_DAT3, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
439 OMAP3_MUX(SDMMC2_DAT4, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
440 OMAP3_MUX(SDMMC2_DAT5, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
441 OMAP3_MUX(SDMMC2_DAT6, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
442 OMAP3_MUX(SDMMC2_DAT7, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
443 { .reg_offset = OMAP_MUX_TERMINATOR },
444};
445
446/* Disable input logic and pull all lines down when eMMC is off. */
447static struct omap_board_mux rx51_mmc2_off_mux[] = {
448 OMAP3_MUX(SDMMC2_CMD, OMAP_PULL_ENA | OMAP_MUX_MODE0),
449 OMAP3_MUX(SDMMC2_DAT0, OMAP_PULL_ENA | OMAP_MUX_MODE0),
450 OMAP3_MUX(SDMMC2_DAT1, OMAP_PULL_ENA | OMAP_MUX_MODE0),
451 OMAP3_MUX(SDMMC2_DAT2, OMAP_PULL_ENA | OMAP_MUX_MODE0),
452 OMAP3_MUX(SDMMC2_DAT3, OMAP_PULL_ENA | OMAP_MUX_MODE0),
453 OMAP3_MUX(SDMMC2_DAT4, OMAP_PULL_ENA | OMAP_MUX_MODE0),
454 OMAP3_MUX(SDMMC2_DAT5, OMAP_PULL_ENA | OMAP_MUX_MODE0),
455 OMAP3_MUX(SDMMC2_DAT6, OMAP_PULL_ENA | OMAP_MUX_MODE0),
456 OMAP3_MUX(SDMMC2_DAT7, OMAP_PULL_ENA | OMAP_MUX_MODE0),
457 { .reg_offset = OMAP_MUX_TERMINATOR },
458};
459
112485e9
BC
460static struct omap_mux_partition *partition;
461
ce6f0016
AH
462/*
463 * Current flows to eMMC when eMMC is off and the data lines are pulled up,
464 * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
465 */
466static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
467{
468 if (power_on)
112485e9 469 omap_mux_write_array(partition, rx51_mmc2_on_mux);
ce6f0016 470 else
112485e9 471 omap_mux_write_array(partition, rx51_mmc2_off_mux);
ce6f0016
AH
472}
473
68ff0423 474static struct omap2_hsmmc_info mmc[] __initdata = {
ffe7f95b
LL
475 {
476 .name = "external",
477 .mmc = 1,
3a63833e 478 .caps = MMC_CAP_4_BIT_DATA,
ffe7f95b
LL
479 .cover_only = true,
480 .gpio_cd = 160,
481 .gpio_wp = -EINVAL,
5e763d29 482 .power_saving = true,
ffe7f95b
LL
483 },
484 {
485 .name = "internal",
486 .mmc = 2,
3a63833e
SG
487 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
488 /* See also rx51_mmc2_remux */
ffe7f95b
LL
489 .gpio_cd = -EINVAL,
490 .gpio_wp = -EINVAL,
5e763d29
AH
491 .nonremovable = true,
492 .power_saving = true,
ce6f0016 493 .remux = rx51_mmc2_remux,
ffe7f95b
LL
494 },
495 {} /* Terminator */
496};
497
786b01a8
OD
498static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
499 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
500};
ffe7f95b 501
664a41b8
LT
502static struct regulator_consumer_supply rx51_vaux2_supply[] = {
503 REGULATOR_SUPPLY("vdds_csib", "omap3isp"),
504};
75ccf268 505
786b01a8
OD
506static struct regulator_consumer_supply rx51_vaux3_supply[] = {
507 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
508};
ffe7f95b 509
786b01a8
OD
510static struct regulator_consumer_supply rx51_vsim_supply[] = {
511 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
512};
ffe7f95b 513
4cfcaef1
JN
514static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
515 /* tlv320aic3x analog supplies */
5c7d9bbe
JN
516 REGULATOR_SUPPLY("AVDD", "2-0018"),
517 REGULATOR_SUPPLY("DRVDD", "2-0018"),
caeeb4aa
JN
518 REGULATOR_SUPPLY("AVDD", "2-0019"),
519 REGULATOR_SUPPLY("DRVDD", "2-0019"),
64d06691
JN
520 /* tpa6130a2 */
521 REGULATOR_SUPPLY("Vdd", "2-0060"),
4cfcaef1 522 /* Keep vmmc as last item. It is not iterated for newer boards */
0005ae73 523 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
4cfcaef1
JN
524};
525
526static struct regulator_consumer_supply rx51_vio_supplies[] = {
527 /* tlv320aic3x digital supplies */
5c7d9bbe
JN
528 REGULATOR_SUPPLY("IOVDD", "2-0018"),
529 REGULATOR_SUPPLY("DVDD", "2-0018"),
caeeb4aa
JN
530 REGULATOR_SUPPLY("IOVDD", "2-0019"),
531 REGULATOR_SUPPLY("DVDD", "2-0019"),
589541c0
JN
532 /* Si4713 IO supply */
533 REGULATOR_SUPPLY("vio", "2-0063"),
4cfcaef1
JN
534};
535
0581b52e 536static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
b5b9945b 537 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
589541c0
JN
538 /* Si4713 supply */
539 REGULATOR_SUPPLY("vdd", "2-0063"),
0581b52e
RQ
540};
541
ffe7f95b
LL
542static struct regulator_init_data rx51_vaux1 = {
543 .constraints = {
544 .name = "V28",
545 .min_uV = 2800000,
546 .max_uV = 2800000,
000d534e 547 .always_on = true, /* due battery cover sensor */
ffe7f95b
LL
548 .valid_modes_mask = REGULATOR_MODE_NORMAL
549 | REGULATOR_MODE_STANDBY,
550 .valid_ops_mask = REGULATOR_CHANGE_MODE
551 | REGULATOR_CHANGE_STATUS,
552 },
0581b52e
RQ
553 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux1_consumers),
554 .consumer_supplies = rx51_vaux1_consumers,
ffe7f95b
LL
555};
556
557static struct regulator_init_data rx51_vaux2 = {
558 .constraints = {
559 .name = "VCSI",
560 .min_uV = 1800000,
561 .max_uV = 1800000,
562 .valid_modes_mask = REGULATOR_MODE_NORMAL
563 | REGULATOR_MODE_STANDBY,
564 .valid_ops_mask = REGULATOR_CHANGE_MODE
565 | REGULATOR_CHANGE_STATUS,
566 },
664a41b8
LT
567 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux2_supply),
568 .consumer_supplies = rx51_vaux2_supply,
ffe7f95b
LL
569};
570
571/* VAUX3 - adds more power to VIO_18 rail */
f52eeee8 572static struct regulator_init_data rx51_vaux3_cam = {
ffe7f95b
LL
573 .constraints = {
574 .name = "VCAM_DIG_18",
575 .min_uV = 1800000,
576 .max_uV = 1800000,
577 .apply_uV = true,
578 .valid_modes_mask = REGULATOR_MODE_NORMAL
579 | REGULATOR_MODE_STANDBY,
580 .valid_ops_mask = REGULATOR_CHANGE_MODE
581 | REGULATOR_CHANGE_STATUS,
582 },
583};
584
f52eeee8
AH
585static struct regulator_init_data rx51_vaux3_mmc = {
586 .constraints = {
587 .name = "VMMC2_30",
588 .min_uV = 2800000,
589 .max_uV = 3000000,
590 .apply_uV = true,
591 .valid_modes_mask = REGULATOR_MODE_NORMAL
592 | REGULATOR_MODE_STANDBY,
593 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
594 | REGULATOR_CHANGE_MODE
595 | REGULATOR_CHANGE_STATUS,
596 },
786b01a8
OD
597 .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
598 .consumer_supplies = rx51_vaux3_supply,
f52eeee8
AH
599};
600
ffe7f95b
LL
601static struct regulator_init_data rx51_vaux4 = {
602 .constraints = {
603 .name = "VCAM_ANA_28",
604 .min_uV = 2800000,
605 .max_uV = 2800000,
606 .apply_uV = true,
607 .valid_modes_mask = REGULATOR_MODE_NORMAL
608 | REGULATOR_MODE_STANDBY,
609 .valid_ops_mask = REGULATOR_CHANGE_MODE
610 | REGULATOR_CHANGE_STATUS,
611 },
612};
613
614static struct regulator_init_data rx51_vmmc1 = {
615 .constraints = {
616 .min_uV = 1850000,
617 .max_uV = 3150000,
618 .valid_modes_mask = REGULATOR_MODE_NORMAL
619 | REGULATOR_MODE_STANDBY,
620 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
621 | REGULATOR_CHANGE_MODE
622 | REGULATOR_CHANGE_STATUS,
623 },
786b01a8
OD
624 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
625 .consumer_supplies = rx51_vmmc1_supply,
ffe7f95b
LL
626};
627
628static struct regulator_init_data rx51_vmmc2 = {
629 .constraints = {
f2add1de
JN
630 .name = "V28_A",
631 .min_uV = 2800000,
632 .max_uV = 3000000,
2827411e 633 .always_on = true, /* due VIO leak to AIC34 VDDs */
ffe7f95b
LL
634 .apply_uV = true,
635 .valid_modes_mask = REGULATOR_MODE_NORMAL
636 | REGULATOR_MODE_STANDBY,
637 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
638 | REGULATOR_CHANGE_MODE
639 | REGULATOR_CHANGE_STATUS,
640 },
4cfcaef1
JN
641 .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc2_supplies),
642 .consumer_supplies = rx51_vmmc2_supplies,
ffe7f95b
LL
643};
644
094fc559
KJ
645static struct regulator_init_data rx51_vpll1 = {
646 .constraints = {
647 .name = "VPLL",
648 .min_uV = 1800000,
649 .max_uV = 1800000,
650 .apply_uV = true,
651 .always_on = true,
652 .valid_modes_mask = REGULATOR_MODE_NORMAL
653 | REGULATOR_MODE_STANDBY,
654 .valid_ops_mask = REGULATOR_CHANGE_MODE,
655 },
656};
657
658static struct regulator_init_data rx51_vpll2 = {
659 .constraints = {
660 .name = "VSDI_CSI",
661 .min_uV = 1800000,
662 .max_uV = 1800000,
663 .apply_uV = true,
664 .always_on = true,
665 .valid_modes_mask = REGULATOR_MODE_NORMAL
666 | REGULATOR_MODE_STANDBY,
667 .valid_ops_mask = REGULATOR_CHANGE_MODE,
668 },
669};
670
ffe7f95b
LL
671static struct regulator_init_data rx51_vsim = {
672 .constraints = {
673 .name = "VMMC2_IO_18",
674 .min_uV = 1800000,
675 .max_uV = 1800000,
676 .apply_uV = true,
677 .valid_modes_mask = REGULATOR_MODE_NORMAL
678 | REGULATOR_MODE_STANDBY,
679 .valid_ops_mask = REGULATOR_CHANGE_MODE
680 | REGULATOR_CHANGE_STATUS,
681 },
786b01a8
OD
682 .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
683 .consumer_supplies = rx51_vsim_supply,
ffe7f95b
LL
684};
685
4cfcaef1
JN
686static struct regulator_init_data rx51_vio = {
687 .constraints = {
688 .min_uV = 1800000,
689 .max_uV = 1800000,
690 .valid_modes_mask = REGULATOR_MODE_NORMAL
691 | REGULATOR_MODE_STANDBY,
692 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
693 | REGULATOR_CHANGE_MODE
694 | REGULATOR_CHANGE_STATUS,
695 },
696 .num_consumer_supplies = ARRAY_SIZE(rx51_vio_supplies),
697 .consumer_supplies = rx51_vio_supplies,
698};
699
094fc559
KJ
700static struct regulator_init_data rx51_vintana1 = {
701 .constraints = {
702 .name = "VINTANA1",
703 .min_uV = 1500000,
704 .max_uV = 1500000,
705 .always_on = true,
706 .valid_modes_mask = REGULATOR_MODE_NORMAL
707 | REGULATOR_MODE_STANDBY,
708 .valid_ops_mask = REGULATOR_CHANGE_MODE,
709 },
710};
711
712static struct regulator_init_data rx51_vintana2 = {
713 .constraints = {
714 .name = "VINTANA2",
715 .min_uV = 2750000,
716 .max_uV = 2750000,
717 .apply_uV = true,
718 .always_on = true,
719 .valid_modes_mask = REGULATOR_MODE_NORMAL
720 | REGULATOR_MODE_STANDBY,
721 .valid_ops_mask = REGULATOR_CHANGE_MODE,
722 },
723};
724
725static struct regulator_init_data rx51_vintdig = {
726 .constraints = {
727 .name = "VINTDIG",
728 .min_uV = 1500000,
729 .max_uV = 1500000,
730 .always_on = true,
731 .valid_modes_mask = REGULATOR_MODE_NORMAL
732 | REGULATOR_MODE_STANDBY,
733 .valid_ops_mask = REGULATOR_CHANGE_MODE,
734 },
735};
736
589541c0
JN
737static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
738 .gpio_reset = RX51_FMTX_RESET_GPIO,
739};
740
741static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
742 I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
743 .platform_data = &rx51_si4713_i2c_data,
744};
745
746static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
747 .i2c_bus = 2,
748 .subdev_board_info = &rx51_si4713_board_info,
749};
750
07ad6ab3 751static struct platform_device rx51_si4713_dev = {
589541c0
JN
752 .name = "radio-si4713",
753 .id = -1,
754 .dev = {
755 .platform_data = &rx51_si4713_data,
756 },
757};
758
759static __init void rx51_init_si4713(void)
760{
761 int err;
762
763 err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
764 if (err) {
765 printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
766 return;
767 }
768 rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
769 platform_device_register(&rx51_si4713_dev);
770}
771
ffe7f95b
LL
772static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
773{
774 /* FIXME this gpio setup is just a placeholder for now */
bc593f5d 775 gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
c0ad4fac 776 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "speaker_en");
ffe7f95b 777
ffe7f95b
LL
778 return 0;
779}
780
781static struct twl4030_gpio_platform_data rx51_gpio_data = {
ffe7f95b
LL
782 .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3)
783 | BIT(4) | BIT(5)
784 | BIT(8) | BIT(9) | BIT(10) | BIT(11)
785 | BIT(12) | BIT(13) | BIT(14) | BIT(15)
786 | BIT(16) | BIT(17) ,
787 .setup = rx51_twlgpio_setup,
788};
789
9312fffb
AK
790static struct twl4030_ins sleep_on_seq[] __initdata = {
791/*
3c684e84 792 * Turn off everything
9312fffb 793 */
3c684e84 794 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_SLEEP), 2},
9312fffb
AK
795};
796
797static struct twl4030_script sleep_on_script __initdata = {
798 .script = sleep_on_seq,
799 .size = ARRAY_SIZE(sleep_on_seq),
800 .flags = TWL4030_SLEEP_SCRIPT,
801};
802
803static struct twl4030_ins wakeup_seq[] __initdata = {
804/*
3c684e84 805 * Reenable everything
9312fffb 806 */
3c684e84 807 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
9312fffb
AK
808};
809
810static struct twl4030_script wakeup_script __initdata = {
811 .script = wakeup_seq,
812 .size = ARRAY_SIZE(wakeup_seq),
813 .flags = TWL4030_WAKEUP12_SCRIPT,
814};
815
816static struct twl4030_ins wakeup_p3_seq[] __initdata = {
817/*
3c684e84 818 * Reenable everything
9312fffb 819 */
3c684e84 820 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 1, 0, RES_STATE_ACTIVE), 2},
9312fffb
AK
821};
822
823static struct twl4030_script wakeup_p3_script __initdata = {
824 .script = wakeup_p3_seq,
825 .size = ARRAY_SIZE(wakeup_p3_seq),
826 .flags = TWL4030_WAKEUP3_SCRIPT,
827};
828
829static struct twl4030_ins wrst_seq[] __initdata = {
830/*
831 * Reset twl4030.
832 * Reset VDD1 regulator.
833 * Reset VDD2 regulator.
834 * Reset VPLL1 regulator.
835 * Enable sysclk output.
836 * Reenable twl4030.
837 */
838 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
839 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
840 0x13},
9312fffb
AK
841 {MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
842 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
843 {MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
844 {MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
3c684e84 845 {MSG_SINGULAR(DEV_GRP_P3, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
9312fffb
AK
846 {MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
847};
848
849static struct twl4030_script wrst_script __initdata = {
850 .script = wrst_seq,
851 .size = ARRAY_SIZE(wrst_seq),
852 .flags = TWL4030_WRST_SCRIPT,
853};
854
855static struct twl4030_script *twl4030_scripts[] __initdata = {
856 /* wakeup12 script should be loaded before sleep script, otherwise a
857 board might hit retention before loading of wakeup script is
858 completed. This can cause boot failures depending on timing issues.
859 */
860 &wakeup_script,
861 &sleep_on_script,
862 &wakeup_p3_script,
863 &wrst_script,
864};
865
866static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
3c684e84
AK
867 { .resource = RES_VDD1, .devgroup = -1,
868 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
869 .remap_sleep = RES_STATE_OFF
870 },
871 { .resource = RES_VDD2, .devgroup = -1,
872 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
873 .remap_sleep = RES_STATE_OFF
874 },
875 { .resource = RES_VPLL1, .devgroup = -1,
876 .type = 1, .type2 = -1, .remap_off = RES_STATE_OFF,
877 .remap_sleep = RES_STATE_OFF
878 },
879 { .resource = RES_VPLL2, .devgroup = -1,
880 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
881 },
882 { .resource = RES_VAUX1, .devgroup = -1,
883 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
884 },
885 { .resource = RES_VAUX2, .devgroup = -1,
886 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
887 },
888 { .resource = RES_VAUX3, .devgroup = -1,
889 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
890 },
891 { .resource = RES_VAUX4, .devgroup = -1,
892 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
893 },
894 { .resource = RES_VMMC1, .devgroup = -1,
895 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
896 },
897 { .resource = RES_VMMC2, .devgroup = -1,
898 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
899 },
900 { .resource = RES_VDAC, .devgroup = -1,
901 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
902 },
903 { .resource = RES_VSIM, .devgroup = -1,
904 .type = -1, .type2 = 3, .remap_off = -1, .remap_sleep = -1
905 },
906 { .resource = RES_VINTANA1, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
907 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
908 },
909 { .resource = RES_VINTANA2, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
910 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
911 },
912 { .resource = RES_VINTDIG, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
913 .type = -1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
914 },
915 { .resource = RES_VIO, .devgroup = DEV_GRP_P3,
916 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
917 },
918 { .resource = RES_CLKEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
919 .type = 1, .type2 = -1 , .remap_off = -1, .remap_sleep = -1
920 },
921 { .resource = RES_REGEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
922 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
923 },
924 { .resource = RES_NRES_PWRON, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
925 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
926 },
927 { .resource = RES_SYSEN, .devgroup = DEV_GRP_P1 | DEV_GRP_P3,
928 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
929 },
930 { .resource = RES_HFCLKOUT, .devgroup = DEV_GRP_P3,
931 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
932 },
933 { .resource = RES_32KCLKOUT, .devgroup = -1,
934 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
935 },
936 { .resource = RES_RESET, .devgroup = -1,
937 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
938 },
d7ac829f 939 { .resource = RES_MAIN_REF, .devgroup = -1,
3c684e84
AK
940 .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
941 },
9312fffb
AK
942 { 0, 0},
943};
944
945static struct twl4030_power_data rx51_t2scripts_data __initdata = {
946 .scripts = twl4030_scripts,
947 .num = ARRAY_SIZE(twl4030_scripts),
948 .resource_config = twl4030_rconfig,
949};
950
8c3d4534 951static struct twl4030_vibra_data rx51_vibra_data __initdata = {
b7a834cc
IK
952 .coexist = 0,
953};
954
8c3d4534 955static struct twl4030_audio_data rx51_audio_data __initdata = {
b7a834cc
IK
956 .audio_mclk = 26000000,
957 .vibra = &rx51_vibra_data,
958};
9312fffb 959
9312fffb 960static struct twl4030_platform_data rx51_twldata __initdata = {
ffe7f95b
LL
961 /* platform_data for children goes here */
962 .gpio = &rx51_gpio_data,
963 .keypad = &rx51_kp_data,
9312fffb 964 .power = &rx51_t2scripts_data,
4ae6df5e 965 .audio = &rx51_audio_data,
ffe7f95b
LL
966
967 .vaux1 = &rx51_vaux1,
968 .vaux2 = &rx51_vaux2,
ffe7f95b
LL
969 .vaux4 = &rx51_vaux4,
970 .vmmc1 = &rx51_vmmc1,
094fc559
KJ
971 .vpll1 = &rx51_vpll1,
972 .vpll2 = &rx51_vpll2,
ffe7f95b 973 .vsim = &rx51_vsim,
094fc559
KJ
974 .vintana1 = &rx51_vintana1,
975 .vintana2 = &rx51_vintana2,
976 .vintdig = &rx51_vintdig,
4cfcaef1 977 .vio = &rx51_vio,
ffe7f95b
LL
978};
979
f0c61d3d 980static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
64d06691
JN
981 .power_gpio = 98,
982};
983
f0fba2ad
LG
984/* Audio setup data */
985static struct aic3x_setup_data rx51_aic34_setup = {
986 .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
987 .gpio_func[1] = AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT,
988};
989
e4862f2f 990static struct aic3x_pdata rx51_aic3x_data = {
f0fba2ad
LG
991 .setup = &rx51_aic34_setup,
992 .gpio_reset = 60,
993};
994
caeeb4aa
JN
995static struct aic3x_pdata rx51_aic3x_data2 = {
996 .gpio_reset = 60,
997};
998
dabe929b
JN
999static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
1000 {
1001 I2C_BOARD_INFO("tlv320aic3x", 0x18),
87581fd4 1002 .platform_data = &rx51_aic3x_data,
dabe929b 1003 },
caeeb4aa
JN
1004 {
1005 I2C_BOARD_INFO("tlv320aic3x", 0x19),
1006 .platform_data = &rx51_aic3x_data2,
1007 },
70b5d737
MN
1008#if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
1009 {
1010 I2C_BOARD_INFO("tsl2563", 0x29),
1011 .platform_data = &rx51_tsl2563_platform_data,
1012 },
eeada9e8
AP
1013#endif
1014#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
1015 {
1016 I2C_BOARD_INFO("lp5523", 0x32),
1017 .platform_data = &rx51_lp5523_platform_data,
1018 },
70b5d737 1019#endif
d77711aa
PR
1020 {
1021 I2C_BOARD_INFO("bq27200", 0x55),
1022 },
64d06691
JN
1023 {
1024 I2C_BOARD_INFO("tpa6130a2", 0x60),
1025 .platform_data = &rx51_tpa6130a2_data,
1026 }
dabe929b
JN
1027};
1028
3b511201
AP
1029static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
1030#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1031 {
1032 I2C_BOARD_INFO("lis3lv02d", 0x1d),
1033 .platform_data = &rx51_lis3lv02d_data,
3b511201
AP
1034 },
1035#endif
1036};
1037
ffe7f95b
LL
1038static int __init rx51_i2c_init(void)
1039{
f52eeee8 1040 if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
4cfcaef1 1041 system_rev >= SYSTEM_REV_B_USES_VAUX3) {
f52eeee8 1042 rx51_twldata.vaux3 = &rx51_vaux3_mmc;
4cfcaef1
JN
1043 /* Only older boards use VMMC2 for internal MMC */
1044 rx51_vmmc2.num_consumer_supplies--;
1045 } else {
f52eeee8 1046 rx51_twldata.vaux3 = &rx51_vaux3_cam;
f52eeee8 1047 }
4cfcaef1 1048 rx51_twldata.vmmc2 = &rx51_vmmc2;
827ed9ae 1049 omap3_pmic_get_config(&rx51_twldata,
b252b0ef
PU
1050 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
1051 TWL_COMMON_REGULATOR_VDAC);
1052
1053 rx51_twldata.vdac->constraints.apply_uV = true;
1054 rx51_twldata.vdac->constraints.name = "VDAC";
1055
7d7e1eba 1056 omap_pmic_init(1, 2200, "twl5030", 7 + OMAP_INTC_START, &rx51_twldata);
dabe929b
JN
1057 omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
1058 ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
4d04317f
TL
1059#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
1060 rx51_lis3lv02d_data.irq2 = gpio_to_irq(LIS302_IRQ2_GPIO);
1061 rx51_peripherals_i2c_board_info_3[0].irq = gpio_to_irq(LIS302_IRQ1_GPIO);
1062#endif
3b511201
AP
1063 omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
1064 ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
ffe7f95b
LL
1065 return 0;
1066}
1067
aa62e90f
JY
1068#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
1069 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
1070
1071static struct mtd_partition onenand_partitions[] = {
1072 {
1073 .name = "bootloader",
1074 .offset = 0,
1075 .size = 0x20000,
1076 .mask_flags = MTD_WRITEABLE, /* Force read-only */
1077 },
1078 {
1079 .name = "config",
1080 .offset = MTDPART_OFS_APPEND,
1081 .size = 0x60000,
1082 },
1083 {
1084 .name = "log",
1085 .offset = MTDPART_OFS_APPEND,
1086 .size = 0x40000,
1087 },
1088 {
1089 .name = "kernel",
1090 .offset = MTDPART_OFS_APPEND,
1091 .size = 0x200000,
1092 },
1093 {
1094 .name = "initfs",
1095 .offset = MTDPART_OFS_APPEND,
1096 .size = 0x200000,
1097 },
1098 {
1099 .name = "rootfs",
1100 .offset = MTDPART_OFS_APPEND,
1101 .size = MTDPART_SIZ_FULL,
1102 },
1103};
1104
5403187f
AK
1105static struct omap_onenand_platform_data board_onenand_data[] = {
1106 {
1107 .cs = 0,
1108 .gpio_irq = 65,
1109 .parts = onenand_partitions,
1110 .nr_parts = ARRAY_SIZE(onenand_partitions),
1111 .flags = ONENAND_SYNC_READWRITE,
1112 }
aa62e90f 1113};
aa62e90f 1114#endif
ffe7f95b 1115
1a48e157
TL
1116#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1117
1118static struct omap_smc91x_platform_data board_smc91x_data = {
1119 .cs = 1,
1120 .gpio_irq = 54,
1121 .gpio_pwrdwn = 86,
1122 .gpio_reset = 164,
1123 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
1124};
1125
1126static void __init board_smc91x_init(void)
1127{
4896e394
TL
1128 omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
1129 omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
1130 omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
1a48e157
TL
1131
1132 gpmc_smc91x_init(&board_smc91x_data);
1133}
1134
1135#else
1136
1137static inline void board_smc91x_init(void)
1138{
1139}
1140
1141#endif
1142
a24e61a9
KV
1143static void rx51_wl1251_set_power(bool enable)
1144{
1145 gpio_set_value(RX51_WL1251_POWER_GPIO, enable);
1146}
1147
bc593f5d
IG
1148static struct gpio rx51_wl1251_gpios[] __initdata = {
1149 { RX51_WL1251_POWER_GPIO, GPIOF_OUT_INIT_LOW, "wl1251 power" },
1150 { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" },
1151};
1152
a24e61a9
KV
1153static void __init rx51_init_wl1251(void)
1154{
1155 int irq, ret;
1156
bc593f5d
IG
1157 ret = gpio_request_array(rx51_wl1251_gpios,
1158 ARRAY_SIZE(rx51_wl1251_gpios));
a24e61a9
KV
1159 if (ret < 0)
1160 goto error;
1161
a24e61a9
KV
1162 irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
1163 if (irq < 0)
1164 goto err_irq;
1165
1166 wl1251_pdata.set_power = rx51_wl1251_set_power;
1167 rx51_peripherals_spi_board_info[RX51_SPI_WL1251].irq = irq;
1168
1169 return;
1170
1171err_irq:
1172 gpio_free(RX51_WL1251_IRQ_GPIO);
a24e61a9 1173 gpio_free(RX51_WL1251_POWER_GPIO);
a24e61a9
KV
1174error:
1175 printk(KERN_ERR "wl1251 board initialisation failed\n");
1176 wl1251_pdata.set_power = NULL;
1177
1178 /*
1179 * Now rx51_peripherals_spi_board_info[1].irq is zero and
1180 * set_power is null, and wl1251_probe() will fail.
1181 */
1182}
1183
3dad5356
AK
1184static struct tsc2005_platform_data tsc2005_pdata = {
1185 .ts_pressure_max = 2048,
1186 .ts_pressure_fudge = 2,
1187 .ts_x_max = 4096,
1188 .ts_x_fudge = 4,
1189 .ts_y_max = 4096,
1190 .ts_y_fudge = 7,
1191 .ts_x_plate_ohm = 280,
1192 .esd_timeout_ms = 8000,
1193};
1194
d4860ebe
VZ
1195static struct gpio rx51_tsc2005_gpios[] __initdata = {
1196 { RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ" },
1197 { RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "tsc2005 reset" },
1198};
1199
3dad5356
AK
1200static void rx51_tsc2005_set_reset(bool enable)
1201{
1202 gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
1203}
1204
1205static void __init rx51_init_tsc2005(void)
1206{
1207 int r;
1208
d4860ebe
VZ
1209 omap_mux_init_gpio(RX51_TSC2005_RESET_GPIO, OMAP_PIN_OUTPUT);
1210 omap_mux_init_gpio(RX51_TSC2005_IRQ_GPIO, OMAP_PIN_INPUT_PULLUP);
3dad5356 1211
d4860ebe
VZ
1212 r = gpio_request_array(rx51_tsc2005_gpios,
1213 ARRAY_SIZE(rx51_tsc2005_gpios));
1214 if (r < 0) {
1215 printk(KERN_ERR "tsc2005 board initialization failed\n");
3dad5356 1216 tsc2005_pdata.esd_timeout_ms = 0;
d4860ebe 1217 return;
3dad5356 1218 }
d4860ebe
VZ
1219
1220 tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
2533c2cf
TL
1221 rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq =
1222 gpio_to_irq(RX51_TSC2005_IRQ_GPIO);
3dad5356
AK
1223}
1224
322c183c
TK
1225#if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE)
1226static struct lirc_rx51_platform_data rx51_lirc_data = {
1227 .set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
1228 .pwm_timer = 9, /* Use GPT 9 for CIR */
1229};
1230
1231static struct platform_device rx51_lirc_device = {
1232 .name = "lirc_rx51",
1233 .id = -1,
1234 .dev = {
1235 .platform_data = &rx51_lirc_data,
1236 },
1237};
1238
1239static void __init rx51_init_lirc(void)
1240{
1241 platform_device_register(&rx51_lirc_device);
1242}
1243#else
1244static void __init rx51_init_lirc(void)
1245{
1246}
1247#endif
1248
ffe7f95b
LL
1249void __init rx51_peripherals_init(void)
1250{
ffe7f95b 1251 rx51_i2c_init();
094fc559 1252 regulator_has_full_constraints();
5403187f 1253 gpmc_onenand_init(board_onenand_data);
1a48e157 1254 board_smc91x_init();
f014ee32 1255 rx51_add_gpio_keys();
a24e61a9 1256 rx51_init_wl1251();
3dad5356 1257 rx51_init_tsc2005();
589541c0 1258 rx51_init_si4713();
322c183c 1259 rx51_init_lirc();
a24e61a9
KV
1260 spi_register_board_info(rx51_peripherals_spi_board_info,
1261 ARRAY_SIZE(rx51_peripherals_spi_board_info));
112485e9
BC
1262
1263 partition = omap_mux_get("core");
1264 if (partition)
3b972bf0 1265 omap_hsmmc_init(mmc);
112485e9 1266
10299e2e 1267 rx51_charger_init();
ffe7f95b
LL
1268}
1269