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[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / cclock44xx_data.c
CommitLineData
cb26867e
RN		 1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Mike Turquette (mturquette@ti.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back
18 * in.
17b7e7d3 19 *
ee877acd
PW		 20 * XXX All of the remaining MODULEMODE clock nodes should be removed
21 * once the drivers are updated to use pm_runtime or to use the appropriate
22 * upstream clock node for rate/parent selection.
cb26867e
RN		 23 */
24
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/clk-private.h>
28#include <linux/clkdev.h>
29#include <linux/io.h>
30
31#include "soc.h"
32#include "iomap.h"
33#include "clock.h"
34#include "clock44xx.h"
35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "cm-regbits-44xx.h"
38#include "prm44xx.h"
39#include "prm-regbits-44xx.h"
40#include "control.h"
41#include "scrm44xx.h"
42
43/* OMAP4 modulemode control */
44#define OMAP4430_MODULEMODE_HWCTRL_SHIFT 0
45#define OMAP4430_MODULEMODE_SWCTRL_SHIFT 1
46
8c197ccf
JH		 47/*
48 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
49 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
50 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
51 * half of this value.
52 */
53#define OMAP4_DPLL_ABE_DEFFREQ 98304000
54
71b37071
JH		 55/*
56 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
57 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
58 * locked frequency for the USB DPLL is 960MHz.
59 */
60#define OMAP4_DPLL_USB_DEFFREQ 960000000
61
cb26867e
RN		 62/* Root clocks */
63
64DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
65
66DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
67
68DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
69 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
70 0x0, NULL);
71
72DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
73
74DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
75
76DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
77
78DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
79 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
80 0x0, NULL);
81
82DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
83
84DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
85
86DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
87
88DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
89
90DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
91
92DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
93
94DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
95
96DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
97
98static const char *sys_clkin_ck_parents[] = {
99 "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
100 "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
101 "virt_38400000_ck",
102};
103
104DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
105 OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
106 OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
107
108DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
109
110DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
111
112DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
113
114DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
115
116DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
117
118/* Module clocks and DPLL outputs */
119
120static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
121 "sys_clkin_ck", "sys_32k_ck",
122};
123
124DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
125 NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
126 OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
127
128DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
129 0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
130 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
131
132/* DPLL_ABE */
133static struct dpll_data dpll_abe_dd = {
134 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
135 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
136 .clk_ref = &abe_dpll_refclk_mux_ck,
137 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
138 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
139 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
140 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
141 .mult_mask = OMAP4430_DPLL_MULT_MASK,
142 .div1_mask = OMAP4430_DPLL_DIV_MASK,
143 .enable_mask = OMAP4430_DPLL_EN_MASK,
144 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
145 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
3ff51ed8
JH		 146 .m4xen_mask = OMAP4430_DPLL_REGM4XEN_MASK,
147 .lpmode_mask = OMAP4430_DPLL_LPMODE_EN_MASK,
cb26867e
RN		 148 .max_multiplier = 2047,
149 .max_divider = 128,
150 .min_divider = 1,
151};
152
153
154static const char *dpll_abe_ck_parents[] = {
155 "abe_dpll_refclk_mux_ck",
156};
157
158static struct clk dpll_abe_ck;
159
160static const struct clk_ops dpll_abe_ck_ops = {
161 .enable = &omap3_noncore_dpll_enable,
162 .disable = &omap3_noncore_dpll_disable,
163 .recalc_rate = &omap4_dpll_regm4xen_recalc,
164 .round_rate = &omap4_dpll_regm4xen_round_rate,
165 .set_rate = &omap3_noncore_dpll_set_rate,
166 .get_parent = &omap2_init_dpll_parent,
167};
168
169static struct clk_hw_omap dpll_abe_ck_hw = {
170 .hw = {
171 .clk = &dpll_abe_ck,
172 },
173 .dpll_data = &dpll_abe_dd,
174 .ops = &clkhwops_omap3_dpll,
175};
176
177DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
178
179static const char *dpll_abe_x2_ck_parents[] = {
180 "dpll_abe_ck",
181};
182
183static struct clk dpll_abe_x2_ck;
184
185static const struct clk_ops dpll_abe_x2_ck_ops = {
186 .recalc_rate = &omap3_clkoutx2_recalc,
187};
188
189static struct clk_hw_omap dpll_abe_x2_ck_hw = {
190 .hw = {
191 .clk = &dpll_abe_x2_ck,
192 },
193 .flags = CLOCK_CLKOUTX2,
194 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
195 .ops = &clkhwops_omap4_dpllmx,
196};
197
198DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
199
200static const struct clk_ops omap_hsdivider_ops = {
201 .set_rate = &omap2_clksel_set_rate,
202 .recalc_rate = &omap2_clksel_recalc,
203 .round_rate = &omap2_clksel_round_rate,
204};
205
206DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
207 0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
208 OMAP4430_DPLL_CLKOUT_DIV_MASK);
209
210DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
211 0x0, 1, 8);
212
213DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
214 OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
215 OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
216
217DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
218 OMAP4430_CM1_ABE_AESS_CLKCTRL,
219 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
220 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
221 0x0, NULL);
222
223DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
224 0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
225 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
226
227static const char *core_hsd_byp_clk_mux_ck_parents[] = {
228 "sys_clkin_ck", "dpll_abe_m3x2_ck",
229};
230
231DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
232 0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
233 OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
234 0x0, NULL);
235
236/* DPLL_CORE */
237static struct dpll_data dpll_core_dd = {
238 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
239 .clk_bypass = &core_hsd_byp_clk_mux_ck,
240 .clk_ref = &sys_clkin_ck,
241 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
242 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
243 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
244 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
245 .mult_mask = OMAP4430_DPLL_MULT_MASK,
246 .div1_mask = OMAP4430_DPLL_DIV_MASK,
247 .enable_mask = OMAP4430_DPLL_EN_MASK,
248 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
249 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
250 .max_multiplier = 2047,
251 .max_divider = 128,
252 .min_divider = 1,
253};
254
255
256static const char *dpll_core_ck_parents[] = {
b8675e2c 257 "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
cb26867e
RN		 258};
259
260static struct clk dpll_core_ck;
261
262static const struct clk_ops dpll_core_ck_ops = {
263 .recalc_rate = &omap3_dpll_recalc,
264 .get_parent = &omap2_init_dpll_parent,
265};
266
267static struct clk_hw_omap dpll_core_ck_hw = {
268 .hw = {
269 .clk = &dpll_core_ck,
270 },
271 .dpll_data = &dpll_core_dd,
272 .ops = &clkhwops_omap3_dpll,
273};
274
275DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
276
277static const char *dpll_core_x2_ck_parents[] = {
278 "dpll_core_ck",
279};
280
281static struct clk dpll_core_x2_ck;
282
283static struct clk_hw_omap dpll_core_x2_ck_hw = {
284 .hw = {
285 .clk = &dpll_core_x2_ck,
286 },
287};
288
289DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
290
291DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
292 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
293 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
294
295DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
296 OMAP4430_CM_DIV_M2_DPLL_CORE,
297 OMAP4430_DPLL_CLKOUT_DIV_MASK);
298
299DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
300 2);
301
302DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
303 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
304 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
305
306DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
307 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
308 OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
309
628a37d4
PW		 310DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
311 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
312 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
cb26867e
RN		 313
314DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
315 0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
316 OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
317
318DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
319 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
320 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
321
322DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
323 0x0, 1, 2);
324
325DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
326 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
327 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
328
ee877acd 329static const struct clk_ops dpll_hsd_ops = {
cb26867e
RN		 330 .enable = &omap2_dflt_clk_enable,
331 .disable = &omap2_dflt_clk_disable,
332 .is_enabled = &omap2_dflt_clk_is_enabled,
333 .recalc_rate = &omap2_clksel_recalc,
334 .get_parent = &omap2_clksel_find_parent_index,
335 .set_parent = &omap2_clksel_set_parent,
336 .init = &omap2_init_clk_clkdm,
337};
338
ee877acd
PW		 339static const struct clk_ops func_dmic_abe_gfclk_ops = {
340 .recalc_rate = &omap2_clksel_recalc,
341 .get_parent = &omap2_clksel_find_parent_index,
342 .set_parent = &omap2_clksel_set_parent,
343};
344
cb26867e
RN		 345static const char *dpll_core_m3x2_ck_parents[] = {
346 "dpll_core_x2_ck",
347};
348
349static const struct clksel dpll_core_m3x2_div[] = {
350 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
351 { .parent = NULL },
352};
353
354/* XXX Missing round_rate, set_rate in ops */
355DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
356 OMAP4430_CM_DIV_M3_DPLL_CORE,
357 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
358 OMAP4430_CM_DIV_M3_DPLL_CORE,
359 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
ee877acd 360 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
cb26867e
RN		 361
362DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
363 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
364 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
365
366static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
367 "sys_clkin_ck", "div_iva_hs_clk",
368};
369
370DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
371 0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
372 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
373
374/* DPLL_IVA */
375static struct dpll_data dpll_iva_dd = {
376 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
377 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
378 .clk_ref = &sys_clkin_ck,
379 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
380 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
381 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
382 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
383 .mult_mask = OMAP4430_DPLL_MULT_MASK,
384 .div1_mask = OMAP4430_DPLL_DIV_MASK,
385 .enable_mask = OMAP4430_DPLL_EN_MASK,
386 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
387 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
388 .max_multiplier = 2047,
389 .max_divider = 128,
390 .min_divider = 1,
391};
392
b8675e2c
PW		 393static const char *dpll_iva_ck_parents[] = {
394 "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
395};
396
cb26867e
RN		 397static struct clk dpll_iva_ck;
398
9b4fcc86
JH		 399static const struct clk_ops dpll_ck_ops = {
400 .enable = &omap3_noncore_dpll_enable,
401 .disable = &omap3_noncore_dpll_disable,
402 .recalc_rate = &omap3_dpll_recalc,
403 .round_rate = &omap2_dpll_round_rate,
404 .set_rate = &omap3_noncore_dpll_set_rate,
405 .get_parent = &omap2_init_dpll_parent,
406};
407
cb26867e
RN		 408static struct clk_hw_omap dpll_iva_ck_hw = {
409 .hw = {
410 .clk = &dpll_iva_ck,
411 },
412 .dpll_data = &dpll_iva_dd,
413 .ops = &clkhwops_omap3_dpll,
414};
415
b8675e2c 416DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
cb26867e
RN		 417
418static const char *dpll_iva_x2_ck_parents[] = {
419 "dpll_iva_ck",
420};
421
422static struct clk dpll_iva_x2_ck;
423
424static struct clk_hw_omap dpll_iva_x2_ck_hw = {
425 .hw = {
426 .clk = &dpll_iva_x2_ck,
427 },
428};
429
430DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
431
432DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
433 0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
434 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
435
436DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
437 0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
438 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
439
440/* DPLL_MPU */
441static struct dpll_data dpll_mpu_dd = {
442 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
443 .clk_bypass = &div_mpu_hs_clk,
444 .clk_ref = &sys_clkin_ck,
445 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
446 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
447 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
448 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
449 .mult_mask = OMAP4430_DPLL_MULT_MASK,
450 .div1_mask = OMAP4430_DPLL_DIV_MASK,
451 .enable_mask = OMAP4430_DPLL_EN_MASK,
452 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
453 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
454 .max_multiplier = 2047,
455 .max_divider = 128,
456 .min_divider = 1,
457};
458
b8675e2c
PW		 459static const char *dpll_mpu_ck_parents[] = {
460 "sys_clkin_ck", "div_mpu_hs_clk"
461};
462
cb26867e
RN		 463static struct clk dpll_mpu_ck;
464
465static struct clk_hw_omap dpll_mpu_ck_hw = {
466 .hw = {
467 .clk = &dpll_mpu_ck,
468 },
469 .dpll_data = &dpll_mpu_dd,
470 .ops = &clkhwops_omap3_dpll,
471};
472
b8675e2c 473DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
cb26867e
RN		 474
475DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
476
477DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
478 OMAP4430_CM_DIV_M2_DPLL_MPU,
479 OMAP4430_DPLL_CLKOUT_DIV_MASK);
480
481DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
482 &dpll_abe_m3x2_ck, 0x0, 1, 2);
483
484static const char *per_hsd_byp_clk_mux_ck_parents[] = {
485 "sys_clkin_ck", "per_hs_clk_div_ck",
486};
487
488DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
489 0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
490 OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
491
492/* DPLL_PER */
493static struct dpll_data dpll_per_dd = {
494 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
495 .clk_bypass = &per_hsd_byp_clk_mux_ck,
496 .clk_ref = &sys_clkin_ck,
497 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
498 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
499 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
500 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
501 .mult_mask = OMAP4430_DPLL_MULT_MASK,
502 .div1_mask = OMAP4430_DPLL_DIV_MASK,
503 .enable_mask = OMAP4430_DPLL_EN_MASK,
504 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
505 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
506 .max_multiplier = 2047,
507 .max_divider = 128,
508 .min_divider = 1,
509};
510
b8675e2c
PW		 511static const char *dpll_per_ck_parents[] = {
512 "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
513};
cb26867e
RN		 514
515static struct clk dpll_per_ck;
516
517static struct clk_hw_omap dpll_per_ck_hw = {
518 .hw = {
519 .clk = &dpll_per_ck,
520 },
521 .dpll_data = &dpll_per_dd,
522 .ops = &clkhwops_omap3_dpll,
523};
524
b8675e2c 525DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
cb26867e
RN		 526
527DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
528 OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
529 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
530
531static const char *dpll_per_x2_ck_parents[] = {
532 "dpll_per_ck",
533};
534
535static struct clk dpll_per_x2_ck;
536
537static struct clk_hw_omap dpll_per_x2_ck_hw = {
538 .hw = {
539 .clk = &dpll_per_x2_ck,
540 },
541 .flags = CLOCK_CLKOUTX2,
542 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
543 .ops = &clkhwops_omap4_dpllmx,
544};
545
546DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
547
548DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
549 0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
550 OMAP4430_DPLL_CLKOUT_DIV_MASK);
551
552static const char *dpll_per_m3x2_ck_parents[] = {
553 "dpll_per_x2_ck",
554};
555
556static const struct clksel dpll_per_m3x2_div[] = {
557 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
558 { .parent = NULL },
559};
560
561/* XXX Missing round_rate, set_rate in ops */
562DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
563 OMAP4430_CM_DIV_M3_DPLL_PER,
564 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
565 OMAP4430_CM_DIV_M3_DPLL_PER,
566 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
ee877acd 567 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
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RN		 568
569DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
570 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
571 OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
572
573DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
574 0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
575 OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
576
577DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
578 0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
579 OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
580
581DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
582 0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
583 OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
584
585DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
586 &dpll_abe_m3x2_ck, 0x0, 1, 3);
587
588/* DPLL_USB */
589static struct dpll_data dpll_usb_dd = {
590 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
591 .clk_bypass = &usb_hs_clk_div_ck,
592 .flags = DPLL_J_TYPE,
593 .clk_ref = &sys_clkin_ck,
594 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
595 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
596 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
597 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
598 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
599 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
600 .enable_mask = OMAP4430_DPLL_EN_MASK,
601 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
602 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
603 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
604 .max_multiplier = 4095,
605 .max_divider = 256,
606 .min_divider = 1,
607};
608
b8675e2c
PW		 609static const char *dpll_usb_ck_parents[] = {
610 "sys_clkin_ck", "usb_hs_clk_div_ck"
611};
612
cb26867e
RN		 613static struct clk dpll_usb_ck;
614
d0758237
RN		 615static const struct clk_ops dpll_usb_ck_ops = {
616 .enable = &omap3_noncore_dpll_enable,
617 .disable = &omap3_noncore_dpll_disable,
618 .recalc_rate = &omap3_dpll_recalc,
619 .round_rate = &omap2_dpll_round_rate,
620 .set_rate = &omap3_noncore_dpll_set_rate,
621 .get_parent = &omap2_init_dpll_parent,
622 .init = &omap2_init_clk_clkdm,
623};
624
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RN		 625static struct clk_hw_omap dpll_usb_ck_hw = {
626 .hw = {
627 .clk = &dpll_usb_ck,
628 },
629 .dpll_data = &dpll_usb_dd,
d0758237 630 .clkdm_name = "l3_init_clkdm",
cb26867e
RN		 631 .ops = &clkhwops_omap3_dpll,
632};
633
d0758237 634DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
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RN		 635
636static const char *dpll_usb_clkdcoldo_ck_parents[] = {
637 "dpll_usb_ck",
638};
639
640static struct clk dpll_usb_clkdcoldo_ck;
641
642static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
643};
644
645static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
646 .hw = {
647 .clk = &dpll_usb_clkdcoldo_ck,
648 },
649 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
650 .ops = &clkhwops_omap4_dpllmx,
651};
652
653DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
654 dpll_usb_clkdcoldo_ck_ops);
655
656DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
657 OMAP4430_CM_DIV_M2_DPLL_USB,
658 OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
659
660static const char *ducati_clk_mux_ck_parents[] = {
661 "div_core_ck", "dpll_per_m6x2_ck",
662};
663
664DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
665 OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
666 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
667
668DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
669 0x0, 1, 16);
670
671DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
672 1, 4);
673
674DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
675 0x0, 1, 8);
676
677static const struct clk_div_table func_48m_fclk_rates[] = {
678 { .div = 4, .val = 0 },
679 { .div = 8, .val = 1 },
680 { .div = 0 },
681};
682DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
683 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
684 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
685 NULL);
686
687DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
688 0x0, 1, 4);
689
690static const struct clk_div_table func_64m_fclk_rates[] = {
691 { .div = 2, .val = 0 },
692 { .div = 4, .val = 1 },
693 { .div = 0 },
694};
695DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
696 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
697 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
698 NULL);
699
700static const struct clk_div_table func_96m_fclk_rates[] = {
701 { .div = 2, .val = 0 },
702 { .div = 4, .val = 1 },
703 { .div = 0 },
704};
705DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
706 0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
707 OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
708 NULL);
709
710static const struct clk_div_table init_60m_fclk_rates[] = {
711 { .div = 1, .val = 0 },
712 { .div = 8, .val = 1 },
713 { .div = 0 },
714};
715DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
716 0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
717 OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
718 0x0, init_60m_fclk_rates, NULL);
719
720DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
721 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
722 OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
723
724DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
725 OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
726 OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
727
728DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
729 0x0, 1, 16);
730
731static const char *l4_wkup_clk_mux_ck_parents[] = {
732 "sys_clkin_ck", "lp_clk_div_ck",
733};
734
735DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
736 OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
737 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
738
739static const struct clk_div_table ocp_abe_iclk_rates[] = {
740 { .div = 2, .val = 0 },
741 { .div = 1, .val = 1 },
742 { .div = 0 },
743};
744DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
745 OMAP4430_CM1_ABE_AESS_CLKCTRL,
746 OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
747 OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
748 0x0, ocp_abe_iclk_rates, NULL);
749
750DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
751 0x0, 1, 4);
752
753DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
754 OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
755 OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
756
757DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
758 OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
759 OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
760
b8675e2c
PW		 761static const char *dbgclk_mux_ck_parents[] = {
762 "sys_clkin_ck"
763};
764
cb26867e
RN		 765static struct clk dbgclk_mux_ck;
766DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
b8675e2c 767DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
cb26867e
RN		 768 dpll_usb_clkdcoldo_ck_ops);
769
770/* Leaf clocks controlled by modules */
771
772DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
773 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
774 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
775
776DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
777 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
778 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
779
cb26867e
RN		 780DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
781 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
782 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
783
784static const struct clk_div_table div_ts_ck_rates[] = {
785 { .div = 8, .val = 0 },
786 { .div = 16, .val = 1 },
787 { .div = 32, .val = 2 },
788 { .div = 0 },
789};
790DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
791 0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
792 OMAP4430_CLKSEL_24_25_SHIFT,
793 OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
794 NULL);
795
796DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
797 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
798 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
799 0x0, NULL);
800
cb26867e
RN		 801static const char *dmic_sync_mux_ck_parents[] = {
802 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
803};
804
805DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
806 0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
807 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
808 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
809
810static const struct clksel func_dmic_abe_gfclk_sel[] = {
811 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
812 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
813 { .parent = &slimbus_clk, .rates = div_1_2_rates },
814 { .parent = NULL },
815};
816
ee877acd 817static const char *func_dmic_abe_gfclk_parents[] = {
cb26867e
RN		 818 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
819};
820
ee877acd
PW		 821DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
822 OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
823 func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
cb26867e 824
cb26867e
RN		 825DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
826 OMAP4430_CM_DSS_DSS_CLKCTRL,
827 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
828
829DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
830 OMAP4430_CM_DSS_DSS_CLKCTRL,
831 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
832
a861389a
TV		 833DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
834 CLK_SET_RATE_PARENT,
cb26867e
RN		 835 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
836 0x0, NULL);
837
838DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
839 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
840 0x0, NULL);
841
842DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
843 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
844 0x0, NULL);
845
cb26867e
RN		 846DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
847 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
848 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
849
cb26867e
RN		 850DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
851 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
852 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
853
cb26867e
RN		 854DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
855 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
856 0x0, NULL);
857
cb26867e
RN		 858DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
859 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
860 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
861
cb26867e
RN		 862DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
863 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
864 0x0, NULL);
865
cb26867e
RN		 866DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
867 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
868 0x0, NULL);
869
cb26867e
RN		 870DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
871 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
872 0x0, NULL);
873
cb26867e
RN		 874static const struct clksel sgx_clk_mux_sel[] = {
875 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
876 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
877 { .parent = NULL },
878};
879
ee877acd 880static const char *sgx_clk_mux_parents[] = {
cb26867e
RN		 881 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
882};
883
ee877acd
PW		 884DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
885 OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
886 sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
cb26867e 887
cb26867e
RN		 888DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
889 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
890 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
891 NULL);
892
cb26867e
RN		 893DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
894 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
895 0x0, NULL);
896
cb26867e
RN		 897DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
898 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
899 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
900 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
901
902static const struct clksel func_mcasp_abe_gfclk_sel[] = {
903 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
904 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
905 { .parent = &slimbus_clk, .rates = div_1_2_rates },
906 { .parent = NULL },
907};
908
ee877acd 909static const char *func_mcasp_abe_gfclk_parents[] = {
cb26867e
RN		 910 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
911};
912
ee877acd
PW		 913DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
914 OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
915 func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
cb26867e
RN		 916
917DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
918 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
919 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
920 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
921
922static const struct clksel func_mcbsp1_gfclk_sel[] = {
923 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
924 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
925 { .parent = &slimbus_clk, .rates = div_1_2_rates },
926 { .parent = NULL },
927};
928
ee877acd 929static const char *func_mcbsp1_gfclk_parents[] = {
cb26867e
RN		 930 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
931};
932
ee877acd
PW		 933DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
934 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
935 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
936 func_dmic_abe_gfclk_ops);
cb26867e
RN		 937
938DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
939 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
940 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
941 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
942
943static const struct clksel func_mcbsp2_gfclk_sel[] = {
944 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
945 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
946 { .parent = &slimbus_clk, .rates = div_1_2_rates },
947 { .parent = NULL },
948};
949
ee877acd 950static const char *func_mcbsp2_gfclk_parents[] = {
cb26867e
RN		 951 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
952};
953
ee877acd
PW		 954DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
955 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
956 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
957 func_dmic_abe_gfclk_ops);
cb26867e
RN		 958
959DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
960 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
961 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
962 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
963
964static const struct clksel func_mcbsp3_gfclk_sel[] = {
965 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
966 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
967 { .parent = &slimbus_clk, .rates = div_1_2_rates },
968 { .parent = NULL },
969};
970
ee877acd 971static const char *func_mcbsp3_gfclk_parents[] = {
cb26867e
RN		 972 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
973};
974
ee877acd
PW		 975DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
976 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
977 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
978 func_dmic_abe_gfclk_ops);
cb26867e
RN		 979
980static const char *mcbsp4_sync_mux_ck_parents[] = {
981 "func_96m_fclk", "per_abe_nc_fclk",
982};
983
984DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
985 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
986 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
987 OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
988
989static const struct clksel per_mcbsp4_gfclk_sel[] = {
990 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
991 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
992 { .parent = NULL },
993};
994
ee877acd 995static const char *per_mcbsp4_gfclk_parents[] = {
cb26867e
RN		 996 "mcbsp4_sync_mux_ck", "pad_clks_ck",
997};
998
ee877acd
PW		 999DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1000 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1001 OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
1002 func_dmic_abe_gfclk_ops);
cb26867e 1003
cb26867e
RN		 1004static const struct clksel hsmmc1_fclk_sel[] = {
1005 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1006 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1007 { .parent = NULL },
1008};
1009
ee877acd 1010static const char *hsmmc1_fclk_parents[] = {
cb26867e
RN		 1011 "func_64m_fclk", "func_96m_fclk",
1012};
1013
ee877acd
PW		 1014DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1015 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1016 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
cb26867e 1017
ee877acd
PW		 1018DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1019 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1020 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
cb26867e 1021
92702df3
PW		 1022DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1023 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1024 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1025
cb26867e
RN		 1026DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1027 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1028 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1029
cb26867e
RN		 1030DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1031 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1032 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1033
1034DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1035 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1036 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1037
1038DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1039 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1040 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1041
1042DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1043 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1044 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1045
cb26867e
RN		 1046DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1047 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1048 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1049
1050DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1051 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1052 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1053
1054DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1055 &pad_slimbus_core_clks_ck, 0x0,
1056 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1057 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1058
cb26867e
RN		 1059DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1060 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1061 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1062
1063DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1064 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1065 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1066
1067DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1068 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1069 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1070
1071static const struct clksel dmt1_clk_mux_sel[] = {
1072 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1073 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1074 { .parent = NULL },
1075};
1076
ee877acd
PW		 1077DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1078 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1079 abe_dpll_bypass_clk_mux_ck_parents,
1080 func_dmic_abe_gfclk_ops);
1081
1082DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1083 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
1084 abe_dpll_bypass_clk_mux_ck_parents,
1085 func_dmic_abe_gfclk_ops);
1086
1087DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1088 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
1089 abe_dpll_bypass_clk_mux_ck_parents,
1090 func_dmic_abe_gfclk_ops);
1091
1092DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1093 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1094 abe_dpll_bypass_clk_mux_ck_parents,
1095 func_dmic_abe_gfclk_ops);
1096
1097DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1098 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
1099 abe_dpll_bypass_clk_mux_ck_parents,
1100 func_dmic_abe_gfclk_ops);
1101
1102DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1103 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
1104 abe_dpll_bypass_clk_mux_ck_parents,
1105 func_dmic_abe_gfclk_ops);
cb26867e
RN		 1106
1107static const struct clksel timer5_sync_mux_sel[] = {
1108 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1109 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1110 { .parent = NULL },
1111};
1112
ee877acd 1113static const char *timer5_sync_mux_parents[] = {
cb26867e
RN		 1114 "syc_clk_div_ck", "sys_32k_ck",
1115};
1116
ee877acd
PW		 1117DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1118 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1119 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1120
1121DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1122 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1123 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1124
1125DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1126 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1127 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1128
1129DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1130 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1131 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1132
1133DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1134 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
1135 abe_dpll_bypass_clk_mux_ck_parents,
1136 func_dmic_abe_gfclk_ops);
cb26867e 1137
cb26867e
RN		 1138static struct clk usb_host_fs_fck;
1139
1140static const char *usb_host_fs_fck_parent_names[] = {
1141 "func_48mc_fclk",
1142};
1143
1144static const struct clk_ops usb_host_fs_fck_ops = {
1145 .enable = &omap2_dflt_clk_enable,
1146 .disable = &omap2_dflt_clk_disable,
1147 .is_enabled = &omap2_dflt_clk_is_enabled,
1148};
1149
1150static struct clk_hw_omap usb_host_fs_fck_hw = {
1151 .hw = {
1152 .clk = &usb_host_fs_fck,
1153 },
1154 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1155 .enable_bit = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1156 .clkdm_name = "l3_init_clkdm",
1157};
1158
1159DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1160 usb_host_fs_fck_ops);
1161
1162static const char *utmi_p1_gfclk_parents[] = {
1163 "init_60m_fclk", "xclk60mhsp1_ck",
1164};
1165
1166DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1167 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1168 OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1169 0x0, NULL);
1170
1171DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1172 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1173 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1174
1175static const char *utmi_p2_gfclk_parents[] = {
1176 "init_60m_fclk", "xclk60mhsp2_ck",
1177};
1178
1179DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1180 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1181 OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1182 0x0, NULL);
1183
1184DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1185 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1186 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1187
1188DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1189 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1190 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1191
1192DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1193 &dpll_usb_m2_ck, 0x0,
1194 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1195 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1196
1197DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1198 &init_60m_fclk, 0x0,
1199 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1200 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1201
1202DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1203 &init_60m_fclk, 0x0,
1204 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1205 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1206
1207DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1208 &dpll_usb_m2_ck, 0x0,
1209 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1210 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1211
1212DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1213 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1214 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1215
1216DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1217 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1218 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1219
1220static const char *otg_60m_gfclk_parents[] = {
1221 "utmi_phy_clkout_ck", "xclk60motg_ck",
1222};
1223
1224DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1225 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1226 OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1227
1228DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1229 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1230 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1231
1232DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1233 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1234 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1235
1236DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1237 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1238 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1239
1240DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1241 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1242 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1243
1244DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1245 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1246 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1247
1248DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1249 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1250 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1251
1252DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1253 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1254 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1255
1256static const struct clk_div_table usim_ck_rates[] = {
1257 { .div = 14, .val = 0 },
1258 { .div = 18, .val = 1 },
1259 { .div = 0 },
1260};
1261DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1262 OMAP4430_CM_WKUP_USIM_CLKCTRL,
1263 OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1264 0x0, usim_ck_rates, NULL);
1265
1266DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1267 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1268 0x0, NULL);
1269
cb26867e
RN		 1270/* Remaining optional clocks */
1271static const char *pmd_stm_clock_mux_ck_parents[] = {
1272 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1273};
1274
1275DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1276 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1277 OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1278
1279DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1280 OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1281 OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1282 OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1283
1284DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1285 &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1286 OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1287 OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1288 NULL);
1289
1290static const char *trace_clk_div_ck_parents[] = {
1291 "pmd_trace_clk_mux_ck",
1292};
1293
1294static const struct clksel trace_clk_div_div[] = {
1295 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1296 { .parent = NULL },
1297};
1298
1299static struct clk trace_clk_div_ck;
1300
1301static const struct clk_ops trace_clk_div_ck_ops = {
1302 .recalc_rate = &omap2_clksel_recalc,
1303 .set_rate = &omap2_clksel_set_rate,
1304 .round_rate = &omap2_clksel_round_rate,
1305 .init = &omap2_init_clk_clkdm,
1306 .enable = &omap2_clkops_enable_clkdm,
1307 .disable = &omap2_clkops_disable_clkdm,
1308};
1309
1310static struct clk_hw_omap trace_clk_div_ck_hw = {
1311 .hw = {
1312 .clk = &trace_clk_div_ck,
1313 },
1314 .clkdm_name = "emu_sys_clkdm",
1315 .clksel = trace_clk_div_div,
1316 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1317 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1318};
1319
1320DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1321 trace_clk_div_ck_ops);
1322
1323/* SCRM aux clk nodes */
1324
1325static const struct clksel auxclk_src_sel[] = {
1326 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1327 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1328 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1329 { .parent = NULL },
1330};
1331
1332static const char *auxclk_src_ck_parents[] = {
1333 "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1334};
1335
1336static const struct clk_ops auxclk_src_ck_ops = {
1337 .enable = &omap2_dflt_clk_enable,
1338 .disable = &omap2_dflt_clk_disable,
1339 .is_enabled = &omap2_dflt_clk_is_enabled,
1340 .recalc_rate = &omap2_clksel_recalc,
1341 .get_parent = &omap2_clksel_find_parent_index,
1342};
1343
1344DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1345 OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1346 OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1347 auxclk_src_ck_parents, auxclk_src_ck_ops);
1348
1349DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1350 OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1351 0x0, NULL);
1352
1353DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1354 OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1355 OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1356 auxclk_src_ck_parents, auxclk_src_ck_ops);
1357
1358DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1359 OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1360 0x0, NULL);
1361
1362DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1363 OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1364 OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1365 auxclk_src_ck_parents, auxclk_src_ck_ops);
1366
1367DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1368 OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1369 0x0, NULL);
1370
1371DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1372 OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1373 OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1374 auxclk_src_ck_parents, auxclk_src_ck_ops);
1375
1376DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1377 OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1378 0x0, NULL);
1379
1380DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1381 OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1382 OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1383 auxclk_src_ck_parents, auxclk_src_ck_ops);
1384
1385DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1386 OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1387 0x0, NULL);
1388
1389DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1390 OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1391 OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1392 auxclk_src_ck_parents, auxclk_src_ck_ops);
1393
1394DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1395 OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1396 0x0, NULL);
1397
1398static const char *auxclkreq_ck_parents[] = {
1399 "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1400 "auxclk5_ck",
1401};
1402
1403DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1404 OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1405 0x0, NULL);
1406
1407DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1408 OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1409 0x0, NULL);
1410
1411DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1412 OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1413 0x0, NULL);
1414
1415DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1416 OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1417 0x0, NULL);
1418
1419DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1420 OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1421 0x0, NULL);
1422
1423DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1424 OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1425 0x0, NULL);
1426
1427/*
78e52e02 1428 * clocks specific to omap4460
cb26867e 1429 */
78e52e02
K		 1430static struct omap_clk omap446x_clks[] = {
1431 CLK(NULL, "div_ts_ck", &div_ts_ck),
1432 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
1433};
1434
1435/*
1436 * clocks specific to omap4430
1437 */
1438static struct omap_clk omap443x_clks[] = {
1439 CLK(NULL, "bandgap_fclk", &bandgap_fclk),
1440};
cb26867e 1441
78e52e02
K		 1442/*
1443 * clocks common to omap44xx
1444 */
cb26867e 1445static struct omap_clk omap44xx_clks[] = {
78e52e02
K		 1446 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
1447 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
1448 CLK(NULL, "pad_clks_ck", &pad_clks_ck),
1449 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
1450 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
1451 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
1452 CLK(NULL, "slimbus_clk", &slimbus_clk),
1453 CLK(NULL, "sys_32k_ck", &sys_32k_ck),
1454 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
1455 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
1456 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
1457 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
1458 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
1459 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
1460 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
1461 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
1462 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
1463 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
1464 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
1465 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
1466 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
1467 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
1468 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
1469 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
1470 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
1471 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
1472 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
1473 CLK(NULL, "abe_clk", &abe_clk),
1474 CLK(NULL, "aess_fclk", &aess_fclk),
1475 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
1476 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
1477 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
1478 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
1479 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
1480 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
1481 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
1482 CLK(NULL, "ddrphy_ck", &ddrphy_ck),
1483 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
1484 CLK(NULL, "div_core_ck", &div_core_ck),
1485 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
1486 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
1487 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
1488 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
1489 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
1490 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
1491 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
1492 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
1493 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
1494 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
1495 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
1496 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
1497 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
1498 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
1499 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
1500 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
1501 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
1502 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
1503 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
1504 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
1505 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
1506 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
1507 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
1508 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
1509 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
1510 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
1511 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
1512 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
1513 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
1514 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
1515 CLK(NULL, "func_12m_fclk", &func_12m_fclk),
1516 CLK(NULL, "func_24m_clk", &func_24m_clk),
1517 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
1518 CLK(NULL, "func_48m_fclk", &func_48m_fclk),
1519 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
1520 CLK(NULL, "func_64m_fclk", &func_64m_fclk),
1521 CLK(NULL, "func_96m_fclk", &func_96m_fclk),
1522 CLK(NULL, "init_60m_fclk", &init_60m_fclk),
1523 CLK(NULL, "l3_div_ck", &l3_div_ck),
1524 CLK(NULL, "l4_div_ck", &l4_div_ck),
1525 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
1526 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
1527 CLK("smp_twd", NULL, &mpu_periphclk),
1528 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
1529 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
1530 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
1531 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
1532 CLK(NULL, "aes1_fck", &aes1_fck),
1533 CLK(NULL, "aes2_fck", &aes2_fck),
1534 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
1535 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
1536 CLK(NULL, "dss_sys_clk", &dss_sys_clk),
1537 CLK(NULL, "dss_tv_clk", &dss_tv_clk),
1538 CLK(NULL, "dss_dss_clk", &dss_dss_clk),
1539 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
1540 CLK(NULL, "dss_fck", &dss_fck),
1541 CLK("omapdss_dss", "ick", &dss_fck),
1542 CLK(NULL, "fdif_fck", &fdif_fck),
1543 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
1544 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
1545 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
1546 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
1547 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
1548 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
1549 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
1550 CLK(NULL, "hsi_fck", &hsi_fck),
1551 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
1552 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
1553 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
1554 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
1555 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
1556 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
1557 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
1558 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
1559 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
1560 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
1561 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
1562 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
1563 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
afcf7924 1564 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m),
78e52e02
K		 1565 CLK(NULL, "sha2md5_fck", &sha2md5_fck),
1566 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
1567 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
1568 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
1569 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
1570 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
1571 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
1572 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
1573 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
1574 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
1575 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
1576 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
1577 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
1578 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
1579 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
1580 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
1581 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
1582 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
1583 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
1584 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
1585 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
1586 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
1587 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
1588 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
1589 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
1590 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
1591 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
1592 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
1593 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
1594 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
1595 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
1596 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
1597 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
1598 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
1599 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
1600 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
1601 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
1602 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
1603 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
1604 CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
1605 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
1606 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
1607 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
1608 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
1609 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
1610 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
1611 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
1612 CLK(NULL, "usim_ck", &usim_ck),
1613 CLK(NULL, "usim_fclk", &usim_fclk),
1614 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
1615 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
1616 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
1617 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
1618 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
1619 CLK(NULL, "auxclk0_ck", &auxclk0_ck),
1620 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
1621 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
1622 CLK(NULL, "auxclk1_ck", &auxclk1_ck),
1623 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
1624 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
1625 CLK(NULL, "auxclk2_ck", &auxclk2_ck),
1626 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
1627 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
1628 CLK(NULL, "auxclk3_ck", &auxclk3_ck),
1629 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
1630 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
1631 CLK(NULL, "auxclk4_ck", &auxclk4_ck),
1632 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
1633 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1634 CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1635 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
2cfeed31 1636 CLK("50000000.gpmc", "fck", &dummy_ck),
78e52e02
K		 1637 CLK("omap_i2c.1", "ick", &dummy_ck),
1638 CLK("omap_i2c.2", "ick", &dummy_ck),
1639 CLK("omap_i2c.3", "ick", &dummy_ck),
1640 CLK("omap_i2c.4", "ick", &dummy_ck),
1641 CLK(NULL, "mailboxes_ick", &dummy_ck),
1642 CLK("omap_hsmmc.0", "ick", &dummy_ck),
1643 CLK("omap_hsmmc.1", "ick", &dummy_ck),
1644 CLK("omap_hsmmc.2", "ick", &dummy_ck),
1645 CLK("omap_hsmmc.3", "ick", &dummy_ck),
1646 CLK("omap_hsmmc.4", "ick", &dummy_ck),
1647 CLK("omap-mcbsp.1", "ick", &dummy_ck),
1648 CLK("omap-mcbsp.2", "ick", &dummy_ck),
1649 CLK("omap-mcbsp.3", "ick", &dummy_ck),
1650 CLK("omap-mcbsp.4", "ick", &dummy_ck),
1651 CLK("omap2_mcspi.1", "ick", &dummy_ck),
1652 CLK("omap2_mcspi.2", "ick", &dummy_ck),
1653 CLK("omap2_mcspi.3", "ick", &dummy_ck),
1654 CLK("omap2_mcspi.4", "ick", &dummy_ck),
1655 CLK(NULL, "uart1_ick", &dummy_ck),
1656 CLK(NULL, "uart2_ick", &dummy_ck),
1657 CLK(NULL, "uart3_ick", &dummy_ck),
1658 CLK(NULL, "uart4_ick", &dummy_ck),
1659 CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
1660 CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
1661 CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
1662 CLK("omap_wdt", "ick", &dummy_ck),
1663 CLK(NULL, "timer_32k_ck", &sys_32k_ck),
cb26867e 1664 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
78e52e02
K		 1665 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
1666 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
1667 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
1668 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
1669 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
1670 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
1671 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
1672 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
1673 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
1674 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
1675 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
1676 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
1677 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
1678 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
1679 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
1680 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
1681 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
1682 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
1683 CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
1684 CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
1685 CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
1686 CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
1687 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
cb26867e
RN		 1688};
1689
cb26867e
RN		 1690int __init omap4xxx_clk_init(void)
1691{
8c197ccf 1692 int rc;
cb26867e
RN		 1693
1694 if (cpu_is_omap443x()) {
1695 cpu_mask = RATE_IN_4430;
78e52e02 1696 omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
cb26867e
RN		 1697 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1698 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
78e52e02 1699 omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
cb26867e
RN		 1700 if (cpu_is_omap447x())
1701 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1702 } else {
1703 return 0;
1704 }
1705
78e52e02 1706 omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
cb26867e
RN		 1707
1708 omap2_clk_disable_autoidle_all();
1709
eeb6603f
RN		 1710 /*
1711 * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
1712 * when its in bypass. So always lock USB before ABE DPLL.
1713 */
1714 /*
1715 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1716 * domain can transition to retention state when not in use.
1717 */
1718 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1719 if (rc)
1720 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1721
8c197ccf
JH		 1722 /*
1723 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
1724 * state when turning the ABE clock domain. Workaround this by
1725 * locking the ABE DPLL on boot.
981827a2 1726 * Lock the ABE DPLL in any case to avoid issues with audio.
8c197ccf 1727 */
981827a2
PU		 1728 rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
1729 if (!rc)
1730 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
1731 if (rc)
1732 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
8c197ccf 1733
cb26867e
RN		 1734 return 0;
1735}
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