[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / clkt_dpll.c

/*
 * OMAP2/3/4 DPLL clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/div64.h>

#include <plat/clock.h>

#include "clock.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"

/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER		2
#define DPLL_MIN_DIVIDER		1

/* Possible error results from _dpll_test_mult */
#define DPLL_MULT_UNDERFLOW		-1

/*
 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
 * The higher the scale factor, the greater the risk of arithmetic overflow,
 * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
 * must be a power of DPLL_SCALE_BASE.
 */
#define DPLL_SCALE_FACTOR		64
#define DPLL_SCALE_BASE			2
#define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))

/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define DPLL_FINT_BAND1_MIN		750000
#define DPLL_FINT_BAND1_MAX		2100000
#define DPLL_FINT_BAND2_MIN		7500000
#define DPLL_FINT_BAND2_MAX		21000000

/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW		-1
#define DPLL_FINT_INVALID		-2

/* Private functions */

/*
 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
 * @clk: DPLL struct clk to test
 * @n: divider value (N) to test
 *
 * Tests whether a particular divider @n will result in a valid DPLL
 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
 * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
 * (assuming that it is counting N upwards), or -2 if the enclosing loop
 * should skip to the next iteration (again assuming N is increasing).
 */
static int _dpll_test_fint(struct clk *clk, u8 n)
{
	struct dpll_data *dd;
	long fint;
	int ret = 0;

	dd = clk->dpll_data;

	/* DPLL divider must result in a valid jitter correction val */
	fint = clk->parent->rate / n;
	if (fint < DPLL_FINT_BAND1_MIN) {

		pr_debug("rejecting n=%d due to Fint failure, "
			 "lowering max_divider\n", n);
		dd->max_divider = n;
		ret = DPLL_FINT_UNDERFLOW;

	} else if (fint > DPLL_FINT_BAND1_MAX &&
		   fint < DPLL_FINT_BAND2_MIN) {

		pr_debug("rejecting n=%d due to Fint failure\n", n);
		ret = DPLL_FINT_INVALID;

	} else if (fint > DPLL_FINT_BAND2_MAX) {

		pr_debug("rejecting n=%d due to Fint failure, "
			 "boosting min_divider\n", n);
		dd->min_divider = n;
		ret = DPLL_FINT_INVALID;

	}

	return ret;
}

static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
					    unsigned int m, unsigned int n)
{
	unsigned long long num;

	num = (unsigned long long)parent_rate * m;
	do_div(num, n);
	return num;
}

/*
 * _dpll_test_mult - test a DPLL multiplier value
 * @m: pointer to the DPLL m (multiplier) value under test
 * @n: current DPLL n (divider) value under test
 * @new_rate: pointer to storage for the resulting rounded rate
 * @target_rate: the desired DPLL rate
 * @parent_rate: the DPLL's parent clock rate
 *
 * This code tests a DPLL multiplier value, ensuring that the
 * resulting rate will not be higher than the target_rate, and that
 * the multiplier value itself is valid for the DPLL.  Initially, the
 * integer pointed to by the m argument should be prescaled by
 * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
 * a non-scaled m upon return.  This non-scaled m will result in a
 * new_rate as close as possible to target_rate (but not greater than
 * target_rate) given the current (parent_rate, n, prescaled m)
 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
 * non-scaled m attempted to underflow, which can allow the calling
 * function to bail out early; or 0 upon success.
 */
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
			   unsigned long target_rate,
			   unsigned long parent_rate)
{
	int r = 0, carry = 0;

	/* Unscale m and round if necessary */
	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
		carry = 1;
	*m = (*m / DPLL_SCALE_FACTOR) + carry;

	/*
	 * The new rate must be <= the target rate to avoid programming
	 * a rate that is impossible for the hardware to handle
	 */
	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
	if (*new_rate > target_rate) {
		(*m)--;
		*new_rate = 0;
	}

	/* Guard against m underflow */
	if (*m < DPLL_MIN_MULTIPLIER) {
		*m = DPLL_MIN_MULTIPLIER;
		*new_rate = 0;
		r = DPLL_MULT_UNDERFLOW;
	}

	if (*new_rate == 0)
		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);

	return r;
}

/* Public functions */

void omap2_init_dpll_parent(struct clk *clk)
{
	u32 v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return;

	/* Return bypass rate if DPLL is bypassed */
	v = __raw_readl(dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	/* Reparent in case the dpll is in bypass */
	if (cpu_is_omap24xx()) {
		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
			clk_reparent(clk, dd->clk_bypass);
	} else if (cpu_is_omap34xx()) {
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
			clk_reparent(clk, dd->clk_bypass);
	} else if (cpu_is_omap44xx()) {
		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
			clk_reparent(clk, dd->clk_bypass);
	}
	return;
}

/**
 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
 * @clk: struct clk * of a DPLL
 *
 * DPLLs can be locked or bypassed - basically, enabled or disabled.
 * When locked, the DPLL output depends on the M and N values.  When
 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
 * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
 * if the clock @clk is not a DPLL.
 */
u32 omap2_get_dpll_rate(struct clk *clk)
{
	long long dpll_clk;
	u32 dpll_mult, dpll_div, v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return 0;

	/* Return bypass rate if DPLL is bypassed */
	v = __raw_readl(dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	if (cpu_is_omap24xx()) {
		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
			return dd->clk_bypass->rate;
	} else if (cpu_is_omap34xx()) {
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
			return dd->clk_bypass->rate;
	} else if (cpu_is_omap44xx()) {
		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
			return dd->clk_bypass->rate;
	}

	v = __raw_readl(dd->mult_div1_reg);
	dpll_mult = v & dd->mult_mask;
	dpll_mult >>= __ffs(dd->mult_mask);
	dpll_div = v & dd->div1_mask;
	dpll_div >>= __ffs(dd->div1_mask);

	dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
	do_div(dpll_clk, dpll_div + 1);

	return dpll_clk;
}

/* DPLL rate rounding code */

/**
 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
 * @clk: struct clk * of the DPLL
 * @tolerance: maximum rate error tolerance
 *
 * Set the maximum DPLL rate error tolerance for the rate rounding
 * algorithm.  The rate tolerance is an attempt to balance DPLL power
 * saving (the least divider value "n") vs. rate fidelity (the least
 * difference between the desired DPLL target rate and the rounded
 * rate out of the algorithm).  So, increasing the tolerance is likely
 * to decrease DPLL power consumption and increase DPLL rate error.
 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
 * DPLL; or 0 upon success.
 */
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
{
	if (!clk || !clk->dpll_data)
		return -EINVAL;

	clk->dpll_data->rate_tolerance = tolerance;

	return 0;
}

/**
 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
 * @clk: struct clk * for a DPLL
 * @target_rate: desired DPLL clock rate
 *
 * Given a DPLL, a desired target rate, and a rate tolerance, round
 * the target rate to a possible, programmable rate for this DPLL.
 * Rate tolerance is assumed to be set by the caller before this
 * function is called.  Attempts to select the minimum possible n
 * within the tolerance to reduce power consumption.  Stores the
 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
 * will not need to call this (expensive) function again.  Returns ~0
 * if the target rate cannot be rounded, either because the rate is
 * too low or because the rate tolerance is set too tightly; or the
 * rounded rate upon success.
 */
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
{
	int m, n, r, e, scaled_max_m;
	unsigned long scaled_rt_rp, new_rate;
	int min_e = -1, min_e_m = -1, min_e_n = -1;
	struct dpll_data *dd;

	if (!clk || !clk->dpll_data)
		return ~0;

	dd = clk->dpll_data;

	pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
		 "%ld\n", clk->name, target_rate);

	scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;

	dd->last_rounded_rate = 0;

	for (n = dd->min_divider; n <= dd->max_divider; n++) {

		/* Is the (input clk, divider) pair valid for the DPLL? */
		r = _dpll_test_fint(clk, n);
		if (r == DPLL_FINT_UNDERFLOW)
			break;
		else if (r == DPLL_FINT_INVALID)
			continue;

		/* Compute the scaled DPLL multiplier, based on the divider */
		m = scaled_rt_rp * n;

		/*
		 * Since we're counting n up, a m overflow means we
		 * can bail out completely (since as n increases in
		 * the next iteration, there's no way that m can
		 * increase beyond the current m)
		 */
		if (m > scaled_max_m)
			break;

		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
				    dd->clk_ref->rate);

		/* m can't be set low enough for this n - try with a larger n */
		if (r == DPLL_MULT_UNDERFLOW)
			continue;

		e = target_rate - new_rate;
		pr_debug("clock: n = %d: m = %d: rate error is %d "
			 "(new_rate = %ld)\n", n, m, e, new_rate);

		if (min_e == -1 ||
		    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
			min_e = e;
			min_e_m = m;
			min_e_n = n;

			pr_debug("clock: found new least error %d\n", min_e);

			/* We found good settings -- bail out now */
			if (min_e <= dd->rate_tolerance)
				break;
		}
	}

	if (min_e < 0) {
		pr_debug("clock: error: target rate or tolerance too low\n");
		return ~0;
	}

	dd->last_rounded_m = min_e_m;
	dd->last_rounded_n = min_e_n;
	dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
						       min_e_m,  min_e_n);

	pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
		 min_e, min_e_m, min_e_n);
	pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
		 dd->last_rounded_rate, target_rate);

	return dd->last_rounded_rate;
}
Commit	Line	Data
0b96af68 PW	1	/*
	2	* OMAP2/3/4 DPLL clock functions
	3	*
	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2010 Nokia Corporation
	6	*
	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15	#undef DEBUG
	16
	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
	21
	22	#include <asm/div64.h>
	23
	24	#include <plat/clock.h>
	25
	26	#include "clock.h"
0b96af68 PW	27	#include "cm-regbits-24xx.h"
	28	#include "cm-regbits-34xx.h"
	29
	30	/* DPLL rate rounding: minimum DPLL multiplier, divider values */
93340a22	31	#define DPLL_MIN_MULTIPLIER 2
0b96af68 PW	32	#define DPLL_MIN_DIVIDER 1
	33
	34	/* Possible error results from _dpll_test_mult */
	35	#define DPLL_MULT_UNDERFLOW -1
	36
	37	/*
	38	* Scale factor to mitigate roundoff errors in DPLL rate rounding.
	39	* The higher the scale factor, the greater the risk of arithmetic overflow,
	40	* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
	41	* must be a power of DPLL_SCALE_BASE.
	42	*/
	43	#define DPLL_SCALE_FACTOR 64
	44	#define DPLL_SCALE_BASE 2
	45	#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
	46	(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
	47
	48	/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
	49	#define DPLL_FINT_BAND1_MIN 750000
	50	#define DPLL_FINT_BAND1_MAX 2100000
	51	#define DPLL_FINT_BAND2_MIN 7500000
	52	#define DPLL_FINT_BAND2_MAX 21000000
	53
	54	/* _dpll_test_fint() return codes */
	55	#define DPLL_FINT_UNDERFLOW -1
	56	#define DPLL_FINT_INVALID -2
	57
	58	/* Private functions */
	59
	60	/*
	61	* _dpll_test_fint - test whether an Fint value is valid for the DPLL
	62	* @clk: DPLL struct clk to test
	63	* @n: divider value (N) to test
	64	*
	65	* Tests whether a particular divider @n will result in a valid DPLL
	66	* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
	67	* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
	68	* (assuming that it is counting N upwards), or -2 if the enclosing loop
	69	* should skip to the next iteration (again assuming N is increasing).
	70	*/
	71	static int _dpll_test_fint(struct clk *clk, u8 n)
	72	{
	73	struct dpll_data *dd;
	74	long fint;
	75	int ret = 0;
	76
	77	dd = clk->dpll_data;
	78
	79	/* DPLL divider must result in a valid jitter correction val */
ea68c00e	80	fint = clk->parent->rate / n;
0b96af68 PW	81	if (fint < DPLL_FINT_BAND1_MIN) {
	82
	83	pr_debug("rejecting n=%d due to Fint failure, "
	84	"lowering max_divider\n", n);
	85	dd->max_divider = n;
	86	ret = DPLL_FINT_UNDERFLOW;
	87
	88	} else if (fint > DPLL_FINT_BAND1_MAX &&
	89	fint < DPLL_FINT_BAND2_MIN) {
	90
	91	pr_debug("rejecting n=%d due to Fint failure\n", n);
	92	ret = DPLL_FINT_INVALID;
	93
	94	} else if (fint > DPLL_FINT_BAND2_MAX) {
	95
	96	pr_debug("rejecting n=%d due to Fint failure, "
	97	"boosting min_divider\n", n);
	98	dd->min_divider = n;
	99	ret = DPLL_FINT_INVALID;
	100
	101	}
	102
	103	return ret;
	104	}
	105
	106	static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
	107	unsigned int m, unsigned int n)
	108	{
	109	unsigned long long num;
	110
	111	num = (unsigned long long)parent_rate * m;
	112	do_div(num, n);
	113	return num;
	114	}
	115
	116	/*
	117	* _dpll_test_mult - test a DPLL multiplier value
	118	* @m: pointer to the DPLL m (multiplier) value under test
	119	* @n: current DPLL n (divider) value under test
	120	* @new_rate: pointer to storage for the resulting rounded rate
	121	* @target_rate: the desired DPLL rate
	122	* @parent_rate: the DPLL's parent clock rate
	123	*
	124	* This code tests a DPLL multiplier value, ensuring that the
	125	* resulting rate will not be higher than the target_rate, and that
	126	* the multiplier value itself is valid for the DPLL. Initially, the
	127	* integer pointed to by the m argument should be prescaled by
	128	* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
	129	* a non-scaled m upon return. This non-scaled m will result in a
	130	* new_rate as close as possible to target_rate (but not greater than
	131	* target_rate) given the current (parent_rate, n, prescaled m)
	132	* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
	133	* non-scaled m attempted to underflow, which can allow the calling
	134	* function to bail out early; or 0 upon success.
	135	*/
	136	static int _dpll_test_mult(int m, int n, unsigned long new_rate,
	137	unsigned long target_rate,
	138	unsigned long parent_rate)
	139	{
	140	int r = 0, carry = 0;
	141
	142	/* Unscale m and round if necessary */
	143	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
	144	carry = 1;
145	m = (m / DPLL_SCALE_FACTOR) + carry;
146
147	/*
148	* The new rate must be <= the target rate to avoid programming
149	* a rate that is impossible for the hardware to handle
150	*/
151	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
152	if (*new_rate > target_rate) {
153	(*m)--;
154	*new_rate = 0;
155	}
156
157	/* Guard against m underflow */
158	if (*m < DPLL_MIN_MULTIPLIER) {
159	*m = DPLL_MIN_MULTIPLIER;
160	*new_rate = 0;
161	r = DPLL_MULT_UNDERFLOW;
162	}
163
164	if (*new_rate == 0)
165	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
166
167	return r;
168	}
169
170	/* Public functions */
171
172	void omap2_init_dpll_parent(struct clk *clk)
173	{
174	u32 v;
175	struct dpll_data *dd;
176
177	dd = clk->dpll_data;
178	if (!dd)
179	return;
180
181	/* Return bypass rate if DPLL is bypassed */
182	v = __raw_readl(dd->control_reg);
183	v &= dd->enable_mask;
184	v >>= __ffs(dd->enable_mask);
185
186	/* Reparent in case the dpll is in bypass */
187	if (cpu_is_omap24xx()) {
188	if (v == OMAP2XXX_EN_DPLL_LPBYPASS \|\|
189	v == OMAP2XXX_EN_DPLL_FRBYPASS)
190	clk_reparent(clk, dd->clk_bypass);
191	} else if (cpu_is_omap34xx()) {
192	if (v == OMAP3XXX_EN_DPLL_LPBYPASS \|\|
193	v == OMAP3XXX_EN_DPLL_FRBYPASS)
194	clk_reparent(clk, dd->clk_bypass);
195	} else if (cpu_is_omap44xx()) {
196	if (v == OMAP4XXX_EN_DPLL_LPBYPASS \|\|
197	v == OMAP4XXX_EN_DPLL_FRBYPASS \|\|
198	v == OMAP4XXX_EN_DPLL_MNBYPASS)
199	clk_reparent(clk, dd->clk_bypass);
200	}
201	return;
202	}
203
204	/**
205	* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
206	* @clk: struct clk * of a DPLL
207	*
208	* DPLLs can be locked or bypassed - basically, enabled or disabled.
209	* When locked, the DPLL output depends on the M and N values. When
210	* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
211	* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
212	* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
213	* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
214	* Returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is
215	* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
216	* if the clock @clk is not a DPLL.
217	*/
218	u32 omap2_get_dpll_rate(struct clk *clk)
219	{
220	long long dpll_clk;
221	u32 dpll_mult, dpll_div, v;
222	struct dpll_data *dd;
223
224	dd = clk->dpll_data;
225	if (!dd)
226	return 0;
227
228	/* Return bypass rate if DPLL is bypassed */
229	v = __raw_readl(dd->control_reg);
230	v &= dd->enable_mask;
231	v >>= __ffs(dd->enable_mask);
232
233	if (cpu_is_omap24xx()) {
234	if (v == OMAP2XXX_EN_DPLL_LPBYPASS \|\|
235	v == OMAP2XXX_EN_DPLL_FRBYPASS)
236	return dd->clk_bypass->rate;
237	} else if (cpu_is_omap34xx()) {
238	if (v == OMAP3XXX_EN_DPLL_LPBYPASS \|\|
239	v == OMAP3XXX_EN_DPLL_FRBYPASS)
240	return dd->clk_bypass->rate;
241	} else if (cpu_is_omap44xx()) {
242	if (v == OMAP4XXX_EN_DPLL_LPBYPASS \|\|
243	v == OMAP4XXX_EN_DPLL_FRBYPASS \|\|
244	v == OMAP4XXX_EN_DPLL_MNBYPASS)
245	return dd->clk_bypass->rate;
246	}
247
248	v = __raw_readl(dd->mult_div1_reg);
249	dpll_mult = v & dd->mult_mask;
250	dpll_mult >>= __ffs(dd->mult_mask);
251	dpll_div = v & dd->div1_mask;
252	dpll_div >>= __ffs(dd->div1_mask);
253
254	dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
255	do_div(dpll_clk, dpll_div + 1);
256
257	return dpll_clk;
258	}
259
260	/* DPLL rate rounding code */
261
262	/**
263	* omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
264	* @clk: struct clk * of the DPLL
265	* @tolerance: maximum rate error tolerance
266	*
267	* Set the maximum DPLL rate error tolerance for the rate rounding
268	* algorithm. The rate tolerance is an attempt to balance DPLL power
269	* saving (the least divider value "n") vs. rate fidelity (the least
270	* difference between the desired DPLL target rate and the rounded
271	* rate out of the algorithm). So, increasing the tolerance is likely
272	* to decrease DPLL power consumption and increase DPLL rate error.
273	* Returns -EINVAL if provided a null clock ptr or a clk that is not a
274	* DPLL; or 0 upon success.
275	*/
276	int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
277	{
278	if (!clk \|\| !clk->dpll_data)
279	return -EINVAL;
280
281	clk->dpll_data->rate_tolerance = tolerance;
282
283	return 0;
284	}
285
286	/**
287	* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
288	* @clk: struct clk * for a DPLL
289	* @target_rate: desired DPLL clock rate
290	*
291	* Given a DPLL, a desired target rate, and a rate tolerance, round
292	* the target rate to a possible, programmable rate for this DPLL.
293	* Rate tolerance is assumed to be set by the caller before this
294	* function is called. Attempts to select the minimum possible n
295	* within the tolerance to reduce power consumption. Stores the
296	* computed (m, n) in the DPLL's dpll_data structure so set_rate()
297	* will not need to call this (expensive) function again. Returns ~0
298	* if the target rate cannot be rounded, either because the rate is
299	* too low or because the rate tolerance is set too tightly; or the
300	* rounded rate upon success.
301	*/
302	long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
303	{
304	int m, n, r, e, scaled_max_m;
305	unsigned long scaled_rt_rp, new_rate;
306	int min_e = -1, min_e_m = -1, min_e_n = -1;
307	struct dpll_data *dd;
308
309	if (!clk \|\| !clk->dpll_data)
310	return ~0;
311
312	dd = clk->dpll_data;
313
314	pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
315	"%ld\n", clk->name, target_rate);
316
317	scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
318	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
319
320	dd->last_rounded_rate = 0;
321
322	for (n = dd->min_divider; n <= dd->max_divider; n++) {
323
324	/* Is the (input clk, divider) pair valid for the DPLL? */
325	r = _dpll_test_fint(clk, n);
326	if (r == DPLL_FINT_UNDERFLOW)
327	break;
328	else if (r == DPLL_FINT_INVALID)
329	continue;
330
331	/* Compute the scaled DPLL multiplier, based on the divider */
332	m = scaled_rt_rp * n;
333
334	/*
335	* Since we're counting n up, a m overflow means we
336	* can bail out completely (since as n increases in
337	* the next iteration, there's no way that m can
338	* increase beyond the current m)
339	*/
340	if (m > scaled_max_m)
341	break;
342
343	r = _dpll_test_mult(&m, n, &new_rate, target_rate,
344	dd->clk_ref->rate);
345
346	/* m can't be set low enough for this n - try with a larger n */
347	if (r == DPLL_MULT_UNDERFLOW)
348	continue;
349
350	e = target_rate - new_rate;
351	pr_debug("clock: n = %d: m = %d: rate error is %d "
352	"(new_rate = %ld)\n", n, m, e, new_rate);
353
354	if (min_e == -1 \|\|
355	min_e >= (int)(abs(e) - dd->rate_tolerance)) {
356	min_e = e;
357	min_e_m = m;
358	min_e_n = n;
359
360	pr_debug("clock: found new least error %d\n", min_e);
361
362	/* We found good settings -- bail out now */
363	if (min_e <= dd->rate_tolerance)
364	break;
365	}
366	}
367
368	if (min_e < 0) {
369	pr_debug("clock: error: target rate or tolerance too low\n");
370	return ~0;
371	}
372
373	dd->last_rounded_m = min_e_m;
374	dd->last_rounded_n = min_e_n;
375	dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
376	min_e_m, min_e_n);
377
378	pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
379	min_e, min_e_m, min_e_n);
380	pr_debug("clock: final rate: %ld (target rate: %ld)\n",
381	dd->last_rounded_rate, target_rate);
382
383	return dd->last_rounded_rate;
384	}
385