[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-omap2 / clkt_dpll.c

/*
 * OMAP2/3/4 DPLL clock functions
 *
 * Copyright (C) 2005-2008 Texas Instruments, Inc.
 * Copyright (C) 2004-2010 Nokia Corporation
 *
 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk-provider.h>
#include <linux/io.h>

#include <asm/div64.h>

#include "soc.h"
#include "clock.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"

/* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER		2
#define DPLL_MIN_DIVIDER		1

/* Possible error results from _dpll_test_mult */
#define DPLL_MULT_UNDERFLOW		-1

/*
 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
 * The higher the scale factor, the greater the risk of arithmetic overflow,
 * but the closer the rounded rate to the target rate.  DPLL_SCALE_FACTOR
 * must be a power of DPLL_SCALE_BASE.
 */
#define DPLL_SCALE_FACTOR		64
#define DPLL_SCALE_BASE			2
#define DPLL_ROUNDING_VAL		((DPLL_SCALE_BASE / 2) * \
					 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))

/*
 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
 * From device data manual section 4.3 "DPLL and DLL Specifications".
 */
#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN	500000
#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX	2500000

/* _dpll_test_fint() return codes */
#define DPLL_FINT_UNDERFLOW		-1
#define DPLL_FINT_INVALID		-2

/* Private functions */

/*
 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
 * @clk: DPLL struct clk to test
 * @n: divider value (N) to test
 *
 * Tests whether a particular divider @n will result in a valid DPLL
 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
 * Correction".  Returns 0 if OK, -1 if the enclosing loop can terminate
 * (assuming that it is counting N upwards), or -2 if the enclosing loop
 * should skip to the next iteration (again assuming N is increasing).
 */
static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
{
	struct dpll_data *dd;
	long fint, fint_min, fint_max;
	int ret = 0;

	dd = clk->dpll_data;

	/* DPLL divider must result in a valid jitter correction val */
	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;

	if (dd->flags & DPLL_J_TYPE) {
		fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
		fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	} else {
		fint_min = ti_clk_features.fint_min;
		fint_max = ti_clk_features.fint_max;
	}

	if (!fint_min || !fint_max) {
		WARN(1, "No fint limits available!\n");
		return DPLL_FINT_INVALID;
	}

	if (fint < ti_clk_features.fint_min) {
		pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
			 n);
		dd->max_divider = n;
		ret = DPLL_FINT_UNDERFLOW;
	} else if (fint > ti_clk_features.fint_max) {
		pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
			 n);
		dd->min_divider = n;
		ret = DPLL_FINT_INVALID;
	} else if (fint > ti_clk_features.fint_band1_max &&
		   fint < ti_clk_features.fint_band2_min) {
		pr_debug("rejecting n=%d due to Fint failure\n", n);
		ret = DPLL_FINT_INVALID;
	}

	return ret;
}

static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
					    unsigned int m, unsigned int n)
{
	unsigned long long num;

	num = (unsigned long long)parent_rate * m;
	do_div(num, n);
	return num;
}

/*
 * _dpll_test_mult - test a DPLL multiplier value
 * @m: pointer to the DPLL m (multiplier) value under test
 * @n: current DPLL n (divider) value under test
 * @new_rate: pointer to storage for the resulting rounded rate
 * @target_rate: the desired DPLL rate
 * @parent_rate: the DPLL's parent clock rate
 *
 * This code tests a DPLL multiplier value, ensuring that the
 * resulting rate will not be higher than the target_rate, and that
 * the multiplier value itself is valid for the DPLL.  Initially, the
 * integer pointed to by the m argument should be prescaled by
 * multiplying by DPLL_SCALE_FACTOR.  The code will replace this with
 * a non-scaled m upon return.  This non-scaled m will result in a
 * new_rate as close as possible to target_rate (but not greater than
 * target_rate) given the current (parent_rate, n, prescaled m)
 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
 * non-scaled m attempted to underflow, which can allow the calling
 * function to bail out early; or 0 upon success.
 */
static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
			   unsigned long target_rate,
			   unsigned long parent_rate)
{
	int r = 0, carry = 0;

	/* Unscale m and round if necessary */
	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
		carry = 1;
	*m = (*m / DPLL_SCALE_FACTOR) + carry;

	/*
	 * The new rate must be <= the target rate to avoid programming
	 * a rate that is impossible for the hardware to handle
	 */
	*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
	if (*new_rate > target_rate) {
		(*m)--;
		*new_rate = 0;
	}

	/* Guard against m underflow */
	if (*m < DPLL_MIN_MULTIPLIER) {
		*m = DPLL_MIN_MULTIPLIER;
		*new_rate = 0;
		r = DPLL_MULT_UNDERFLOW;
	}

	if (*new_rate == 0)
		*new_rate = _dpll_compute_new_rate(parent_rate, *m, n);

	return r;
}

/* Public functions */
u8 omap2_init_dpll_parent(struct clk_hw *hw)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	u32 v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return -EINVAL;

	v = omap2_clk_readl(clk, dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	/* Reparent the struct clk in case the dpll is in bypass */
	if (cpu_is_omap24xx()) {
		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
			return 1;
	} else if (cpu_is_omap34xx()) {
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
			return 1;
	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
			return 1;
	}
	return 0;
}

/**
 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
 * @clk: struct clk * of a DPLL
 *
 * DPLLs can be locked or bypassed - basically, enabled or disabled.
 * When locked, the DPLL output depends on the M and N values.  When
 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
 * or sys_clk.  Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is
 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
 * if the clock @clk is not a DPLL.
 */
unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
{
	long long dpll_clk;
	u32 dpll_mult, dpll_div, v;
	struct dpll_data *dd;

	dd = clk->dpll_data;
	if (!dd)
		return 0;

	/* Return bypass rate if DPLL is bypassed */
	v = omap2_clk_readl(clk, dd->control_reg);
	v &= dd->enable_mask;
	v >>= __ffs(dd->enable_mask);

	if (cpu_is_omap24xx()) {
		if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP2XXX_EN_DPLL_FRBYPASS)
			return __clk_get_rate(dd->clk_bypass);
	} else if (cpu_is_omap34xx()) {
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP3XXX_EN_DPLL_FRBYPASS)
			return __clk_get_rate(dd->clk_bypass);
	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
			return __clk_get_rate(dd->clk_bypass);
	}

	v = omap2_clk_readl(clk, dd->mult_div1_reg);
	dpll_mult = v & dd->mult_mask;
	dpll_mult >>= __ffs(dd->mult_mask);
	dpll_div = v & dd->div1_mask;
	dpll_div >>= __ffs(dd->div1_mask);

	dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
	do_div(dpll_clk, dpll_div + 1);

	return dpll_clk;
}

/* DPLL rate rounding code */

/**
 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
 * @clk: struct clk * for a DPLL
 * @target_rate: desired DPLL clock rate
 *
 * Given a DPLL and a desired target rate, round the target rate to a
 * possible, programmable rate for this DPLL.  Attempts to select the
 * minimum possible n.  Stores the computed (m, n) in the DPLL's
 * dpll_data structure so set_rate() will not need to call this
 * (expensive) function again.  Returns ~0 if the target rate cannot
 * be rounded, or the rounded rate upon success.
 */
long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
		unsigned long *parent_rate)
{
	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
	int m, n, r, scaled_max_m;
	unsigned long scaled_rt_rp;
	unsigned long new_rate = 0;
	struct dpll_data *dd;
	unsigned long ref_rate;
	const char *clk_name;

	if (!clk || !clk->dpll_data)
		return ~0;

	dd = clk->dpll_data;

	ref_rate = __clk_get_rate(dd->clk_ref);
	clk_name = __clk_get_name(hw->clk);
	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
		 clk_name, target_rate);

	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;

	dd->last_rounded_rate = 0;

	for (n = dd->min_divider; n <= dd->max_divider; n++) {

		/* Is the (input clk, divider) pair valid for the DPLL? */
		r = _dpll_test_fint(clk, n);
		if (r == DPLL_FINT_UNDERFLOW)
			break;
		else if (r == DPLL_FINT_INVALID)
			continue;

		/* Compute the scaled DPLL multiplier, based on the divider */
		m = scaled_rt_rp * n;

		/*
		 * Since we're counting n up, a m overflow means we
		 * can bail out completely (since as n increases in
		 * the next iteration, there's no way that m can
		 * increase beyond the current m)
		 */
		if (m > scaled_max_m)
			break;

		r = _dpll_test_mult(&m, n, &new_rate, target_rate,
				    ref_rate);

		/* m can't be set low enough for this n - try with a larger n */
		if (r == DPLL_MULT_UNDERFLOW)
			continue;

		pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
			 clk_name, m, n, new_rate);

		if (target_rate == new_rate) {
			dd->last_rounded_m = m;
			dd->last_rounded_n = n;
			dd->last_rounded_rate = target_rate;
			break;
		}
	}

	if (target_rate != new_rate) {
		pr_debug("clock: %s: cannot round to rate %lu\n",
			 clk_name, target_rate);
		return ~0;
	}

	return target_rate;
}
Commit	Line	Data
0b96af68 PW	1	/*
	2	* OMAP2/3/4 DPLL clock functions
	3	*
	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
	5	* Copyright (C) 2004-2010 Nokia Corporation
	6	*
	7	* Contacts:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15	#undef DEBUG
	16
	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
32cc0021	19	#include <linux/clk-provider.h>
0b96af68 PW	20	#include <linux/io.h>
	21
	22	#include <asm/div64.h>
	23
dbc04161	24	#include "soc.h"
0b96af68	25	#include "clock.h"
0b96af68 PW	26	#include "cm-regbits-24xx.h"
	27	#include "cm-regbits-34xx.h"
	28
	29	/* DPLL rate rounding: minimum DPLL multiplier, divider values */
93340a22	30	#define DPLL_MIN_MULTIPLIER 2
0b96af68 PW	31	#define DPLL_MIN_DIVIDER 1
	32
	33	/* Possible error results from _dpll_test_mult */
	34	#define DPLL_MULT_UNDERFLOW -1
	35
	36	/*
	37	* Scale factor to mitigate roundoff errors in DPLL rate rounding.
	38	* The higher the scale factor, the greater the risk of arithmetic overflow,
	39	* but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
	40	* must be a power of DPLL_SCALE_BASE.
	41	*/
	42	#define DPLL_SCALE_FACTOR 64
	43	#define DPLL_SCALE_BASE 2
	44	#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
	45	(DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
	46
1194d7b8 JH	47	/*
	48	* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
	49	* From device data manual section 4.3 "DPLL and DLL Specifications".
	50	*/
	51	#define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000
	52	#define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000
0b96af68 PW	53
	54	/* _dpll_test_fint() return codes */
	55	#define DPLL_FINT_UNDERFLOW -1
	56	#define DPLL_FINT_INVALID -2
	57
	58	/* Private functions */
	59
	60	/*
	61	* _dpll_test_fint - test whether an Fint value is valid for the DPLL
	62	* @clk: DPLL struct clk to test
	63	* @n: divider value (N) to test
	64	*
	65	* Tests whether a particular divider @n will result in a valid DPLL
	66	* internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
	67	* Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
	68	* (assuming that it is counting N upwards), or -2 if the enclosing loop
	69	* should skip to the next iteration (again assuming N is increasing).
	70	*/
32cc0021	71	static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n)
0b96af68 PW	72	{
0b96af68 PW	73	struct dpll_data *dd;
1194d7b8	74	long fint, fint_min, fint_max;
0b96af68 PW	75	int ret = 0;
	76
	77	dd = clk->dpll_data;
	78
	79	/* DPLL divider must result in a valid jitter correction val */
32cc0021	80	fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n;
0b96af68	81
a24886e2	82	if (dd->flags & DPLL_J_TYPE) {
1194d7b8 JH	83	fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN;
	84	fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX;
	85	} else {
a24886e2 TK	86	fint_min = ti_clk_features.fint_min;
	87	fint_max = ti_clk_features.fint_max;
	88	}
	89
	90	if (!fint_min \|\| !fint_max) {
	91	WARN(1, "No fint limits available!\n");
	92	return DPLL_FINT_INVALID;
1194d7b8 JH	93	}
1194d7b8 JH	94
a24886e2	95	if (fint < ti_clk_features.fint_min) {
7852ec05 PW	96	pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
7852ec05 PW	97	n);
0b96af68 PW	98	dd->max_divider = n;
0b96af68 PW	99	ret = DPLL_FINT_UNDERFLOW;
a24886e2	100	} else if (fint > ti_clk_features.fint_max) {
7852ec05 PW	101	pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
7852ec05 PW	102	n);
0b96af68 PW	103	dd->min_divider = n;
0b96af68 PW	104	ret = DPLL_FINT_INVALID;
a24886e2 TK	105	} else if (fint > ti_clk_features.fint_band1_max &&
a24886e2 TK	106	fint < ti_clk_features.fint_band2_min) {
1194d7b8 JH	107	pr_debug("rejecting n=%d due to Fint failure\n", n);
1194d7b8 JH	108	ret = DPLL_FINT_INVALID;
0b96af68 PW	109	}
	110
	111	return ret;
	112	}
	113
	114	static unsigned long _dpll_compute_new_rate(unsigned long parent_rate,
	115	unsigned int m, unsigned int n)
	116	{
	117	unsigned long long num;
	118
	119	num = (unsigned long long)parent_rate * m;
	120	do_div(num, n);
	121	return num;
	122	}
	123
	124	/*
	125	* _dpll_test_mult - test a DPLL multiplier value
	126	* @m: pointer to the DPLL m (multiplier) value under test
	127	* @n: current DPLL n (divider) value under test
	128	* @new_rate: pointer to storage for the resulting rounded rate
	129	* @target_rate: the desired DPLL rate
	130	* @parent_rate: the DPLL's parent clock rate
	131	*
	132	* This code tests a DPLL multiplier value, ensuring that the
	133	* resulting rate will not be higher than the target_rate, and that
	134	* the multiplier value itself is valid for the DPLL. Initially, the
	135	* integer pointed to by the m argument should be prescaled by
	136	* multiplying by DPLL_SCALE_FACTOR. The code will replace this with
	137	* a non-scaled m upon return. This non-scaled m will result in a
	138	* new_rate as close as possible to target_rate (but not greater than
	139	* target_rate) given the current (parent_rate, n, prescaled m)
	140	* triple. Returns DPLL_MULT_UNDERFLOW in the event that the
	141	* non-scaled m attempted to underflow, which can allow the calling
	142	* function to bail out early; or 0 upon success.
	143	*/
	144	static int _dpll_test_mult(int m, int n, unsigned long new_rate,
	145	unsigned long target_rate,
	146	unsigned long parent_rate)
	147	{
	148	int r = 0, carry = 0;
	149
	150	/* Unscale m and round if necessary */
	151	if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
	152	carry = 1;
	153	m = (m / DPLL_SCALE_FACTOR) + carry;
	154
	155	/*
	156	* The new rate must be <= the target rate to avoid programming
	157	* a rate that is impossible for the hardware to handle
	158	*/
	159	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
	160	if (*new_rate > target_rate) {
	161	(*m)--;
	162	*new_rate = 0;
	163	}
	164
	165	/* Guard against m underflow */
	166	if (*m < DPLL_MIN_MULTIPLIER) {
	167	*m = DPLL_MIN_MULTIPLIER;
	168	*new_rate = 0;
	169	r = DPLL_MULT_UNDERFLOW;
	170	}
	171
	172	if (*new_rate == 0)
173	new_rate = _dpll_compute_new_rate(parent_rate, m, n);
174
175	return r;
176	}
177
178	/* Public functions */
32cc0021 MT	179	u8 omap2_init_dpll_parent(struct clk_hw *hw)
	180	{
	181	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0b96af68 PW	182	u32 v;
	183	struct dpll_data *dd;
	184
	185	dd = clk->dpll_data;
	186	if (!dd)
32cc0021	187	return -EINVAL;
0b96af68	188
519ab8b2	189	v = omap2_clk_readl(clk, dd->control_reg);
0b96af68 PW	190	v &= dd->enable_mask;
	191	v >>= __ffs(dd->enable_mask);
	192
241d3a8d	193	/* Reparent the struct clk in case the dpll is in bypass */
0b96af68 PW	194	if (cpu_is_omap24xx()) {
	195	if (v == OMAP2XXX_EN_DPLL_LPBYPASS \|\|
	196	v == OMAP2XXX_EN_DPLL_FRBYPASS)
32cc0021	197	return 1;
0b96af68 PW	198	} else if (cpu_is_omap34xx()) {
	199	if (v == OMAP3XXX_EN_DPLL_LPBYPASS \|\|
	200	v == OMAP3XXX_EN_DPLL_FRBYPASS)
32cc0021	201	return 1;
8e4cb9aa	202	} else if (soc_is_am33xx() \|\| cpu_is_omap44xx() \|\| soc_is_am43xx()) {
0b96af68 PW	203	if (v == OMAP4XXX_EN_DPLL_LPBYPASS \|\|
	204	v == OMAP4XXX_EN_DPLL_FRBYPASS \|\|
	205	v == OMAP4XXX_EN_DPLL_MNBYPASS)
32cc0021	206	return 1;
0b96af68	207	}
32cc0021	208	return 0;
0b96af68 PW	209	}
	210
	211	/**
	212	* omap2_get_dpll_rate - returns the current DPLL CLKOUT rate
	213	* @clk: struct clk * of a DPLL
	214	*
	215	* DPLLs can be locked or bypassed - basically, enabled or disabled.
	216	* When locked, the DPLL output depends on the M and N values. When
	217	* bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock
	218	* or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and
	219	* 2 are bypassed with dpll1_fclk and dpll2_fclk respectively
	220	* (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk.
	221	* Returns the current DPLL CLKOUT rate (not CLKOUTX2) if the DPLL is
	222	* locked, or the appropriate bypass rate if the DPLL is bypassed, or 0
	223	* if the clock @clk is not a DPLL.
	224	*/
32cc0021	225	unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
0b96af68 PW	226	{
	227	long long dpll_clk;
	228	u32 dpll_mult, dpll_div, v;
	229	struct dpll_data *dd;
	230
	231	dd = clk->dpll_data;
	232	if (!dd)
	233	return 0;
	234
	235	/* Return bypass rate if DPLL is bypassed */
519ab8b2	236	v = omap2_clk_readl(clk, dd->control_reg);
0b96af68 PW	237	v &= dd->enable_mask;
	238	v >>= __ffs(dd->enable_mask);
	239
	240	if (cpu_is_omap24xx()) {
	241	if (v == OMAP2XXX_EN_DPLL_LPBYPASS \|\|
	242	v == OMAP2XXX_EN_DPLL_FRBYPASS)
5dcc3b97	243	return __clk_get_rate(dd->clk_bypass);
0b96af68 PW	244	} else if (cpu_is_omap34xx()) {
	245	if (v == OMAP3XXX_EN_DPLL_LPBYPASS \|\|
	246	v == OMAP3XXX_EN_DPLL_FRBYPASS)
5dcc3b97	247	return __clk_get_rate(dd->clk_bypass);
8e4cb9aa	248	} else if (soc_is_am33xx() \|\| cpu_is_omap44xx() \|\| soc_is_am43xx()) {
0b96af68 PW	249	if (v == OMAP4XXX_EN_DPLL_LPBYPASS \|\|
	250	v == OMAP4XXX_EN_DPLL_FRBYPASS \|\|
	251	v == OMAP4XXX_EN_DPLL_MNBYPASS)
5dcc3b97	252	return __clk_get_rate(dd->clk_bypass);
0b96af68 PW	253	}
0b96af68 PW	254
519ab8b2	255	v = omap2_clk_readl(clk, dd->mult_div1_reg);
0b96af68 PW	256	dpll_mult = v & dd->mult_mask;
	257	dpll_mult >>= __ffs(dd->mult_mask);
	258	dpll_div = v & dd->div1_mask;
	259	dpll_div >>= __ffs(dd->div1_mask);
	260
5dcc3b97	261	dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
0b96af68 PW	262	do_div(dpll_clk, dpll_div + 1);
	263
	264	return dpll_clk;
	265	}
	266
	267	/* DPLL rate rounding code */
	268
0b96af68 PW	269	/**
	270	* omap2_dpll_round_rate - round a target rate for an OMAP DPLL
	271	* @clk: struct clk * for a DPLL
	272	* @target_rate: desired DPLL clock rate
	273	*
241d3a8d PW	274	* Given a DPLL and a desired target rate, round the target rate to a
	275	* possible, programmable rate for this DPLL. Attempts to select the
	276	* minimum possible n. Stores the computed (m, n) in the DPLL's
	277	* dpll_data structure so set_rate() will not need to call this
	278	* (expensive) function again. Returns ~0 if the target rate cannot
	279	* be rounded, or the rounded rate upon success.
0b96af68	280	*/
32cc0021 MT	281	long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
	282	unsigned long *parent_rate)
	283	{
	284	struct clk_hw_omap *clk = to_clk_hw_omap(hw);
241d3a8d PW	285	int m, n, r, scaled_max_m;
	286	unsigned long scaled_rt_rp;
	287	unsigned long new_rate = 0;
0b96af68	288	struct dpll_data *dd;
5dcc3b97 RN	289	unsigned long ref_rate;
5dcc3b97 RN	290	const char *clk_name;
0b96af68 PW	291
	292	if (!clk \|\| !clk->dpll_data)
	293	return ~0;
	294
	295	dd = clk->dpll_data;
	296
5dcc3b97	297	ref_rate = __clk_get_rate(dd->clk_ref);
32cc0021	298	clk_name = __clk_get_name(hw->clk);
0cc1d944	299	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",
5dcc3b97	300	clk_name, target_rate);
0b96af68	301
5dcc3b97	302	scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
0b96af68 PW	303	scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
	304
	305	dd->last_rounded_rate = 0;
	306
	307	for (n = dd->min_divider; n <= dd->max_divider; n++) {
	308
	309	/* Is the (input clk, divider) pair valid for the DPLL? */
	310	r = _dpll_test_fint(clk, n);
	311	if (r == DPLL_FINT_UNDERFLOW)
	312	break;
	313	else if (r == DPLL_FINT_INVALID)
	314	continue;
	315
	316	/* Compute the scaled DPLL multiplier, based on the divider */
	317	m = scaled_rt_rp * n;
	318
	319	/*
	320	* Since we're counting n up, a m overflow means we
	321	* can bail out completely (since as n increases in
	322	* the next iteration, there's no way that m can
	323	* increase beyond the current m)
	324	*/
	325	if (m > scaled_max_m)
	326	break;
	327
	328	r = _dpll_test_mult(&m, n, &new_rate, target_rate,
5dcc3b97	329	ref_rate);
0b96af68 PW	330
	331	/* m can't be set low enough for this n - try with a larger n */
	332	if (r == DPLL_MULT_UNDERFLOW)
	333	continue;
	334
0cc1d944	335	pr_debug("clock: %s: m = %d: n = %d: new_rate = %lu\n",
5dcc3b97	336	clk_name, m, n, new_rate);
0b96af68	337
241d3a8d PW	338	if (target_rate == new_rate) {
	339	dd->last_rounded_m = m;
	340	dd->last_rounded_n = n;
	341	dd->last_rounded_rate = target_rate;
	342	break;
0b96af68 PW	343	}
	344	}
	345
241d3a8d	346	if (target_rate != new_rate) {
0cc1d944	347	pr_debug("clock: %s: cannot round to rate %lu\n",
5dcc3b97	348	clk_name, target_rate);
0b96af68 PW	349	return ~0;
	350	}
	351
241d3a8d	352	return target_rate;
0b96af68 PW	353	}
0b96af68 PW	354