[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / clock.c

/*
 *  linux/arch/arm/mach-omap2/clock.c
 *
 *  Copyright (C) 2005-2008 Texas Instruments, Inc.
 *  Copyright (C) 2004-2010 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/of_address.h>
#include <asm/cpu.h>

#include <trace/events/power.h>

#include "soc.h"
#include "clockdomain.h"
#include "clock.h"
#include "cm.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
#include "common.h"

u16 cpu_mask;

/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
#define OMAP3430_DPLL_FINT_BAND1_MIN	750000
#define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
#define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
#define OMAP3430_DPLL_FINT_BAND2_MAX	21000000

/*
 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
 * From device data manual section 4.3 "DPLL and DLL Specifications".
 */
#define OMAP3PLUS_DPLL_FINT_MIN		32000
#define OMAP3PLUS_DPLL_FINT_MAX		52000000

struct ti_clk_ll_ops omap_clk_ll_ops = {
	.clkdm_clk_enable = clkdm_clk_enable,
	.clkdm_clk_disable = clkdm_clk_disable,
	.clkdm_lookup = clkdm_lookup,
	.cm_wait_module_ready = omap_cm_wait_module_ready,
	.cm_split_idlest_reg = cm_split_idlest_reg,
};

/**
 * omap2_clk_setup_ll_ops - setup clock driver low-level ops
 *
 * Sets up clock driver low-level platform ops. These are needed
 * for register accesses and various other misc platform operations.
 * Returns 0 on success, -EBUSY if low level ops have been registered
 * already.
 */
int __init omap2_clk_setup_ll_ops(void)
{
	return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
}

/*
 * OMAP2+ specific clock functions
 */

/**
 * ti_clk_init_features - init clock features struct for the SoC
 *
 * Initializes the clock features struct based on the SoC type.
 */
void __init ti_clk_init_features(void)
{
	struct ti_clk_features features = { 0 };
	/* Fint setup for DPLLs */
	if (cpu_is_omap3430()) {
		features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
		features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
		features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
		features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
	} else {
		features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
		features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
	}

	/* Bypass value setup for DPLLs */
	if (cpu_is_omap24xx()) {
		features.dpll_bypass_vals |=
			(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
			(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
	} else if (cpu_is_omap34xx()) {
		features.dpll_bypass_vals |=
			(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
			(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
		   soc_is_omap54xx() || soc_is_dra7xx()) {
		features.dpll_bypass_vals |=
			(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
	}

	/* Jitter correction only available on OMAP343X */
	if (cpu_is_omap343x())
		features.flags |= TI_CLK_DPLL_HAS_FREQSEL;

	/* Idlest value for interface clocks.
	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
	 * 34xx reverses this, just to keep us on our toes
	 * AM35xx uses both, depending on the module.
	 */
	if (cpu_is_omap24xx())
		features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
	else if (cpu_is_omap34xx())
		features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;

	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
	if (omap_rev() == OMAP3430_REV_ES1_0)
		features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;

	/* Errata I810 for omap5 / dra7 */
	if (soc_is_omap54xx() || soc_is_dra7xx())
		features.flags |= TI_CLK_ERRATA_I810;

	ti_clk_setup_features(&features);
}
Commit	Line	Data
543d9378 PW	1	/*
	2	* linux/arch/arm/mach-omap2/clock.c
	3	*
a16e9703	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
8c34974a	5	* Copyright (C) 2004-2010 Nokia Corporation
543d9378	6	*
a16e9703 TL	7	* Contacts:
a16e9703 TL	8	* Richard Woodruff <r-woodruff2@ti.com>
543d9378 PW	9	* Paul Walmsley
543d9378 PW	10	*
543d9378 PW	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15	#undef DEBUG
	16
543d9378	17	#include <linux/kernel.h>
1fe9be82	18	#include <linux/export.h>
543d9378 PW	19	#include <linux/list.h>
543d9378 PW	20	#include <linux/errno.h>
4d30e82c PW	21	#include <linux/err.h>
4d30e82c PW	22	#include <linux/delay.h>
f5b00f6f	23	#include <linux/clk.h>
32cc0021	24	#include <linux/clk-provider.h>
fced80c7	25	#include <linux/io.h>
fbd3bdb2	26	#include <linux/bitops.h>
9f029b15	27	#include <linux/of_address.h>
5e7c58dc	28	#include <asm/cpu.h>
dbc04161	29
dbc04161 TL	30	#include <trace/events/power.h>
	31
	32	#include "soc.h"
	33	#include "clockdomain.h"
543d9378	34	#include "clock.h"
c4ceedcb	35	#include "cm.h"
ff4ae5d9 PW	36	#include "cm2xxx.h"
ff4ae5d9 PW	37	#include "cm3xxx.h"
543d9378 PW	38	#include "cm-regbits-24xx.h"
543d9378 PW	39	#include "cm-regbits-34xx.h"
c4ceedcb PW	40	#include "common.h"
c4ceedcb PW	41
99541195	42	u16 cpu_mask;
543d9378	43
a24886e2 TK	44	/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
	45	#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
	46	#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
	47	#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
	48	#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
	49
	50	/*
	51	* DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
	52	* From device data manual section 4.3 "DPLL and DLL Specifications".
	53	*/
	54	#define OMAP3PLUS_DPLL_FINT_MIN 32000
	55	#define OMAP3PLUS_DPLL_FINT_MAX 52000000
	56
6c0afb50	57	struct ti_clk_ll_ops omap_clk_ll_ops = {
9a356d62 TK	58	.clkdm_clk_enable = clkdm_clk_enable,
9a356d62 TK	59	.clkdm_clk_disable = clkdm_clk_disable,
b6f27b2d	60	.clkdm_lookup = clkdm_lookup,
192383d8 TK	61	.cm_wait_module_ready = omap_cm_wait_module_ready,
192383d8 TK	62	.cm_split_idlest_reg = cm_split_idlest_reg,
9f029b15 TK	63	};
9f029b15 TK	64
e9e63088 TK	65	/**
	66	* omap2_clk_setup_ll_ops - setup clock driver low-level ops
	67	*
	68	* Sets up clock driver low-level platform ops. These are needed
	69	* for register accesses and various other misc platform operations.
	70	* Returns 0 on success, -EBUSY if low level ops have been registered
	71	* already.
	72	*/
	73	int __init omap2_clk_setup_ll_ops(void)
	74	{
	75	return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
	76	}
	77
30962d9d PW	78	/*
	79	* OMAP2+ specific clock functions
	80	*/
543d9378	81
8111e010 TK	82	/**
	83	* ti_clk_init_features - init clock features struct for the SoC
	84	*
	85	* Initializes the clock features struct based on the SoC type.
	86	*/
	87	void __init ti_clk_init_features(void)
	88	{
f3b19aa5	89	struct ti_clk_features features = { 0 };
a24886e2 TK	90	/* Fint setup for DPLLs */
a24886e2 TK	91	if (cpu_is_omap3430()) {
f3b19aa5 TK	92	features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
	93	features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
	94	features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
	95	features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
a24886e2	96	} else {
f3b19aa5 TK	97	features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
f3b19aa5 TK	98	features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
a24886e2	99	}
512d91cb TK	100
	101	/* Bypass value setup for DPLLs */
	102	if (cpu_is_omap24xx()) {
f3b19aa5	103	features.dpll_bypass_vals \|=
512d91cb TK	104	(1 << OMAP2XXX_EN_DPLL_LPBYPASS) \|
	105	(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
	106	} else if (cpu_is_omap34xx()) {
f3b19aa5	107	features.dpll_bypass_vals \|=
512d91cb TK	108	(1 << OMAP3XXX_EN_DPLL_LPBYPASS) \|
	109	(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
	110	} else if (soc_is_am33xx() \|\| cpu_is_omap44xx() \|\| soc_is_am43xx() \|\|
	111	soc_is_omap54xx() \|\| soc_is_dra7xx()) {
f3b19aa5	112	features.dpll_bypass_vals \|=
512d91cb TK	113	(1 << OMAP4XXX_EN_DPLL_LPBYPASS) \|
	114	(1 << OMAP4XXX_EN_DPLL_FRBYPASS) \|
	115	(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
	116	}
2337c5b5 TK	117
	118	/* Jitter correction only available on OMAP343X */
	119	if (cpu_is_omap343x())
f3b19aa5	120	features.flags \|= TI_CLK_DPLL_HAS_FREQSEL;
066edb2d TK	121
	122	/* Idlest value for interface clocks.
	123	* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
	124	* 34xx reverses this, just to keep us on our toes
	125	* AM35xx uses both, depending on the module.
	126	*/
	127	if (cpu_is_omap24xx())
f3b19aa5	128	features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
066edb2d	129	else if (cpu_is_omap34xx())
f3b19aa5	130	features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
f0d2f68a TK	131
	132	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
	133	if (omap_rev() == OMAP3430_REV_ES1_0)
f3b19aa5 TK	134	features.flags \|= TI_CLK_DPLL4_DENY_REPROGRAM;
f3b19aa5 TK	135
07ff73a9 TK	136	/* Errata I810 for omap5 / dra7 */
	137	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	138	features.flags \|= TI_CLK_ERRATA_I810;
	139
f3b19aa5	140	ti_clk_setup_features(&features);
8111e010	141	}