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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
543d9378 PW |
2 | /* |
3 | * linux/arch/arm/mach-omap2/clock.c | |
4 | * | |
a16e9703 | 5 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
8c34974a | 6 | * Copyright (C) 2004-2010 Nokia Corporation |
543d9378 | 7 | * |
a16e9703 TL |
8 | * Contacts: |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
543d9378 | 10 | * Paul Walmsley |
543d9378 PW |
11 | */ |
12 | #undef DEBUG | |
13 | ||
543d9378 | 14 | #include <linux/kernel.h> |
1fe9be82 | 15 | #include <linux/export.h> |
543d9378 PW |
16 | #include <linux/list.h> |
17 | #include <linux/errno.h> | |
4d30e82c PW |
18 | #include <linux/err.h> |
19 | #include <linux/delay.h> | |
f5b00f6f | 20 | #include <linux/clk.h> |
32cc0021 | 21 | #include <linux/clk-provider.h> |
fced80c7 | 22 | #include <linux/io.h> |
fbd3bdb2 | 23 | #include <linux/bitops.h> |
9f029b15 | 24 | #include <linux/of_address.h> |
5e7c58dc | 25 | #include <asm/cpu.h> |
dbc04161 | 26 | |
dbc04161 TL |
27 | #include <trace/events/power.h> |
28 | ||
29 | #include "soc.h" | |
30 | #include "clockdomain.h" | |
543d9378 | 31 | #include "clock.h" |
c4ceedcb | 32 | #include "cm.h" |
ff4ae5d9 PW |
33 | #include "cm2xxx.h" |
34 | #include "cm3xxx.h" | |
543d9378 PW |
35 | #include "cm-regbits-24xx.h" |
36 | #include "cm-regbits-34xx.h" | |
c4ceedcb PW |
37 | #include "common.h" |
38 | ||
99541195 | 39 | u16 cpu_mask; |
543d9378 | 40 | |
a24886e2 TK |
41 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ |
42 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 | |
43 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 | |
44 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 | |
45 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 | |
46 | ||
47 | /* | |
48 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. | |
49 | * From device data manual section 4.3 "DPLL and DLL Specifications". | |
50 | */ | |
51 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 | |
52 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 | |
53 | ||
6c0afb50 | 54 | struct ti_clk_ll_ops omap_clk_ll_ops = { |
9a356d62 TK |
55 | .clkdm_clk_enable = clkdm_clk_enable, |
56 | .clkdm_clk_disable = clkdm_clk_disable, | |
b6f27b2d | 57 | .clkdm_lookup = clkdm_lookup, |
192383d8 TK |
58 | .cm_wait_module_ready = omap_cm_wait_module_ready, |
59 | .cm_split_idlest_reg = cm_split_idlest_reg, | |
9f029b15 TK |
60 | }; |
61 | ||
e9e63088 TK |
62 | /** |
63 | * omap2_clk_setup_ll_ops - setup clock driver low-level ops | |
64 | * | |
65 | * Sets up clock driver low-level platform ops. These are needed | |
66 | * for register accesses and various other misc platform operations. | |
67 | * Returns 0 on success, -EBUSY if low level ops have been registered | |
68 | * already. | |
69 | */ | |
70 | int __init omap2_clk_setup_ll_ops(void) | |
71 | { | |
72 | return ti_clk_setup_ll_ops(&omap_clk_ll_ops); | |
73 | } | |
74 | ||
30962d9d PW |
75 | /* |
76 | * OMAP2+ specific clock functions | |
77 | */ | |
543d9378 | 78 | |
8111e010 TK |
79 | /** |
80 | * ti_clk_init_features - init clock features struct for the SoC | |
81 | * | |
82 | * Initializes the clock features struct based on the SoC type. | |
83 | */ | |
84 | void __init ti_clk_init_features(void) | |
85 | { | |
f3b19aa5 | 86 | struct ti_clk_features features = { 0 }; |
a24886e2 TK |
87 | /* Fint setup for DPLLs */ |
88 | if (cpu_is_omap3430()) { | |
f3b19aa5 TK |
89 | features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; |
90 | features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; | |
91 | features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; | |
92 | features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; | |
a24886e2 | 93 | } else { |
f3b19aa5 TK |
94 | features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; |
95 | features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; | |
a24886e2 | 96 | } |
512d91cb TK |
97 | |
98 | /* Bypass value setup for DPLLs */ | |
99 | if (cpu_is_omap24xx()) { | |
f3b19aa5 | 100 | features.dpll_bypass_vals |= |
512d91cb TK |
101 | (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | |
102 | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); | |
103 | } else if (cpu_is_omap34xx()) { | |
f3b19aa5 | 104 | features.dpll_bypass_vals |= |
512d91cb TK |
105 | (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | |
106 | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); | |
107 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || | |
108 | soc_is_omap54xx() || soc_is_dra7xx()) { | |
f3b19aa5 | 109 | features.dpll_bypass_vals |= |
512d91cb TK |
110 | (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | |
111 | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | | |
112 | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); | |
113 | } | |
2337c5b5 TK |
114 | |
115 | /* Jitter correction only available on OMAP343X */ | |
116 | if (cpu_is_omap343x()) | |
f3b19aa5 | 117 | features.flags |= TI_CLK_DPLL_HAS_FREQSEL; |
066edb2d | 118 | |
869decd1 TK |
119 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) |
120 | features.flags |= TI_CLK_DEVICE_TYPE_GP; | |
121 | ||
066edb2d TK |
122 | /* Idlest value for interface clocks. |
123 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | |
124 | * 34xx reverses this, just to keep us on our toes | |
125 | * AM35xx uses both, depending on the module. | |
126 | */ | |
127 | if (cpu_is_omap24xx()) | |
f3b19aa5 | 128 | features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; |
066edb2d | 129 | else if (cpu_is_omap34xx()) |
f3b19aa5 | 130 | features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; |
f0d2f68a TK |
131 | |
132 | /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ | |
133 | if (omap_rev() == OMAP3430_REV_ES1_0) | |
f3b19aa5 TK |
134 | features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; |
135 | ||
07ff73a9 TK |
136 | /* Errata I810 for omap5 / dra7 */ |
137 | if (soc_is_omap54xx() || soc_is_dra7xx()) | |
138 | features.flags |= TI_CLK_ERRATA_I810; | |
139 | ||
f3b19aa5 | 140 | ti_clk_setup_features(&features); |
8111e010 | 141 | } |