[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-omap2 / clock.h

/*
 *  linux/arch/arm/mach-omap2/clock.h
 *
 *  Copyright (C) 2005-2008 Texas Instruments, Inc.
 *  Copyright (C) 2004-2008 Nokia Corporation
 *
 *  Contacts:
 *  Richard Woodruff <r-woodruff2@ti.com>
 *  Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H

#include <mach/clock.h>

/* The maximum error between a target DPLL rate and the rounded rate in Hz */
#define DEFAULT_DPLL_RATE_TOLERANCE	50000

int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk);
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);

#ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk);
#else
#define omap2_clk_disable_unused	NULL
#endif

void omap2_clksel_recalc(struct clk *clk);
void omap2_init_clksel_parent(struct clk *clk);
u32 omap2_clksel_get_divisor(struct clk *clk);
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
				u32 *new_div);
u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
void omap2_fixed_divisor_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
void omap2_clk_prepare_for_reboot(void);

extern u8 cpu_mask;

/* clksel_rate data common to 24xx/343x */
static const struct clksel_rate gpt_32k_rates[] = {
	 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
	 { .div = 0 }
};

static const struct clksel_rate gpt_sys_rates[] = {
	 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
	 { .div = 0 }
};

static const struct clksel_rate gfx_l3_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
	{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
	{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
	{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
	{ .div = 0 }
};


#endif
Commit	Line	Data
543d9378 PW	1	/*
	2	* linux/arch/arm/mach-omap2/clock.h
	3	*
a16e9703 TL	4	* Copyright (C) 2005-2008 Texas Instruments, Inc.
a16e9703 TL	5	* Copyright (C) 2004-2008 Nokia Corporation
543d9378	6	*
a16e9703 TL	7	* Contacts:
a16e9703 TL	8	* Richard Woodruff <r-woodruff2@ti.com>
543d9378 PW	9	* Paul Walmsley
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
	17	#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
	18
a09e64fb	19	#include <mach/clock.h>
543d9378	20
88b8ba90 PW	21	/* The maximum error between a target DPLL rate and the rounded rate in Hz */
	22	#define DEFAULT_DPLL_RATE_TOLERANCE 50000
	23
543d9378 PW	24	int omap2_clk_enable(struct clk *clk);
	25	void omap2_clk_disable(struct clk *clk);
	26	long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
	27	int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
	28	int omap2_clk_set_parent(struct clk clk, struct clk new_parent);
88b8ba90 PW	29	int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
88b8ba90 PW	30	long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
543d9378 PW	31
	32	#ifdef CONFIG_OMAP_RESET_CLOCKS
	33	void omap2_clk_disable_unused(struct clk *clk);
	34	#else
	35	#define omap2_clk_disable_unused NULL
	36	#endif
	37
	38	void omap2_clksel_recalc(struct clk *clk);
	39	void omap2_init_clksel_parent(struct clk *clk);
	40	u32 omap2_clksel_get_divisor(struct clk *clk);
	41	u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
	42	u32 *new_div);
	43	u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
	44	u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
	45	void omap2_fixed_divisor_recalc(struct clk *clk);
	46	long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
	47	int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
	48	u32 omap2_get_dpll_rate(struct clk *clk);
	49	int omap2_wait_clock_ready(void __iomem reg, u32 cval, const char name);
ff00fcc9	50	void omap2_clk_prepare_for_reboot(void);
543d9378 PW	51
	52	extern u8 cpu_mask;
	53
	54	/* clksel_rate data common to 24xx/343x */
	55	static const struct clksel_rate gpt_32k_rates[] = {
	56	{ .div = 1, .val = 0, .flags = RATE_IN_24XX \| RATE_IN_343X \| DEFAULT_RATE },
	57	{ .div = 0 }
	58	};
	59
	60	static const struct clksel_rate gpt_sys_rates[] = {
	61	{ .div = 1, .val = 1, .flags = RATE_IN_24XX \| RATE_IN_343X \| DEFAULT_RATE },
	62	{ .div = 0 }
	63	};
	64
	65	static const struct clksel_rate gfx_l3_rates[] = {
	66	{ .div = 1, .val = 1, .flags = RATE_IN_24XX \| RATE_IN_343X },
	67	{ .div = 2, .val = 2, .flags = RATE_IN_24XX \| RATE_IN_343X \| DEFAULT_RATE },
	68	{ .div = 3, .val = 3, .flags = RATE_IN_243X \| RATE_IN_343X },
	69	{ .div = 4, .val = 4, .flags = RATE_IN_243X \| RATE_IN_343X },
	70	{ .div = 0 }
	71	};
	72
	73
	74	#endif