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[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / clock2xxx.c
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046d6b28 1/*
da4d2904 2 * clock2xxx.c - OMAP2xxx-specific clock integration code
046d6b28 3 *
da4d2904
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4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
046d6b28 6 *
da4d2904
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7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
046d6b28 10 *
da4d2904
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11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
046d6b28
TL
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
6b8858a9
PW
18#undef DEBUG
19
046d6b28 20#include <linux/kernel.h>
046d6b28 21#include <linux/errno.h>
f8ce2547 22#include <linux/clk.h>
6b8858a9 23#include <linux/io.h>
046d6b28 24
2c799cef 25#include <plat/cpu.h>
ce491cf8 26#include <plat/clock.h>
046d6b28 27
6b8858a9 28#include "clock.h"
d8a94458 29#include "clock2xxx.h"
6b8858a9
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30#include "cm.h"
31#include "cm-regbits-24xx.h"
046d6b28 32
d8a94458 33struct clk *vclk, *sclk, *dclk;
046d6b28 34
da4d2904 35/*
6b8858a9 36 * Omap24xx specific clock functions
da4d2904 37 */
046d6b28 38
ae78dcf7
TL
39/*
40 * Set clocks for bypass mode for reboot to work.
41 */
feec1277 42void omap2xxx_clk_prepare_for_reboot(void)
ae78dcf7
TL
43{
44 u32 rate;
45
46 if (vclk == NULL || sclk == NULL)
47 return;
48
49 rate = clk_get_rate(sclk);
50 clk_set_rate(vclk, rate);
51}
52
046d6b28 53/*
4d30e82c
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54 * Switch the MPU rate if specified on cmdline. We cannot do this
55 * early until cmdline is parsed. XXX This should be removed from the
56 * clock code and handled by the OPP layer code in the near future.
046d6b28 57 */
4680c29f 58static int __init omap2xxx_clk_arch_init(void)
046d6b28 59{
4d30e82c 60 int ret;
d8a94458 61
4680c29f
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62 if (!cpu_is_omap24xx())
63 return 0;
64
4d30e82c
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65 ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set");
66 if (!ret)
67 omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck");
046d6b28 68
4d30e82c 69 return ret;
046d6b28 70}
4d30e82c 71
4680c29f 72arch_initcall(omap2xxx_clk_arch_init);
046d6b28 73
046d6b28 74