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1 | /* |
2 | * OMAP3 clock data | |
3 | * | |
4 | * Copyright (C) 2007-2009 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2009 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander | |
9 | * DPLL bypass clock support added by Roman Tereshonkov | |
10 | * | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Virtual clocks are introduced as convenient tools. | |
15 | * They are sources for other clocks and not supposed | |
16 | * to be requested from drivers directly. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/clk.h> | |
22 | ||
23 | #include <plat/control.h> | |
24 | #include <plat/clkdev_omap.h> | |
25 | ||
26 | #include "clock.h" | |
27 | #include "clock34xx.h" | |
28 | #include "cm.h" | |
29 | #include "cm-regbits-34xx.h" | |
30 | #include "prm.h" | |
31 | #include "prm-regbits-34xx.h" | |
32 | ||
33 | /* | |
34 | * clocks | |
35 | */ | |
36 | ||
37 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR | |
38 | ||
39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | |
40 | #define OMAP3_MAX_DPLL_MULT 2048 | |
41 | #define OMAP3_MAX_DPLL_DIV 128 | |
42 | ||
43 | /* | |
44 | * DPLL1 supplies clock to the MPU. | |
45 | * DPLL2 supplies clock to the IVA2. | |
46 | * DPLL3 supplies CORE domain clocks. | |
47 | * DPLL4 supplies peripheral clocks. | |
48 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | |
49 | */ | |
50 | ||
51 | /* Forward declarations for DPLL bypass clocks */ | |
52 | static struct clk dpll1_fck; | |
53 | static struct clk dpll2_fck; | |
54 | ||
55 | /* PRM CLOCKS */ | |
56 | ||
57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | |
58 | static struct clk omap_32k_fck = { | |
59 | .name = "omap_32k_fck", | |
60 | .ops = &clkops_null, | |
61 | .rate = 32768, | |
62 | .flags = RATE_FIXED, | |
63 | }; | |
64 | ||
65 | static struct clk secure_32k_fck = { | |
66 | .name = "secure_32k_fck", | |
67 | .ops = &clkops_null, | |
68 | .rate = 32768, | |
69 | .flags = RATE_FIXED, | |
70 | }; | |
71 | ||
72 | /* Virtual source clocks for osc_sys_ck */ | |
73 | static struct clk virt_12m_ck = { | |
74 | .name = "virt_12m_ck", | |
75 | .ops = &clkops_null, | |
76 | .rate = 12000000, | |
77 | .flags = RATE_FIXED, | |
78 | }; | |
79 | ||
80 | static struct clk virt_13m_ck = { | |
81 | .name = "virt_13m_ck", | |
82 | .ops = &clkops_null, | |
83 | .rate = 13000000, | |
84 | .flags = RATE_FIXED, | |
85 | }; | |
86 | ||
87 | static struct clk virt_16_8m_ck = { | |
88 | .name = "virt_16_8m_ck", | |
89 | .ops = &clkops_null, | |
90 | .rate = 16800000, | |
91 | .flags = RATE_FIXED, | |
92 | }; | |
93 | ||
94 | static struct clk virt_19_2m_ck = { | |
95 | .name = "virt_19_2m_ck", | |
96 | .ops = &clkops_null, | |
97 | .rate = 19200000, | |
98 | .flags = RATE_FIXED, | |
99 | }; | |
100 | ||
101 | static struct clk virt_26m_ck = { | |
102 | .name = "virt_26m_ck", | |
103 | .ops = &clkops_null, | |
104 | .rate = 26000000, | |
105 | .flags = RATE_FIXED, | |
106 | }; | |
107 | ||
108 | static struct clk virt_38_4m_ck = { | |
109 | .name = "virt_38_4m_ck", | |
110 | .ops = &clkops_null, | |
111 | .rate = 38400000, | |
112 | .flags = RATE_FIXED, | |
113 | }; | |
114 | ||
115 | static const struct clksel_rate osc_sys_12m_rates[] = { | |
116 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
117 | { .div = 0 } | |
118 | }; | |
119 | ||
120 | static const struct clksel_rate osc_sys_13m_rates[] = { | |
121 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
122 | { .div = 0 } | |
123 | }; | |
124 | ||
125 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | |
126 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | |
127 | { .div = 0 } | |
128 | }; | |
129 | ||
130 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | |
131 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
132 | { .div = 0 } | |
133 | }; | |
134 | ||
135 | static const struct clksel_rate osc_sys_26m_rates[] = { | |
136 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
137 | { .div = 0 } | |
138 | }; | |
139 | ||
140 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | |
141 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
142 | { .div = 0 } | |
143 | }; | |
144 | ||
145 | static const struct clksel osc_sys_clksel[] = { | |
146 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | |
147 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | |
148 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | |
149 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | |
150 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | |
151 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | |
152 | { .parent = NULL }, | |
153 | }; | |
154 | ||
155 | /* Oscillator clock */ | |
156 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | |
157 | static struct clk osc_sys_ck = { | |
158 | .name = "osc_sys_ck", | |
159 | .ops = &clkops_null, | |
160 | .init = &omap2_init_clksel_parent, | |
161 | .clksel_reg = OMAP3430_PRM_CLKSEL, | |
162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | |
163 | .clksel = osc_sys_clksel, | |
164 | /* REVISIT: deal with autoextclkmode? */ | |
165 | .flags = RATE_FIXED, | |
166 | .recalc = &omap2_clksel_recalc, | |
167 | }; | |
168 | ||
169 | static const struct clksel_rate div2_rates[] = { | |
170 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
171 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
172 | { .div = 0 } | |
173 | }; | |
174 | ||
175 | static const struct clksel sys_clksel[] = { | |
176 | { .parent = &osc_sys_ck, .rates = div2_rates }, | |
177 | { .parent = NULL } | |
178 | }; | |
179 | ||
180 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | |
181 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | |
182 | static struct clk sys_ck = { | |
183 | .name = "sys_ck", | |
184 | .ops = &clkops_null, | |
185 | .parent = &osc_sys_ck, | |
186 | .init = &omap2_init_clksel_parent, | |
187 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | |
188 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | |
189 | .clksel = sys_clksel, | |
190 | .recalc = &omap2_clksel_recalc, | |
191 | }; | |
192 | ||
193 | static struct clk sys_altclk = { | |
194 | .name = "sys_altclk", | |
195 | .ops = &clkops_null, | |
196 | }; | |
197 | ||
198 | /* Optional external clock input for some McBSPs */ | |
199 | static struct clk mcbsp_clks = { | |
200 | .name = "mcbsp_clks", | |
201 | .ops = &clkops_null, | |
202 | }; | |
203 | ||
204 | /* PRM EXTERNAL CLOCK OUTPUT */ | |
205 | ||
206 | static struct clk sys_clkout1 = { | |
207 | .name = "sys_clkout1", | |
208 | .ops = &clkops_omap2_dflt, | |
209 | .parent = &osc_sys_ck, | |
210 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | |
211 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | |
212 | .recalc = &followparent_recalc, | |
213 | }; | |
214 | ||
215 | /* DPLLS */ | |
216 | ||
217 | /* CM CLOCKS */ | |
218 | ||
219 | static const struct clksel_rate div16_dpll_rates[] = { | |
220 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
221 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
222 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
223 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
224 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | |
225 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
226 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | |
227 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
228 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | |
229 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | |
230 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | |
231 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | |
232 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | |
233 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | |
234 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | |
235 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | |
236 | { .div = 0 } | |
237 | }; | |
238 | ||
239 | /* DPLL1 */ | |
240 | /* MPU clock source */ | |
241 | /* Type: DPLL */ | |
242 | static struct dpll_data dpll1_dd = { | |
243 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
244 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | |
245 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | |
246 | .clk_bypass = &dpll1_fck, | |
247 | .clk_ref = &sys_ck, | |
248 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, | |
249 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | |
250 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | |
251 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
252 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, | |
253 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | |
254 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | |
255 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), | |
256 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | |
257 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
258 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, | |
259 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
260 | .min_divider = 1, | |
261 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
262 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
263 | }; | |
264 | ||
265 | static struct clk dpll1_ck = { | |
266 | .name = "dpll1_ck", | |
267 | .ops = &clkops_null, | |
268 | .parent = &sys_ck, | |
269 | .dpll_data = &dpll1_dd, | |
270 | .round_rate = &omap2_dpll_round_rate, | |
271 | .set_rate = &omap3_noncore_dpll_set_rate, | |
272 | .clkdm_name = "dpll1_clkdm", | |
273 | .recalc = &omap3_dpll_recalc, | |
274 | }; | |
275 | ||
276 | /* | |
277 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
278 | * DPLL isn't bypassed. | |
279 | */ | |
280 | static struct clk dpll1_x2_ck = { | |
281 | .name = "dpll1_x2_ck", | |
282 | .ops = &clkops_null, | |
283 | .parent = &dpll1_ck, | |
284 | .clkdm_name = "dpll1_clkdm", | |
285 | .recalc = &omap3_clkoutx2_recalc, | |
286 | }; | |
287 | ||
288 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | |
289 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | |
290 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | |
291 | { .parent = NULL } | |
292 | }; | |
293 | ||
294 | /* | |
295 | * Does not exist in the TRM - needed to separate the M2 divider from | |
296 | * bypass selection in mpu_ck | |
297 | */ | |
298 | static struct clk dpll1_x2m2_ck = { | |
299 | .name = "dpll1_x2m2_ck", | |
300 | .ops = &clkops_null, | |
301 | .parent = &dpll1_x2_ck, | |
302 | .init = &omap2_init_clksel_parent, | |
303 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
304 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | |
305 | .clksel = div16_dpll1_x2m2_clksel, | |
306 | .clkdm_name = "dpll1_clkdm", | |
307 | .recalc = &omap2_clksel_recalc, | |
308 | }; | |
309 | ||
310 | /* DPLL2 */ | |
311 | /* IVA2 clock source */ | |
312 | /* Type: DPLL */ | |
313 | ||
314 | static struct dpll_data dpll2_dd = { | |
315 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
316 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | |
317 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | |
318 | .clk_bypass = &dpll2_fck, | |
319 | .clk_ref = &sys_ck, | |
320 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, | |
321 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | |
322 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | |
323 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | | |
324 | (1 << DPLL_LOW_POWER_BYPASS), | |
325 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, | |
326 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | |
327 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | |
328 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), | |
329 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | |
330 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | |
331 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, | |
332 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
333 | .min_divider = 1, | |
334 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
335 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
336 | }; | |
337 | ||
338 | static struct clk dpll2_ck = { | |
339 | .name = "dpll2_ck", | |
340 | .ops = &clkops_noncore_dpll_ops, | |
341 | .parent = &sys_ck, | |
342 | .dpll_data = &dpll2_dd, | |
343 | .round_rate = &omap2_dpll_round_rate, | |
344 | .set_rate = &omap3_noncore_dpll_set_rate, | |
345 | .clkdm_name = "dpll2_clkdm", | |
346 | .recalc = &omap3_dpll_recalc, | |
347 | }; | |
348 | ||
349 | static const struct clksel div16_dpll2_m2x2_clksel[] = { | |
350 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | |
351 | { .parent = NULL } | |
352 | }; | |
353 | ||
354 | /* | |
355 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | |
356 | * or CLKOUTX2. CLKOUT seems most plausible. | |
357 | */ | |
358 | static struct clk dpll2_m2_ck = { | |
359 | .name = "dpll2_m2_ck", | |
360 | .ops = &clkops_null, | |
361 | .parent = &dpll2_ck, | |
362 | .init = &omap2_init_clksel_parent, | |
363 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | |
364 | OMAP3430_CM_CLKSEL2_PLL), | |
365 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | |
366 | .clksel = div16_dpll2_m2x2_clksel, | |
367 | .clkdm_name = "dpll2_clkdm", | |
368 | .recalc = &omap2_clksel_recalc, | |
369 | }; | |
370 | ||
371 | /* | |
372 | * DPLL3 | |
373 | * Source clock for all interfaces and for some device fclks | |
374 | * REVISIT: Also supports fast relock bypass - not included below | |
375 | */ | |
376 | static struct dpll_data dpll3_dd = { | |
377 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
378 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | |
379 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | |
380 | .clk_bypass = &sys_ck, | |
381 | .clk_ref = &sys_ck, | |
382 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, | |
383 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
384 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | |
385 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | |
386 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | |
387 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | |
388 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | |
389 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | |
390 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
391 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | |
392 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
393 | .min_divider = 1, | |
394 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
395 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
396 | }; | |
397 | ||
398 | static struct clk dpll3_ck = { | |
399 | .name = "dpll3_ck", | |
400 | .ops = &clkops_null, | |
401 | .parent = &sys_ck, | |
402 | .dpll_data = &dpll3_dd, | |
403 | .round_rate = &omap2_dpll_round_rate, | |
404 | .clkdm_name = "dpll3_clkdm", | |
405 | .recalc = &omap3_dpll_recalc, | |
406 | }; | |
407 | ||
408 | /* | |
409 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
410 | * DPLL isn't bypassed | |
411 | */ | |
412 | static struct clk dpll3_x2_ck = { | |
413 | .name = "dpll3_x2_ck", | |
414 | .ops = &clkops_null, | |
415 | .parent = &dpll3_ck, | |
416 | .clkdm_name = "dpll3_clkdm", | |
417 | .recalc = &omap3_clkoutx2_recalc, | |
418 | }; | |
419 | ||
420 | static const struct clksel_rate div31_dpll3_rates[] = { | |
421 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
422 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
423 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | |
424 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | |
425 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | |
426 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | |
427 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | |
428 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | |
429 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | |
430 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | |
431 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | |
432 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | |
433 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | |
434 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | |
435 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | |
436 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | |
437 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | |
438 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | |
439 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | |
440 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | |
441 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | |
442 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | |
443 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | |
444 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | |
445 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | |
446 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | |
447 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | |
448 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | |
449 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | |
450 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | |
451 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | |
452 | { .div = 0 }, | |
453 | }; | |
454 | ||
455 | static const struct clksel div31_dpll3m2_clksel[] = { | |
456 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | |
457 | { .parent = NULL } | |
458 | }; | |
459 | ||
460 | /* DPLL3 output M2 - primary control point for CORE speed */ | |
461 | static struct clk dpll3_m2_ck = { | |
462 | .name = "dpll3_m2_ck", | |
463 | .ops = &clkops_null, | |
464 | .parent = &dpll3_ck, | |
465 | .init = &omap2_init_clksel_parent, | |
466 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
467 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
468 | .clksel = div31_dpll3m2_clksel, | |
469 | .clkdm_name = "dpll3_clkdm", | |
470 | .round_rate = &omap2_clksel_round_rate, | |
471 | .set_rate = &omap3_core_dpll_m2_set_rate, | |
472 | .recalc = &omap2_clksel_recalc, | |
473 | }; | |
474 | ||
475 | static struct clk core_ck = { | |
476 | .name = "core_ck", | |
477 | .ops = &clkops_null, | |
478 | .parent = &dpll3_m2_ck, | |
479 | .recalc = &followparent_recalc, | |
480 | }; | |
481 | ||
482 | static struct clk dpll3_m2x2_ck = { | |
483 | .name = "dpll3_m2x2_ck", | |
484 | .ops = &clkops_null, | |
485 | .parent = &dpll3_m2_ck, | |
486 | .clkdm_name = "dpll3_clkdm", | |
487 | .recalc = &omap3_clkoutx2_recalc, | |
488 | }; | |
489 | ||
490 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
491 | static const struct clksel div16_dpll3_clksel[] = { | |
492 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | |
493 | { .parent = NULL } | |
494 | }; | |
495 | ||
496 | /* This virtual clock is the source for dpll3_m3x2_ck */ | |
497 | static struct clk dpll3_m3_ck = { | |
498 | .name = "dpll3_m3_ck", | |
499 | .ops = &clkops_null, | |
500 | .parent = &dpll3_ck, | |
501 | .init = &omap2_init_clksel_parent, | |
502 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
503 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | |
504 | .clksel = div16_dpll3_clksel, | |
505 | .clkdm_name = "dpll3_clkdm", | |
506 | .recalc = &omap2_clksel_recalc, | |
507 | }; | |
508 | ||
509 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
510 | static struct clk dpll3_m3x2_ck = { | |
511 | .name = "dpll3_m3x2_ck", | |
512 | .ops = &clkops_omap2_dflt_wait, | |
513 | .parent = &dpll3_m3_ck, | |
514 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
515 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | |
516 | .flags = INVERT_ENABLE, | |
517 | .clkdm_name = "dpll3_clkdm", | |
518 | .recalc = &omap3_clkoutx2_recalc, | |
519 | }; | |
520 | ||
521 | static struct clk emu_core_alwon_ck = { | |
522 | .name = "emu_core_alwon_ck", | |
523 | .ops = &clkops_null, | |
524 | .parent = &dpll3_m3x2_ck, | |
525 | .clkdm_name = "dpll3_clkdm", | |
526 | .recalc = &followparent_recalc, | |
527 | }; | |
528 | ||
529 | /* DPLL4 */ | |
530 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | |
531 | /* Type: DPLL */ | |
532 | static struct dpll_data dpll4_dd = { | |
533 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | |
534 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | |
535 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | |
536 | .clk_bypass = &sys_ck, | |
537 | .clk_ref = &sys_ck, | |
538 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, | |
539 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
540 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | |
541 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | |
542 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, | |
543 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | |
544 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | |
545 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | |
546 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | |
547 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
548 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, | |
549 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
550 | .min_divider = 1, | |
551 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
552 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
553 | }; | |
554 | ||
555 | static struct clk dpll4_ck = { | |
556 | .name = "dpll4_ck", | |
557 | .ops = &clkops_noncore_dpll_ops, | |
558 | .parent = &sys_ck, | |
559 | .dpll_data = &dpll4_dd, | |
560 | .round_rate = &omap2_dpll_round_rate, | |
561 | .set_rate = &omap3_dpll4_set_rate, | |
562 | .clkdm_name = "dpll4_clkdm", | |
563 | .recalc = &omap3_dpll_recalc, | |
564 | }; | |
565 | ||
566 | /* | |
567 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
568 | * DPLL isn't bypassed -- | |
569 | * XXX does this serve any downstream clocks? | |
570 | */ | |
571 | static struct clk dpll4_x2_ck = { | |
572 | .name = "dpll4_x2_ck", | |
573 | .ops = &clkops_null, | |
574 | .parent = &dpll4_ck, | |
575 | .clkdm_name = "dpll4_clkdm", | |
576 | .recalc = &omap3_clkoutx2_recalc, | |
577 | }; | |
578 | ||
579 | static const struct clksel div16_dpll4_clksel[] = { | |
580 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, | |
581 | { .parent = NULL } | |
582 | }; | |
583 | ||
584 | /* This virtual clock is the source for dpll4_m2x2_ck */ | |
585 | static struct clk dpll4_m2_ck = { | |
586 | .name = "dpll4_m2_ck", | |
587 | .ops = &clkops_null, | |
588 | .parent = &dpll4_ck, | |
589 | .init = &omap2_init_clksel_parent, | |
590 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | |
591 | .clksel_mask = OMAP3430_DIV_96M_MASK, | |
592 | .clksel = div16_dpll4_clksel, | |
593 | .clkdm_name = "dpll4_clkdm", | |
594 | .recalc = &omap2_clksel_recalc, | |
595 | }; | |
596 | ||
597 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
598 | static struct clk dpll4_m2x2_ck = { | |
599 | .name = "dpll4_m2x2_ck", | |
600 | .ops = &clkops_omap2_dflt_wait, | |
601 | .parent = &dpll4_m2_ck, | |
602 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
603 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | |
604 | .flags = INVERT_ENABLE, | |
605 | .clkdm_name = "dpll4_clkdm", | |
606 | .recalc = &omap3_clkoutx2_recalc, | |
607 | }; | |
608 | ||
609 | /* | |
610 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as | |
611 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: | |
612 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | |
613 | * CM_96K_(F)CLK. | |
614 | */ | |
615 | static struct clk omap_96m_alwon_fck = { | |
616 | .name = "omap_96m_alwon_fck", | |
617 | .ops = &clkops_null, | |
618 | .parent = &dpll4_m2x2_ck, | |
619 | .recalc = &followparent_recalc, | |
620 | }; | |
621 | ||
622 | static struct clk cm_96m_fck = { | |
623 | .name = "cm_96m_fck", | |
624 | .ops = &clkops_null, | |
625 | .parent = &omap_96m_alwon_fck, | |
626 | .recalc = &followparent_recalc, | |
627 | }; | |
628 | ||
629 | static const struct clksel_rate omap_96m_dpll_rates[] = { | |
630 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
631 | { .div = 0 } | |
632 | }; | |
633 | ||
634 | static const struct clksel_rate omap_96m_sys_rates[] = { | |
635 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
636 | { .div = 0 } | |
637 | }; | |
638 | ||
639 | static const struct clksel omap_96m_fck_clksel[] = { | |
640 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | |
641 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | |
642 | { .parent = NULL } | |
643 | }; | |
644 | ||
645 | static struct clk omap_96m_fck = { | |
646 | .name = "omap_96m_fck", | |
647 | .ops = &clkops_null, | |
648 | .parent = &sys_ck, | |
649 | .init = &omap2_init_clksel_parent, | |
650 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
651 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, | |
652 | .clksel = omap_96m_fck_clksel, | |
653 | .recalc = &omap2_clksel_recalc, | |
654 | }; | |
655 | ||
656 | /* This virtual clock is the source for dpll4_m3x2_ck */ | |
657 | static struct clk dpll4_m3_ck = { | |
658 | .name = "dpll4_m3_ck", | |
659 | .ops = &clkops_null, | |
660 | .parent = &dpll4_ck, | |
661 | .init = &omap2_init_clksel_parent, | |
662 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
663 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | |
664 | .clksel = div16_dpll4_clksel, | |
665 | .clkdm_name = "dpll4_clkdm", | |
666 | .recalc = &omap2_clksel_recalc, | |
667 | }; | |
668 | ||
669 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
670 | static struct clk dpll4_m3x2_ck = { | |
671 | .name = "dpll4_m3x2_ck", | |
672 | .ops = &clkops_omap2_dflt_wait, | |
673 | .parent = &dpll4_m3_ck, | |
674 | .init = &omap2_init_clksel_parent, | |
675 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
676 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | |
677 | .flags = INVERT_ENABLE, | |
678 | .clkdm_name = "dpll4_clkdm", | |
679 | .recalc = &omap3_clkoutx2_recalc, | |
680 | }; | |
681 | ||
682 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | |
683 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
684 | { .div = 0 } | |
685 | }; | |
686 | ||
687 | static const struct clksel_rate omap_54m_alt_rates[] = { | |
688 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
689 | { .div = 0 } | |
690 | }; | |
691 | ||
692 | static const struct clksel omap_54m_clksel[] = { | |
693 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, | |
694 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | |
695 | { .parent = NULL } | |
696 | }; | |
697 | ||
698 | static struct clk omap_54m_fck = { | |
699 | .name = "omap_54m_fck", | |
700 | .ops = &clkops_null, | |
701 | .init = &omap2_init_clksel_parent, | |
702 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
703 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, | |
704 | .clksel = omap_54m_clksel, | |
705 | .recalc = &omap2_clksel_recalc, | |
706 | }; | |
707 | ||
708 | static const struct clksel_rate omap_48m_cm96m_rates[] = { | |
709 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
710 | { .div = 0 } | |
711 | }; | |
712 | ||
713 | static const struct clksel_rate omap_48m_alt_rates[] = { | |
714 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
715 | { .div = 0 } | |
716 | }; | |
717 | ||
718 | static const struct clksel omap_48m_clksel[] = { | |
719 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, | |
720 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | |
721 | { .parent = NULL } | |
722 | }; | |
723 | ||
724 | static struct clk omap_48m_fck = { | |
725 | .name = "omap_48m_fck", | |
726 | .ops = &clkops_null, | |
727 | .init = &omap2_init_clksel_parent, | |
728 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
729 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, | |
730 | .clksel = omap_48m_clksel, | |
731 | .recalc = &omap2_clksel_recalc, | |
732 | }; | |
733 | ||
734 | static struct clk omap_12m_fck = { | |
735 | .name = "omap_12m_fck", | |
736 | .ops = &clkops_null, | |
737 | .parent = &omap_48m_fck, | |
738 | .fixed_div = 4, | |
739 | .recalc = &omap2_fixed_divisor_recalc, | |
740 | }; | |
741 | ||
742 | /* This virstual clock is the source for dpll4_m4x2_ck */ | |
743 | static struct clk dpll4_m4_ck = { | |
744 | .name = "dpll4_m4_ck", | |
745 | .ops = &clkops_null, | |
746 | .parent = &dpll4_ck, | |
747 | .init = &omap2_init_clksel_parent, | |
748 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
749 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | |
750 | .clksel = div16_dpll4_clksel, | |
751 | .clkdm_name = "dpll4_clkdm", | |
752 | .recalc = &omap2_clksel_recalc, | |
753 | .set_rate = &omap2_clksel_set_rate, | |
754 | .round_rate = &omap2_clksel_round_rate, | |
755 | }; | |
756 | ||
757 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
758 | static struct clk dpll4_m4x2_ck = { | |
759 | .name = "dpll4_m4x2_ck", | |
760 | .ops = &clkops_omap2_dflt_wait, | |
761 | .parent = &dpll4_m4_ck, | |
762 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
763 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
764 | .flags = INVERT_ENABLE, | |
765 | .clkdm_name = "dpll4_clkdm", | |
766 | .recalc = &omap3_clkoutx2_recalc, | |
767 | }; | |
768 | ||
769 | /* This virtual clock is the source for dpll4_m5x2_ck */ | |
770 | static struct clk dpll4_m5_ck = { | |
771 | .name = "dpll4_m5_ck", | |
772 | .ops = &clkops_null, | |
773 | .parent = &dpll4_ck, | |
774 | .init = &omap2_init_clksel_parent, | |
775 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | |
776 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | |
777 | .clksel = div16_dpll4_clksel, | |
778 | .clkdm_name = "dpll4_clkdm", | |
779 | .recalc = &omap2_clksel_recalc, | |
780 | }; | |
781 | ||
782 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
783 | static struct clk dpll4_m5x2_ck = { | |
784 | .name = "dpll4_m5x2_ck", | |
785 | .ops = &clkops_omap2_dflt_wait, | |
786 | .parent = &dpll4_m5_ck, | |
787 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
788 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
789 | .flags = INVERT_ENABLE, | |
790 | .clkdm_name = "dpll4_clkdm", | |
791 | .recalc = &omap3_clkoutx2_recalc, | |
792 | }; | |
793 | ||
794 | /* This virtual clock is the source for dpll4_m6x2_ck */ | |
795 | static struct clk dpll4_m6_ck = { | |
796 | .name = "dpll4_m6_ck", | |
797 | .ops = &clkops_null, | |
798 | .parent = &dpll4_ck, | |
799 | .init = &omap2_init_clksel_parent, | |
800 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
801 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | |
802 | .clksel = div16_dpll4_clksel, | |
803 | .clkdm_name = "dpll4_clkdm", | |
804 | .recalc = &omap2_clksel_recalc, | |
805 | }; | |
806 | ||
807 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
808 | static struct clk dpll4_m6x2_ck = { | |
809 | .name = "dpll4_m6x2_ck", | |
810 | .ops = &clkops_omap2_dflt_wait, | |
811 | .parent = &dpll4_m6_ck, | |
812 | .init = &omap2_init_clksel_parent, | |
813 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
814 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | |
815 | .flags = INVERT_ENABLE, | |
816 | .clkdm_name = "dpll4_clkdm", | |
817 | .recalc = &omap3_clkoutx2_recalc, | |
818 | }; | |
819 | ||
820 | static struct clk emu_per_alwon_ck = { | |
821 | .name = "emu_per_alwon_ck", | |
822 | .ops = &clkops_null, | |
823 | .parent = &dpll4_m6x2_ck, | |
824 | .clkdm_name = "dpll4_clkdm", | |
825 | .recalc = &followparent_recalc, | |
826 | }; | |
827 | ||
828 | /* DPLL5 */ | |
829 | /* Supplies 120MHz clock, USIM source clock */ | |
830 | /* Type: DPLL */ | |
831 | /* 3430ES2 only */ | |
832 | static struct dpll_data dpll5_dd = { | |
833 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | |
834 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | |
835 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | |
836 | .clk_bypass = &sys_ck, | |
837 | .clk_ref = &sys_ck, | |
838 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, | |
839 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | |
840 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | |
841 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | |
842 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, | |
843 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | |
844 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | |
845 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), | |
846 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | |
847 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
848 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | |
849 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | |
850 | .min_divider = 1, | |
851 | .max_divider = OMAP3_MAX_DPLL_DIV, | |
852 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
853 | }; | |
854 | ||
855 | static struct clk dpll5_ck = { | |
856 | .name = "dpll5_ck", | |
857 | .ops = &clkops_noncore_dpll_ops, | |
858 | .parent = &sys_ck, | |
859 | .dpll_data = &dpll5_dd, | |
860 | .round_rate = &omap2_dpll_round_rate, | |
861 | .set_rate = &omap3_noncore_dpll_set_rate, | |
862 | .clkdm_name = "dpll5_clkdm", | |
863 | .recalc = &omap3_dpll_recalc, | |
864 | }; | |
865 | ||
866 | static const struct clksel div16_dpll5_clksel[] = { | |
867 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, | |
868 | { .parent = NULL } | |
869 | }; | |
870 | ||
871 | static struct clk dpll5_m2_ck = { | |
872 | .name = "dpll5_m2_ck", | |
873 | .ops = &clkops_null, | |
874 | .parent = &dpll5_ck, | |
875 | .init = &omap2_init_clksel_parent, | |
876 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | |
877 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | |
878 | .clksel = div16_dpll5_clksel, | |
879 | .clkdm_name = "dpll5_clkdm", | |
880 | .recalc = &omap2_clksel_recalc, | |
881 | }; | |
882 | ||
883 | /* CM EXTERNAL CLOCK OUTPUTS */ | |
884 | ||
885 | static const struct clksel_rate clkout2_src_core_rates[] = { | |
886 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
887 | { .div = 0 } | |
888 | }; | |
889 | ||
890 | static const struct clksel_rate clkout2_src_sys_rates[] = { | |
891 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
892 | { .div = 0 } | |
893 | }; | |
894 | ||
895 | static const struct clksel_rate clkout2_src_96m_rates[] = { | |
896 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
897 | { .div = 0 } | |
898 | }; | |
899 | ||
900 | static const struct clksel_rate clkout2_src_54m_rates[] = { | |
901 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
902 | { .div = 0 } | |
903 | }; | |
904 | ||
905 | static const struct clksel clkout2_src_clksel[] = { | |
906 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | |
907 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | |
908 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, | |
909 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | |
910 | { .parent = NULL } | |
911 | }; | |
912 | ||
913 | static struct clk clkout2_src_ck = { | |
914 | .name = "clkout2_src_ck", | |
915 | .ops = &clkops_omap2_dflt, | |
916 | .init = &omap2_init_clksel_parent, | |
917 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | |
918 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | |
919 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
920 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | |
921 | .clksel = clkout2_src_clksel, | |
922 | .clkdm_name = "core_clkdm", | |
923 | .recalc = &omap2_clksel_recalc, | |
924 | }; | |
925 | ||
926 | static const struct clksel_rate sys_clkout2_rates[] = { | |
927 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
928 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
929 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | |
930 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | |
931 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | |
932 | { .div = 0 }, | |
933 | }; | |
934 | ||
935 | static const struct clksel sys_clkout2_clksel[] = { | |
936 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | |
937 | { .parent = NULL }, | |
938 | }; | |
939 | ||
940 | static struct clk sys_clkout2 = { | |
941 | .name = "sys_clkout2", | |
942 | .ops = &clkops_null, | |
943 | .init = &omap2_init_clksel_parent, | |
944 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
945 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | |
946 | .clksel = sys_clkout2_clksel, | |
947 | .recalc = &omap2_clksel_recalc, | |
948 | }; | |
949 | ||
950 | /* CM OUTPUT CLOCKS */ | |
951 | ||
952 | static struct clk corex2_fck = { | |
953 | .name = "corex2_fck", | |
954 | .ops = &clkops_null, | |
955 | .parent = &dpll3_m2x2_ck, | |
956 | .recalc = &followparent_recalc, | |
957 | }; | |
958 | ||
959 | /* DPLL power domain clock controls */ | |
960 | ||
961 | static const struct clksel_rate div4_rates[] = { | |
962 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
963 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
964 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
965 | { .div = 0 } | |
966 | }; | |
967 | ||
968 | static const struct clksel div4_core_clksel[] = { | |
969 | { .parent = &core_ck, .rates = div4_rates }, | |
970 | { .parent = NULL } | |
971 | }; | |
972 | ||
973 | /* | |
974 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | |
975 | * may be inconsistent here? | |
976 | */ | |
977 | static struct clk dpll1_fck = { | |
978 | .name = "dpll1_fck", | |
979 | .ops = &clkops_null, | |
980 | .parent = &core_ck, | |
981 | .init = &omap2_init_clksel_parent, | |
982 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
983 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | |
984 | .clksel = div4_core_clksel, | |
985 | .recalc = &omap2_clksel_recalc, | |
986 | }; | |
987 | ||
988 | static struct clk mpu_ck = { | |
989 | .name = "mpu_ck", | |
990 | .ops = &clkops_null, | |
991 | .parent = &dpll1_x2m2_ck, | |
992 | .clkdm_name = "mpu_clkdm", | |
993 | .recalc = &followparent_recalc, | |
994 | }; | |
995 | ||
996 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | |
997 | static const struct clksel_rate arm_fck_rates[] = { | |
998 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
999 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
1000 | { .div = 0 }, | |
1001 | }; | |
1002 | ||
1003 | static const struct clksel arm_fck_clksel[] = { | |
1004 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | |
1005 | { .parent = NULL } | |
1006 | }; | |
1007 | ||
1008 | static struct clk arm_fck = { | |
1009 | .name = "arm_fck", | |
1010 | .ops = &clkops_null, | |
1011 | .parent = &mpu_ck, | |
1012 | .init = &omap2_init_clksel_parent, | |
1013 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1014 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1015 | .clksel = arm_fck_clksel, | |
1016 | .clkdm_name = "mpu_clkdm", | |
1017 | .recalc = &omap2_clksel_recalc, | |
1018 | }; | |
1019 | ||
1020 | /* XXX What about neon_clkdm ? */ | |
1021 | ||
1022 | /* | |
1023 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | |
1024 | * although it is referenced - so this is a guess | |
1025 | */ | |
1026 | static struct clk emu_mpu_alwon_ck = { | |
1027 | .name = "emu_mpu_alwon_ck", | |
1028 | .ops = &clkops_null, | |
1029 | .parent = &mpu_ck, | |
1030 | .recalc = &followparent_recalc, | |
1031 | }; | |
1032 | ||
1033 | static struct clk dpll2_fck = { | |
1034 | .name = "dpll2_fck", | |
1035 | .ops = &clkops_null, | |
1036 | .parent = &core_ck, | |
1037 | .init = &omap2_init_clksel_parent, | |
1038 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
1039 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | |
1040 | .clksel = div4_core_clksel, | |
1041 | .recalc = &omap2_clksel_recalc, | |
1042 | }; | |
1043 | ||
1044 | static struct clk iva2_ck = { | |
1045 | .name = "iva2_ck", | |
1046 | .ops = &clkops_omap2_dflt_wait, | |
1047 | .parent = &dpll2_m2_ck, | |
1048 | .init = &omap2_init_clksel_parent, | |
1049 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), | |
1050 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
1051 | .clkdm_name = "iva2_clkdm", | |
1052 | .recalc = &followparent_recalc, | |
1053 | }; | |
1054 | ||
1055 | /* Common interface clocks */ | |
1056 | ||
1057 | static const struct clksel div2_core_clksel[] = { | |
1058 | { .parent = &core_ck, .rates = div2_rates }, | |
1059 | { .parent = NULL } | |
1060 | }; | |
1061 | ||
1062 | static struct clk l3_ick = { | |
1063 | .name = "l3_ick", | |
1064 | .ops = &clkops_null, | |
1065 | .parent = &core_ck, | |
1066 | .init = &omap2_init_clksel_parent, | |
1067 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1068 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | |
1069 | .clksel = div2_core_clksel, | |
1070 | .clkdm_name = "core_l3_clkdm", | |
1071 | .recalc = &omap2_clksel_recalc, | |
1072 | }; | |
1073 | ||
1074 | static const struct clksel div2_l3_clksel[] = { | |
1075 | { .parent = &l3_ick, .rates = div2_rates }, | |
1076 | { .parent = NULL } | |
1077 | }; | |
1078 | ||
1079 | static struct clk l4_ick = { | |
1080 | .name = "l4_ick", | |
1081 | .ops = &clkops_null, | |
1082 | .parent = &l3_ick, | |
1083 | .init = &omap2_init_clksel_parent, | |
1084 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1085 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | |
1086 | .clksel = div2_l3_clksel, | |
1087 | .clkdm_name = "core_l4_clkdm", | |
1088 | .recalc = &omap2_clksel_recalc, | |
1089 | ||
1090 | }; | |
1091 | ||
1092 | static const struct clksel div2_l4_clksel[] = { | |
1093 | { .parent = &l4_ick, .rates = div2_rates }, | |
1094 | { .parent = NULL } | |
1095 | }; | |
1096 | ||
1097 | static struct clk rm_ick = { | |
1098 | .name = "rm_ick", | |
1099 | .ops = &clkops_null, | |
1100 | .parent = &l4_ick, | |
1101 | .init = &omap2_init_clksel_parent, | |
1102 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1103 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | |
1104 | .clksel = div2_l4_clksel, | |
1105 | .recalc = &omap2_clksel_recalc, | |
1106 | }; | |
1107 | ||
1108 | /* GFX power domain */ | |
1109 | ||
1110 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ | |
1111 | ||
1112 | static const struct clksel gfx_l3_clksel[] = { | |
1113 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | |
1114 | { .parent = NULL } | |
1115 | }; | |
1116 | ||
1117 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | |
1118 | static struct clk gfx_l3_ck = { | |
1119 | .name = "gfx_l3_ck", | |
1120 | .ops = &clkops_omap2_dflt_wait, | |
1121 | .parent = &l3_ick, | |
1122 | .init = &omap2_init_clksel_parent, | |
1123 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
1124 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
1125 | .recalc = &followparent_recalc, | |
1126 | }; | |
1127 | ||
1128 | static struct clk gfx_l3_fck = { | |
1129 | .name = "gfx_l3_fck", | |
1130 | .ops = &clkops_null, | |
1131 | .parent = &gfx_l3_ck, | |
1132 | .init = &omap2_init_clksel_parent, | |
1133 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
1134 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
1135 | .clksel = gfx_l3_clksel, | |
1136 | .clkdm_name = "gfx_3430es1_clkdm", | |
1137 | .recalc = &omap2_clksel_recalc, | |
1138 | }; | |
1139 | ||
1140 | static struct clk gfx_l3_ick = { | |
1141 | .name = "gfx_l3_ick", | |
1142 | .ops = &clkops_null, | |
1143 | .parent = &gfx_l3_ck, | |
1144 | .clkdm_name = "gfx_3430es1_clkdm", | |
1145 | .recalc = &followparent_recalc, | |
1146 | }; | |
1147 | ||
1148 | static struct clk gfx_cg1_ck = { | |
1149 | .name = "gfx_cg1_ck", | |
1150 | .ops = &clkops_omap2_dflt_wait, | |
1151 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
1152 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
1153 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | |
1154 | .clkdm_name = "gfx_3430es1_clkdm", | |
1155 | .recalc = &followparent_recalc, | |
1156 | }; | |
1157 | ||
1158 | static struct clk gfx_cg2_ck = { | |
1159 | .name = "gfx_cg2_ck", | |
1160 | .ops = &clkops_omap2_dflt_wait, | |
1161 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
1162 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
1163 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | |
1164 | .clkdm_name = "gfx_3430es1_clkdm", | |
1165 | .recalc = &followparent_recalc, | |
1166 | }; | |
1167 | ||
1168 | /* SGX power domain - 3430ES2 only */ | |
1169 | ||
1170 | static const struct clksel_rate sgx_core_rates[] = { | |
1171 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1172 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | |
1173 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | |
1174 | { .div = 0 }, | |
1175 | }; | |
1176 | ||
1177 | static const struct clksel_rate sgx_96m_rates[] = { | |
1178 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1179 | { .div = 0 }, | |
1180 | }; | |
1181 | ||
1182 | static const struct clksel sgx_clksel[] = { | |
1183 | { .parent = &core_ck, .rates = sgx_core_rates }, | |
1184 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | |
1185 | { .parent = NULL }, | |
1186 | }; | |
1187 | ||
1188 | static struct clk sgx_fck = { | |
1189 | .name = "sgx_fck", | |
1190 | .ops = &clkops_omap2_dflt_wait, | |
1191 | .init = &omap2_init_clksel_parent, | |
1192 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | |
1193 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, | |
1194 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | |
1195 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | |
1196 | .clksel = sgx_clksel, | |
1197 | .clkdm_name = "sgx_clkdm", | |
1198 | .recalc = &omap2_clksel_recalc, | |
1199 | }; | |
1200 | ||
1201 | static struct clk sgx_ick = { | |
1202 | .name = "sgx_ick", | |
1203 | .ops = &clkops_omap2_dflt_wait, | |
1204 | .parent = &l3_ick, | |
1205 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | |
1206 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, | |
1207 | .clkdm_name = "sgx_clkdm", | |
1208 | .recalc = &followparent_recalc, | |
1209 | }; | |
1210 | ||
1211 | /* CORE power domain */ | |
1212 | ||
1213 | static struct clk d2d_26m_fck = { | |
1214 | .name = "d2d_26m_fck", | |
1215 | .ops = &clkops_omap2_dflt_wait, | |
1216 | .parent = &sys_ck, | |
1217 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1218 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | |
1219 | .clkdm_name = "d2d_clkdm", | |
1220 | .recalc = &followparent_recalc, | |
1221 | }; | |
1222 | ||
1223 | static struct clk modem_fck = { | |
1224 | .name = "modem_fck", | |
1225 | .ops = &clkops_omap2_dflt_wait, | |
1226 | .parent = &sys_ck, | |
1227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1228 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | |
1229 | .clkdm_name = "d2d_clkdm", | |
1230 | .recalc = &followparent_recalc, | |
1231 | }; | |
1232 | ||
1233 | static struct clk sad2d_ick = { | |
1234 | .name = "sad2d_ick", | |
1235 | .ops = &clkops_omap2_dflt_wait, | |
1236 | .parent = &l3_ick, | |
1237 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1238 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, | |
1239 | .clkdm_name = "d2d_clkdm", | |
1240 | .recalc = &followparent_recalc, | |
1241 | }; | |
1242 | ||
1243 | static struct clk mad2d_ick = { | |
1244 | .name = "mad2d_ick", | |
1245 | .ops = &clkops_omap2_dflt_wait, | |
1246 | .parent = &l3_ick, | |
1247 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1248 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, | |
1249 | .clkdm_name = "d2d_clkdm", | |
1250 | .recalc = &followparent_recalc, | |
1251 | }; | |
1252 | ||
1253 | static const struct clksel omap343x_gpt_clksel[] = { | |
1254 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | |
1255 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
1256 | { .parent = NULL} | |
1257 | }; | |
1258 | ||
1259 | static struct clk gpt10_fck = { | |
1260 | .name = "gpt10_fck", | |
1261 | .ops = &clkops_omap2_dflt_wait, | |
1262 | .parent = &sys_ck, | |
1263 | .init = &omap2_init_clksel_parent, | |
1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1265 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1266 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1267 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | |
1268 | .clksel = omap343x_gpt_clksel, | |
1269 | .clkdm_name = "core_l4_clkdm", | |
1270 | .recalc = &omap2_clksel_recalc, | |
1271 | }; | |
1272 | ||
1273 | static struct clk gpt11_fck = { | |
1274 | .name = "gpt11_fck", | |
1275 | .ops = &clkops_omap2_dflt_wait, | |
1276 | .parent = &sys_ck, | |
1277 | .init = &omap2_init_clksel_parent, | |
1278 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1279 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1280 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1281 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | |
1282 | .clksel = omap343x_gpt_clksel, | |
1283 | .clkdm_name = "core_l4_clkdm", | |
1284 | .recalc = &omap2_clksel_recalc, | |
1285 | }; | |
1286 | ||
1287 | static struct clk cpefuse_fck = { | |
1288 | .name = "cpefuse_fck", | |
1289 | .ops = &clkops_omap2_dflt, | |
1290 | .parent = &sys_ck, | |
1291 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1292 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | |
1293 | .recalc = &followparent_recalc, | |
1294 | }; | |
1295 | ||
1296 | static struct clk ts_fck = { | |
1297 | .name = "ts_fck", | |
1298 | .ops = &clkops_omap2_dflt, | |
1299 | .parent = &omap_32k_fck, | |
1300 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1301 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | |
1302 | .recalc = &followparent_recalc, | |
1303 | }; | |
1304 | ||
1305 | static struct clk usbtll_fck = { | |
1306 | .name = "usbtll_fck", | |
1307 | .ops = &clkops_omap2_dflt, | |
1308 | .parent = &dpll5_m2_ck, | |
1309 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1310 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1311 | .recalc = &followparent_recalc, | |
1312 | }; | |
1313 | ||
1314 | /* CORE 96M FCLK-derived clocks */ | |
1315 | ||
1316 | static struct clk core_96m_fck = { | |
1317 | .name = "core_96m_fck", | |
1318 | .ops = &clkops_null, | |
1319 | .parent = &omap_96m_fck, | |
1320 | .clkdm_name = "core_l4_clkdm", | |
1321 | .recalc = &followparent_recalc, | |
1322 | }; | |
1323 | ||
1324 | static struct clk mmchs3_fck = { | |
1325 | .name = "mmchs_fck", | |
1326 | .ops = &clkops_omap2_dflt_wait, | |
1327 | .id = 2, | |
1328 | .parent = &core_96m_fck, | |
1329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1330 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1331 | .clkdm_name = "core_l4_clkdm", | |
1332 | .recalc = &followparent_recalc, | |
1333 | }; | |
1334 | ||
1335 | static struct clk mmchs2_fck = { | |
1336 | .name = "mmchs_fck", | |
1337 | .ops = &clkops_omap2_dflt_wait, | |
1338 | .id = 1, | |
1339 | .parent = &core_96m_fck, | |
1340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1341 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1342 | .clkdm_name = "core_l4_clkdm", | |
1343 | .recalc = &followparent_recalc, | |
1344 | }; | |
1345 | ||
1346 | static struct clk mspro_fck = { | |
1347 | .name = "mspro_fck", | |
1348 | .ops = &clkops_omap2_dflt_wait, | |
1349 | .parent = &core_96m_fck, | |
1350 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1351 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1352 | .clkdm_name = "core_l4_clkdm", | |
1353 | .recalc = &followparent_recalc, | |
1354 | }; | |
1355 | ||
1356 | static struct clk mmchs1_fck = { | |
1357 | .name = "mmchs_fck", | |
1358 | .ops = &clkops_omap2_dflt_wait, | |
1359 | .parent = &core_96m_fck, | |
1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1361 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1362 | .clkdm_name = "core_l4_clkdm", | |
1363 | .recalc = &followparent_recalc, | |
1364 | }; | |
1365 | ||
1366 | static struct clk i2c3_fck = { | |
1367 | .name = "i2c_fck", | |
1368 | .ops = &clkops_omap2_dflt_wait, | |
1369 | .id = 3, | |
1370 | .parent = &core_96m_fck, | |
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1372 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1373 | .clkdm_name = "core_l4_clkdm", | |
1374 | .recalc = &followparent_recalc, | |
1375 | }; | |
1376 | ||
1377 | static struct clk i2c2_fck = { | |
1378 | .name = "i2c_fck", | |
1379 | .ops = &clkops_omap2_dflt_wait, | |
1380 | .id = 2, | |
1381 | .parent = &core_96m_fck, | |
1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1383 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1384 | .clkdm_name = "core_l4_clkdm", | |
1385 | .recalc = &followparent_recalc, | |
1386 | }; | |
1387 | ||
1388 | static struct clk i2c1_fck = { | |
1389 | .name = "i2c_fck", | |
1390 | .ops = &clkops_omap2_dflt_wait, | |
1391 | .id = 1, | |
1392 | .parent = &core_96m_fck, | |
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1394 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1395 | .clkdm_name = "core_l4_clkdm", | |
1396 | .recalc = &followparent_recalc, | |
1397 | }; | |
1398 | ||
1399 | /* | |
1400 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | |
1401 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | |
1402 | */ | |
1403 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1404 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1405 | { .div = 0 } | |
1406 | }; | |
1407 | ||
1408 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1409 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1410 | { .div = 0 } | |
1411 | }; | |
1412 | ||
1413 | static const struct clksel mcbsp_15_clksel[] = { | |
1414 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | |
1415 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1416 | { .parent = NULL } | |
1417 | }; | |
1418 | ||
1419 | static struct clk mcbsp5_fck = { | |
1420 | .name = "mcbsp_fck", | |
1421 | .ops = &clkops_omap2_dflt_wait, | |
1422 | .id = 5, | |
1423 | .init = &omap2_init_clksel_parent, | |
1424 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1425 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1426 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
1427 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1428 | .clksel = mcbsp_15_clksel, | |
1429 | .clkdm_name = "core_l4_clkdm", | |
1430 | .recalc = &omap2_clksel_recalc, | |
1431 | }; | |
1432 | ||
1433 | static struct clk mcbsp1_fck = { | |
1434 | .name = "mcbsp_fck", | |
1435 | .ops = &clkops_omap2_dflt_wait, | |
1436 | .id = 1, | |
1437 | .init = &omap2_init_clksel_parent, | |
1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1439 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1440 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1441 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1442 | .clksel = mcbsp_15_clksel, | |
1443 | .clkdm_name = "core_l4_clkdm", | |
1444 | .recalc = &omap2_clksel_recalc, | |
1445 | }; | |
1446 | ||
1447 | /* CORE_48M_FCK-derived clocks */ | |
1448 | ||
1449 | static struct clk core_48m_fck = { | |
1450 | .name = "core_48m_fck", | |
1451 | .ops = &clkops_null, | |
1452 | .parent = &omap_48m_fck, | |
1453 | .clkdm_name = "core_l4_clkdm", | |
1454 | .recalc = &followparent_recalc, | |
1455 | }; | |
1456 | ||
1457 | static struct clk mcspi4_fck = { | |
1458 | .name = "mcspi_fck", | |
1459 | .ops = &clkops_omap2_dflt_wait, | |
1460 | .id = 4, | |
1461 | .parent = &core_48m_fck, | |
1462 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1463 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1464 | .recalc = &followparent_recalc, | |
1465 | }; | |
1466 | ||
1467 | static struct clk mcspi3_fck = { | |
1468 | .name = "mcspi_fck", | |
1469 | .ops = &clkops_omap2_dflt_wait, | |
1470 | .id = 3, | |
1471 | .parent = &core_48m_fck, | |
1472 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1473 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1474 | .recalc = &followparent_recalc, | |
1475 | }; | |
1476 | ||
1477 | static struct clk mcspi2_fck = { | |
1478 | .name = "mcspi_fck", | |
1479 | .ops = &clkops_omap2_dflt_wait, | |
1480 | .id = 2, | |
1481 | .parent = &core_48m_fck, | |
1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1483 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1484 | .recalc = &followparent_recalc, | |
1485 | }; | |
1486 | ||
1487 | static struct clk mcspi1_fck = { | |
1488 | .name = "mcspi_fck", | |
1489 | .ops = &clkops_omap2_dflt_wait, | |
1490 | .id = 1, | |
1491 | .parent = &core_48m_fck, | |
1492 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1493 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1494 | .recalc = &followparent_recalc, | |
1495 | }; | |
1496 | ||
1497 | static struct clk uart2_fck = { | |
1498 | .name = "uart2_fck", | |
1499 | .ops = &clkops_omap2_dflt_wait, | |
1500 | .parent = &core_48m_fck, | |
1501 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1502 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
9b5bc5fa | 1503 | .clkdm_name = "core_l4_clkdm", |
82e9bd58 PW |
1504 | .recalc = &followparent_recalc, |
1505 | }; | |
1506 | ||
1507 | static struct clk uart1_fck = { | |
1508 | .name = "uart1_fck", | |
1509 | .ops = &clkops_omap2_dflt_wait, | |
1510 | .parent = &core_48m_fck, | |
1511 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1512 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
9b5bc5fa | 1513 | .clkdm_name = "core_l4_clkdm", |
82e9bd58 PW |
1514 | .recalc = &followparent_recalc, |
1515 | }; | |
1516 | ||
1517 | static struct clk fshostusb_fck = { | |
1518 | .name = "fshostusb_fck", | |
1519 | .ops = &clkops_omap2_dflt_wait, | |
1520 | .parent = &core_48m_fck, | |
1521 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1522 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1523 | .recalc = &followparent_recalc, | |
1524 | }; | |
1525 | ||
1526 | /* CORE_12M_FCK based clocks */ | |
1527 | ||
1528 | static struct clk core_12m_fck = { | |
1529 | .name = "core_12m_fck", | |
1530 | .ops = &clkops_null, | |
1531 | .parent = &omap_12m_fck, | |
1532 | .clkdm_name = "core_l4_clkdm", | |
1533 | .recalc = &followparent_recalc, | |
1534 | }; | |
1535 | ||
1536 | static struct clk hdq_fck = { | |
1537 | .name = "hdq_fck", | |
1538 | .ops = &clkops_omap2_dflt_wait, | |
1539 | .parent = &core_12m_fck, | |
1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1541 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1542 | .recalc = &followparent_recalc, | |
1543 | }; | |
1544 | ||
1545 | /* DPLL3-derived clock */ | |
1546 | ||
1547 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | |
1548 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1549 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
1550 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
1551 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1552 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
1553 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1554 | { .div = 0 } | |
1555 | }; | |
1556 | ||
1557 | static const struct clksel ssi_ssr_clksel[] = { | |
1558 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | |
1559 | { .parent = NULL } | |
1560 | }; | |
1561 | ||
1562 | static struct clk ssi_ssr_fck_3430es1 = { | |
1563 | .name = "ssi_ssr_fck", | |
1564 | .ops = &clkops_omap2_dflt, | |
1565 | .init = &omap2_init_clksel_parent, | |
1566 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1567 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1568 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1569 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1570 | .clksel = ssi_ssr_clksel, | |
1571 | .clkdm_name = "core_l4_clkdm", | |
1572 | .recalc = &omap2_clksel_recalc, | |
1573 | }; | |
1574 | ||
1575 | static struct clk ssi_ssr_fck_3430es2 = { | |
1576 | .name = "ssi_ssr_fck", | |
1577 | .ops = &clkops_omap3430es2_ssi_wait, | |
1578 | .init = &omap2_init_clksel_parent, | |
1579 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1580 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1581 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1582 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1583 | .clksel = ssi_ssr_clksel, | |
1584 | .clkdm_name = "core_l4_clkdm", | |
1585 | .recalc = &omap2_clksel_recalc, | |
1586 | }; | |
1587 | ||
1588 | static struct clk ssi_sst_fck_3430es1 = { | |
1589 | .name = "ssi_sst_fck", | |
1590 | .ops = &clkops_null, | |
1591 | .parent = &ssi_ssr_fck_3430es1, | |
1592 | .fixed_div = 2, | |
1593 | .recalc = &omap2_fixed_divisor_recalc, | |
1594 | }; | |
1595 | ||
1596 | static struct clk ssi_sst_fck_3430es2 = { | |
1597 | .name = "ssi_sst_fck", | |
1598 | .ops = &clkops_null, | |
1599 | .parent = &ssi_ssr_fck_3430es2, | |
1600 | .fixed_div = 2, | |
1601 | .recalc = &omap2_fixed_divisor_recalc, | |
1602 | }; | |
1603 | ||
1604 | ||
1605 | ||
1606 | /* CORE_L3_ICK based clocks */ | |
1607 | ||
1608 | /* | |
1609 | * XXX must add clk_enable/clk_disable for these if standard code won't | |
1610 | * handle it | |
1611 | */ | |
1612 | static struct clk core_l3_ick = { | |
1613 | .name = "core_l3_ick", | |
1614 | .ops = &clkops_null, | |
1615 | .parent = &l3_ick, | |
1616 | .clkdm_name = "core_l3_clkdm", | |
1617 | .recalc = &followparent_recalc, | |
1618 | }; | |
1619 | ||
1620 | static struct clk hsotgusb_ick_3430es1 = { | |
1621 | .name = "hsotgusb_ick", | |
1622 | .ops = &clkops_omap2_dflt, | |
1623 | .parent = &core_l3_ick, | |
1624 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1625 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1626 | .clkdm_name = "core_l3_clkdm", | |
1627 | .recalc = &followparent_recalc, | |
1628 | }; | |
1629 | ||
1630 | static struct clk hsotgusb_ick_3430es2 = { | |
1631 | .name = "hsotgusb_ick", | |
1632 | .ops = &clkops_omap3430es2_hsotgusb_wait, | |
1633 | .parent = &core_l3_ick, | |
1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1635 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1636 | .clkdm_name = "core_l3_clkdm", | |
1637 | .recalc = &followparent_recalc, | |
1638 | }; | |
1639 | ||
1640 | static struct clk sdrc_ick = { | |
1641 | .name = "sdrc_ick", | |
1642 | .ops = &clkops_omap2_dflt_wait, | |
1643 | .parent = &core_l3_ick, | |
1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1645 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | |
1646 | .flags = ENABLE_ON_INIT, | |
1647 | .clkdm_name = "core_l3_clkdm", | |
1648 | .recalc = &followparent_recalc, | |
1649 | }; | |
1650 | ||
1651 | static struct clk gpmc_fck = { | |
1652 | .name = "gpmc_fck", | |
1653 | .ops = &clkops_null, | |
1654 | .parent = &core_l3_ick, | |
1655 | .flags = ENABLE_ON_INIT, /* huh? */ | |
1656 | .clkdm_name = "core_l3_clkdm", | |
1657 | .recalc = &followparent_recalc, | |
1658 | }; | |
1659 | ||
1660 | /* SECURITY_L3_ICK based clocks */ | |
1661 | ||
1662 | static struct clk security_l3_ick = { | |
1663 | .name = "security_l3_ick", | |
1664 | .ops = &clkops_null, | |
1665 | .parent = &l3_ick, | |
1666 | .recalc = &followparent_recalc, | |
1667 | }; | |
1668 | ||
1669 | static struct clk pka_ick = { | |
1670 | .name = "pka_ick", | |
1671 | .ops = &clkops_omap2_dflt_wait, | |
1672 | .parent = &security_l3_ick, | |
1673 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1674 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | |
1675 | .recalc = &followparent_recalc, | |
1676 | }; | |
1677 | ||
1678 | /* CORE_L4_ICK based clocks */ | |
1679 | ||
1680 | static struct clk core_l4_ick = { | |
1681 | .name = "core_l4_ick", | |
1682 | .ops = &clkops_null, | |
1683 | .parent = &l4_ick, | |
1684 | .clkdm_name = "core_l4_clkdm", | |
1685 | .recalc = &followparent_recalc, | |
1686 | }; | |
1687 | ||
1688 | static struct clk usbtll_ick = { | |
1689 | .name = "usbtll_ick", | |
1690 | .ops = &clkops_omap2_dflt_wait, | |
1691 | .parent = &core_l4_ick, | |
1692 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1693 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1694 | .clkdm_name = "core_l4_clkdm", | |
1695 | .recalc = &followparent_recalc, | |
1696 | }; | |
1697 | ||
1698 | static struct clk mmchs3_ick = { | |
1699 | .name = "mmchs_ick", | |
1700 | .ops = &clkops_omap2_dflt_wait, | |
1701 | .id = 2, | |
1702 | .parent = &core_l4_ick, | |
1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1704 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1705 | .clkdm_name = "core_l4_clkdm", | |
1706 | .recalc = &followparent_recalc, | |
1707 | }; | |
1708 | ||
1709 | /* Intersystem Communication Registers - chassis mode only */ | |
1710 | static struct clk icr_ick = { | |
1711 | .name = "icr_ick", | |
1712 | .ops = &clkops_omap2_dflt_wait, | |
1713 | .parent = &core_l4_ick, | |
1714 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1715 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | |
1716 | .clkdm_name = "core_l4_clkdm", | |
1717 | .recalc = &followparent_recalc, | |
1718 | }; | |
1719 | ||
1720 | static struct clk aes2_ick = { | |
1721 | .name = "aes2_ick", | |
1722 | .ops = &clkops_omap2_dflt_wait, | |
1723 | .parent = &core_l4_ick, | |
1724 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1725 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | |
1726 | .clkdm_name = "core_l4_clkdm", | |
1727 | .recalc = &followparent_recalc, | |
1728 | }; | |
1729 | ||
1730 | static struct clk sha12_ick = { | |
1731 | .name = "sha12_ick", | |
1732 | .ops = &clkops_omap2_dflt_wait, | |
1733 | .parent = &core_l4_ick, | |
1734 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1735 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | |
1736 | .clkdm_name = "core_l4_clkdm", | |
1737 | .recalc = &followparent_recalc, | |
1738 | }; | |
1739 | ||
1740 | static struct clk des2_ick = { | |
1741 | .name = "des2_ick", | |
1742 | .ops = &clkops_omap2_dflt_wait, | |
1743 | .parent = &core_l4_ick, | |
1744 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1745 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | |
1746 | .clkdm_name = "core_l4_clkdm", | |
1747 | .recalc = &followparent_recalc, | |
1748 | }; | |
1749 | ||
1750 | static struct clk mmchs2_ick = { | |
1751 | .name = "mmchs_ick", | |
1752 | .ops = &clkops_omap2_dflt_wait, | |
1753 | .id = 1, | |
1754 | .parent = &core_l4_ick, | |
1755 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1756 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1757 | .clkdm_name = "core_l4_clkdm", | |
1758 | .recalc = &followparent_recalc, | |
1759 | }; | |
1760 | ||
1761 | static struct clk mmchs1_ick = { | |
1762 | .name = "mmchs_ick", | |
1763 | .ops = &clkops_omap2_dflt_wait, | |
1764 | .parent = &core_l4_ick, | |
1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1766 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1767 | .clkdm_name = "core_l4_clkdm", | |
1768 | .recalc = &followparent_recalc, | |
1769 | }; | |
1770 | ||
1771 | static struct clk mspro_ick = { | |
1772 | .name = "mspro_ick", | |
1773 | .ops = &clkops_omap2_dflt_wait, | |
1774 | .parent = &core_l4_ick, | |
1775 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1776 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1777 | .clkdm_name = "core_l4_clkdm", | |
1778 | .recalc = &followparent_recalc, | |
1779 | }; | |
1780 | ||
1781 | static struct clk hdq_ick = { | |
1782 | .name = "hdq_ick", | |
1783 | .ops = &clkops_omap2_dflt_wait, | |
1784 | .parent = &core_l4_ick, | |
1785 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1786 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1787 | .clkdm_name = "core_l4_clkdm", | |
1788 | .recalc = &followparent_recalc, | |
1789 | }; | |
1790 | ||
1791 | static struct clk mcspi4_ick = { | |
1792 | .name = "mcspi_ick", | |
1793 | .ops = &clkops_omap2_dflt_wait, | |
1794 | .id = 4, | |
1795 | .parent = &core_l4_ick, | |
1796 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1797 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1798 | .clkdm_name = "core_l4_clkdm", | |
1799 | .recalc = &followparent_recalc, | |
1800 | }; | |
1801 | ||
1802 | static struct clk mcspi3_ick = { | |
1803 | .name = "mcspi_ick", | |
1804 | .ops = &clkops_omap2_dflt_wait, | |
1805 | .id = 3, | |
1806 | .parent = &core_l4_ick, | |
1807 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1808 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1809 | .clkdm_name = "core_l4_clkdm", | |
1810 | .recalc = &followparent_recalc, | |
1811 | }; | |
1812 | ||
1813 | static struct clk mcspi2_ick = { | |
1814 | .name = "mcspi_ick", | |
1815 | .ops = &clkops_omap2_dflt_wait, | |
1816 | .id = 2, | |
1817 | .parent = &core_l4_ick, | |
1818 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1819 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1820 | .clkdm_name = "core_l4_clkdm", | |
1821 | .recalc = &followparent_recalc, | |
1822 | }; | |
1823 | ||
1824 | static struct clk mcspi1_ick = { | |
1825 | .name = "mcspi_ick", | |
1826 | .ops = &clkops_omap2_dflt_wait, | |
1827 | .id = 1, | |
1828 | .parent = &core_l4_ick, | |
1829 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1830 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1831 | .clkdm_name = "core_l4_clkdm", | |
1832 | .recalc = &followparent_recalc, | |
1833 | }; | |
1834 | ||
1835 | static struct clk i2c3_ick = { | |
1836 | .name = "i2c_ick", | |
1837 | .ops = &clkops_omap2_dflt_wait, | |
1838 | .id = 3, | |
1839 | .parent = &core_l4_ick, | |
1840 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1841 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1842 | .clkdm_name = "core_l4_clkdm", | |
1843 | .recalc = &followparent_recalc, | |
1844 | }; | |
1845 | ||
1846 | static struct clk i2c2_ick = { | |
1847 | .name = "i2c_ick", | |
1848 | .ops = &clkops_omap2_dflt_wait, | |
1849 | .id = 2, | |
1850 | .parent = &core_l4_ick, | |
1851 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1852 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1853 | .clkdm_name = "core_l4_clkdm", | |
1854 | .recalc = &followparent_recalc, | |
1855 | }; | |
1856 | ||
1857 | static struct clk i2c1_ick = { | |
1858 | .name = "i2c_ick", | |
1859 | .ops = &clkops_omap2_dflt_wait, | |
1860 | .id = 1, | |
1861 | .parent = &core_l4_ick, | |
1862 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1863 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1864 | .clkdm_name = "core_l4_clkdm", | |
1865 | .recalc = &followparent_recalc, | |
1866 | }; | |
1867 | ||
1868 | static struct clk uart2_ick = { | |
1869 | .name = "uart2_ick", | |
1870 | .ops = &clkops_omap2_dflt_wait, | |
1871 | .parent = &core_l4_ick, | |
1872 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1873 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1874 | .clkdm_name = "core_l4_clkdm", | |
1875 | .recalc = &followparent_recalc, | |
1876 | }; | |
1877 | ||
1878 | static struct clk uart1_ick = { | |
1879 | .name = "uart1_ick", | |
1880 | .ops = &clkops_omap2_dflt_wait, | |
1881 | .parent = &core_l4_ick, | |
1882 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1883 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1884 | .clkdm_name = "core_l4_clkdm", | |
1885 | .recalc = &followparent_recalc, | |
1886 | }; | |
1887 | ||
1888 | static struct clk gpt11_ick = { | |
1889 | .name = "gpt11_ick", | |
1890 | .ops = &clkops_omap2_dflt_wait, | |
1891 | .parent = &core_l4_ick, | |
1892 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1893 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1894 | .clkdm_name = "core_l4_clkdm", | |
1895 | .recalc = &followparent_recalc, | |
1896 | }; | |
1897 | ||
1898 | static struct clk gpt10_ick = { | |
1899 | .name = "gpt10_ick", | |
1900 | .ops = &clkops_omap2_dflt_wait, | |
1901 | .parent = &core_l4_ick, | |
1902 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1903 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1904 | .clkdm_name = "core_l4_clkdm", | |
1905 | .recalc = &followparent_recalc, | |
1906 | }; | |
1907 | ||
1908 | static struct clk mcbsp5_ick = { | |
1909 | .name = "mcbsp_ick", | |
1910 | .ops = &clkops_omap2_dflt_wait, | |
1911 | .id = 5, | |
1912 | .parent = &core_l4_ick, | |
1913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1914 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1915 | .clkdm_name = "core_l4_clkdm", | |
1916 | .recalc = &followparent_recalc, | |
1917 | }; | |
1918 | ||
1919 | static struct clk mcbsp1_ick = { | |
1920 | .name = "mcbsp_ick", | |
1921 | .ops = &clkops_omap2_dflt_wait, | |
1922 | .id = 1, | |
1923 | .parent = &core_l4_ick, | |
1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1925 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1926 | .clkdm_name = "core_l4_clkdm", | |
1927 | .recalc = &followparent_recalc, | |
1928 | }; | |
1929 | ||
1930 | static struct clk fac_ick = { | |
1931 | .name = "fac_ick", | |
1932 | .ops = &clkops_omap2_dflt_wait, | |
1933 | .parent = &core_l4_ick, | |
1934 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1935 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | |
1936 | .clkdm_name = "core_l4_clkdm", | |
1937 | .recalc = &followparent_recalc, | |
1938 | }; | |
1939 | ||
1940 | static struct clk mailboxes_ick = { | |
1941 | .name = "mailboxes_ick", | |
1942 | .ops = &clkops_omap2_dflt_wait, | |
1943 | .parent = &core_l4_ick, | |
1944 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1945 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
1946 | .clkdm_name = "core_l4_clkdm", | |
1947 | .recalc = &followparent_recalc, | |
1948 | }; | |
1949 | ||
1950 | static struct clk omapctrl_ick = { | |
1951 | .name = "omapctrl_ick", | |
1952 | .ops = &clkops_omap2_dflt_wait, | |
1953 | .parent = &core_l4_ick, | |
1954 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1955 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | |
1956 | .flags = ENABLE_ON_INIT, | |
1957 | .recalc = &followparent_recalc, | |
1958 | }; | |
1959 | ||
1960 | /* SSI_L4_ICK based clocks */ | |
1961 | ||
1962 | static struct clk ssi_l4_ick = { | |
1963 | .name = "ssi_l4_ick", | |
1964 | .ops = &clkops_null, | |
1965 | .parent = &l4_ick, | |
1966 | .clkdm_name = "core_l4_clkdm", | |
1967 | .recalc = &followparent_recalc, | |
1968 | }; | |
1969 | ||
1970 | static struct clk ssi_ick_3430es1 = { | |
1971 | .name = "ssi_ick", | |
1972 | .ops = &clkops_omap2_dflt, | |
1973 | .parent = &ssi_l4_ick, | |
1974 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1975 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1976 | .clkdm_name = "core_l4_clkdm", | |
1977 | .recalc = &followparent_recalc, | |
1978 | }; | |
1979 | ||
1980 | static struct clk ssi_ick_3430es2 = { | |
1981 | .name = "ssi_ick", | |
1982 | .ops = &clkops_omap3430es2_ssi_wait, | |
1983 | .parent = &ssi_l4_ick, | |
1984 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1985 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1986 | .clkdm_name = "core_l4_clkdm", | |
1987 | .recalc = &followparent_recalc, | |
1988 | }; | |
1989 | ||
1990 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | |
1991 | * but l4_ick makes more sense to me */ | |
1992 | ||
1993 | static const struct clksel usb_l4_clksel[] = { | |
1994 | { .parent = &l4_ick, .rates = div2_rates }, | |
1995 | { .parent = NULL }, | |
1996 | }; | |
1997 | ||
1998 | static struct clk usb_l4_ick = { | |
1999 | .name = "usb_l4_ick", | |
2000 | .ops = &clkops_omap2_dflt_wait, | |
2001 | .parent = &l4_ick, | |
2002 | .init = &omap2_init_clksel_parent, | |
2003 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
2004 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
2005 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
2006 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | |
2007 | .clksel = usb_l4_clksel, | |
2008 | .recalc = &omap2_clksel_recalc, | |
2009 | }; | |
2010 | ||
2011 | /* SECURITY_L4_ICK2 based clocks */ | |
2012 | ||
2013 | static struct clk security_l4_ick2 = { | |
2014 | .name = "security_l4_ick2", | |
2015 | .ops = &clkops_null, | |
2016 | .parent = &l4_ick, | |
2017 | .recalc = &followparent_recalc, | |
2018 | }; | |
2019 | ||
2020 | static struct clk aes1_ick = { | |
2021 | .name = "aes1_ick", | |
2022 | .ops = &clkops_omap2_dflt_wait, | |
2023 | .parent = &security_l4_ick2, | |
2024 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2025 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | |
2026 | .recalc = &followparent_recalc, | |
2027 | }; | |
2028 | ||
2029 | static struct clk rng_ick = { | |
2030 | .name = "rng_ick", | |
2031 | .ops = &clkops_omap2_dflt_wait, | |
2032 | .parent = &security_l4_ick2, | |
2033 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2034 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | |
2035 | .recalc = &followparent_recalc, | |
2036 | }; | |
2037 | ||
2038 | static struct clk sha11_ick = { | |
2039 | .name = "sha11_ick", | |
2040 | .ops = &clkops_omap2_dflt_wait, | |
2041 | .parent = &security_l4_ick2, | |
2042 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2043 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | |
2044 | .recalc = &followparent_recalc, | |
2045 | }; | |
2046 | ||
2047 | static struct clk des1_ick = { | |
2048 | .name = "des1_ick", | |
2049 | .ops = &clkops_omap2_dflt_wait, | |
2050 | .parent = &security_l4_ick2, | |
2051 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2052 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | |
2053 | .recalc = &followparent_recalc, | |
2054 | }; | |
2055 | ||
2056 | /* DSS */ | |
2057 | static struct clk dss1_alwon_fck_3430es1 = { | |
2058 | .name = "dss1_alwon_fck", | |
2059 | .ops = &clkops_omap2_dflt, | |
2060 | .parent = &dpll4_m4x2_ck, | |
2061 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2062 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
2063 | .clkdm_name = "dss_clkdm", | |
2064 | .recalc = &followparent_recalc, | |
2065 | }; | |
2066 | ||
2067 | static struct clk dss1_alwon_fck_3430es2 = { | |
2068 | .name = "dss1_alwon_fck", | |
2069 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2070 | .parent = &dpll4_m4x2_ck, | |
2071 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2072 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
2073 | .clkdm_name = "dss_clkdm", | |
2074 | .recalc = &followparent_recalc, | |
2075 | }; | |
2076 | ||
2077 | static struct clk dss_tv_fck = { | |
2078 | .name = "dss_tv_fck", | |
2079 | .ops = &clkops_omap2_dflt, | |
2080 | .parent = &omap_54m_fck, | |
2081 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2082 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
2083 | .clkdm_name = "dss_clkdm", | |
2084 | .recalc = &followparent_recalc, | |
2085 | }; | |
2086 | ||
2087 | static struct clk dss_96m_fck = { | |
2088 | .name = "dss_96m_fck", | |
2089 | .ops = &clkops_omap2_dflt, | |
2090 | .parent = &omap_96m_fck, | |
2091 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2092 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
2093 | .clkdm_name = "dss_clkdm", | |
2094 | .recalc = &followparent_recalc, | |
2095 | }; | |
2096 | ||
2097 | static struct clk dss2_alwon_fck = { | |
2098 | .name = "dss2_alwon_fck", | |
2099 | .ops = &clkops_omap2_dflt, | |
2100 | .parent = &sys_ck, | |
2101 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2102 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | |
2103 | .clkdm_name = "dss_clkdm", | |
2104 | .recalc = &followparent_recalc, | |
2105 | }; | |
2106 | ||
2107 | static struct clk dss_ick_3430es1 = { | |
2108 | /* Handles both L3 and L4 clocks */ | |
2109 | .name = "dss_ick", | |
2110 | .ops = &clkops_omap2_dflt, | |
2111 | .parent = &l4_ick, | |
2112 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | |
2113 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
2114 | .clkdm_name = "dss_clkdm", | |
2115 | .recalc = &followparent_recalc, | |
2116 | }; | |
2117 | ||
2118 | static struct clk dss_ick_3430es2 = { | |
2119 | /* Handles both L3 and L4 clocks */ | |
2120 | .name = "dss_ick", | |
2121 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2122 | .parent = &l4_ick, | |
2123 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | |
2124 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
2125 | .clkdm_name = "dss_clkdm", | |
2126 | .recalc = &followparent_recalc, | |
2127 | }; | |
2128 | ||
2129 | /* CAM */ | |
2130 | ||
2131 | static struct clk cam_mclk = { | |
2132 | .name = "cam_mclk", | |
2133 | .ops = &clkops_omap2_dflt, | |
2134 | .parent = &dpll4_m5x2_ck, | |
2135 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | |
2136 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2137 | .clkdm_name = "cam_clkdm", | |
2138 | .recalc = &followparent_recalc, | |
2139 | }; | |
2140 | ||
2141 | static struct clk cam_ick = { | |
2142 | /* Handles both L3 and L4 clocks */ | |
2143 | .name = "cam_ick", | |
2144 | .ops = &clkops_omap2_dflt, | |
2145 | .parent = &l4_ick, | |
2146 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | |
2147 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2148 | .clkdm_name = "cam_clkdm", | |
2149 | .recalc = &followparent_recalc, | |
2150 | }; | |
2151 | ||
2152 | static struct clk csi2_96m_fck = { | |
2153 | .name = "csi2_96m_fck", | |
2154 | .ops = &clkops_omap2_dflt, | |
2155 | .parent = &core_96m_fck, | |
2156 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | |
2157 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | |
2158 | .clkdm_name = "cam_clkdm", | |
2159 | .recalc = &followparent_recalc, | |
2160 | }; | |
2161 | ||
2162 | /* USBHOST - 3430ES2 only */ | |
2163 | ||
2164 | static struct clk usbhost_120m_fck = { | |
2165 | .name = "usbhost_120m_fck", | |
2166 | .ops = &clkops_omap2_dflt, | |
2167 | .parent = &dpll5_m2_ck, | |
2168 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
2169 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | |
2170 | .clkdm_name = "usbhost_clkdm", | |
2171 | .recalc = &followparent_recalc, | |
2172 | }; | |
2173 | ||
2174 | static struct clk usbhost_48m_fck = { | |
2175 | .name = "usbhost_48m_fck", | |
2176 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2177 | .parent = &omap_48m_fck, | |
2178 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
2179 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
2180 | .clkdm_name = "usbhost_clkdm", | |
2181 | .recalc = &followparent_recalc, | |
2182 | }; | |
2183 | ||
2184 | static struct clk usbhost_ick = { | |
2185 | /* Handles both L3 and L4 clocks */ | |
2186 | .name = "usbhost_ick", | |
2187 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2188 | .parent = &l4_ick, | |
2189 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | |
2190 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
2191 | .clkdm_name = "usbhost_clkdm", | |
2192 | .recalc = &followparent_recalc, | |
2193 | }; | |
2194 | ||
2195 | /* WKUP */ | |
2196 | ||
2197 | static const struct clksel_rate usim_96m_rates[] = { | |
2198 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2199 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2200 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | |
2201 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | |
2202 | { .div = 0 }, | |
2203 | }; | |
2204 | ||
2205 | static const struct clksel_rate usim_120m_rates[] = { | |
2206 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2207 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
2208 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | |
2209 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | |
2210 | { .div = 0 }, | |
2211 | }; | |
2212 | ||
2213 | static const struct clksel usim_clksel[] = { | |
2214 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | |
2215 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, | |
2216 | { .parent = &sys_ck, .rates = div2_rates }, | |
2217 | { .parent = NULL }, | |
2218 | }; | |
2219 | ||
2220 | /* 3430ES2 only */ | |
2221 | static struct clk usim_fck = { | |
2222 | .name = "usim_fck", | |
2223 | .ops = &clkops_omap2_dflt_wait, | |
2224 | .init = &omap2_init_clksel_parent, | |
2225 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2226 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2227 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2228 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | |
2229 | .clksel = usim_clksel, | |
2230 | .recalc = &omap2_clksel_recalc, | |
2231 | }; | |
2232 | ||
2233 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | |
2234 | static struct clk gpt1_fck = { | |
2235 | .name = "gpt1_fck", | |
2236 | .ops = &clkops_omap2_dflt_wait, | |
2237 | .init = &omap2_init_clksel_parent, | |
2238 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2239 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2240 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2241 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | |
2242 | .clksel = omap343x_gpt_clksel, | |
2243 | .clkdm_name = "wkup_clkdm", | |
2244 | .recalc = &omap2_clksel_recalc, | |
2245 | }; | |
2246 | ||
2247 | static struct clk wkup_32k_fck = { | |
2248 | .name = "wkup_32k_fck", | |
2249 | .ops = &clkops_null, | |
2250 | .parent = &omap_32k_fck, | |
2251 | .clkdm_name = "wkup_clkdm", | |
2252 | .recalc = &followparent_recalc, | |
2253 | }; | |
2254 | ||
2255 | static struct clk gpio1_dbck = { | |
2256 | .name = "gpio1_dbck", | |
2257 | .ops = &clkops_omap2_dflt, | |
2258 | .parent = &wkup_32k_fck, | |
2259 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2260 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2261 | .clkdm_name = "wkup_clkdm", | |
2262 | .recalc = &followparent_recalc, | |
2263 | }; | |
2264 | ||
2265 | static struct clk wdt2_fck = { | |
2266 | .name = "wdt2_fck", | |
2267 | .ops = &clkops_omap2_dflt_wait, | |
2268 | .parent = &wkup_32k_fck, | |
2269 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2270 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2271 | .clkdm_name = "wkup_clkdm", | |
2272 | .recalc = &followparent_recalc, | |
2273 | }; | |
2274 | ||
2275 | static struct clk wkup_l4_ick = { | |
2276 | .name = "wkup_l4_ick", | |
2277 | .ops = &clkops_null, | |
2278 | .parent = &sys_ck, | |
2279 | .clkdm_name = "wkup_clkdm", | |
2280 | .recalc = &followparent_recalc, | |
2281 | }; | |
2282 | ||
2283 | /* 3430ES2 only */ | |
2284 | /* Never specifically named in the TRM, so we have to infer a likely name */ | |
2285 | static struct clk usim_ick = { | |
2286 | .name = "usim_ick", | |
2287 | .ops = &clkops_omap2_dflt_wait, | |
2288 | .parent = &wkup_l4_ick, | |
2289 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2290 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2291 | .clkdm_name = "wkup_clkdm", | |
2292 | .recalc = &followparent_recalc, | |
2293 | }; | |
2294 | ||
2295 | static struct clk wdt2_ick = { | |
2296 | .name = "wdt2_ick", | |
2297 | .ops = &clkops_omap2_dflt_wait, | |
2298 | .parent = &wkup_l4_ick, | |
2299 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2300 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2301 | .clkdm_name = "wkup_clkdm", | |
2302 | .recalc = &followparent_recalc, | |
2303 | }; | |
2304 | ||
2305 | static struct clk wdt1_ick = { | |
2306 | .name = "wdt1_ick", | |
2307 | .ops = &clkops_omap2_dflt_wait, | |
2308 | .parent = &wkup_l4_ick, | |
2309 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2310 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | |
2311 | .clkdm_name = "wkup_clkdm", | |
2312 | .recalc = &followparent_recalc, | |
2313 | }; | |
2314 | ||
2315 | static struct clk gpio1_ick = { | |
2316 | .name = "gpio1_ick", | |
2317 | .ops = &clkops_omap2_dflt_wait, | |
2318 | .parent = &wkup_l4_ick, | |
2319 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2320 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2321 | .clkdm_name = "wkup_clkdm", | |
2322 | .recalc = &followparent_recalc, | |
2323 | }; | |
2324 | ||
2325 | static struct clk omap_32ksync_ick = { | |
2326 | .name = "omap_32ksync_ick", | |
2327 | .ops = &clkops_omap2_dflt_wait, | |
2328 | .parent = &wkup_l4_ick, | |
2329 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2330 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | |
2331 | .clkdm_name = "wkup_clkdm", | |
2332 | .recalc = &followparent_recalc, | |
2333 | }; | |
2334 | ||
2335 | /* XXX This clock no longer exists in 3430 TRM rev F */ | |
2336 | static struct clk gpt12_ick = { | |
2337 | .name = "gpt12_ick", | |
2338 | .ops = &clkops_omap2_dflt_wait, | |
2339 | .parent = &wkup_l4_ick, | |
2340 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2341 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | |
2342 | .clkdm_name = "wkup_clkdm", | |
2343 | .recalc = &followparent_recalc, | |
2344 | }; | |
2345 | ||
2346 | static struct clk gpt1_ick = { | |
2347 | .name = "gpt1_ick", | |
2348 | .ops = &clkops_omap2_dflt_wait, | |
2349 | .parent = &wkup_l4_ick, | |
2350 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2351 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2352 | .clkdm_name = "wkup_clkdm", | |
2353 | .recalc = &followparent_recalc, | |
2354 | }; | |
2355 | ||
2356 | ||
2357 | ||
2358 | /* PER clock domain */ | |
2359 | ||
2360 | static struct clk per_96m_fck = { | |
2361 | .name = "per_96m_fck", | |
2362 | .ops = &clkops_null, | |
2363 | .parent = &omap_96m_alwon_fck, | |
2364 | .clkdm_name = "per_clkdm", | |
2365 | .recalc = &followparent_recalc, | |
2366 | }; | |
2367 | ||
2368 | static struct clk per_48m_fck = { | |
2369 | .name = "per_48m_fck", | |
2370 | .ops = &clkops_null, | |
2371 | .parent = &omap_48m_fck, | |
2372 | .clkdm_name = "per_clkdm", | |
2373 | .recalc = &followparent_recalc, | |
2374 | }; | |
2375 | ||
2376 | static struct clk uart3_fck = { | |
2377 | .name = "uart3_fck", | |
2378 | .ops = &clkops_omap2_dflt_wait, | |
2379 | .parent = &per_48m_fck, | |
2380 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2381 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2382 | .clkdm_name = "per_clkdm", | |
2383 | .recalc = &followparent_recalc, | |
2384 | }; | |
2385 | ||
2386 | static struct clk gpt2_fck = { | |
2387 | .name = "gpt2_fck", | |
2388 | .ops = &clkops_omap2_dflt_wait, | |
2389 | .init = &omap2_init_clksel_parent, | |
2390 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2391 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2392 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2393 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | |
2394 | .clksel = omap343x_gpt_clksel, | |
2395 | .clkdm_name = "per_clkdm", | |
2396 | .recalc = &omap2_clksel_recalc, | |
2397 | }; | |
2398 | ||
2399 | static struct clk gpt3_fck = { | |
2400 | .name = "gpt3_fck", | |
2401 | .ops = &clkops_omap2_dflt_wait, | |
2402 | .init = &omap2_init_clksel_parent, | |
2403 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2404 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2405 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2406 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | |
2407 | .clksel = omap343x_gpt_clksel, | |
2408 | .clkdm_name = "per_clkdm", | |
2409 | .recalc = &omap2_clksel_recalc, | |
2410 | }; | |
2411 | ||
2412 | static struct clk gpt4_fck = { | |
2413 | .name = "gpt4_fck", | |
2414 | .ops = &clkops_omap2_dflt_wait, | |
2415 | .init = &omap2_init_clksel_parent, | |
2416 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2417 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2418 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2419 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | |
2420 | .clksel = omap343x_gpt_clksel, | |
2421 | .clkdm_name = "per_clkdm", | |
2422 | .recalc = &omap2_clksel_recalc, | |
2423 | }; | |
2424 | ||
2425 | static struct clk gpt5_fck = { | |
2426 | .name = "gpt5_fck", | |
2427 | .ops = &clkops_omap2_dflt_wait, | |
2428 | .init = &omap2_init_clksel_parent, | |
2429 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2430 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2431 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2432 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | |
2433 | .clksel = omap343x_gpt_clksel, | |
2434 | .clkdm_name = "per_clkdm", | |
2435 | .recalc = &omap2_clksel_recalc, | |
2436 | }; | |
2437 | ||
2438 | static struct clk gpt6_fck = { | |
2439 | .name = "gpt6_fck", | |
2440 | .ops = &clkops_omap2_dflt_wait, | |
2441 | .init = &omap2_init_clksel_parent, | |
2442 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2443 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2444 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2445 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | |
2446 | .clksel = omap343x_gpt_clksel, | |
2447 | .clkdm_name = "per_clkdm", | |
2448 | .recalc = &omap2_clksel_recalc, | |
2449 | }; | |
2450 | ||
2451 | static struct clk gpt7_fck = { | |
2452 | .name = "gpt7_fck", | |
2453 | .ops = &clkops_omap2_dflt_wait, | |
2454 | .init = &omap2_init_clksel_parent, | |
2455 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2456 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2457 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2458 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | |
2459 | .clksel = omap343x_gpt_clksel, | |
2460 | .clkdm_name = "per_clkdm", | |
2461 | .recalc = &omap2_clksel_recalc, | |
2462 | }; | |
2463 | ||
2464 | static struct clk gpt8_fck = { | |
2465 | .name = "gpt8_fck", | |
2466 | .ops = &clkops_omap2_dflt_wait, | |
2467 | .init = &omap2_init_clksel_parent, | |
2468 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2469 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2470 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2471 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | |
2472 | .clksel = omap343x_gpt_clksel, | |
2473 | .clkdm_name = "per_clkdm", | |
2474 | .recalc = &omap2_clksel_recalc, | |
2475 | }; | |
2476 | ||
2477 | static struct clk gpt9_fck = { | |
2478 | .name = "gpt9_fck", | |
2479 | .ops = &clkops_omap2_dflt_wait, | |
2480 | .init = &omap2_init_clksel_parent, | |
2481 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2482 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2483 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2484 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | |
2485 | .clksel = omap343x_gpt_clksel, | |
2486 | .clkdm_name = "per_clkdm", | |
2487 | .recalc = &omap2_clksel_recalc, | |
2488 | }; | |
2489 | ||
2490 | static struct clk per_32k_alwon_fck = { | |
2491 | .name = "per_32k_alwon_fck", | |
2492 | .ops = &clkops_null, | |
2493 | .parent = &omap_32k_fck, | |
2494 | .clkdm_name = "per_clkdm", | |
2495 | .recalc = &followparent_recalc, | |
2496 | }; | |
2497 | ||
2498 | static struct clk gpio6_dbck = { | |
2499 | .name = "gpio6_dbck", | |
2500 | .ops = &clkops_omap2_dflt, | |
2501 | .parent = &per_32k_alwon_fck, | |
2502 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2503 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2504 | .clkdm_name = "per_clkdm", | |
2505 | .recalc = &followparent_recalc, | |
2506 | }; | |
2507 | ||
2508 | static struct clk gpio5_dbck = { | |
2509 | .name = "gpio5_dbck", | |
2510 | .ops = &clkops_omap2_dflt, | |
2511 | .parent = &per_32k_alwon_fck, | |
2512 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2513 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2514 | .clkdm_name = "per_clkdm", | |
2515 | .recalc = &followparent_recalc, | |
2516 | }; | |
2517 | ||
2518 | static struct clk gpio4_dbck = { | |
2519 | .name = "gpio4_dbck", | |
2520 | .ops = &clkops_omap2_dflt, | |
2521 | .parent = &per_32k_alwon_fck, | |
2522 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2523 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2524 | .clkdm_name = "per_clkdm", | |
2525 | .recalc = &followparent_recalc, | |
2526 | }; | |
2527 | ||
2528 | static struct clk gpio3_dbck = { | |
2529 | .name = "gpio3_dbck", | |
2530 | .ops = &clkops_omap2_dflt, | |
2531 | .parent = &per_32k_alwon_fck, | |
2532 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2533 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2534 | .clkdm_name = "per_clkdm", | |
2535 | .recalc = &followparent_recalc, | |
2536 | }; | |
2537 | ||
2538 | static struct clk gpio2_dbck = { | |
2539 | .name = "gpio2_dbck", | |
2540 | .ops = &clkops_omap2_dflt, | |
2541 | .parent = &per_32k_alwon_fck, | |
2542 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2543 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
2544 | .clkdm_name = "per_clkdm", | |
2545 | .recalc = &followparent_recalc, | |
2546 | }; | |
2547 | ||
2548 | static struct clk wdt3_fck = { | |
2549 | .name = "wdt3_fck", | |
2550 | .ops = &clkops_omap2_dflt_wait, | |
2551 | .parent = &per_32k_alwon_fck, | |
2552 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2553 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2554 | .clkdm_name = "per_clkdm", | |
2555 | .recalc = &followparent_recalc, | |
2556 | }; | |
2557 | ||
2558 | static struct clk per_l4_ick = { | |
2559 | .name = "per_l4_ick", | |
2560 | .ops = &clkops_null, | |
2561 | .parent = &l4_ick, | |
2562 | .clkdm_name = "per_clkdm", | |
2563 | .recalc = &followparent_recalc, | |
2564 | }; | |
2565 | ||
2566 | static struct clk gpio6_ick = { | |
2567 | .name = "gpio6_ick", | |
2568 | .ops = &clkops_omap2_dflt_wait, | |
2569 | .parent = &per_l4_ick, | |
2570 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2571 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2572 | .clkdm_name = "per_clkdm", | |
2573 | .recalc = &followparent_recalc, | |
2574 | }; | |
2575 | ||
2576 | static struct clk gpio5_ick = { | |
2577 | .name = "gpio5_ick", | |
2578 | .ops = &clkops_omap2_dflt_wait, | |
2579 | .parent = &per_l4_ick, | |
2580 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2581 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2582 | .clkdm_name = "per_clkdm", | |
2583 | .recalc = &followparent_recalc, | |
2584 | }; | |
2585 | ||
2586 | static struct clk gpio4_ick = { | |
2587 | .name = "gpio4_ick", | |
2588 | .ops = &clkops_omap2_dflt_wait, | |
2589 | .parent = &per_l4_ick, | |
2590 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2591 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2592 | .clkdm_name = "per_clkdm", | |
2593 | .recalc = &followparent_recalc, | |
2594 | }; | |
2595 | ||
2596 | static struct clk gpio3_ick = { | |
2597 | .name = "gpio3_ick", | |
2598 | .ops = &clkops_omap2_dflt_wait, | |
2599 | .parent = &per_l4_ick, | |
2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2601 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2602 | .clkdm_name = "per_clkdm", | |
2603 | .recalc = &followparent_recalc, | |
2604 | }; | |
2605 | ||
2606 | static struct clk gpio2_ick = { | |
2607 | .name = "gpio2_ick", | |
2608 | .ops = &clkops_omap2_dflt_wait, | |
2609 | .parent = &per_l4_ick, | |
2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2611 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
2612 | .clkdm_name = "per_clkdm", | |
2613 | .recalc = &followparent_recalc, | |
2614 | }; | |
2615 | ||
2616 | static struct clk wdt3_ick = { | |
2617 | .name = "wdt3_ick", | |
2618 | .ops = &clkops_omap2_dflt_wait, | |
2619 | .parent = &per_l4_ick, | |
2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2621 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2622 | .clkdm_name = "per_clkdm", | |
2623 | .recalc = &followparent_recalc, | |
2624 | }; | |
2625 | ||
2626 | static struct clk uart3_ick = { | |
2627 | .name = "uart3_ick", | |
2628 | .ops = &clkops_omap2_dflt_wait, | |
2629 | .parent = &per_l4_ick, | |
2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2631 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2632 | .clkdm_name = "per_clkdm", | |
2633 | .recalc = &followparent_recalc, | |
2634 | }; | |
2635 | ||
2636 | static struct clk gpt9_ick = { | |
2637 | .name = "gpt9_ick", | |
2638 | .ops = &clkops_omap2_dflt_wait, | |
2639 | .parent = &per_l4_ick, | |
2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2641 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2642 | .clkdm_name = "per_clkdm", | |
2643 | .recalc = &followparent_recalc, | |
2644 | }; | |
2645 | ||
2646 | static struct clk gpt8_ick = { | |
2647 | .name = "gpt8_ick", | |
2648 | .ops = &clkops_omap2_dflt_wait, | |
2649 | .parent = &per_l4_ick, | |
2650 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2651 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2652 | .clkdm_name = "per_clkdm", | |
2653 | .recalc = &followparent_recalc, | |
2654 | }; | |
2655 | ||
2656 | static struct clk gpt7_ick = { | |
2657 | .name = "gpt7_ick", | |
2658 | .ops = &clkops_omap2_dflt_wait, | |
2659 | .parent = &per_l4_ick, | |
2660 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2661 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2662 | .clkdm_name = "per_clkdm", | |
2663 | .recalc = &followparent_recalc, | |
2664 | }; | |
2665 | ||
2666 | static struct clk gpt6_ick = { | |
2667 | .name = "gpt6_ick", | |
2668 | .ops = &clkops_omap2_dflt_wait, | |
2669 | .parent = &per_l4_ick, | |
2670 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2671 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2672 | .clkdm_name = "per_clkdm", | |
2673 | .recalc = &followparent_recalc, | |
2674 | }; | |
2675 | ||
2676 | static struct clk gpt5_ick = { | |
2677 | .name = "gpt5_ick", | |
2678 | .ops = &clkops_omap2_dflt_wait, | |
2679 | .parent = &per_l4_ick, | |
2680 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2681 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2682 | .clkdm_name = "per_clkdm", | |
2683 | .recalc = &followparent_recalc, | |
2684 | }; | |
2685 | ||
2686 | static struct clk gpt4_ick = { | |
2687 | .name = "gpt4_ick", | |
2688 | .ops = &clkops_omap2_dflt_wait, | |
2689 | .parent = &per_l4_ick, | |
2690 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2691 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2692 | .clkdm_name = "per_clkdm", | |
2693 | .recalc = &followparent_recalc, | |
2694 | }; | |
2695 | ||
2696 | static struct clk gpt3_ick = { | |
2697 | .name = "gpt3_ick", | |
2698 | .ops = &clkops_omap2_dflt_wait, | |
2699 | .parent = &per_l4_ick, | |
2700 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2701 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2702 | .clkdm_name = "per_clkdm", | |
2703 | .recalc = &followparent_recalc, | |
2704 | }; | |
2705 | ||
2706 | static struct clk gpt2_ick = { | |
2707 | .name = "gpt2_ick", | |
2708 | .ops = &clkops_omap2_dflt_wait, | |
2709 | .parent = &per_l4_ick, | |
2710 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2711 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2712 | .clkdm_name = "per_clkdm", | |
2713 | .recalc = &followparent_recalc, | |
2714 | }; | |
2715 | ||
2716 | static struct clk mcbsp2_ick = { | |
2717 | .name = "mcbsp_ick", | |
2718 | .ops = &clkops_omap2_dflt_wait, | |
2719 | .id = 2, | |
2720 | .parent = &per_l4_ick, | |
2721 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2722 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2723 | .clkdm_name = "per_clkdm", | |
2724 | .recalc = &followparent_recalc, | |
2725 | }; | |
2726 | ||
2727 | static struct clk mcbsp3_ick = { | |
2728 | .name = "mcbsp_ick", | |
2729 | .ops = &clkops_omap2_dflt_wait, | |
2730 | .id = 3, | |
2731 | .parent = &per_l4_ick, | |
2732 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2733 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2734 | .clkdm_name = "per_clkdm", | |
2735 | .recalc = &followparent_recalc, | |
2736 | }; | |
2737 | ||
2738 | static struct clk mcbsp4_ick = { | |
2739 | .name = "mcbsp_ick", | |
2740 | .ops = &clkops_omap2_dflt_wait, | |
2741 | .id = 4, | |
2742 | .parent = &per_l4_ick, | |
2743 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2744 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2745 | .clkdm_name = "per_clkdm", | |
2746 | .recalc = &followparent_recalc, | |
2747 | }; | |
2748 | ||
2749 | static const struct clksel mcbsp_234_clksel[] = { | |
073463ca | 2750 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
82e9bd58 PW |
2751 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
2752 | { .parent = NULL } | |
2753 | }; | |
2754 | ||
2755 | static struct clk mcbsp2_fck = { | |
2756 | .name = "mcbsp_fck", | |
2757 | .ops = &clkops_omap2_dflt_wait, | |
2758 | .id = 2, | |
2759 | .init = &omap2_init_clksel_parent, | |
2760 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2761 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2762 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
2763 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
2764 | .clksel = mcbsp_234_clksel, | |
2765 | .clkdm_name = "per_clkdm", | |
2766 | .recalc = &omap2_clksel_recalc, | |
2767 | }; | |
2768 | ||
2769 | static struct clk mcbsp3_fck = { | |
2770 | .name = "mcbsp_fck", | |
2771 | .ops = &clkops_omap2_dflt_wait, | |
2772 | .id = 3, | |
2773 | .init = &omap2_init_clksel_parent, | |
2774 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2775 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2776 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2777 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
2778 | .clksel = mcbsp_234_clksel, | |
2779 | .clkdm_name = "per_clkdm", | |
2780 | .recalc = &omap2_clksel_recalc, | |
2781 | }; | |
2782 | ||
2783 | static struct clk mcbsp4_fck = { | |
2784 | .name = "mcbsp_fck", | |
2785 | .ops = &clkops_omap2_dflt_wait, | |
2786 | .id = 4, | |
2787 | .init = &omap2_init_clksel_parent, | |
2788 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2789 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2790 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2791 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
2792 | .clksel = mcbsp_234_clksel, | |
2793 | .clkdm_name = "per_clkdm", | |
2794 | .recalc = &omap2_clksel_recalc, | |
2795 | }; | |
2796 | ||
2797 | /* EMU clocks */ | |
2798 | ||
2799 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | |
2800 | ||
2801 | static const struct clksel_rate emu_src_sys_rates[] = { | |
2802 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2803 | { .div = 0 }, | |
2804 | }; | |
2805 | ||
2806 | static const struct clksel_rate emu_src_core_rates[] = { | |
2807 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2808 | { .div = 0 }, | |
2809 | }; | |
2810 | ||
2811 | static const struct clksel_rate emu_src_per_rates[] = { | |
2812 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2813 | { .div = 0 }, | |
2814 | }; | |
2815 | ||
2816 | static const struct clksel_rate emu_src_mpu_rates[] = { | |
2817 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2818 | { .div = 0 }, | |
2819 | }; | |
2820 | ||
2821 | static const struct clksel emu_src_clksel[] = { | |
2822 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | |
2823 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | |
2824 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | |
2825 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | |
2826 | { .parent = NULL }, | |
2827 | }; | |
2828 | ||
2829 | /* | |
2830 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | |
2831 | * to switch the source of some of the EMU clocks. | |
2832 | * XXX Are there CLKEN bits for these EMU clks? | |
2833 | */ | |
2834 | static struct clk emu_src_ck = { | |
2835 | .name = "emu_src_ck", | |
2836 | .ops = &clkops_null, | |
2837 | .init = &omap2_init_clksel_parent, | |
2838 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2839 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | |
2840 | .clksel = emu_src_clksel, | |
2841 | .clkdm_name = "emu_clkdm", | |
2842 | .recalc = &omap2_clksel_recalc, | |
2843 | }; | |
2844 | ||
2845 | static const struct clksel_rate pclk_emu_rates[] = { | |
2846 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2847 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2848 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2849 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
2850 | { .div = 0 }, | |
2851 | }; | |
2852 | ||
2853 | static const struct clksel pclk_emu_clksel[] = { | |
2854 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | |
2855 | { .parent = NULL }, | |
2856 | }; | |
2857 | ||
2858 | static struct clk pclk_fck = { | |
2859 | .name = "pclk_fck", | |
2860 | .ops = &clkops_null, | |
2861 | .init = &omap2_init_clksel_parent, | |
2862 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2863 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | |
2864 | .clksel = pclk_emu_clksel, | |
2865 | .clkdm_name = "emu_clkdm", | |
2866 | .recalc = &omap2_clksel_recalc, | |
2867 | }; | |
2868 | ||
2869 | static const struct clksel_rate pclkx2_emu_rates[] = { | |
2870 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2871 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2872 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2873 | { .div = 0 }, | |
2874 | }; | |
2875 | ||
2876 | static const struct clksel pclkx2_emu_clksel[] = { | |
2877 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | |
2878 | { .parent = NULL }, | |
2879 | }; | |
2880 | ||
2881 | static struct clk pclkx2_fck = { | |
2882 | .name = "pclkx2_fck", | |
2883 | .ops = &clkops_null, | |
2884 | .init = &omap2_init_clksel_parent, | |
2885 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2886 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | |
2887 | .clksel = pclkx2_emu_clksel, | |
2888 | .clkdm_name = "emu_clkdm", | |
2889 | .recalc = &omap2_clksel_recalc, | |
2890 | }; | |
2891 | ||
2892 | static const struct clksel atclk_emu_clksel[] = { | |
2893 | { .parent = &emu_src_ck, .rates = div2_rates }, | |
2894 | { .parent = NULL }, | |
2895 | }; | |
2896 | ||
2897 | static struct clk atclk_fck = { | |
2898 | .name = "atclk_fck", | |
2899 | .ops = &clkops_null, | |
2900 | .init = &omap2_init_clksel_parent, | |
2901 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2902 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | |
2903 | .clksel = atclk_emu_clksel, | |
2904 | .clkdm_name = "emu_clkdm", | |
2905 | .recalc = &omap2_clksel_recalc, | |
2906 | }; | |
2907 | ||
2908 | static struct clk traceclk_src_fck = { | |
2909 | .name = "traceclk_src_fck", | |
2910 | .ops = &clkops_null, | |
2911 | .init = &omap2_init_clksel_parent, | |
2912 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2913 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | |
2914 | .clksel = emu_src_clksel, | |
2915 | .clkdm_name = "emu_clkdm", | |
2916 | .recalc = &omap2_clksel_recalc, | |
2917 | }; | |
2918 | ||
2919 | static const struct clksel_rate traceclk_rates[] = { | |
2920 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2921 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2922 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2923 | { .div = 0 }, | |
2924 | }; | |
2925 | ||
2926 | static const struct clksel traceclk_clksel[] = { | |
2927 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | |
2928 | { .parent = NULL }, | |
2929 | }; | |
2930 | ||
2931 | static struct clk traceclk_fck = { | |
2932 | .name = "traceclk_fck", | |
2933 | .ops = &clkops_null, | |
2934 | .init = &omap2_init_clksel_parent, | |
2935 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2936 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | |
2937 | .clksel = traceclk_clksel, | |
2938 | .clkdm_name = "emu_clkdm", | |
2939 | .recalc = &omap2_clksel_recalc, | |
2940 | }; | |
2941 | ||
2942 | /* SR clocks */ | |
2943 | ||
2944 | /* SmartReflex fclk (VDD1) */ | |
2945 | static struct clk sr1_fck = { | |
2946 | .name = "sr1_fck", | |
2947 | .ops = &clkops_omap2_dflt_wait, | |
2948 | .parent = &sys_ck, | |
2949 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2950 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | |
2951 | .recalc = &followparent_recalc, | |
2952 | }; | |
2953 | ||
2954 | /* SmartReflex fclk (VDD2) */ | |
2955 | static struct clk sr2_fck = { | |
2956 | .name = "sr2_fck", | |
2957 | .ops = &clkops_omap2_dflt_wait, | |
2958 | .parent = &sys_ck, | |
2959 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2960 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | |
2961 | .recalc = &followparent_recalc, | |
2962 | }; | |
2963 | ||
2964 | static struct clk sr_l4_ick = { | |
2965 | .name = "sr_l4_ick", | |
2966 | .ops = &clkops_null, /* RMK: missing? */ | |
2967 | .parent = &l4_ick, | |
2968 | .clkdm_name = "core_l4_clkdm", | |
2969 | .recalc = &followparent_recalc, | |
2970 | }; | |
2971 | ||
2972 | /* SECURE_32K_FCK clocks */ | |
2973 | ||
2974 | static struct clk gpt12_fck = { | |
2975 | .name = "gpt12_fck", | |
2976 | .ops = &clkops_null, | |
2977 | .parent = &secure_32k_fck, | |
2978 | .recalc = &followparent_recalc, | |
2979 | }; | |
2980 | ||
2981 | static struct clk wdt1_fck = { | |
2982 | .name = "wdt1_fck", | |
2983 | .ops = &clkops_null, | |
2984 | .parent = &secure_32k_fck, | |
2985 | .recalc = &followparent_recalc, | |
2986 | }; | |
2987 | ||
2988 | ||
2989 | /* | |
2990 | * clkdev | |
2991 | */ | |
2992 | ||
2993 | static struct omap_clk omap34xx_clks[] = { | |
2994 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | |
2995 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | |
2996 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | |
2997 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | |
2998 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | |
2999 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | |
3000 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | |
3001 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | |
3002 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | |
3003 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | |
3004 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | |
3005 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | |
3006 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | |
3007 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | |
3008 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | |
3009 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | |
3010 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | |
3011 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | |
3012 | CLK(NULL, "core_ck", &core_ck, CK_343X), | |
3013 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | |
3014 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | |
3015 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | |
3016 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | |
3017 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | |
3018 | CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | |
3019 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | |
3020 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | |
3021 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | |
3022 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | |
3023 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | |
3024 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | |
3025 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | |
3026 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | |
3027 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | |
3028 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | |
3029 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | |
3030 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | |
3031 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | |
3032 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | |
3033 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | |
3034 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | |
3035 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | |
3036 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | |
3037 | CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | |
3038 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | |
3039 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | |
3040 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | |
3041 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | |
3042 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | |
3043 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | |
3044 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | |
3045 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | |
3046 | CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | |
3047 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | |
3048 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | |
3049 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | |
3050 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | |
3051 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | |
3052 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | |
3053 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | |
3054 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | |
3055 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | |
3056 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | |
3057 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | |
3058 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | |
3059 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | |
3060 | CLK(NULL, "modem_fck", &modem_fck, CK_343X), | |
3061 | CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), | |
3062 | CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), | |
3063 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | |
3064 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | |
3065 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | |
3066 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | |
3067 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | |
3068 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | |
3069 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | |
3070 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | |
3071 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | |
3072 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | |
3073 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | |
3074 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | |
3075 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | |
3076 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | |
3077 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | |
3078 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | |
3079 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | |
3080 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | |
3081 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | |
3082 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | |
3083 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | |
3084 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | |
3085 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | |
3086 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | |
3087 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | |
3088 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), | |
3089 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), | |
3090 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), | |
3091 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), | |
3092 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | |
3093 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), | |
3094 | CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), | |
3095 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | |
3096 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | |
3097 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | |
3098 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | |
3099 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | |
3100 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | |
3101 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | |
3102 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | |
3103 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | |
3104 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | |
3105 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | |
3106 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | |
3107 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | |
3108 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | |
3109 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | |
3110 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | |
3111 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | |
3112 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | |
3113 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | |
3114 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | |
3115 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | |
3116 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | |
3117 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | |
3118 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | |
3119 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | |
3120 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | |
3121 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | |
3122 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | |
3123 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | |
3124 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | |
3125 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | |
3126 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | |
3127 | CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), | |
3128 | CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), | |
3129 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | |
3130 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | |
3131 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | |
3132 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | |
3133 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | |
3134 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | |
3135 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), | |
3136 | CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2), | |
3137 | CLK("omapdss", "tv_fck", &dss_tv_fck, CK_343X), | |
3138 | CLK("omapdss", "video_fck", &dss_96m_fck, CK_343X), | |
3139 | CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_343X), | |
3140 | CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), | |
3141 | CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2), | |
3142 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | |
3143 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | |
3144 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | |
3145 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | |
3146 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | |
3147 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | |
3148 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | |
3149 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | |
3150 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | |
3151 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | |
3152 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | |
3153 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | |
3154 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | |
3155 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | |
3156 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | |
3157 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | |
3158 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | |
3159 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | |
3160 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | |
3161 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | |
3162 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | |
3163 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | |
3164 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | |
3165 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | |
3166 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | |
3167 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | |
3168 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | |
3169 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | |
3170 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | |
3171 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | |
3172 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | |
3173 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | |
3174 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | |
3175 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | |
3176 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | |
3177 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | |
3178 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | |
3179 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | |
3180 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | |
3181 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | |
3182 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | |
3183 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | |
3184 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | |
3185 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | |
3186 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | |
3187 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | |
3188 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | |
3189 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | |
3190 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | |
3191 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | |
3192 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | |
3193 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | |
3194 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | |
3195 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | |
3196 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | |
3197 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | |
3198 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | |
3199 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | |
3200 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | |
3201 | CLK("etb", "emu_src_ck", &emu_src_ck, CK_343X), | |
3202 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | |
3203 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | |
3204 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | |
3205 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | |
3206 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | |
3207 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | |
3208 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | |
3209 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | |
3210 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | |
3211 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | |
3212 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | |
3213 | }; | |
3214 | ||
3215 | ||
3216 | int __init omap2_clk_init(void) | |
3217 | { | |
3218 | /* struct prcm_config *prcm; */ | |
3219 | struct omap_clk *c; | |
3220 | /* u32 clkrate; */ | |
3221 | u32 cpu_clkflg; | |
3222 | ||
3223 | if (cpu_is_omap34xx()) { | |
3224 | cpu_mask = RATE_IN_343X; | |
3225 | cpu_clkflg = CK_343X; | |
3226 | ||
3227 | /* | |
3228 | * Update this if there are further clock changes between ES2 | |
3229 | * and production parts | |
3230 | */ | |
3231 | if (omap_rev() == OMAP3430_REV_ES1_0) { | |
3232 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | |
3233 | cpu_clkflg |= CK_3430ES1; | |
3234 | } else { | |
3235 | cpu_mask |= RATE_IN_3430ES2; | |
3236 | cpu_clkflg |= CK_3430ES2; | |
3237 | } | |
3238 | } | |
3239 | ||
3240 | clk_init(&omap2_clk_functions); | |
3241 | ||
3242 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | |
3243 | clk_preinit(c->lk.clk); | |
3244 | ||
3245 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) | |
3246 | if (c->cpu & cpu_clkflg) { | |
3247 | clkdev_add(&c->lk); | |
3248 | clk_register(c->lk.clk); | |
3249 | omap2_init_clk_clkdm(c->lk.clk); | |
3250 | } | |
3251 | ||
3252 | /* REVISIT: Not yet ready for OMAP3 */ | |
3253 | #if 0 | |
3254 | /* Check the MPU rate set by bootloader */ | |
3255 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | |
3256 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
3257 | if (!(prcm->flags & cpu_mask)) | |
3258 | continue; | |
3259 | if (prcm->xtal_speed != sys_ck.rate) | |
3260 | continue; | |
3261 | if (prcm->dpll_speed <= clkrate) | |
3262 | break; | |
3263 | } | |
3264 | curr_prcm_set = prcm; | |
3265 | #endif | |
3266 | ||
3267 | recalculate_root_clocks(); | |
3268 | ||
3269 | printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " | |
3270 | "%ld.%01ld/%ld/%ld MHz\n", | |
3271 | (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, | |
3272 | (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); | |
3273 | ||
3274 | /* | |
3275 | * Only enable those clocks we will need, let the drivers | |
3276 | * enable other clocks as necessary | |
3277 | */ | |
3278 | clk_enable_init_clocks(); | |
3279 | ||
3280 | /* | |
3281 | * Lock DPLL5 and put it in autoidle. | |
3282 | */ | |
3283 | if (omap_rev() >= OMAP3430_REV_ES2_0) | |
3284 | omap3_clk_lock_dpll5(); | |
3285 | ||
3286 | /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ | |
3287 | sdrc_ick_p = clk_get(NULL, "sdrc_ick"); | |
3288 | arm_fck_p = clk_get(NULL, "arm_fck"); | |
3289 | ||
3290 | return 0; | |
3291 | } |