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Commit | Line | Data |
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972c5427 RN |
1 | /* |
2 | * OMAP4 Clock data | |
3 | * | |
54776050 RN |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
972c5427 RN |
6 | * |
7 | * Paul Walmsley (paul@pwsan.com) | |
8 | * Rajendra Nayak (rnayak@ti.com) | |
9 | * Benoit Cousson (b-cousson@ti.com) | |
10 | * | |
11 | * This file is automatically generated from the OMAP hardware databases. | |
12 | * We respectfully ask that any modifications to this file be coordinated | |
13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
14 | * authors above to ensure that the autogeneration scripts are kept | |
15 | * up-to-date with the file contents. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License version 2 as | |
19 | * published by the Free Software Foundation. | |
76cf5295 RN |
20 | * |
21 | * XXX Some of the ES1 clocks have been removed/changed; once support | |
22 | * is added for discriminating clocks by ES level, these should be added back | |
23 | * in. | |
972c5427 RN |
24 | */ |
25 | ||
26 | #include <linux/kernel.h> | |
93340a22 | 27 | #include <linux/list.h> |
972c5427 | 28 | #include <linux/clk.h> |
6f6f6a70 | 29 | #include <linux/io.h> |
ee0839c2 | 30 | |
972c5427 RN |
31 | #include <plat/clkdev_omap.h> |
32 | ||
dbc04161 | 33 | #include "soc.h" |
ee0839c2 | 34 | #include "iomap.h" |
972c5427 RN |
35 | #include "clock.h" |
36 | #include "clock44xx.h" | |
d198b514 PW |
37 | #include "cm1_44xx.h" |
38 | #include "cm2_44xx.h" | |
972c5427 | 39 | #include "cm-regbits-44xx.h" |
59fb659b | 40 | #include "prm44xx.h" |
972c5427 | 41 | #include "prm-regbits-44xx.h" |
4814ced5 | 42 | #include "control.h" |
e0cb70c5 | 43 | #include "scrm44xx.h" |
972c5427 | 44 | |
59fb659b PW |
45 | /* OMAP4 modulemode control */ |
46 | #define OMAP4430_MODULEMODE_HWCTRL 0 | |
47 | #define OMAP4430_MODULEMODE_SWCTRL 1 | |
48 | ||
972c5427 RN |
49 | /* Root clocks */ |
50 | ||
51 | static struct clk extalt_clkin_ck = { | |
52 | .name = "extalt_clkin_ck", | |
53 | .rate = 59000000, | |
54 | .ops = &clkops_null, | |
972c5427 RN |
55 | }; |
56 | ||
57 | static struct clk pad_clks_ck = { | |
58 | .name = "pad_clks_ck", | |
59 | .rate = 12000000, | |
7ecd4228 BC |
60 | .ops = &clkops_omap2_dflt, |
61 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
62 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, | |
972c5427 RN |
63 | }; |
64 | ||
65 | static struct clk pad_slimbus_core_clks_ck = { | |
66 | .name = "pad_slimbus_core_clks_ck", | |
67 | .rate = 12000000, | |
68 | .ops = &clkops_null, | |
972c5427 RN |
69 | }; |
70 | ||
71 | static struct clk secure_32k_clk_src_ck = { | |
72 | .name = "secure_32k_clk_src_ck", | |
73 | .rate = 32768, | |
74 | .ops = &clkops_null, | |
972c5427 RN |
75 | }; |
76 | ||
77 | static struct clk slimbus_clk = { | |
78 | .name = "slimbus_clk", | |
79 | .rate = 12000000, | |
7ecd4228 BC |
80 | .ops = &clkops_omap2_dflt, |
81 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, | |
82 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, | |
972c5427 RN |
83 | }; |
84 | ||
85 | static struct clk sys_32k_ck = { | |
86 | .name = "sys_32k_ck", | |
9a47d32d | 87 | .clkdm_name = "prm_clkdm", |
972c5427 RN |
88 | .rate = 32768, |
89 | .ops = &clkops_null, | |
972c5427 RN |
90 | }; |
91 | ||
92 | static struct clk virt_12000000_ck = { | |
93 | .name = "virt_12000000_ck", | |
94 | .ops = &clkops_null, | |
95 | .rate = 12000000, | |
96 | }; | |
97 | ||
98 | static struct clk virt_13000000_ck = { | |
99 | .name = "virt_13000000_ck", | |
100 | .ops = &clkops_null, | |
101 | .rate = 13000000, | |
102 | }; | |
103 | ||
104 | static struct clk virt_16800000_ck = { | |
105 | .name = "virt_16800000_ck", | |
106 | .ops = &clkops_null, | |
107 | .rate = 16800000, | |
108 | }; | |
109 | ||
972c5427 RN |
110 | static struct clk virt_27000000_ck = { |
111 | .name = "virt_27000000_ck", | |
112 | .ops = &clkops_null, | |
113 | .rate = 27000000, | |
114 | }; | |
115 | ||
116 | static struct clk virt_38400000_ck = { | |
117 | .name = "virt_38400000_ck", | |
118 | .ops = &clkops_null, | |
119 | .rate = 38400000, | |
120 | }; | |
121 | ||
972c5427 RN |
122 | static const struct clksel_rate div_1_5_rates[] = { |
123 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, | |
124 | { .div = 0 }, | |
125 | }; | |
126 | ||
127 | static const struct clksel_rate div_1_6_rates[] = { | |
128 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, | |
129 | { .div = 0 }, | |
130 | }; | |
131 | ||
132 | static const struct clksel_rate div_1_7_rates[] = { | |
133 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, | |
134 | { .div = 0 }, | |
135 | }; | |
136 | ||
137 | static const struct clksel sys_clkin_sel[] = { | |
138 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, | |
139 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, | |
140 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, | |
141 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, | |
142 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, | |
143 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, | |
144 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, | |
145 | { .parent = NULL }, | |
146 | }; | |
147 | ||
148 | static struct clk sys_clkin_ck = { | |
149 | .name = "sys_clkin_ck", | |
150 | .rate = 38400000, | |
151 | .clksel = sys_clkin_sel, | |
152 | .init = &omap2_init_clksel_parent, | |
153 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, | |
154 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, | |
155 | .ops = &clkops_null, | |
156 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
157 | }; |
158 | ||
76cf5295 RN |
159 | static struct clk tie_low_clock_ck = { |
160 | .name = "tie_low_clock_ck", | |
161 | .rate = 0, | |
162 | .ops = &clkops_null, | |
163 | }; | |
164 | ||
972c5427 RN |
165 | static struct clk utmi_phy_clkout_ck = { |
166 | .name = "utmi_phy_clkout_ck", | |
76cf5295 | 167 | .rate = 60000000, |
972c5427 | 168 | .ops = &clkops_null, |
972c5427 RN |
169 | }; |
170 | ||
171 | static struct clk xclk60mhsp1_ck = { | |
172 | .name = "xclk60mhsp1_ck", | |
76cf5295 | 173 | .rate = 60000000, |
972c5427 | 174 | .ops = &clkops_null, |
972c5427 RN |
175 | }; |
176 | ||
177 | static struct clk xclk60mhsp2_ck = { | |
178 | .name = "xclk60mhsp2_ck", | |
76cf5295 | 179 | .rate = 60000000, |
972c5427 | 180 | .ops = &clkops_null, |
972c5427 RN |
181 | }; |
182 | ||
183 | static struct clk xclk60motg_ck = { | |
184 | .name = "xclk60motg_ck", | |
185 | .rate = 60000000, | |
186 | .ops = &clkops_null, | |
972c5427 RN |
187 | }; |
188 | ||
189 | /* Module clocks and DPLL outputs */ | |
190 | ||
76cf5295 RN |
191 | static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { |
192 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
193 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
194 | { .parent = NULL }, |
195 | }; | |
196 | ||
76cf5295 RN |
197 | static struct clk abe_dpll_bypass_clk_mux_ck = { |
198 | .name = "abe_dpll_bypass_clk_mux_ck", | |
972c5427 | 199 | .parent = &sys_clkin_ck, |
972c5427 | 200 | .ops = &clkops_null, |
76cf5295 | 201 | .recalc = &followparent_recalc, |
972c5427 RN |
202 | }; |
203 | ||
204 | static struct clk abe_dpll_refclk_mux_ck = { | |
205 | .name = "abe_dpll_refclk_mux_ck", | |
76cf5295 RN |
206 | .parent = &sys_clkin_ck, |
207 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
972c5427 RN |
208 | .init = &omap2_init_clksel_parent, |
209 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, | |
210 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
211 | .ops = &clkops_null, | |
212 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
213 | }; |
214 | ||
215 | /* DPLL_ABE */ | |
216 | static struct dpll_data dpll_abe_dd = { | |
217 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, | |
76cf5295 | 218 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, |
972c5427 RN |
219 | .clk_ref = &abe_dpll_refclk_mux_ck, |
220 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, | |
221 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
222 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, | |
223 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, | |
224 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
225 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
226 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
227 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
228 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
628479a8 BC |
229 | .max_multiplier = 2047, |
230 | .max_divider = 128, | |
972c5427 RN |
231 | .min_divider = 1, |
232 | }; | |
233 | ||
234 | ||
235 | static struct clk dpll_abe_ck = { | |
236 | .name = "dpll_abe_ck", | |
237 | .parent = &abe_dpll_refclk_mux_ck, | |
238 | .dpll_data = &dpll_abe_dd, | |
911bd739 | 239 | .init = &omap2_init_dpll_parent, |
657ebfad | 240 | .ops = &clkops_omap3_noncore_dpll_ops, |
a1900f2e MT |
241 | .recalc = &omap4_dpll_regm4xen_recalc, |
242 | .round_rate = &omap4_dpll_regm4xen_round_rate, | |
972c5427 | 243 | .set_rate = &omap3_noncore_dpll_set_rate, |
972c5427 RN |
244 | }; |
245 | ||
032b5a7e TG |
246 | static struct clk dpll_abe_x2_ck = { |
247 | .name = "dpll_abe_x2_ck", | |
248 | .parent = &dpll_abe_ck, | |
7ecd4228 | 249 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
70db8a62 RN |
250 | .flags = CLOCK_CLKOUTX2, |
251 | .ops = &clkops_omap4_dpllmx_ops, | |
032b5a7e TG |
252 | .recalc = &omap3_clkoutx2_recalc, |
253 | }; | |
254 | ||
032b5a7e TG |
255 | static const struct clksel dpll_abe_m2x2_div[] = { |
256 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, | |
257 | { .parent = NULL }, | |
258 | }; | |
259 | ||
972c5427 RN |
260 | static struct clk dpll_abe_m2x2_ck = { |
261 | .name = "dpll_abe_m2x2_ck", | |
032b5a7e TG |
262 | .parent = &dpll_abe_x2_ck, |
263 | .clksel = dpll_abe_m2x2_div, | |
264 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, | |
265 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 266 | .ops = &clkops_omap4_dpllmx_ops, |
032b5a7e TG |
267 | .recalc = &omap2_clksel_recalc, |
268 | .round_rate = &omap2_clksel_round_rate, | |
269 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
270 | }; |
271 | ||
272 | static struct clk abe_24m_fclk = { | |
273 | .name = "abe_24m_fclk", | |
274 | .parent = &dpll_abe_m2x2_ck, | |
275 | .ops = &clkops_null, | |
f17f9726 JH |
276 | .fixed_div = 8, |
277 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
278 | }; |
279 | ||
280 | static const struct clksel_rate div3_1to4_rates[] = { | |
281 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
282 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
283 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
284 | { .div = 0 }, | |
285 | }; | |
286 | ||
287 | static const struct clksel abe_clk_div[] = { | |
288 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, | |
289 | { .parent = NULL }, | |
290 | }; | |
291 | ||
292 | static struct clk abe_clk = { | |
293 | .name = "abe_clk", | |
294 | .parent = &dpll_abe_m2x2_ck, | |
295 | .clksel = abe_clk_div, | |
296 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, | |
297 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, | |
298 | .ops = &clkops_null, | |
299 | .recalc = &omap2_clksel_recalc, | |
300 | .round_rate = &omap2_clksel_round_rate, | |
301 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
302 | }; |
303 | ||
76cf5295 RN |
304 | static const struct clksel_rate div2_1to2_rates[] = { |
305 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
306 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
307 | { .div = 0 }, | |
308 | }; | |
309 | ||
972c5427 RN |
310 | static const struct clksel aess_fclk_div[] = { |
311 | { .parent = &abe_clk, .rates = div2_1to2_rates }, | |
312 | { .parent = NULL }, | |
313 | }; | |
314 | ||
315 | static struct clk aess_fclk = { | |
316 | .name = "aess_fclk", | |
317 | .parent = &abe_clk, | |
318 | .clksel = aess_fclk_div, | |
319 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
320 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, | |
321 | .ops = &clkops_null, | |
322 | .recalc = &omap2_clksel_recalc, | |
323 | .round_rate = &omap2_clksel_round_rate, | |
324 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
325 | }; |
326 | ||
032b5a7e TG |
327 | static struct clk dpll_abe_m3x2_ck = { |
328 | .name = "dpll_abe_m3x2_ck", | |
329 | .parent = &dpll_abe_x2_ck, | |
330 | .clksel = dpll_abe_m2x2_div, | |
972c5427 RN |
331 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
332 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
70db8a62 | 333 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
334 | .recalc = &omap2_clksel_recalc, |
335 | .round_rate = &omap2_clksel_round_rate, | |
336 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
337 | }; |
338 | ||
339 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 340 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
032b5a7e | 341 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
342 | { .parent = NULL }, |
343 | }; | |
344 | ||
345 | static struct clk core_hsd_byp_clk_mux_ck = { | |
346 | .name = "core_hsd_byp_clk_mux_ck", | |
76cf5295 | 347 | .parent = &sys_clkin_ck, |
972c5427 RN |
348 | .clksel = core_hsd_byp_clk_mux_sel, |
349 | .init = &omap2_init_clksel_parent, | |
350 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
351 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
352 | .ops = &clkops_null, | |
353 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
354 | }; |
355 | ||
356 | /* DPLL_CORE */ | |
357 | static struct dpll_data dpll_core_dd = { | |
358 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, | |
359 | .clk_bypass = &core_hsd_byp_clk_mux_ck, | |
76cf5295 | 360 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
361 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, |
362 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
363 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, | |
364 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, | |
365 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
366 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
367 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
368 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
369 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
628479a8 BC |
370 | .max_multiplier = 2047, |
371 | .max_divider = 128, | |
972c5427 RN |
372 | .min_divider = 1, |
373 | }; | |
374 | ||
375 | ||
376 | static struct clk dpll_core_ck = { | |
377 | .name = "dpll_core_ck", | |
76cf5295 | 378 | .parent = &sys_clkin_ck, |
972c5427 | 379 | .dpll_data = &dpll_core_dd, |
911bd739 | 380 | .init = &omap2_init_dpll_parent, |
6c6f5a74 | 381 | .ops = &clkops_omap3_core_dpll_ops, |
972c5427 | 382 | .recalc = &omap3_dpll_recalc, |
972c5427 RN |
383 | }; |
384 | ||
032b5a7e TG |
385 | static struct clk dpll_core_x2_ck = { |
386 | .name = "dpll_core_x2_ck", | |
387 | .parent = &dpll_core_ck, | |
70db8a62 | 388 | .flags = CLOCK_CLKOUTX2, |
032b5a7e TG |
389 | .ops = &clkops_null, |
390 | .recalc = &omap3_clkoutx2_recalc, | |
391 | }; | |
392 | ||
393 | static const struct clksel dpll_core_m6x2_div[] = { | |
394 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
395 | { .parent = NULL }, |
396 | }; | |
397 | ||
032b5a7e TG |
398 | static struct clk dpll_core_m6x2_ck = { |
399 | .name = "dpll_core_m6x2_ck", | |
400 | .parent = &dpll_core_x2_ck, | |
401 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
402 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
403 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
70db8a62 | 404 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
405 | .recalc = &omap2_clksel_recalc, |
406 | .round_rate = &omap2_clksel_round_rate, | |
407 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
408 | }; |
409 | ||
410 | static const struct clksel dbgclk_mux_sel[] = { | |
411 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 412 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
413 | { .parent = NULL }, |
414 | }; | |
415 | ||
416 | static struct clk dbgclk_mux_ck = { | |
417 | .name = "dbgclk_mux_ck", | |
418 | .parent = &sys_clkin_ck, | |
419 | .ops = &clkops_null, | |
420 | .recalc = &followparent_recalc, | |
972c5427 RN |
421 | }; |
422 | ||
032b5a7e TG |
423 | static const struct clksel dpll_core_m2_div[] = { |
424 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, | |
425 | { .parent = NULL }, | |
426 | }; | |
427 | ||
972c5427 RN |
428 | static struct clk dpll_core_m2_ck = { |
429 | .name = "dpll_core_m2_ck", | |
430 | .parent = &dpll_core_ck, | |
032b5a7e | 431 | .clksel = dpll_core_m2_div, |
972c5427 RN |
432 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
433 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 434 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
435 | .recalc = &omap2_clksel_recalc, |
436 | .round_rate = &omap2_clksel_round_rate, | |
437 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
438 | }; |
439 | ||
440 | static struct clk ddrphy_ck = { | |
441 | .name = "ddrphy_ck", | |
442 | .parent = &dpll_core_m2_ck, | |
443 | .ops = &clkops_null, | |
9a47d32d | 444 | .clkdm_name = "l3_emif_clkdm", |
f17f9726 JH |
445 | .fixed_div = 2, |
446 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
447 | }; |
448 | ||
032b5a7e TG |
449 | static struct clk dpll_core_m5x2_ck = { |
450 | .name = "dpll_core_m5x2_ck", | |
451 | .parent = &dpll_core_x2_ck, | |
452 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
453 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
454 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
70db8a62 | 455 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
456 | .recalc = &omap2_clksel_recalc, |
457 | .round_rate = &omap2_clksel_round_rate, | |
458 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
459 | }; |
460 | ||
461 | static const struct clksel div_core_div[] = { | |
032b5a7e | 462 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
972c5427 RN |
463 | { .parent = NULL }, |
464 | }; | |
465 | ||
466 | static struct clk div_core_ck = { | |
467 | .name = "div_core_ck", | |
032b5a7e | 468 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
469 | .clksel = div_core_div, |
470 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
471 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, | |
472 | .ops = &clkops_null, | |
473 | .recalc = &omap2_clksel_recalc, | |
474 | .round_rate = &omap2_clksel_round_rate, | |
475 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
476 | }; |
477 | ||
478 | static const struct clksel_rate div4_1to8_rates[] = { | |
479 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
480 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
481 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, | |
482 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, | |
483 | { .div = 0 }, | |
484 | }; | |
485 | ||
486 | static const struct clksel div_iva_hs_clk_div[] = { | |
032b5a7e | 487 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
972c5427 RN |
488 | { .parent = NULL }, |
489 | }; | |
490 | ||
491 | static struct clk div_iva_hs_clk = { | |
492 | .name = "div_iva_hs_clk", | |
032b5a7e | 493 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
494 | .clksel = div_iva_hs_clk_div, |
495 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, | |
496 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
497 | .ops = &clkops_null, | |
498 | .recalc = &omap2_clksel_recalc, | |
499 | .round_rate = &omap2_clksel_round_rate, | |
500 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
501 | }; |
502 | ||
503 | static struct clk div_mpu_hs_clk = { | |
504 | .name = "div_mpu_hs_clk", | |
032b5a7e | 505 | .parent = &dpll_core_m5x2_ck, |
972c5427 RN |
506 | .clksel = div_iva_hs_clk_div, |
507 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, | |
508 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, | |
509 | .ops = &clkops_null, | |
510 | .recalc = &omap2_clksel_recalc, | |
511 | .round_rate = &omap2_clksel_round_rate, | |
512 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
513 | }; |
514 | ||
032b5a7e TG |
515 | static struct clk dpll_core_m4x2_ck = { |
516 | .name = "dpll_core_m4x2_ck", | |
517 | .parent = &dpll_core_x2_ck, | |
518 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
519 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
520 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
70db8a62 | 521 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
522 | .recalc = &omap2_clksel_recalc, |
523 | .round_rate = &omap2_clksel_round_rate, | |
524 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
525 | }; |
526 | ||
527 | static struct clk dll_clk_div_ck = { | |
528 | .name = "dll_clk_div_ck", | |
032b5a7e | 529 | .parent = &dpll_core_m4x2_ck, |
972c5427 | 530 | .ops = &clkops_null, |
f17f9726 JH |
531 | .fixed_div = 2, |
532 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
533 | }; |
534 | ||
032b5a7e TG |
535 | static const struct clksel dpll_abe_m2_div[] = { |
536 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, | |
537 | { .parent = NULL }, | |
538 | }; | |
539 | ||
972c5427 RN |
540 | static struct clk dpll_abe_m2_ck = { |
541 | .name = "dpll_abe_m2_ck", | |
542 | .parent = &dpll_abe_ck, | |
032b5a7e | 543 | .clksel = dpll_abe_m2_div, |
972c5427 RN |
544 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
545 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 546 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
547 | .recalc = &omap2_clksel_recalc, |
548 | .round_rate = &omap2_clksel_round_rate, | |
549 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
550 | }; |
551 | ||
032b5a7e TG |
552 | static struct clk dpll_core_m3x2_ck = { |
553 | .name = "dpll_core_m3x2_ck", | |
554 | .parent = &dpll_core_x2_ck, | |
555 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
556 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
557 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
cb13459b | 558 | .ops = &clkops_omap2_dflt, |
972c5427 RN |
559 | .recalc = &omap2_clksel_recalc, |
560 | .round_rate = &omap2_clksel_round_rate, | |
561 | .set_rate = &omap2_clksel_set_rate, | |
7ecd4228 BC |
562 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
563 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | |
972c5427 RN |
564 | }; |
565 | ||
032b5a7e TG |
566 | static struct clk dpll_core_m7x2_ck = { |
567 | .name = "dpll_core_m7x2_ck", | |
568 | .parent = &dpll_core_x2_ck, | |
569 | .clksel = dpll_core_m6x2_div, | |
972c5427 RN |
570 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
571 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
70db8a62 | 572 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
573 | .recalc = &omap2_clksel_recalc, |
574 | .round_rate = &omap2_clksel_round_rate, | |
575 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
576 | }; |
577 | ||
578 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 579 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
580 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, |
581 | { .parent = NULL }, | |
582 | }; | |
583 | ||
584 | static struct clk iva_hsd_byp_clk_mux_ck = { | |
585 | .name = "iva_hsd_byp_clk_mux_ck", | |
76cf5295 | 586 | .parent = &sys_clkin_ck, |
768ab94f JB |
587 | .clksel = iva_hsd_byp_clk_mux_sel, |
588 | .init = &omap2_init_clksel_parent, | |
589 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
590 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
972c5427 | 591 | .ops = &clkops_null, |
768ab94f | 592 | .recalc = &omap2_clksel_recalc, |
972c5427 RN |
593 | }; |
594 | ||
595 | /* DPLL_IVA */ | |
596 | static struct dpll_data dpll_iva_dd = { | |
597 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, | |
598 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, | |
76cf5295 | 599 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
600 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, |
601 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
602 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, | |
603 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, | |
604 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
605 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
606 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
607 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
608 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
628479a8 BC |
609 | .max_multiplier = 2047, |
610 | .max_divider = 128, | |
972c5427 RN |
611 | .min_divider = 1, |
612 | }; | |
613 | ||
614 | ||
615 | static struct clk dpll_iva_ck = { | |
616 | .name = "dpll_iva_ck", | |
76cf5295 | 617 | .parent = &sys_clkin_ck, |
972c5427 | 618 | .dpll_data = &dpll_iva_dd, |
911bd739 | 619 | .init = &omap2_init_dpll_parent, |
657ebfad | 620 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
621 | .recalc = &omap3_dpll_recalc, |
622 | .round_rate = &omap2_dpll_round_rate, | |
623 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
624 | }; |
625 | ||
032b5a7e TG |
626 | static struct clk dpll_iva_x2_ck = { |
627 | .name = "dpll_iva_x2_ck", | |
628 | .parent = &dpll_iva_ck, | |
70db8a62 | 629 | .flags = CLOCK_CLKOUTX2, |
032b5a7e TG |
630 | .ops = &clkops_null, |
631 | .recalc = &omap3_clkoutx2_recalc, | |
632 | }; | |
633 | ||
634 | static const struct clksel dpll_iva_m4x2_div[] = { | |
635 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, | |
972c5427 RN |
636 | { .parent = NULL }, |
637 | }; | |
638 | ||
032b5a7e TG |
639 | static struct clk dpll_iva_m4x2_ck = { |
640 | .name = "dpll_iva_m4x2_ck", | |
641 | .parent = &dpll_iva_x2_ck, | |
642 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
643 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
644 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
70db8a62 | 645 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
646 | .recalc = &omap2_clksel_recalc, |
647 | .round_rate = &omap2_clksel_round_rate, | |
648 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
649 | }; |
650 | ||
032b5a7e TG |
651 | static struct clk dpll_iva_m5x2_ck = { |
652 | .name = "dpll_iva_m5x2_ck", | |
653 | .parent = &dpll_iva_x2_ck, | |
654 | .clksel = dpll_iva_m4x2_div, | |
972c5427 RN |
655 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
656 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
70db8a62 | 657 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
658 | .recalc = &omap2_clksel_recalc, |
659 | .round_rate = &omap2_clksel_round_rate, | |
660 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
661 | }; |
662 | ||
663 | /* DPLL_MPU */ | |
664 | static struct dpll_data dpll_mpu_dd = { | |
665 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, | |
666 | .clk_bypass = &div_mpu_hs_clk, | |
76cf5295 | 667 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
668 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, |
669 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
670 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, | |
671 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, | |
672 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
673 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
674 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
675 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
676 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
628479a8 BC |
677 | .max_multiplier = 2047, |
678 | .max_divider = 128, | |
972c5427 RN |
679 | .min_divider = 1, |
680 | }; | |
681 | ||
682 | ||
683 | static struct clk dpll_mpu_ck = { | |
684 | .name = "dpll_mpu_ck", | |
76cf5295 | 685 | .parent = &sys_clkin_ck, |
972c5427 | 686 | .dpll_data = &dpll_mpu_dd, |
911bd739 | 687 | .init = &omap2_init_dpll_parent, |
657ebfad | 688 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
689 | .recalc = &omap3_dpll_recalc, |
690 | .round_rate = &omap2_dpll_round_rate, | |
691 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
692 | }; |
693 | ||
694 | static const struct clksel dpll_mpu_m2_div[] = { | |
695 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, | |
696 | { .parent = NULL }, | |
697 | }; | |
698 | ||
699 | static struct clk dpll_mpu_m2_ck = { | |
700 | .name = "dpll_mpu_m2_ck", | |
701 | .parent = &dpll_mpu_ck, | |
9a47d32d | 702 | .clkdm_name = "cm_clkdm", |
972c5427 RN |
703 | .clksel = dpll_mpu_m2_div, |
704 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, | |
705 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 706 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
707 | .recalc = &omap2_clksel_recalc, |
708 | .round_rate = &omap2_clksel_round_rate, | |
709 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
710 | }; |
711 | ||
712 | static struct clk per_hs_clk_div_ck = { | |
713 | .name = "per_hs_clk_div_ck", | |
032b5a7e | 714 | .parent = &dpll_abe_m3x2_ck, |
972c5427 | 715 | .ops = &clkops_null, |
f17f9726 JH |
716 | .fixed_div = 2, |
717 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
718 | }; |
719 | ||
720 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { | |
76cf5295 | 721 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
972c5427 RN |
722 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, |
723 | { .parent = NULL }, | |
724 | }; | |
725 | ||
726 | static struct clk per_hsd_byp_clk_mux_ck = { | |
727 | .name = "per_hsd_byp_clk_mux_ck", | |
76cf5295 | 728 | .parent = &sys_clkin_ck, |
972c5427 RN |
729 | .clksel = per_hsd_byp_clk_mux_sel, |
730 | .init = &omap2_init_clksel_parent, | |
731 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
732 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, | |
733 | .ops = &clkops_null, | |
734 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
735 | }; |
736 | ||
737 | /* DPLL_PER */ | |
738 | static struct dpll_data dpll_per_dd = { | |
739 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, | |
740 | .clk_bypass = &per_hsd_byp_clk_mux_ck, | |
76cf5295 | 741 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
742 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, |
743 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
744 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, | |
745 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, | |
746 | .mult_mask = OMAP4430_DPLL_MULT_MASK, | |
747 | .div1_mask = OMAP4430_DPLL_DIV_MASK, | |
748 | .enable_mask = OMAP4430_DPLL_EN_MASK, | |
749 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
750 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
628479a8 BC |
751 | .max_multiplier = 2047, |
752 | .max_divider = 128, | |
972c5427 RN |
753 | .min_divider = 1, |
754 | }; | |
755 | ||
756 | ||
757 | static struct clk dpll_per_ck = { | |
758 | .name = "dpll_per_ck", | |
76cf5295 | 759 | .parent = &sys_clkin_ck, |
972c5427 | 760 | .dpll_data = &dpll_per_dd, |
911bd739 | 761 | .init = &omap2_init_dpll_parent, |
657ebfad | 762 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
763 | .recalc = &omap3_dpll_recalc, |
764 | .round_rate = &omap2_dpll_round_rate, | |
765 | .set_rate = &omap3_noncore_dpll_set_rate, | |
972c5427 RN |
766 | }; |
767 | ||
768 | static const struct clksel dpll_per_m2_div[] = { | |
769 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, | |
770 | { .parent = NULL }, | |
771 | }; | |
772 | ||
773 | static struct clk dpll_per_m2_ck = { | |
774 | .name = "dpll_per_m2_ck", | |
775 | .parent = &dpll_per_ck, | |
776 | .clksel = dpll_per_m2_div, | |
777 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
778 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 779 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
780 | .recalc = &omap2_clksel_recalc, |
781 | .round_rate = &omap2_clksel_round_rate, | |
782 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
783 | }; |
784 | ||
032b5a7e TG |
785 | static struct clk dpll_per_x2_ck = { |
786 | .name = "dpll_per_x2_ck", | |
787 | .parent = &dpll_per_ck, | |
7ecd4228 | 788 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
70db8a62 RN |
789 | .flags = CLOCK_CLKOUTX2, |
790 | .ops = &clkops_omap4_dpllmx_ops, | |
032b5a7e TG |
791 | .recalc = &omap3_clkoutx2_recalc, |
792 | }; | |
793 | ||
794 | static const struct clksel dpll_per_m2x2_div[] = { | |
795 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, | |
796 | { .parent = NULL }, | |
797 | }; | |
798 | ||
972c5427 RN |
799 | static struct clk dpll_per_m2x2_ck = { |
800 | .name = "dpll_per_m2x2_ck", | |
032b5a7e TG |
801 | .parent = &dpll_per_x2_ck, |
802 | .clksel = dpll_per_m2x2_div, | |
803 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, | |
804 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, | |
70db8a62 | 805 | .ops = &clkops_omap4_dpllmx_ops, |
032b5a7e TG |
806 | .recalc = &omap2_clksel_recalc, |
807 | .round_rate = &omap2_clksel_round_rate, | |
808 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
809 | }; |
810 | ||
032b5a7e TG |
811 | static struct clk dpll_per_m3x2_ck = { |
812 | .name = "dpll_per_m3x2_ck", | |
813 | .parent = &dpll_per_x2_ck, | |
814 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
815 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
816 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, | |
cb13459b | 817 | .ops = &clkops_omap2_dflt, |
972c5427 RN |
818 | .recalc = &omap2_clksel_recalc, |
819 | .round_rate = &omap2_clksel_round_rate, | |
820 | .set_rate = &omap2_clksel_set_rate, | |
7ecd4228 BC |
821 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
822 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, | |
972c5427 RN |
823 | }; |
824 | ||
032b5a7e TG |
825 | static struct clk dpll_per_m4x2_ck = { |
826 | .name = "dpll_per_m4x2_ck", | |
827 | .parent = &dpll_per_x2_ck, | |
828 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
829 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
830 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, | |
70db8a62 | 831 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
832 | .recalc = &omap2_clksel_recalc, |
833 | .round_rate = &omap2_clksel_round_rate, | |
834 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
835 | }; |
836 | ||
032b5a7e TG |
837 | static struct clk dpll_per_m5x2_ck = { |
838 | .name = "dpll_per_m5x2_ck", | |
839 | .parent = &dpll_per_x2_ck, | |
840 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
841 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
842 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, | |
70db8a62 | 843 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
844 | .recalc = &omap2_clksel_recalc, |
845 | .round_rate = &omap2_clksel_round_rate, | |
846 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
847 | }; |
848 | ||
032b5a7e TG |
849 | static struct clk dpll_per_m6x2_ck = { |
850 | .name = "dpll_per_m6x2_ck", | |
851 | .parent = &dpll_per_x2_ck, | |
852 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
853 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
854 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, | |
70db8a62 | 855 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
856 | .recalc = &omap2_clksel_recalc, |
857 | .round_rate = &omap2_clksel_round_rate, | |
858 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
859 | }; |
860 | ||
032b5a7e TG |
861 | static struct clk dpll_per_m7x2_ck = { |
862 | .name = "dpll_per_m7x2_ck", | |
863 | .parent = &dpll_per_x2_ck, | |
864 | .clksel = dpll_per_m2x2_div, | |
972c5427 RN |
865 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
866 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, | |
70db8a62 | 867 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
868 | .recalc = &omap2_clksel_recalc, |
869 | .round_rate = &omap2_clksel_round_rate, | |
870 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
871 | }; |
872 | ||
972c5427 RN |
873 | static struct clk usb_hs_clk_div_ck = { |
874 | .name = "usb_hs_clk_div_ck", | |
032b5a7e | 875 | .parent = &dpll_abe_m3x2_ck, |
972c5427 | 876 | .ops = &clkops_null, |
f17f9726 JH |
877 | .fixed_div = 3, |
878 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
879 | }; |
880 | ||
881 | /* DPLL_USB */ | |
882 | static struct dpll_data dpll_usb_dd = { | |
883 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, | |
884 | .clk_bypass = &usb_hs_clk_div_ck, | |
a36795c1 | 885 | .flags = DPLL_J_TYPE, |
76cf5295 | 886 | .clk_ref = &sys_clkin_ck, |
972c5427 RN |
887 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
888 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | |
889 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, | |
890 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, | |
91a290c4 AP |
891 | .mult_mask = OMAP4430_DPLL_MULT_USB_MASK, |
892 | .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK, | |
972c5427 RN |
893 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
894 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, | |
895 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, | |
962519e0 | 896 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, |
628479a8 BC |
897 | .max_multiplier = 4095, |
898 | .max_divider = 256, | |
972c5427 RN |
899 | .min_divider = 1, |
900 | }; | |
901 | ||
902 | ||
903 | static struct clk dpll_usb_ck = { | |
904 | .name = "dpll_usb_ck", | |
76cf5295 | 905 | .parent = &sys_clkin_ck, |
972c5427 | 906 | .dpll_data = &dpll_usb_dd, |
911bd739 | 907 | .init = &omap2_init_dpll_parent, |
657ebfad | 908 | .ops = &clkops_omap3_noncore_dpll_ops, |
972c5427 RN |
909 | .recalc = &omap3_dpll_recalc, |
910 | .round_rate = &omap2_dpll_round_rate, | |
911 | .set_rate = &omap3_noncore_dpll_set_rate, | |
6c4a057b | 912 | .clkdm_name = "l3_init_clkdm", |
972c5427 RN |
913 | }; |
914 | ||
915 | static struct clk dpll_usb_clkdcoldo_ck = { | |
916 | .name = "dpll_usb_clkdcoldo_ck", | |
917 | .parent = &dpll_usb_ck, | |
70db8a62 | 918 | .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, |
7ecd4228 | 919 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 | 920 | .recalc = &followparent_recalc, |
972c5427 RN |
921 | }; |
922 | ||
923 | static const struct clksel dpll_usb_m2_div[] = { | |
924 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, | |
925 | { .parent = NULL }, | |
926 | }; | |
927 | ||
928 | static struct clk dpll_usb_m2_ck = { | |
929 | .name = "dpll_usb_m2_ck", | |
930 | .parent = &dpll_usb_ck, | |
931 | .clksel = dpll_usb_m2_div, | |
932 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, | |
933 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, | |
70db8a62 | 934 | .ops = &clkops_omap4_dpllmx_ops, |
972c5427 RN |
935 | .recalc = &omap2_clksel_recalc, |
936 | .round_rate = &omap2_clksel_round_rate, | |
937 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
938 | }; |
939 | ||
940 | static const struct clksel ducati_clk_mux_sel[] = { | |
941 | { .parent = &div_core_ck, .rates = div_1_0_rates }, | |
032b5a7e | 942 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
972c5427 RN |
943 | { .parent = NULL }, |
944 | }; | |
945 | ||
946 | static struct clk ducati_clk_mux_ck = { | |
947 | .name = "ducati_clk_mux_ck", | |
948 | .parent = &div_core_ck, | |
949 | .clksel = ducati_clk_mux_sel, | |
950 | .init = &omap2_init_clksel_parent, | |
951 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, | |
952 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
953 | .ops = &clkops_null, | |
954 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
955 | }; |
956 | ||
957 | static struct clk func_12m_fclk = { | |
958 | .name = "func_12m_fclk", | |
959 | .parent = &dpll_per_m2x2_ck, | |
960 | .ops = &clkops_null, | |
f17f9726 JH |
961 | .fixed_div = 16, |
962 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
963 | }; |
964 | ||
965 | static struct clk func_24m_clk = { | |
966 | .name = "func_24m_clk", | |
967 | .parent = &dpll_per_m2_ck, | |
968 | .ops = &clkops_null, | |
f17f9726 JH |
969 | .fixed_div = 4, |
970 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
971 | }; |
972 | ||
973 | static struct clk func_24mc_fclk = { | |
974 | .name = "func_24mc_fclk", | |
975 | .parent = &dpll_per_m2x2_ck, | |
976 | .ops = &clkops_null, | |
f17f9726 JH |
977 | .fixed_div = 8, |
978 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
979 | }; |
980 | ||
981 | static const struct clksel_rate div2_4to8_rates[] = { | |
982 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, | |
983 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
984 | { .div = 0 }, | |
985 | }; | |
986 | ||
987 | static const struct clksel func_48m_fclk_div[] = { | |
988 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, | |
989 | { .parent = NULL }, | |
990 | }; | |
991 | ||
992 | static struct clk func_48m_fclk = { | |
993 | .name = "func_48m_fclk", | |
994 | .parent = &dpll_per_m2x2_ck, | |
995 | .clksel = func_48m_fclk_div, | |
996 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
997 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
998 | .ops = &clkops_null, | |
999 | .recalc = &omap2_clksel_recalc, | |
1000 | .round_rate = &omap2_clksel_round_rate, | |
1001 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1002 | }; |
1003 | ||
1004 | static struct clk func_48mc_fclk = { | |
1005 | .name = "func_48mc_fclk", | |
1006 | .parent = &dpll_per_m2x2_ck, | |
1007 | .ops = &clkops_null, | |
f17f9726 JH |
1008 | .fixed_div = 4, |
1009 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
1010 | }; |
1011 | ||
1012 | static const struct clksel_rate div2_2to4_rates[] = { | |
1013 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, | |
1014 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, | |
1015 | { .div = 0 }, | |
1016 | }; | |
1017 | ||
1018 | static const struct clksel func_64m_fclk_div[] = { | |
032b5a7e | 1019 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
972c5427 RN |
1020 | { .parent = NULL }, |
1021 | }; | |
1022 | ||
1023 | static struct clk func_64m_fclk = { | |
1024 | .name = "func_64m_fclk", | |
032b5a7e | 1025 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1026 | .clksel = func_64m_fclk_div, |
1027 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1028 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1029 | .ops = &clkops_null, | |
1030 | .recalc = &omap2_clksel_recalc, | |
1031 | .round_rate = &omap2_clksel_round_rate, | |
1032 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1033 | }; |
1034 | ||
1035 | static const struct clksel func_96m_fclk_div[] = { | |
1036 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, | |
1037 | { .parent = NULL }, | |
1038 | }; | |
1039 | ||
1040 | static struct clk func_96m_fclk = { | |
1041 | .name = "func_96m_fclk", | |
1042 | .parent = &dpll_per_m2x2_ck, | |
1043 | .clksel = func_96m_fclk_div, | |
1044 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1045 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1046 | .ops = &clkops_null, | |
1047 | .recalc = &omap2_clksel_recalc, | |
1048 | .round_rate = &omap2_clksel_round_rate, | |
1049 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1050 | }; |
1051 | ||
972c5427 RN |
1052 | static const struct clksel_rate div2_1to8_rates[] = { |
1053 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
1054 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, | |
1055 | { .div = 0 }, | |
1056 | }; | |
1057 | ||
1058 | static const struct clksel init_60m_fclk_div[] = { | |
1059 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, | |
1060 | { .parent = NULL }, | |
1061 | }; | |
1062 | ||
1063 | static struct clk init_60m_fclk = { | |
1064 | .name = "init_60m_fclk", | |
1065 | .parent = &dpll_usb_m2_ck, | |
1066 | .clksel = init_60m_fclk_div, | |
1067 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, | |
1068 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1069 | .ops = &clkops_null, | |
1070 | .recalc = &omap2_clksel_recalc, | |
1071 | .round_rate = &omap2_clksel_round_rate, | |
1072 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1073 | }; |
1074 | ||
1075 | static const struct clksel l3_div_div[] = { | |
1076 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, | |
1077 | { .parent = NULL }, | |
1078 | }; | |
1079 | ||
1080 | static struct clk l3_div_ck = { | |
1081 | .name = "l3_div_ck", | |
1082 | .parent = &div_core_ck, | |
9a47d32d | 1083 | .clkdm_name = "cm_clkdm", |
972c5427 RN |
1084 | .clksel = l3_div_div, |
1085 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1086 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, | |
1087 | .ops = &clkops_null, | |
1088 | .recalc = &omap2_clksel_recalc, | |
1089 | .round_rate = &omap2_clksel_round_rate, | |
1090 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1091 | }; |
1092 | ||
1093 | static const struct clksel l4_div_div[] = { | |
1094 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, | |
1095 | { .parent = NULL }, | |
1096 | }; | |
1097 | ||
1098 | static struct clk l4_div_ck = { | |
1099 | .name = "l4_div_ck", | |
1100 | .parent = &l3_div_ck, | |
1101 | .clksel = l4_div_div, | |
1102 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, | |
1103 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, | |
1104 | .ops = &clkops_null, | |
1105 | .recalc = &omap2_clksel_recalc, | |
1106 | .round_rate = &omap2_clksel_round_rate, | |
1107 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1108 | }; |
1109 | ||
1110 | static struct clk lp_clk_div_ck = { | |
1111 | .name = "lp_clk_div_ck", | |
1112 | .parent = &dpll_abe_m2x2_ck, | |
1113 | .ops = &clkops_null, | |
f17f9726 JH |
1114 | .fixed_div = 16, |
1115 | .recalc = &omap_fixed_divisor_recalc, | |
972c5427 RN |
1116 | }; |
1117 | ||
1118 | static const struct clksel l4_wkup_clk_mux_sel[] = { | |
1119 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
1120 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, | |
1121 | { .parent = NULL }, | |
1122 | }; | |
1123 | ||
1124 | static struct clk l4_wkup_clk_mux_ck = { | |
1125 | .name = "l4_wkup_clk_mux_ck", | |
1126 | .parent = &sys_clkin_ck, | |
1127 | .clksel = l4_wkup_clk_mux_sel, | |
1128 | .init = &omap2_init_clksel_parent, | |
1129 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, | |
1130 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1131 | .ops = &clkops_null, | |
1132 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1133 | }; |
1134 | ||
cf2a82d7 JH |
1135 | static const struct clksel_rate div2_2to1_rates[] = { |
1136 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, | |
1137 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, | |
1138 | { .div = 0 }, | |
1139 | }; | |
1140 | ||
1141 | static const struct clksel ocp_abe_iclk_div[] = { | |
1142 | { .parent = &aess_fclk, .rates = div2_2to1_rates }, | |
1143 | { .parent = NULL }, | |
1144 | }; | |
1145 | ||
30c95692 SS |
1146 | static struct clk mpu_periphclk = { |
1147 | .name = "mpu_periphclk", | |
1148 | .parent = &dpll_mpu_ck, | |
1149 | .ops = &clkops_null, | |
1150 | .fixed_div = 2, | |
1151 | .recalc = &omap_fixed_divisor_recalc, | |
1152 | }; | |
1153 | ||
de474535 JH |
1154 | static struct clk ocp_abe_iclk = { |
1155 | .name = "ocp_abe_iclk", | |
1156 | .parent = &aess_fclk, | |
cf2a82d7 JH |
1157 | .clksel = ocp_abe_iclk_div, |
1158 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
1159 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, | |
de474535 | 1160 | .ops = &clkops_null, |
cf2a82d7 | 1161 | .recalc = &omap2_clksel_recalc, |
de474535 JH |
1162 | }; |
1163 | ||
1164 | static struct clk per_abe_24m_fclk = { | |
1165 | .name = "per_abe_24m_fclk", | |
1166 | .parent = &dpll_abe_m2_ck, | |
1167 | .ops = &clkops_null, | |
1168 | .fixed_div = 4, | |
1169 | .recalc = &omap_fixed_divisor_recalc, | |
1170 | }; | |
1171 | ||
972c5427 RN |
1172 | static const struct clksel per_abe_nc_fclk_div[] = { |
1173 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, | |
1174 | { .parent = NULL }, | |
1175 | }; | |
1176 | ||
1177 | static struct clk per_abe_nc_fclk = { | |
1178 | .name = "per_abe_nc_fclk", | |
1179 | .parent = &dpll_abe_m2_ck, | |
1180 | .clksel = per_abe_nc_fclk_div, | |
1181 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, | |
1182 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, | |
1183 | .ops = &clkops_null, | |
1184 | .recalc = &omap2_clksel_recalc, | |
1185 | .round_rate = &omap2_clksel_round_rate, | |
1186 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1187 | }; |
1188 | ||
972c5427 RN |
1189 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
1190 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, | |
032b5a7e | 1191 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
76cf5295 | 1192 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
972c5427 RN |
1193 | { .parent = NULL }, |
1194 | }; | |
1195 | ||
1196 | static struct clk pmd_stm_clock_mux_ck = { | |
1197 | .name = "pmd_stm_clock_mux_ck", | |
1198 | .parent = &sys_clkin_ck, | |
1199 | .ops = &clkops_null, | |
1200 | .recalc = &followparent_recalc, | |
972c5427 RN |
1201 | }; |
1202 | ||
1203 | static struct clk pmd_trace_clk_mux_ck = { | |
1204 | .name = "pmd_trace_clk_mux_ck", | |
1205 | .parent = &sys_clkin_ck, | |
1206 | .ops = &clkops_null, | |
1207 | .recalc = &followparent_recalc, | |
972c5427 RN |
1208 | }; |
1209 | ||
76cf5295 RN |
1210 | static const struct clksel syc_clk_div_div[] = { |
1211 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, | |
1212 | { .parent = NULL }, | |
1213 | }; | |
1214 | ||
972c5427 RN |
1215 | static struct clk syc_clk_div_ck = { |
1216 | .name = "syc_clk_div_ck", | |
1217 | .parent = &sys_clkin_ck, | |
76cf5295 | 1218 | .clksel = syc_clk_div_div, |
972c5427 RN |
1219 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, |
1220 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, | |
1221 | .ops = &clkops_null, | |
1222 | .recalc = &omap2_clksel_recalc, | |
1223 | .round_rate = &omap2_clksel_round_rate, | |
1224 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1225 | }; |
1226 | ||
1227 | /* Leaf clocks controlled by modules */ | |
1228 | ||
54776050 RN |
1229 | static struct clk aes1_fck = { |
1230 | .name = "aes1_fck", | |
972c5427 RN |
1231 | .ops = &clkops_omap2_dflt, |
1232 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, | |
1233 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1234 | .clkdm_name = "l4_secure_clkdm", | |
1235 | .parent = &l3_div_ck, | |
1236 | .recalc = &followparent_recalc, | |
1237 | }; | |
1238 | ||
54776050 RN |
1239 | static struct clk aes2_fck = { |
1240 | .name = "aes2_fck", | |
972c5427 RN |
1241 | .ops = &clkops_omap2_dflt, |
1242 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, | |
1243 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1244 | .clkdm_name = "l4_secure_clkdm", | |
1245 | .parent = &l3_div_ck, | |
1246 | .recalc = &followparent_recalc, | |
1247 | }; | |
1248 | ||
54776050 RN |
1249 | static struct clk aess_fck = { |
1250 | .name = "aess_fck", | |
972c5427 RN |
1251 | .ops = &clkops_omap2_dflt, |
1252 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, | |
1253 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1254 | .clkdm_name = "abe_clkdm", | |
1255 | .parent = &aess_fclk, | |
1256 | .recalc = &followparent_recalc, | |
1257 | }; | |
1258 | ||
1c03f42f BC |
1259 | static struct clk bandgap_fclk = { |
1260 | .name = "bandgap_fclk", | |
1261 | .ops = &clkops_omap2_dflt, | |
1262 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
1263 | .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, | |
1264 | .clkdm_name = "l4_wkup_clkdm", | |
1265 | .parent = &sys_32k_ck, | |
1266 | .recalc = &followparent_recalc, | |
1267 | }; | |
1268 | ||
54776050 RN |
1269 | static struct clk des3des_fck = { |
1270 | .name = "des3des_fck", | |
972c5427 RN |
1271 | .ops = &clkops_omap2_dflt, |
1272 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, | |
1273 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1274 | .clkdm_name = "l4_secure_clkdm", | |
1275 | .parent = &l4_div_ck, | |
1276 | .recalc = &followparent_recalc, | |
1277 | }; | |
1278 | ||
1279 | static const struct clksel dmic_sync_mux_sel[] = { | |
1280 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, | |
1281 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, | |
1282 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, | |
1283 | { .parent = NULL }, | |
1284 | }; | |
1285 | ||
1286 | static struct clk dmic_sync_mux_ck = { | |
1287 | .name = "dmic_sync_mux_ck", | |
1288 | .parent = &abe_24m_fclk, | |
1289 | .clksel = dmic_sync_mux_sel, | |
1290 | .init = &omap2_init_clksel_parent, | |
1291 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1292 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1293 | .ops = &clkops_null, | |
1294 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1295 | }; |
1296 | ||
1297 | static const struct clksel func_dmic_abe_gfclk_sel[] = { | |
1298 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, | |
1299 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1300 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1301 | { .parent = NULL }, | |
1302 | }; | |
1303 | ||
54776050 RN |
1304 | /* Merged func_dmic_abe_gfclk into dmic */ |
1305 | static struct clk dmic_fck = { | |
1306 | .name = "dmic_fck", | |
972c5427 RN |
1307 | .parent = &dmic_sync_mux_ck, |
1308 | .clksel = func_dmic_abe_gfclk_sel, | |
1309 | .init = &omap2_init_clksel_parent, | |
1310 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, | |
1311 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1312 | .ops = &clkops_omap2_dflt, | |
1313 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1314 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
1315 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1316 | .clkdm_name = "abe_clkdm", | |
1317 | }; | |
1318 | ||
0e433271 BC |
1319 | static struct clk dsp_fck = { |
1320 | .name = "dsp_fck", | |
1321 | .ops = &clkops_omap2_dflt, | |
1322 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, | |
1323 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1324 | .clkdm_name = "tesla_clkdm", | |
032b5a7e | 1325 | .parent = &dpll_iva_m4x2_ck, |
0e433271 BC |
1326 | .recalc = &followparent_recalc, |
1327 | }; | |
1328 | ||
1c03f42f BC |
1329 | static struct clk dss_sys_clk = { |
1330 | .name = "dss_sys_clk", | |
1331 | .ops = &clkops_omap2_dflt, | |
1332 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1333 | .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, | |
1334 | .clkdm_name = "l3_dss_clkdm", | |
1335 | .parent = &syc_clk_div_ck, | |
1336 | .recalc = &followparent_recalc, | |
1337 | }; | |
1338 | ||
1339 | static struct clk dss_tv_clk = { | |
1340 | .name = "dss_tv_clk", | |
1341 | .ops = &clkops_omap2_dflt, | |
1342 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1343 | .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, | |
1344 | .clkdm_name = "l3_dss_clkdm", | |
1345 | .parent = &extalt_clkin_ck, | |
1346 | .recalc = &followparent_recalc, | |
1347 | }; | |
1348 | ||
1349 | static struct clk dss_dss_clk = { | |
1350 | .name = "dss_dss_clk", | |
1351 | .ops = &clkops_omap2_dflt, | |
1352 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1353 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, | |
1354 | .clkdm_name = "l3_dss_clkdm", | |
032b5a7e | 1355 | .parent = &dpll_per_m5x2_ck, |
1c03f42f BC |
1356 | .recalc = &followparent_recalc, |
1357 | }; | |
1358 | ||
257d643d | 1359 | static const struct clksel_rate div3_8to32_rates[] = { |
52a3a4d4 PW |
1360 | { .div = 8, .val = 0, .flags = RATE_IN_4460 }, |
1361 | { .div = 16, .val = 1, .flags = RATE_IN_4460 }, | |
1362 | { .div = 32, .val = 2, .flags = RATE_IN_4460 }, | |
257d643d RN |
1363 | { .div = 0 }, |
1364 | }; | |
1365 | ||
1366 | static const struct clksel div_ts_div[] = { | |
1367 | { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, | |
1368 | { .parent = NULL }, | |
1369 | }; | |
1370 | ||
1371 | static struct clk div_ts_ck = { | |
1372 | .name = "div_ts_ck", | |
1373 | .parent = &l4_wkup_clk_mux_ck, | |
1374 | .clksel = div_ts_div, | |
1375 | .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
1376 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, | |
1377 | .ops = &clkops_null, | |
1378 | .recalc = &omap2_clksel_recalc, | |
1379 | .round_rate = &omap2_clksel_round_rate, | |
1380 | .set_rate = &omap2_clksel_set_rate, | |
1381 | }; | |
1382 | ||
1383 | static struct clk bandgap_ts_fclk = { | |
1384 | .name = "bandgap_ts_fclk", | |
1385 | .ops = &clkops_omap2_dflt, | |
1386 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, | |
1387 | .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, | |
1388 | .clkdm_name = "l4_wkup_clkdm", | |
1389 | .parent = &div_ts_ck, | |
1390 | .recalc = &followparent_recalc, | |
1391 | }; | |
1392 | ||
1c03f42f BC |
1393 | static struct clk dss_48mhz_clk = { |
1394 | .name = "dss_48mhz_clk", | |
1395 | .ops = &clkops_omap2_dflt, | |
1396 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1397 | .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, | |
1398 | .clkdm_name = "l3_dss_clkdm", | |
1399 | .parent = &func_48mc_fclk, | |
1400 | .recalc = &followparent_recalc, | |
1401 | }; | |
1402 | ||
54776050 RN |
1403 | static struct clk dss_fck = { |
1404 | .name = "dss_fck", | |
972c5427 RN |
1405 | .ops = &clkops_omap2_dflt, |
1406 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, | |
1407 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1408 | .clkdm_name = "l3_dss_clkdm", | |
1409 | .parent = &l3_div_ck, | |
1410 | .recalc = &followparent_recalc, | |
1411 | }; | |
1412 | ||
0e433271 BC |
1413 | static struct clk efuse_ctrl_cust_fck = { |
1414 | .name = "efuse_ctrl_cust_fck", | |
972c5427 | 1415 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
1416 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
1417 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1418 | .clkdm_name = "l4_cefuse_clkdm", | |
1419 | .parent = &sys_clkin_ck, | |
972c5427 RN |
1420 | .recalc = &followparent_recalc, |
1421 | }; | |
1422 | ||
0e433271 BC |
1423 | static struct clk emif1_fck = { |
1424 | .name = "emif1_fck", | |
972c5427 RN |
1425 | .ops = &clkops_omap2_dflt, |
1426 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, | |
1427 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1428 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1429 | .clkdm_name = "l3_emif_clkdm", |
1430 | .parent = &ddrphy_ck, | |
1431 | .recalc = &followparent_recalc, | |
1432 | }; | |
1433 | ||
0e433271 BC |
1434 | static struct clk emif2_fck = { |
1435 | .name = "emif2_fck", | |
972c5427 RN |
1436 | .ops = &clkops_omap2_dflt, |
1437 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, | |
1438 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
090830b4 | 1439 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1440 | .clkdm_name = "l3_emif_clkdm", |
1441 | .parent = &ddrphy_ck, | |
1442 | .recalc = &followparent_recalc, | |
1443 | }; | |
1444 | ||
1445 | static const struct clksel fdif_fclk_div[] = { | |
032b5a7e | 1446 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
972c5427 RN |
1447 | { .parent = NULL }, |
1448 | }; | |
1449 | ||
54776050 RN |
1450 | /* Merged fdif_fclk into fdif */ |
1451 | static struct clk fdif_fck = { | |
1452 | .name = "fdif_fck", | |
032b5a7e | 1453 | .parent = &dpll_per_m4x2_ck, |
972c5427 RN |
1454 | .clksel = fdif_fclk_div, |
1455 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, | |
1456 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, | |
1457 | .ops = &clkops_omap2_dflt, | |
1458 | .recalc = &omap2_clksel_recalc, | |
1459 | .round_rate = &omap2_clksel_round_rate, | |
1460 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1461 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
1462 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1463 | .clkdm_name = "iss_clkdm", | |
1464 | }; | |
1465 | ||
0e433271 BC |
1466 | static struct clk fpka_fck = { |
1467 | .name = "fpka_fck", | |
972c5427 | 1468 | .ops = &clkops_omap2_dflt, |
0e433271 | 1469 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
972c5427 | 1470 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 BC |
1471 | .clkdm_name = "l4_secure_clkdm", |
1472 | .parent = &l4_div_ck, | |
1473 | .recalc = &followparent_recalc, | |
972c5427 RN |
1474 | }; |
1475 | ||
1c03f42f BC |
1476 | static struct clk gpio1_dbclk = { |
1477 | .name = "gpio1_dbclk", | |
1478 | .ops = &clkops_omap2_dflt, | |
1479 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1480 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1481 | .clkdm_name = "l4_wkup_clkdm", | |
1482 | .parent = &sys_32k_ck, | |
1483 | .recalc = &followparent_recalc, | |
1484 | }; | |
1485 | ||
54776050 RN |
1486 | static struct clk gpio1_ick = { |
1487 | .name = "gpio1_ick", | |
972c5427 RN |
1488 | .ops = &clkops_omap2_dflt, |
1489 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, | |
1490 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1491 | .clkdm_name = "l4_wkup_clkdm", | |
1492 | .parent = &l4_wkup_clk_mux_ck, | |
1493 | .recalc = &followparent_recalc, | |
1494 | }; | |
1495 | ||
1c03f42f BC |
1496 | static struct clk gpio2_dbclk = { |
1497 | .name = "gpio2_dbclk", | |
1498 | .ops = &clkops_omap2_dflt, | |
1499 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1500 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1501 | .clkdm_name = "l4_per_clkdm", | |
1502 | .parent = &sys_32k_ck, | |
1503 | .recalc = &followparent_recalc, | |
1504 | }; | |
1505 | ||
54776050 RN |
1506 | static struct clk gpio2_ick = { |
1507 | .name = "gpio2_ick", | |
972c5427 RN |
1508 | .ops = &clkops_omap2_dflt, |
1509 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, | |
1510 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1511 | .clkdm_name = "l4_per_clkdm", | |
1512 | .parent = &l4_div_ck, | |
1513 | .recalc = &followparent_recalc, | |
1514 | }; | |
1515 | ||
1c03f42f BC |
1516 | static struct clk gpio3_dbclk = { |
1517 | .name = "gpio3_dbclk", | |
1518 | .ops = &clkops_omap2_dflt, | |
1519 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1520 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1521 | .clkdm_name = "l4_per_clkdm", | |
1522 | .parent = &sys_32k_ck, | |
1523 | .recalc = &followparent_recalc, | |
1524 | }; | |
1525 | ||
54776050 RN |
1526 | static struct clk gpio3_ick = { |
1527 | .name = "gpio3_ick", | |
972c5427 RN |
1528 | .ops = &clkops_omap2_dflt, |
1529 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, | |
1530 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1531 | .clkdm_name = "l4_per_clkdm", | |
1532 | .parent = &l4_div_ck, | |
1533 | .recalc = &followparent_recalc, | |
1534 | }; | |
1535 | ||
1c03f42f BC |
1536 | static struct clk gpio4_dbclk = { |
1537 | .name = "gpio4_dbclk", | |
1538 | .ops = &clkops_omap2_dflt, | |
1539 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1540 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1541 | .clkdm_name = "l4_per_clkdm", | |
1542 | .parent = &sys_32k_ck, | |
1543 | .recalc = &followparent_recalc, | |
1544 | }; | |
1545 | ||
54776050 RN |
1546 | static struct clk gpio4_ick = { |
1547 | .name = "gpio4_ick", | |
972c5427 RN |
1548 | .ops = &clkops_omap2_dflt, |
1549 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, | |
1550 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1551 | .clkdm_name = "l4_per_clkdm", | |
1552 | .parent = &l4_div_ck, | |
1553 | .recalc = &followparent_recalc, | |
1554 | }; | |
1555 | ||
1c03f42f BC |
1556 | static struct clk gpio5_dbclk = { |
1557 | .name = "gpio5_dbclk", | |
1558 | .ops = &clkops_omap2_dflt, | |
1559 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1560 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1561 | .clkdm_name = "l4_per_clkdm", | |
1562 | .parent = &sys_32k_ck, | |
1563 | .recalc = &followparent_recalc, | |
1564 | }; | |
1565 | ||
54776050 RN |
1566 | static struct clk gpio5_ick = { |
1567 | .name = "gpio5_ick", | |
972c5427 RN |
1568 | .ops = &clkops_omap2_dflt, |
1569 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, | |
1570 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1571 | .clkdm_name = "l4_per_clkdm", | |
1572 | .parent = &l4_div_ck, | |
1573 | .recalc = &followparent_recalc, | |
1574 | }; | |
1575 | ||
1c03f42f BC |
1576 | static struct clk gpio6_dbclk = { |
1577 | .name = "gpio6_dbclk", | |
1578 | .ops = &clkops_omap2_dflt, | |
1579 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1580 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, | |
1581 | .clkdm_name = "l4_per_clkdm", | |
1582 | .parent = &sys_32k_ck, | |
1583 | .recalc = &followparent_recalc, | |
1584 | }; | |
1585 | ||
54776050 RN |
1586 | static struct clk gpio6_ick = { |
1587 | .name = "gpio6_ick", | |
972c5427 RN |
1588 | .ops = &clkops_omap2_dflt, |
1589 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, | |
1590 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1591 | .clkdm_name = "l4_per_clkdm", | |
1592 | .parent = &l4_div_ck, | |
1593 | .recalc = &followparent_recalc, | |
1594 | }; | |
1595 | ||
54776050 RN |
1596 | static struct clk gpmc_ick = { |
1597 | .name = "gpmc_ick", | |
972c5427 RN |
1598 | .ops = &clkops_omap2_dflt, |
1599 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, | |
1600 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
93cac2ad | 1601 | .flags = ENABLE_ON_INIT, |
972c5427 RN |
1602 | .clkdm_name = "l3_2_clkdm", |
1603 | .parent = &l3_div_ck, | |
1604 | .recalc = &followparent_recalc, | |
1605 | }; | |
1606 | ||
0e433271 | 1607 | static const struct clksel sgx_clk_mux_sel[] = { |
032b5a7e TG |
1608 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
1609 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, | |
972c5427 RN |
1610 | { .parent = NULL }, |
1611 | }; | |
1612 | ||
0e433271 BC |
1613 | /* Merged sgx_clk_mux into gpu */ |
1614 | static struct clk gpu_fck = { | |
1615 | .name = "gpu_fck", | |
032b5a7e | 1616 | .parent = &dpll_core_m7x2_ck, |
0e433271 | 1617 | .clksel = sgx_clk_mux_sel, |
972c5427 | 1618 | .init = &omap2_init_clksel_parent, |
0e433271 BC |
1619 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
1620 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, | |
972c5427 RN |
1621 | .ops = &clkops_omap2_dflt, |
1622 | .recalc = &omap2_clksel_recalc, | |
0e433271 | 1623 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
972c5427 | 1624 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
0e433271 | 1625 | .clkdm_name = "l3_gfx_clkdm", |
972c5427 RN |
1626 | }; |
1627 | ||
54776050 RN |
1628 | static struct clk hdq1w_fck = { |
1629 | .name = "hdq1w_fck", | |
972c5427 RN |
1630 | .ops = &clkops_omap2_dflt, |
1631 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, | |
1632 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1633 | .clkdm_name = "l4_per_clkdm", | |
1634 | .parent = &func_12m_fclk, | |
1635 | .recalc = &followparent_recalc, | |
1636 | }; | |
1637 | ||
76cf5295 RN |
1638 | static const struct clksel hsi_fclk_div[] = { |
1639 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, | |
1640 | { .parent = NULL }, | |
1641 | }; | |
1642 | ||
54776050 | 1643 | /* Merged hsi_fclk into hsi */ |
0e433271 BC |
1644 | static struct clk hsi_fck = { |
1645 | .name = "hsi_fck", | |
972c5427 | 1646 | .parent = &dpll_per_m2x2_ck, |
76cf5295 | 1647 | .clksel = hsi_fclk_div, |
972c5427 RN |
1648 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1649 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, | |
1650 | .ops = &clkops_omap2_dflt, | |
1651 | .recalc = &omap2_clksel_recalc, | |
1652 | .round_rate = &omap2_clksel_round_rate, | |
1653 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
1654 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
1655 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1656 | .clkdm_name = "l3_init_clkdm", | |
1657 | }; | |
1658 | ||
54776050 RN |
1659 | static struct clk i2c1_fck = { |
1660 | .name = "i2c1_fck", | |
972c5427 RN |
1661 | .ops = &clkops_omap2_dflt, |
1662 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, | |
1663 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1664 | .clkdm_name = "l4_per_clkdm", | |
1665 | .parent = &func_96m_fclk, | |
1666 | .recalc = &followparent_recalc, | |
1667 | }; | |
1668 | ||
54776050 RN |
1669 | static struct clk i2c2_fck = { |
1670 | .name = "i2c2_fck", | |
972c5427 RN |
1671 | .ops = &clkops_omap2_dflt, |
1672 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, | |
1673 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1674 | .clkdm_name = "l4_per_clkdm", | |
1675 | .parent = &func_96m_fclk, | |
1676 | .recalc = &followparent_recalc, | |
1677 | }; | |
1678 | ||
54776050 RN |
1679 | static struct clk i2c3_fck = { |
1680 | .name = "i2c3_fck", | |
972c5427 RN |
1681 | .ops = &clkops_omap2_dflt, |
1682 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, | |
1683 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1684 | .clkdm_name = "l4_per_clkdm", | |
1685 | .parent = &func_96m_fclk, | |
1686 | .recalc = &followparent_recalc, | |
1687 | }; | |
1688 | ||
54776050 RN |
1689 | static struct clk i2c4_fck = { |
1690 | .name = "i2c4_fck", | |
972c5427 RN |
1691 | .ops = &clkops_omap2_dflt, |
1692 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, | |
1693 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1694 | .clkdm_name = "l4_per_clkdm", | |
1695 | .parent = &func_96m_fclk, | |
1696 | .recalc = &followparent_recalc, | |
1697 | }; | |
1698 | ||
0e433271 BC |
1699 | static struct clk ipu_fck = { |
1700 | .name = "ipu_fck", | |
1701 | .ops = &clkops_omap2_dflt, | |
1702 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, | |
1703 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1704 | .clkdm_name = "ducati_clkdm", | |
1705 | .parent = &ducati_clk_mux_ck, | |
1706 | .recalc = &followparent_recalc, | |
1707 | }; | |
1708 | ||
1c03f42f BC |
1709 | static struct clk iss_ctrlclk = { |
1710 | .name = "iss_ctrlclk", | |
1711 | .ops = &clkops_omap2_dflt, | |
1712 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1713 | .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, | |
1714 | .clkdm_name = "iss_clkdm", | |
1715 | .parent = &func_96m_fclk, | |
1716 | .recalc = &followparent_recalc, | |
1717 | }; | |
1718 | ||
54776050 RN |
1719 | static struct clk iss_fck = { |
1720 | .name = "iss_fck", | |
972c5427 RN |
1721 | .ops = &clkops_omap2_dflt, |
1722 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, | |
1723 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1724 | .clkdm_name = "iss_clkdm", | |
1725 | .parent = &ducati_clk_mux_ck, | |
1726 | .recalc = &followparent_recalc, | |
1727 | }; | |
1728 | ||
0e433271 BC |
1729 | static struct clk iva_fck = { |
1730 | .name = "iva_fck", | |
972c5427 RN |
1731 | .ops = &clkops_omap2_dflt, |
1732 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, | |
1733 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
1734 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 1735 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
1736 | .recalc = &followparent_recalc, |
1737 | }; | |
1738 | ||
0e433271 BC |
1739 | static struct clk kbd_fck = { |
1740 | .name = "kbd_fck", | |
972c5427 RN |
1741 | .ops = &clkops_omap2_dflt, |
1742 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, | |
1743 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1744 | .clkdm_name = "l4_wkup_clkdm", | |
1745 | .parent = &sys_32k_ck, | |
1746 | .recalc = &followparent_recalc, | |
1747 | }; | |
1748 | ||
0e433271 BC |
1749 | static struct clk l3_instr_ick = { |
1750 | .name = "l3_instr_ick", | |
972c5427 RN |
1751 | .ops = &clkops_omap2_dflt, |
1752 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, | |
1753 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
60a0e5d9 | 1754 | .flags = ENABLE_ON_INIT, |
7ecd4228 | 1755 | .clkdm_name = "l3_instr_clkdm", |
972c5427 RN |
1756 | .parent = &l3_div_ck, |
1757 | .recalc = &followparent_recalc, | |
1758 | }; | |
1759 | ||
0e433271 BC |
1760 | static struct clk l3_main_3_ick = { |
1761 | .name = "l3_main_3_ick", | |
972c5427 RN |
1762 | .ops = &clkops_omap2_dflt, |
1763 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, | |
1764 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
60a0e5d9 | 1765 | .flags = ENABLE_ON_INIT, |
7ecd4228 | 1766 | .clkdm_name = "l3_instr_clkdm", |
972c5427 RN |
1767 | .parent = &l3_div_ck, |
1768 | .recalc = &followparent_recalc, | |
1769 | }; | |
1770 | ||
1771 | static struct clk mcasp_sync_mux_ck = { | |
1772 | .name = "mcasp_sync_mux_ck", | |
1773 | .parent = &abe_24m_fclk, | |
1774 | .clksel = dmic_sync_mux_sel, | |
1775 | .init = &omap2_init_clksel_parent, | |
1776 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1777 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1778 | .ops = &clkops_null, | |
1779 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1780 | }; |
1781 | ||
1782 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { | |
1783 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, | |
1784 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1785 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1786 | { .parent = NULL }, | |
1787 | }; | |
1788 | ||
54776050 RN |
1789 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
1790 | static struct clk mcasp_fck = { | |
1791 | .name = "mcasp_fck", | |
972c5427 RN |
1792 | .parent = &mcasp_sync_mux_ck, |
1793 | .clksel = func_mcasp_abe_gfclk_sel, | |
1794 | .init = &omap2_init_clksel_parent, | |
1795 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, | |
1796 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1797 | .ops = &clkops_omap2_dflt, | |
1798 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1799 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
1800 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1801 | .clkdm_name = "abe_clkdm", | |
1802 | }; | |
1803 | ||
1804 | static struct clk mcbsp1_sync_mux_ck = { | |
1805 | .name = "mcbsp1_sync_mux_ck", | |
1806 | .parent = &abe_24m_fclk, | |
1807 | .clksel = dmic_sync_mux_sel, | |
1808 | .init = &omap2_init_clksel_parent, | |
1809 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1810 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1811 | .ops = &clkops_null, | |
1812 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1813 | }; |
1814 | ||
1815 | static const struct clksel func_mcbsp1_gfclk_sel[] = { | |
1816 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, | |
1817 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1818 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1819 | { .parent = NULL }, | |
1820 | }; | |
1821 | ||
54776050 RN |
1822 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
1823 | static struct clk mcbsp1_fck = { | |
1824 | .name = "mcbsp1_fck", | |
972c5427 RN |
1825 | .parent = &mcbsp1_sync_mux_ck, |
1826 | .clksel = func_mcbsp1_gfclk_sel, | |
1827 | .init = &omap2_init_clksel_parent, | |
1828 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, | |
1829 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1830 | .ops = &clkops_omap2_dflt, | |
1831 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1832 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
1833 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1834 | .clkdm_name = "abe_clkdm", | |
1835 | }; | |
1836 | ||
1837 | static struct clk mcbsp2_sync_mux_ck = { | |
1838 | .name = "mcbsp2_sync_mux_ck", | |
1839 | .parent = &abe_24m_fclk, | |
1840 | .clksel = dmic_sync_mux_sel, | |
1841 | .init = &omap2_init_clksel_parent, | |
1842 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1843 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1844 | .ops = &clkops_null, | |
1845 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1846 | }; |
1847 | ||
1848 | static const struct clksel func_mcbsp2_gfclk_sel[] = { | |
1849 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, | |
1850 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1851 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1852 | { .parent = NULL }, | |
1853 | }; | |
1854 | ||
54776050 RN |
1855 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
1856 | static struct clk mcbsp2_fck = { | |
1857 | .name = "mcbsp2_fck", | |
972c5427 RN |
1858 | .parent = &mcbsp2_sync_mux_ck, |
1859 | .clksel = func_mcbsp2_gfclk_sel, | |
1860 | .init = &omap2_init_clksel_parent, | |
1861 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, | |
1862 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1863 | .ops = &clkops_omap2_dflt, | |
1864 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1865 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
1866 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1867 | .clkdm_name = "abe_clkdm", | |
1868 | }; | |
1869 | ||
1870 | static struct clk mcbsp3_sync_mux_ck = { | |
1871 | .name = "mcbsp3_sync_mux_ck", | |
1872 | .parent = &abe_24m_fclk, | |
1873 | .clksel = dmic_sync_mux_sel, | |
1874 | .init = &omap2_init_clksel_parent, | |
1875 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1876 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1877 | .ops = &clkops_null, | |
1878 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1879 | }; |
1880 | ||
1881 | static const struct clksel func_mcbsp3_gfclk_sel[] = { | |
1882 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, | |
1883 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1884 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, | |
1885 | { .parent = NULL }, | |
1886 | }; | |
1887 | ||
54776050 RN |
1888 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
1889 | static struct clk mcbsp3_fck = { | |
1890 | .name = "mcbsp3_fck", | |
972c5427 RN |
1891 | .parent = &mcbsp3_sync_mux_ck, |
1892 | .clksel = func_mcbsp3_gfclk_sel, | |
1893 | .init = &omap2_init_clksel_parent, | |
1894 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, | |
1895 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, | |
1896 | .ops = &clkops_omap2_dflt, | |
1897 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1898 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
1899 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1900 | .clkdm_name = "abe_clkdm", | |
1901 | }; | |
1902 | ||
de474535 JH |
1903 | static const struct clksel mcbsp4_sync_mux_sel[] = { |
1904 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, | |
1905 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, | |
1906 | { .parent = NULL }, | |
1907 | }; | |
1908 | ||
972c5427 RN |
1909 | static struct clk mcbsp4_sync_mux_ck = { |
1910 | .name = "mcbsp4_sync_mux_ck", | |
1911 | .parent = &func_96m_fclk, | |
de474535 | 1912 | .clksel = mcbsp4_sync_mux_sel, |
972c5427 RN |
1913 | .init = &omap2_init_clksel_parent, |
1914 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1915 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, | |
1916 | .ops = &clkops_null, | |
1917 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1918 | }; |
1919 | ||
1920 | static const struct clksel per_mcbsp4_gfclk_sel[] = { | |
1921 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, | |
1922 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, | |
1923 | { .parent = NULL }, | |
1924 | }; | |
1925 | ||
54776050 RN |
1926 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
1927 | static struct clk mcbsp4_fck = { | |
1928 | .name = "mcbsp4_fck", | |
972c5427 RN |
1929 | .parent = &mcbsp4_sync_mux_ck, |
1930 | .clksel = per_mcbsp4_gfclk_sel, | |
1931 | .init = &omap2_init_clksel_parent, | |
1932 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, | |
1933 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, | |
1934 | .ops = &clkops_omap2_dflt, | |
1935 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
1936 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
1937 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1938 | .clkdm_name = "l4_per_clkdm", | |
1939 | }; | |
1940 | ||
0e433271 BC |
1941 | static struct clk mcpdm_fck = { |
1942 | .name = "mcpdm_fck", | |
1943 | .ops = &clkops_omap2_dflt, | |
1944 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, | |
1945 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1946 | .clkdm_name = "abe_clkdm", | |
1947 | .parent = &pad_clks_ck, | |
1948 | .recalc = &followparent_recalc, | |
1949 | }; | |
1950 | ||
54776050 RN |
1951 | static struct clk mcspi1_fck = { |
1952 | .name = "mcspi1_fck", | |
972c5427 RN |
1953 | .ops = &clkops_omap2_dflt, |
1954 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, | |
1955 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1956 | .clkdm_name = "l4_per_clkdm", | |
1957 | .parent = &func_48m_fclk, | |
1958 | .recalc = &followparent_recalc, | |
1959 | }; | |
1960 | ||
54776050 RN |
1961 | static struct clk mcspi2_fck = { |
1962 | .name = "mcspi2_fck", | |
972c5427 RN |
1963 | .ops = &clkops_omap2_dflt, |
1964 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, | |
1965 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1966 | .clkdm_name = "l4_per_clkdm", | |
1967 | .parent = &func_48m_fclk, | |
1968 | .recalc = &followparent_recalc, | |
1969 | }; | |
1970 | ||
54776050 RN |
1971 | static struct clk mcspi3_fck = { |
1972 | .name = "mcspi3_fck", | |
972c5427 RN |
1973 | .ops = &clkops_omap2_dflt, |
1974 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, | |
1975 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1976 | .clkdm_name = "l4_per_clkdm", | |
1977 | .parent = &func_48m_fclk, | |
1978 | .recalc = &followparent_recalc, | |
1979 | }; | |
1980 | ||
54776050 RN |
1981 | static struct clk mcspi4_fck = { |
1982 | .name = "mcspi4_fck", | |
972c5427 RN |
1983 | .ops = &clkops_omap2_dflt, |
1984 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, | |
1985 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
1986 | .clkdm_name = "l4_per_clkdm", | |
1987 | .parent = &func_48m_fclk, | |
1988 | .recalc = &followparent_recalc, | |
1989 | }; | |
1990 | ||
de474535 JH |
1991 | static const struct clksel hsmmc1_fclk_sel[] = { |
1992 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, | |
1993 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, | |
1994 | { .parent = NULL }, | |
1995 | }; | |
1996 | ||
54776050 RN |
1997 | /* Merged hsmmc1_fclk into mmc1 */ |
1998 | static struct clk mmc1_fck = { | |
1999 | .name = "mmc1_fck", | |
972c5427 | 2000 | .parent = &func_64m_fclk, |
de474535 | 2001 | .clksel = hsmmc1_fclk_sel, |
972c5427 RN |
2002 | .init = &omap2_init_clksel_parent, |
2003 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, | |
2004 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2005 | .ops = &clkops_omap2_dflt, | |
2006 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2007 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
2008 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2009 | .clkdm_name = "l3_init_clkdm", | |
2010 | }; | |
2011 | ||
54776050 RN |
2012 | /* Merged hsmmc2_fclk into mmc2 */ |
2013 | static struct clk mmc2_fck = { | |
2014 | .name = "mmc2_fck", | |
972c5427 | 2015 | .parent = &func_64m_fclk, |
de474535 | 2016 | .clksel = hsmmc1_fclk_sel, |
972c5427 RN |
2017 | .init = &omap2_init_clksel_parent, |
2018 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, | |
2019 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2020 | .ops = &clkops_omap2_dflt, | |
2021 | .recalc = &omap2_clksel_recalc, | |
972c5427 RN |
2022 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
2023 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2024 | .clkdm_name = "l3_init_clkdm", | |
2025 | }; | |
2026 | ||
54776050 RN |
2027 | static struct clk mmc3_fck = { |
2028 | .name = "mmc3_fck", | |
972c5427 RN |
2029 | .ops = &clkops_omap2_dflt, |
2030 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, | |
2031 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2032 | .clkdm_name = "l4_per_clkdm", | |
2033 | .parent = &func_48m_fclk, | |
2034 | .recalc = &followparent_recalc, | |
2035 | }; | |
2036 | ||
54776050 RN |
2037 | static struct clk mmc4_fck = { |
2038 | .name = "mmc4_fck", | |
972c5427 RN |
2039 | .ops = &clkops_omap2_dflt, |
2040 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, | |
2041 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2042 | .clkdm_name = "l4_per_clkdm", | |
2043 | .parent = &func_48m_fclk, | |
2044 | .recalc = &followparent_recalc, | |
2045 | }; | |
2046 | ||
54776050 RN |
2047 | static struct clk mmc5_fck = { |
2048 | .name = "mmc5_fck", | |
972c5427 RN |
2049 | .ops = &clkops_omap2_dflt, |
2050 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, | |
2051 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2052 | .clkdm_name = "l4_per_clkdm", | |
2053 | .parent = &func_48m_fclk, | |
2054 | .recalc = &followparent_recalc, | |
2055 | }; | |
2056 | ||
0edc9e85 BC |
2057 | static struct clk ocp2scp_usb_phy_phy_48m = { |
2058 | .name = "ocp2scp_usb_phy_phy_48m", | |
1c03f42f BC |
2059 | .ops = &clkops_omap2_dflt, |
2060 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2061 | .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, |
1c03f42f | 2062 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2063 | .parent = &func_48m_fclk, |
1c03f42f BC |
2064 | .recalc = &followparent_recalc, |
2065 | }; | |
2066 | ||
0edc9e85 BC |
2067 | static struct clk ocp2scp_usb_phy_ick = { |
2068 | .name = "ocp2scp_usb_phy_ick", | |
1c03f42f BC |
2069 | .ops = &clkops_omap2_dflt, |
2070 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | |
0edc9e85 | 2071 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
1c03f42f | 2072 | .clkdm_name = "l3_init_clkdm", |
0edc9e85 | 2073 | .parent = &l4_div_ck, |
1c03f42f BC |
2074 | .recalc = &followparent_recalc, |
2075 | }; | |
2076 | ||
0e433271 BC |
2077 | static struct clk ocp_wp_noc_ick = { |
2078 | .name = "ocp_wp_noc_ick", | |
972c5427 RN |
2079 | .ops = &clkops_omap2_dflt, |
2080 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, | |
2081 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
60a0e5d9 | 2082 | .flags = ENABLE_ON_INIT, |
7ecd4228 | 2083 | .clkdm_name = "l3_instr_clkdm", |
972c5427 RN |
2084 | .parent = &l3_div_ck, |
2085 | .recalc = &followparent_recalc, | |
2086 | }; | |
2087 | ||
54776050 RN |
2088 | static struct clk rng_ick = { |
2089 | .name = "rng_ick", | |
972c5427 RN |
2090 | .ops = &clkops_omap2_dflt, |
2091 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, | |
2092 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2093 | .clkdm_name = "l4_secure_clkdm", | |
2094 | .parent = &l4_div_ck, | |
2095 | .recalc = &followparent_recalc, | |
2096 | }; | |
2097 | ||
0e433271 BC |
2098 | static struct clk sha2md5_fck = { |
2099 | .name = "sha2md5_fck", | |
972c5427 RN |
2100 | .ops = &clkops_omap2_dflt, |
2101 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, | |
2102 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2103 | .clkdm_name = "l4_secure_clkdm", | |
2104 | .parent = &l3_div_ck, | |
2105 | .recalc = &followparent_recalc, | |
2106 | }; | |
2107 | ||
0e433271 BC |
2108 | static struct clk sl2if_ick = { |
2109 | .name = "sl2if_ick", | |
972c5427 RN |
2110 | .ops = &clkops_omap2_dflt, |
2111 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, | |
2112 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2113 | .clkdm_name = "ivahd_clkdm", | |
032b5a7e | 2114 | .parent = &dpll_iva_m5x2_ck, |
972c5427 RN |
2115 | .recalc = &followparent_recalc, |
2116 | }; | |
2117 | ||
1c03f42f BC |
2118 | static struct clk slimbus1_fclk_1 = { |
2119 | .name = "slimbus1_fclk_1", | |
2120 | .ops = &clkops_omap2_dflt, | |
2121 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2122 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, | |
2123 | .clkdm_name = "abe_clkdm", | |
2124 | .parent = &func_24m_clk, | |
2125 | .recalc = &followparent_recalc, | |
2126 | }; | |
2127 | ||
2128 | static struct clk slimbus1_fclk_0 = { | |
2129 | .name = "slimbus1_fclk_0", | |
2130 | .ops = &clkops_omap2_dflt, | |
2131 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2132 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, | |
2133 | .clkdm_name = "abe_clkdm", | |
2134 | .parent = &abe_24m_fclk, | |
2135 | .recalc = &followparent_recalc, | |
2136 | }; | |
2137 | ||
2138 | static struct clk slimbus1_fclk_2 = { | |
2139 | .name = "slimbus1_fclk_2", | |
2140 | .ops = &clkops_omap2_dflt, | |
2141 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2142 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, | |
2143 | .clkdm_name = "abe_clkdm", | |
2144 | .parent = &pad_clks_ck, | |
2145 | .recalc = &followparent_recalc, | |
2146 | }; | |
2147 | ||
2148 | static struct clk slimbus1_slimbus_clk = { | |
2149 | .name = "slimbus1_slimbus_clk", | |
2150 | .ops = &clkops_omap2_dflt, | |
2151 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2152 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, | |
2153 | .clkdm_name = "abe_clkdm", | |
2154 | .parent = &slimbus_clk, | |
2155 | .recalc = &followparent_recalc, | |
2156 | }; | |
2157 | ||
54776050 RN |
2158 | static struct clk slimbus1_fck = { |
2159 | .name = "slimbus1_fck", | |
972c5427 RN |
2160 | .ops = &clkops_omap2_dflt, |
2161 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, | |
2162 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2163 | .clkdm_name = "abe_clkdm", | |
2164 | .parent = &ocp_abe_iclk, | |
2165 | .recalc = &followparent_recalc, | |
2166 | }; | |
2167 | ||
1c03f42f BC |
2168 | static struct clk slimbus2_fclk_1 = { |
2169 | .name = "slimbus2_fclk_1", | |
2170 | .ops = &clkops_omap2_dflt, | |
2171 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2172 | .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, | |
2173 | .clkdm_name = "l4_per_clkdm", | |
2174 | .parent = &per_abe_24m_fclk, | |
2175 | .recalc = &followparent_recalc, | |
2176 | }; | |
2177 | ||
2178 | static struct clk slimbus2_fclk_0 = { | |
2179 | .name = "slimbus2_fclk_0", | |
2180 | .ops = &clkops_omap2_dflt, | |
2181 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2182 | .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, | |
2183 | .clkdm_name = "l4_per_clkdm", | |
2184 | .parent = &func_24mc_fclk, | |
2185 | .recalc = &followparent_recalc, | |
2186 | }; | |
2187 | ||
2188 | static struct clk slimbus2_slimbus_clk = { | |
2189 | .name = "slimbus2_slimbus_clk", | |
2190 | .ops = &clkops_omap2_dflt, | |
2191 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2192 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, | |
2193 | .clkdm_name = "l4_per_clkdm", | |
2194 | .parent = &pad_slimbus_core_clks_ck, | |
2195 | .recalc = &followparent_recalc, | |
2196 | }; | |
2197 | ||
54776050 RN |
2198 | static struct clk slimbus2_fck = { |
2199 | .name = "slimbus2_fck", | |
972c5427 RN |
2200 | .ops = &clkops_omap2_dflt, |
2201 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, | |
2202 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2203 | .clkdm_name = "l4_per_clkdm", | |
2204 | .parent = &l4_div_ck, | |
2205 | .recalc = &followparent_recalc, | |
2206 | }; | |
2207 | ||
0e433271 BC |
2208 | static struct clk smartreflex_core_fck = { |
2209 | .name = "smartreflex_core_fck", | |
972c5427 RN |
2210 | .ops = &clkops_omap2_dflt, |
2211 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, | |
2212 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2213 | .clkdm_name = "l4_ao_clkdm", | |
2214 | .parent = &l4_wkup_clk_mux_ck, | |
2215 | .recalc = &followparent_recalc, | |
2216 | }; | |
2217 | ||
0e433271 BC |
2218 | static struct clk smartreflex_iva_fck = { |
2219 | .name = "smartreflex_iva_fck", | |
972c5427 RN |
2220 | .ops = &clkops_omap2_dflt, |
2221 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, | |
2222 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2223 | .clkdm_name = "l4_ao_clkdm", | |
2224 | .parent = &l4_wkup_clk_mux_ck, | |
2225 | .recalc = &followparent_recalc, | |
2226 | }; | |
2227 | ||
0e433271 BC |
2228 | static struct clk smartreflex_mpu_fck = { |
2229 | .name = "smartreflex_mpu_fck", | |
972c5427 RN |
2230 | .ops = &clkops_omap2_dflt, |
2231 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, | |
2232 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2233 | .clkdm_name = "l4_ao_clkdm", | |
2234 | .parent = &l4_wkup_clk_mux_ck, | |
2235 | .recalc = &followparent_recalc, | |
2236 | }; | |
2237 | ||
0e433271 BC |
2238 | /* Merged dmt1_clk_mux into timer1 */ |
2239 | static struct clk timer1_fck = { | |
2240 | .name = "timer1_fck", | |
2241 | .parent = &sys_clkin_ck, | |
2242 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2243 | .init = &omap2_init_clksel_parent, | |
2244 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2245 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
972c5427 | 2246 | .ops = &clkops_omap2_dflt, |
0e433271 BC |
2247 | .recalc = &omap2_clksel_recalc, |
2248 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, | |
2249 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2250 | .clkdm_name = "l4_wkup_clkdm", | |
2251 | }; | |
2252 | ||
2253 | /* Merged cm2_dm10_mux into timer10 */ | |
2254 | static struct clk timer10_fck = { | |
2255 | .name = "timer10_fck", | |
2256 | .parent = &sys_clkin_ck, | |
2257 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2258 | .init = &omap2_init_clksel_parent, | |
2259 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2260 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2261 | .ops = &clkops_omap2_dflt, | |
2262 | .recalc = &omap2_clksel_recalc, | |
2263 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, | |
2264 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2265 | .clkdm_name = "l4_per_clkdm", | |
2266 | }; | |
2267 | ||
2268 | /* Merged cm2_dm11_mux into timer11 */ | |
2269 | static struct clk timer11_fck = { | |
2270 | .name = "timer11_fck", | |
2271 | .parent = &sys_clkin_ck, | |
2272 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2273 | .init = &omap2_init_clksel_parent, | |
2274 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2275 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2276 | .ops = &clkops_omap2_dflt, | |
2277 | .recalc = &omap2_clksel_recalc, | |
2278 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, | |
2279 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2280 | .clkdm_name = "l4_per_clkdm", | |
2281 | }; | |
2282 | ||
2283 | /* Merged cm2_dm2_mux into timer2 */ | |
2284 | static struct clk timer2_fck = { | |
2285 | .name = "timer2_fck", | |
2286 | .parent = &sys_clkin_ck, | |
2287 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2288 | .init = &omap2_init_clksel_parent, | |
2289 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2290 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2291 | .ops = &clkops_omap2_dflt, | |
2292 | .recalc = &omap2_clksel_recalc, | |
2293 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, | |
2294 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2295 | .clkdm_name = "l4_per_clkdm", | |
2296 | }; | |
2297 | ||
2298 | /* Merged cm2_dm3_mux into timer3 */ | |
2299 | static struct clk timer3_fck = { | |
2300 | .name = "timer3_fck", | |
2301 | .parent = &sys_clkin_ck, | |
2302 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2303 | .init = &omap2_init_clksel_parent, | |
2304 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2305 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2306 | .ops = &clkops_omap2_dflt, | |
2307 | .recalc = &omap2_clksel_recalc, | |
2308 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, | |
2309 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2310 | .clkdm_name = "l4_per_clkdm", | |
2311 | }; | |
2312 | ||
2313 | /* Merged cm2_dm4_mux into timer4 */ | |
2314 | static struct clk timer4_fck = { | |
2315 | .name = "timer4_fck", | |
2316 | .parent = &sys_clkin_ck, | |
2317 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2318 | .init = &omap2_init_clksel_parent, | |
2319 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2320 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2321 | .ops = &clkops_omap2_dflt, | |
2322 | .recalc = &omap2_clksel_recalc, | |
2323 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, | |
2324 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2325 | .clkdm_name = "l4_per_clkdm", | |
2326 | }; | |
2327 | ||
2328 | static const struct clksel timer5_sync_mux_sel[] = { | |
2329 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, | |
2330 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, | |
2331 | { .parent = NULL }, | |
2332 | }; | |
2333 | ||
2334 | /* Merged timer5_sync_mux into timer5 */ | |
2335 | static struct clk timer5_fck = { | |
2336 | .name = "timer5_fck", | |
2337 | .parent = &syc_clk_div_ck, | |
2338 | .clksel = timer5_sync_mux_sel, | |
2339 | .init = &omap2_init_clksel_parent, | |
2340 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2341 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2342 | .ops = &clkops_omap2_dflt, | |
2343 | .recalc = &omap2_clksel_recalc, | |
2344 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, | |
2345 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2346 | .clkdm_name = "abe_clkdm", | |
2347 | }; | |
2348 | ||
2349 | /* Merged timer6_sync_mux into timer6 */ | |
2350 | static struct clk timer6_fck = { | |
2351 | .name = "timer6_fck", | |
2352 | .parent = &syc_clk_div_ck, | |
2353 | .clksel = timer5_sync_mux_sel, | |
2354 | .init = &omap2_init_clksel_parent, | |
2355 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2356 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2357 | .ops = &clkops_omap2_dflt, | |
2358 | .recalc = &omap2_clksel_recalc, | |
2359 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, | |
2360 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2361 | .clkdm_name = "abe_clkdm", | |
2362 | }; | |
2363 | ||
2364 | /* Merged timer7_sync_mux into timer7 */ | |
2365 | static struct clk timer7_fck = { | |
2366 | .name = "timer7_fck", | |
2367 | .parent = &syc_clk_div_ck, | |
2368 | .clksel = timer5_sync_mux_sel, | |
2369 | .init = &omap2_init_clksel_parent, | |
2370 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2371 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2372 | .ops = &clkops_omap2_dflt, | |
2373 | .recalc = &omap2_clksel_recalc, | |
2374 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, | |
2375 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2376 | .clkdm_name = "abe_clkdm", | |
2377 | }; | |
2378 | ||
2379 | /* Merged timer8_sync_mux into timer8 */ | |
2380 | static struct clk timer8_fck = { | |
2381 | .name = "timer8_fck", | |
2382 | .parent = &syc_clk_div_ck, | |
2383 | .clksel = timer5_sync_mux_sel, | |
2384 | .init = &omap2_init_clksel_parent, | |
2385 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2386 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2387 | .ops = &clkops_omap2_dflt, | |
2388 | .recalc = &omap2_clksel_recalc, | |
2389 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, | |
2390 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2391 | .clkdm_name = "abe_clkdm", | |
2392 | }; | |
2393 | ||
2394 | /* Merged cm2_dm9_mux into timer9 */ | |
2395 | static struct clk timer9_fck = { | |
2396 | .name = "timer9_fck", | |
2397 | .parent = &sys_clkin_ck, | |
2398 | .clksel = abe_dpll_bypass_clk_mux_sel, | |
2399 | .init = &omap2_init_clksel_parent, | |
2400 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2401 | .clksel_mask = OMAP4430_CLKSEL_MASK, | |
2402 | .ops = &clkops_omap2_dflt, | |
2403 | .recalc = &omap2_clksel_recalc, | |
2404 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, | |
2405 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2406 | .clkdm_name = "l4_per_clkdm", | |
972c5427 RN |
2407 | }; |
2408 | ||
54776050 RN |
2409 | static struct clk uart1_fck = { |
2410 | .name = "uart1_fck", | |
972c5427 RN |
2411 | .ops = &clkops_omap2_dflt, |
2412 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, | |
2413 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2414 | .clkdm_name = "l4_per_clkdm", | |
2415 | .parent = &func_48m_fclk, | |
2416 | .recalc = &followparent_recalc, | |
2417 | }; | |
2418 | ||
54776050 RN |
2419 | static struct clk uart2_fck = { |
2420 | .name = "uart2_fck", | |
972c5427 RN |
2421 | .ops = &clkops_omap2_dflt, |
2422 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, | |
2423 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2424 | .clkdm_name = "l4_per_clkdm", | |
2425 | .parent = &func_48m_fclk, | |
2426 | .recalc = &followparent_recalc, | |
2427 | }; | |
2428 | ||
54776050 RN |
2429 | static struct clk uart3_fck = { |
2430 | .name = "uart3_fck", | |
972c5427 RN |
2431 | .ops = &clkops_omap2_dflt, |
2432 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, | |
2433 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2434 | .clkdm_name = "l4_per_clkdm", | |
2435 | .parent = &func_48m_fclk, | |
2436 | .recalc = &followparent_recalc, | |
2437 | }; | |
2438 | ||
54776050 RN |
2439 | static struct clk uart4_fck = { |
2440 | .name = "uart4_fck", | |
972c5427 RN |
2441 | .ops = &clkops_omap2_dflt, |
2442 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, | |
2443 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2444 | .clkdm_name = "l4_per_clkdm", | |
2445 | .parent = &func_48m_fclk, | |
2446 | .recalc = &followparent_recalc, | |
2447 | }; | |
2448 | ||
0e433271 BC |
2449 | static struct clk usb_host_fs_fck = { |
2450 | .name = "usb_host_fs_fck", | |
972c5427 | 2451 | .ops = &clkops_omap2_dflt, |
0e433271 | 2452 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
972c5427 RN |
2453 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
2454 | .clkdm_name = "l3_init_clkdm", | |
0e433271 | 2455 | .parent = &func_48mc_fclk, |
972c5427 RN |
2456 | .recalc = &followparent_recalc, |
2457 | }; | |
2458 | ||
1c03f42f BC |
2459 | static const struct clksel utmi_p1_gfclk_sel[] = { |
2460 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2461 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, | |
2462 | { .parent = NULL }, | |
2463 | }; | |
2464 | ||
2465 | static struct clk utmi_p1_gfclk = { | |
2466 | .name = "utmi_p1_gfclk", | |
2467 | .parent = &init_60m_fclk, | |
2468 | .clksel = utmi_p1_gfclk_sel, | |
2469 | .init = &omap2_init_clksel_parent, | |
2470 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2471 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, | |
2472 | .ops = &clkops_null, | |
2473 | .recalc = &omap2_clksel_recalc, | |
2474 | }; | |
2475 | ||
2476 | static struct clk usb_host_hs_utmi_p1_clk = { | |
2477 | .name = "usb_host_hs_utmi_p1_clk", | |
2478 | .ops = &clkops_omap2_dflt, | |
2479 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2480 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, | |
2481 | .clkdm_name = "l3_init_clkdm", | |
2482 | .parent = &utmi_p1_gfclk, | |
2483 | .recalc = &followparent_recalc, | |
2484 | }; | |
2485 | ||
2486 | static const struct clksel utmi_p2_gfclk_sel[] = { | |
2487 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, | |
2488 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, | |
2489 | { .parent = NULL }, | |
2490 | }; | |
2491 | ||
2492 | static struct clk utmi_p2_gfclk = { | |
2493 | .name = "utmi_p2_gfclk", | |
2494 | .parent = &init_60m_fclk, | |
2495 | .clksel = utmi_p2_gfclk_sel, | |
2496 | .init = &omap2_init_clksel_parent, | |
2497 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2498 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, | |
2499 | .ops = &clkops_null, | |
2500 | .recalc = &omap2_clksel_recalc, | |
2501 | }; | |
2502 | ||
2503 | static struct clk usb_host_hs_utmi_p2_clk = { | |
2504 | .name = "usb_host_hs_utmi_p2_clk", | |
2505 | .ops = &clkops_omap2_dflt, | |
2506 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2507 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, | |
2508 | .clkdm_name = "l3_init_clkdm", | |
2509 | .parent = &utmi_p2_gfclk, | |
2510 | .recalc = &followparent_recalc, | |
2511 | }; | |
2512 | ||
032b5a7e TG |
2513 | static struct clk usb_host_hs_utmi_p3_clk = { |
2514 | .name = "usb_host_hs_utmi_p3_clk", | |
2515 | .ops = &clkops_omap2_dflt, | |
2516 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2517 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, | |
2518 | .clkdm_name = "l3_init_clkdm", | |
2519 | .parent = &init_60m_fclk, | |
2520 | .recalc = &followparent_recalc, | |
2521 | }; | |
2522 | ||
1c03f42f BC |
2523 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
2524 | .name = "usb_host_hs_hsic480m_p1_clk", | |
2525 | .ops = &clkops_omap2_dflt, | |
2526 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2527 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, | |
2528 | .clkdm_name = "l3_init_clkdm", | |
2529 | .parent = &dpll_usb_m2_ck, | |
2530 | .recalc = &followparent_recalc, | |
2531 | }; | |
2532 | ||
032b5a7e TG |
2533 | static struct clk usb_host_hs_hsic60m_p1_clk = { |
2534 | .name = "usb_host_hs_hsic60m_p1_clk", | |
2535 | .ops = &clkops_omap2_dflt, | |
2536 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2537 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, | |
2538 | .clkdm_name = "l3_init_clkdm", | |
2539 | .parent = &init_60m_fclk, | |
2540 | .recalc = &followparent_recalc, | |
2541 | }; | |
2542 | ||
2543 | static struct clk usb_host_hs_hsic60m_p2_clk = { | |
2544 | .name = "usb_host_hs_hsic60m_p2_clk", | |
2545 | .ops = &clkops_omap2_dflt, | |
2546 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2547 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, | |
2548 | .clkdm_name = "l3_init_clkdm", | |
2549 | .parent = &init_60m_fclk, | |
2550 | .recalc = &followparent_recalc, | |
2551 | }; | |
2552 | ||
1c03f42f BC |
2553 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
2554 | .name = "usb_host_hs_hsic480m_p2_clk", | |
2555 | .ops = &clkops_omap2_dflt, | |
2556 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2557 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, | |
2558 | .clkdm_name = "l3_init_clkdm", | |
2559 | .parent = &dpll_usb_m2_ck, | |
2560 | .recalc = &followparent_recalc, | |
2561 | }; | |
2562 | ||
2563 | static struct clk usb_host_hs_func48mclk = { | |
2564 | .name = "usb_host_hs_func48mclk", | |
2565 | .ops = &clkops_omap2_dflt, | |
2566 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2567 | .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, | |
2568 | .clkdm_name = "l3_init_clkdm", | |
2569 | .parent = &func_48mc_fclk, | |
2570 | .recalc = &followparent_recalc, | |
2571 | }; | |
2572 | ||
0e433271 BC |
2573 | static struct clk usb_host_hs_fck = { |
2574 | .name = "usb_host_hs_fck", | |
972c5427 RN |
2575 | .ops = &clkops_omap2_dflt, |
2576 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, | |
2577 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2578 | .clkdm_name = "l3_init_clkdm", | |
2579 | .parent = &init_60m_fclk, | |
2580 | .recalc = &followparent_recalc, | |
2581 | }; | |
2582 | ||
1c03f42f BC |
2583 | static const struct clksel otg_60m_gfclk_sel[] = { |
2584 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, | |
2585 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, | |
2586 | { .parent = NULL }, | |
2587 | }; | |
2588 | ||
2589 | static struct clk otg_60m_gfclk = { | |
2590 | .name = "otg_60m_gfclk", | |
2591 | .parent = &utmi_phy_clkout_ck, | |
2592 | .clksel = otg_60m_gfclk_sel, | |
2593 | .init = &omap2_init_clksel_parent, | |
2594 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2595 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, | |
2596 | .ops = &clkops_null, | |
2597 | .recalc = &omap2_clksel_recalc, | |
2598 | }; | |
2599 | ||
2600 | static struct clk usb_otg_hs_xclk = { | |
2601 | .name = "usb_otg_hs_xclk", | |
2602 | .ops = &clkops_omap2_dflt, | |
2603 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2604 | .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, | |
2605 | .clkdm_name = "l3_init_clkdm", | |
2606 | .parent = &otg_60m_gfclk, | |
2607 | .recalc = &followparent_recalc, | |
2608 | }; | |
2609 | ||
0e433271 BC |
2610 | static struct clk usb_otg_hs_ick = { |
2611 | .name = "usb_otg_hs_ick", | |
972c5427 RN |
2612 | .ops = &clkops_omap2_dflt, |
2613 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, | |
2614 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2615 | .clkdm_name = "l3_init_clkdm", | |
2616 | .parent = &l3_div_ck, | |
2617 | .recalc = &followparent_recalc, | |
2618 | }; | |
2619 | ||
0edc9e85 BC |
2620 | static struct clk usb_phy_cm_clk32k = { |
2621 | .name = "usb_phy_cm_clk32k", | |
2622 | .ops = &clkops_omap2_dflt, | |
2623 | .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, | |
2624 | .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, | |
2625 | .clkdm_name = "l4_ao_clkdm", | |
2626 | .parent = &sys_32k_ck, | |
2627 | .recalc = &followparent_recalc, | |
2628 | }; | |
2629 | ||
1c03f42f BC |
2630 | static struct clk usb_tll_hs_usb_ch2_clk = { |
2631 | .name = "usb_tll_hs_usb_ch2_clk", | |
2632 | .ops = &clkops_omap2_dflt, | |
2633 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2634 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, | |
2635 | .clkdm_name = "l3_init_clkdm", | |
2636 | .parent = &init_60m_fclk, | |
2637 | .recalc = &followparent_recalc, | |
2638 | }; | |
2639 | ||
2640 | static struct clk usb_tll_hs_usb_ch0_clk = { | |
2641 | .name = "usb_tll_hs_usb_ch0_clk", | |
2642 | .ops = &clkops_omap2_dflt, | |
2643 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2644 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, | |
2645 | .clkdm_name = "l3_init_clkdm", | |
2646 | .parent = &init_60m_fclk, | |
2647 | .recalc = &followparent_recalc, | |
2648 | }; | |
2649 | ||
2650 | static struct clk usb_tll_hs_usb_ch1_clk = { | |
2651 | .name = "usb_tll_hs_usb_ch1_clk", | |
2652 | .ops = &clkops_omap2_dflt, | |
2653 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2654 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, | |
2655 | .clkdm_name = "l3_init_clkdm", | |
2656 | .parent = &init_60m_fclk, | |
2657 | .recalc = &followparent_recalc, | |
2658 | }; | |
2659 | ||
0e433271 BC |
2660 | static struct clk usb_tll_hs_ick = { |
2661 | .name = "usb_tll_hs_ick", | |
972c5427 RN |
2662 | .ops = &clkops_omap2_dflt, |
2663 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, | |
2664 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, | |
2665 | .clkdm_name = "l3_init_clkdm", | |
2666 | .parent = &l4_div_ck, | |
2667 | .recalc = &followparent_recalc, | |
2668 | }; | |
2669 | ||
0edc9e85 BC |
2670 | static const struct clksel_rate div2_14to18_rates[] = { |
2671 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, | |
2672 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, | |
2673 | { .div = 0 }, | |
2674 | }; | |
2675 | ||
2676 | static const struct clksel usim_fclk_div[] = { | |
032b5a7e | 2677 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
0edc9e85 BC |
2678 | { .parent = NULL }, |
2679 | }; | |
2680 | ||
2681 | static struct clk usim_ck = { | |
2682 | .name = "usim_ck", | |
032b5a7e | 2683 | .parent = &dpll_per_m4x2_ck, |
0edc9e85 BC |
2684 | .clksel = usim_fclk_div, |
2685 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2686 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, | |
2687 | .ops = &clkops_null, | |
2688 | .recalc = &omap2_clksel_recalc, | |
2689 | .round_rate = &omap2_clksel_round_rate, | |
2690 | .set_rate = &omap2_clksel_set_rate, | |
2691 | }; | |
2692 | ||
2693 | static struct clk usim_fclk = { | |
2694 | .name = "usim_fclk", | |
2695 | .ops = &clkops_omap2_dflt, | |
2696 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
2697 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, | |
2698 | .clkdm_name = "l4_wkup_clkdm", | |
2699 | .parent = &usim_ck, | |
2700 | .recalc = &followparent_recalc, | |
2701 | }; | |
2702 | ||
0e433271 BC |
2703 | static struct clk usim_fck = { |
2704 | .name = "usim_fck", | |
972c5427 RN |
2705 | .ops = &clkops_omap2_dflt, |
2706 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, | |
76cf5295 | 2707 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
972c5427 RN |
2708 | .clkdm_name = "l4_wkup_clkdm", |
2709 | .parent = &sys_32k_ck, | |
2710 | .recalc = &followparent_recalc, | |
2711 | }; | |
2712 | ||
0e433271 BC |
2713 | static struct clk wd_timer2_fck = { |
2714 | .name = "wd_timer2_fck", | |
972c5427 RN |
2715 | .ops = &clkops_omap2_dflt, |
2716 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, | |
2717 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2718 | .clkdm_name = "l4_wkup_clkdm", | |
2719 | .parent = &sys_32k_ck, | |
2720 | .recalc = &followparent_recalc, | |
2721 | }; | |
2722 | ||
0e433271 BC |
2723 | static struct clk wd_timer3_fck = { |
2724 | .name = "wd_timer3_fck", | |
972c5427 RN |
2725 | .ops = &clkops_omap2_dflt, |
2726 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, | |
2727 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, | |
2728 | .clkdm_name = "abe_clkdm", | |
2729 | .parent = &sys_32k_ck, | |
2730 | .recalc = &followparent_recalc, | |
2731 | }; | |
2732 | ||
2733 | /* Remaining optional clocks */ | |
972c5427 RN |
2734 | static const struct clksel stm_clk_div_div[] = { |
2735 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, | |
2736 | { .parent = NULL }, | |
2737 | }; | |
2738 | ||
2739 | static struct clk stm_clk_div_ck = { | |
2740 | .name = "stm_clk_div_ck", | |
2741 | .parent = &pmd_stm_clock_mux_ck, | |
2742 | .clksel = stm_clk_div_div, | |
2743 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2744 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, | |
2745 | .ops = &clkops_null, | |
2746 | .recalc = &omap2_clksel_recalc, | |
2747 | .round_rate = &omap2_clksel_round_rate, | |
2748 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2749 | }; |
2750 | ||
2751 | static const struct clksel trace_clk_div_div[] = { | |
2752 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, | |
2753 | { .parent = NULL }, | |
2754 | }; | |
2755 | ||
2756 | static struct clk trace_clk_div_ck = { | |
2757 | .name = "trace_clk_div_ck", | |
2758 | .parent = &pmd_trace_clk_mux_ck, | |
9a47d32d | 2759 | .clkdm_name = "emu_sys_clkdm", |
972c5427 RN |
2760 | .clksel = trace_clk_div_div, |
2761 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, | |
2762 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, | |
2763 | .ops = &clkops_null, | |
2764 | .recalc = &omap2_clksel_recalc, | |
2765 | .round_rate = &omap2_clksel_round_rate, | |
2766 | .set_rate = &omap2_clksel_set_rate, | |
972c5427 RN |
2767 | }; |
2768 | ||
e0cb70c5 RN |
2769 | /* SCRM aux clk nodes */ |
2770 | ||
ad03f1cb | 2771 | static const struct clksel auxclk_src_sel[] = { |
e0cb70c5 RN |
2772 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
2773 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, | |
2774 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, | |
2775 | { .parent = NULL }, | |
2776 | }; | |
2777 | ||
ad03f1cb RN |
2778 | static const struct clksel_rate div16_1to16_rates[] = { |
2779 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, | |
2780 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, | |
2781 | { .div = 3, .val = 2, .flags = RATE_IN_4430 }, | |
2782 | { .div = 4, .val = 3, .flags = RATE_IN_4430 }, | |
2783 | { .div = 5, .val = 4, .flags = RATE_IN_4430 }, | |
2784 | { .div = 6, .val = 5, .flags = RATE_IN_4430 }, | |
2785 | { .div = 7, .val = 6, .flags = RATE_IN_4430 }, | |
2786 | { .div = 8, .val = 7, .flags = RATE_IN_4430 }, | |
2787 | { .div = 9, .val = 8, .flags = RATE_IN_4430 }, | |
2788 | { .div = 10, .val = 9, .flags = RATE_IN_4430 }, | |
2789 | { .div = 11, .val = 10, .flags = RATE_IN_4430 }, | |
2790 | { .div = 12, .val = 11, .flags = RATE_IN_4430 }, | |
2791 | { .div = 13, .val = 12, .flags = RATE_IN_4430 }, | |
2792 | { .div = 14, .val = 13, .flags = RATE_IN_4430 }, | |
2793 | { .div = 15, .val = 14, .flags = RATE_IN_4430 }, | |
2794 | { .div = 16, .val = 15, .flags = RATE_IN_4430 }, | |
2795 | { .div = 0 }, | |
2796 | }; | |
2797 | ||
2798 | static struct clk auxclk0_src_ck = { | |
2799 | .name = "auxclk0_src_ck", | |
e0cb70c5 RN |
2800 | .parent = &sys_clkin_ck, |
2801 | .init = &omap2_init_clksel_parent, | |
2802 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2803 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2804 | .clksel_reg = OMAP4_SCRM_AUXCLK0, |
2805 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2806 | .recalc = &omap2_clksel_recalc, | |
2807 | .enable_reg = OMAP4_SCRM_AUXCLK0, | |
2808 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2809 | }; | |
2810 | ||
ad03f1cb RN |
2811 | static const struct clksel auxclk0_sel[] = { |
2812 | { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, | |
2813 | { .parent = NULL }, | |
2814 | }; | |
2815 | ||
2816 | static struct clk auxclk0_ck = { | |
2817 | .name = "auxclk0_ck", | |
2818 | .parent = &auxclk0_src_ck, | |
2819 | .clksel = auxclk0_sel, | |
2820 | .clksel_reg = OMAP4_SCRM_AUXCLK0, | |
2821 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2822 | .ops = &clkops_null, | |
2823 | .recalc = &omap2_clksel_recalc, | |
2824 | .round_rate = &omap2_clksel_round_rate, | |
2825 | .set_rate = &omap2_clksel_set_rate, | |
2826 | }; | |
2827 | ||
2828 | static struct clk auxclk1_src_ck = { | |
2829 | .name = "auxclk1_src_ck", | |
e0cb70c5 RN |
2830 | .parent = &sys_clkin_ck, |
2831 | .init = &omap2_init_clksel_parent, | |
2832 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2833 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2834 | .clksel_reg = OMAP4_SCRM_AUXCLK1, |
2835 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2836 | .recalc = &omap2_clksel_recalc, | |
2837 | .enable_reg = OMAP4_SCRM_AUXCLK1, | |
2838 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2839 | }; | |
2840 | ||
ad03f1cb RN |
2841 | static const struct clksel auxclk1_sel[] = { |
2842 | { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, | |
2843 | { .parent = NULL }, | |
2844 | }; | |
2845 | ||
2846 | static struct clk auxclk1_ck = { | |
2847 | .name = "auxclk1_ck", | |
2848 | .parent = &auxclk1_src_ck, | |
2849 | .clksel = auxclk1_sel, | |
2850 | .clksel_reg = OMAP4_SCRM_AUXCLK1, | |
2851 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2852 | .ops = &clkops_null, | |
2853 | .recalc = &omap2_clksel_recalc, | |
2854 | .round_rate = &omap2_clksel_round_rate, | |
2855 | .set_rate = &omap2_clksel_set_rate, | |
2856 | }; | |
2857 | ||
2858 | static struct clk auxclk2_src_ck = { | |
2859 | .name = "auxclk2_src_ck", | |
e0cb70c5 RN |
2860 | .parent = &sys_clkin_ck, |
2861 | .init = &omap2_init_clksel_parent, | |
2862 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2863 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2864 | .clksel_reg = OMAP4_SCRM_AUXCLK2, |
2865 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2866 | .recalc = &omap2_clksel_recalc, | |
2867 | .enable_reg = OMAP4_SCRM_AUXCLK2, | |
2868 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2869 | }; | |
7ecd4228 | 2870 | |
ad03f1cb RN |
2871 | static const struct clksel auxclk2_sel[] = { |
2872 | { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, | |
2873 | { .parent = NULL }, | |
2874 | }; | |
2875 | ||
2876 | static struct clk auxclk2_ck = { | |
2877 | .name = "auxclk2_ck", | |
2878 | .parent = &auxclk2_src_ck, | |
2879 | .clksel = auxclk2_sel, | |
2880 | .clksel_reg = OMAP4_SCRM_AUXCLK2, | |
2881 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2882 | .ops = &clkops_null, | |
2883 | .recalc = &omap2_clksel_recalc, | |
2884 | .round_rate = &omap2_clksel_round_rate, | |
2885 | .set_rate = &omap2_clksel_set_rate, | |
2886 | }; | |
2887 | ||
2888 | static struct clk auxclk3_src_ck = { | |
2889 | .name = "auxclk3_src_ck", | |
e0cb70c5 RN |
2890 | .parent = &sys_clkin_ck, |
2891 | .init = &omap2_init_clksel_parent, | |
2892 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2893 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2894 | .clksel_reg = OMAP4_SCRM_AUXCLK3, |
2895 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2896 | .recalc = &omap2_clksel_recalc, | |
2897 | .enable_reg = OMAP4_SCRM_AUXCLK3, | |
2898 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2899 | }; | |
2900 | ||
ad03f1cb RN |
2901 | static const struct clksel auxclk3_sel[] = { |
2902 | { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, | |
2903 | { .parent = NULL }, | |
2904 | }; | |
2905 | ||
2906 | static struct clk auxclk3_ck = { | |
2907 | .name = "auxclk3_ck", | |
2908 | .parent = &auxclk3_src_ck, | |
2909 | .clksel = auxclk3_sel, | |
2910 | .clksel_reg = OMAP4_SCRM_AUXCLK3, | |
2911 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2912 | .ops = &clkops_null, | |
2913 | .recalc = &omap2_clksel_recalc, | |
2914 | .round_rate = &omap2_clksel_round_rate, | |
2915 | .set_rate = &omap2_clksel_set_rate, | |
2916 | }; | |
2917 | ||
2918 | static struct clk auxclk4_src_ck = { | |
2919 | .name = "auxclk4_src_ck", | |
e0cb70c5 RN |
2920 | .parent = &sys_clkin_ck, |
2921 | .init = &omap2_init_clksel_parent, | |
2922 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2923 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2924 | .clksel_reg = OMAP4_SCRM_AUXCLK4, |
2925 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2926 | .recalc = &omap2_clksel_recalc, | |
2927 | .enable_reg = OMAP4_SCRM_AUXCLK4, | |
2928 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2929 | }; | |
2930 | ||
ad03f1cb RN |
2931 | static const struct clksel auxclk4_sel[] = { |
2932 | { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, | |
2933 | { .parent = NULL }, | |
2934 | }; | |
2935 | ||
2936 | static struct clk auxclk4_ck = { | |
2937 | .name = "auxclk4_ck", | |
2938 | .parent = &auxclk4_src_ck, | |
2939 | .clksel = auxclk4_sel, | |
2940 | .clksel_reg = OMAP4_SCRM_AUXCLK4, | |
2941 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2942 | .ops = &clkops_null, | |
2943 | .recalc = &omap2_clksel_recalc, | |
2944 | .round_rate = &omap2_clksel_round_rate, | |
2945 | .set_rate = &omap2_clksel_set_rate, | |
2946 | }; | |
2947 | ||
2948 | static struct clk auxclk5_src_ck = { | |
2949 | .name = "auxclk5_src_ck", | |
e0cb70c5 RN |
2950 | .parent = &sys_clkin_ck, |
2951 | .init = &omap2_init_clksel_parent, | |
2952 | .ops = &clkops_omap2_dflt, | |
ad03f1cb | 2953 | .clksel = auxclk_src_sel, |
e0cb70c5 RN |
2954 | .clksel_reg = OMAP4_SCRM_AUXCLK5, |
2955 | .clksel_mask = OMAP4_SRCSELECT_MASK, | |
2956 | .recalc = &omap2_clksel_recalc, | |
2957 | .enable_reg = OMAP4_SCRM_AUXCLK5, | |
2958 | .enable_bit = OMAP4_ENABLE_SHIFT, | |
2959 | }; | |
2960 | ||
ad03f1cb RN |
2961 | static const struct clksel auxclk5_sel[] = { |
2962 | { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates }, | |
2963 | { .parent = NULL }, | |
2964 | }; | |
2965 | ||
2966 | static struct clk auxclk5_ck = { | |
2967 | .name = "auxclk5_ck", | |
2968 | .parent = &auxclk5_src_ck, | |
2969 | .clksel = auxclk5_sel, | |
2970 | .clksel_reg = OMAP4_SCRM_AUXCLK5, | |
2971 | .clksel_mask = OMAP4_CLKDIV_MASK, | |
2972 | .ops = &clkops_null, | |
2973 | .recalc = &omap2_clksel_recalc, | |
2974 | .round_rate = &omap2_clksel_round_rate, | |
2975 | .set_rate = &omap2_clksel_set_rate, | |
2976 | }; | |
2977 | ||
e0cb70c5 RN |
2978 | static const struct clksel auxclkreq_sel[] = { |
2979 | { .parent = &auxclk0_ck, .rates = div_1_0_rates }, | |
2980 | { .parent = &auxclk1_ck, .rates = div_1_1_rates }, | |
2981 | { .parent = &auxclk2_ck, .rates = div_1_2_rates }, | |
2982 | { .parent = &auxclk3_ck, .rates = div_1_3_rates }, | |
2983 | { .parent = &auxclk4_ck, .rates = div_1_4_rates }, | |
2984 | { .parent = &auxclk5_ck, .rates = div_1_5_rates }, | |
2985 | { .parent = NULL }, | |
2986 | }; | |
2987 | ||
2988 | static struct clk auxclkreq0_ck = { | |
2989 | .name = "auxclkreq0_ck", | |
2990 | .parent = &auxclk0_ck, | |
2991 | .init = &omap2_init_clksel_parent, | |
2992 | .ops = &clkops_null, | |
2993 | .clksel = auxclkreq_sel, | |
2994 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, | |
2995 | .clksel_mask = OMAP4_MAPPING_MASK, | |
2996 | .recalc = &omap2_clksel_recalc, | |
2997 | }; | |
2998 | ||
2999 | static struct clk auxclkreq1_ck = { | |
3000 | .name = "auxclkreq1_ck", | |
3001 | .parent = &auxclk1_ck, | |
3002 | .init = &omap2_init_clksel_parent, | |
3003 | .ops = &clkops_null, | |
3004 | .clksel = auxclkreq_sel, | |
3005 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, | |
3006 | .clksel_mask = OMAP4_MAPPING_MASK, | |
3007 | .recalc = &omap2_clksel_recalc, | |
3008 | }; | |
3009 | ||
3010 | static struct clk auxclkreq2_ck = { | |
3011 | .name = "auxclkreq2_ck", | |
3012 | .parent = &auxclk2_ck, | |
3013 | .init = &omap2_init_clksel_parent, | |
3014 | .ops = &clkops_null, | |
3015 | .clksel = auxclkreq_sel, | |
3016 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, | |
3017 | .clksel_mask = OMAP4_MAPPING_MASK, | |
3018 | .recalc = &omap2_clksel_recalc, | |
3019 | }; | |
3020 | ||
3021 | static struct clk auxclkreq3_ck = { | |
3022 | .name = "auxclkreq3_ck", | |
3023 | .parent = &auxclk3_ck, | |
3024 | .init = &omap2_init_clksel_parent, | |
3025 | .ops = &clkops_null, | |
3026 | .clksel = auxclkreq_sel, | |
3027 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, | |
3028 | .clksel_mask = OMAP4_MAPPING_MASK, | |
3029 | .recalc = &omap2_clksel_recalc, | |
3030 | }; | |
3031 | ||
3032 | static struct clk auxclkreq4_ck = { | |
3033 | .name = "auxclkreq4_ck", | |
3034 | .parent = &auxclk4_ck, | |
3035 | .init = &omap2_init_clksel_parent, | |
3036 | .ops = &clkops_null, | |
3037 | .clksel = auxclkreq_sel, | |
3038 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, | |
3039 | .clksel_mask = OMAP4_MAPPING_MASK, | |
3040 | .recalc = &omap2_clksel_recalc, | |
3041 | }; | |
3042 | ||
3043 | static struct clk auxclkreq5_ck = { | |
3044 | .name = "auxclkreq5_ck", | |
3045 | .parent = &auxclk5_ck, | |
3046 | .init = &omap2_init_clksel_parent, | |
3047 | .ops = &clkops_null, | |
3048 | .clksel = auxclkreq_sel, | |
3049 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, | |
3050 | .clksel_mask = OMAP4_MAPPING_MASK, | |
3051 | .recalc = &omap2_clksel_recalc, | |
3052 | }; | |
3053 | ||
972c5427 RN |
3054 | /* |
3055 | * clkdev | |
3056 | */ | |
3057 | ||
3058 | static struct omap_clk omap44xx_clks[] = { | |
3059 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), | |
3060 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), | |
3061 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), | |
3062 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), | |
3063 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), | |
3064 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), | |
3065 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), | |
3066 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), | |
3067 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), | |
3068 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), | |
3069 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), | |
3070 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), | |
3071 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), | |
3072 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), | |
76cf5295 | 3073 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), |
972c5427 RN |
3074 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), |
3075 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), | |
3076 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), | |
3077 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), | |
76cf5295 | 3078 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
972c5427 RN |
3079 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
3080 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), | |
032b5a7e | 3081 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), |
972c5427 RN |
3082 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
3083 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), | |
3084 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), | |
3085 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), | |
032b5a7e | 3086 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
972c5427 RN |
3087 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
3088 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), | |
032b5a7e TG |
3089 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
3090 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), | |
972c5427 RN |
3091 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
3092 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), | |
3093 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), | |
032b5a7e | 3094 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
972c5427 RN |
3095 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
3096 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), | |
3097 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), | |
032b5a7e | 3098 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
972c5427 RN |
3099 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
3100 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), | |
032b5a7e TG |
3101 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
3102 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), | |
972c5427 RN |
3103 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
3104 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), | |
032b5a7e TG |
3105 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
3106 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), | |
3107 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), | |
972c5427 RN |
3108 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
3109 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), | |
3110 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), | |
3111 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), | |
3112 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), | |
3113 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), | |
032b5a7e | 3114 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), |
972c5427 | 3115 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
032b5a7e TG |
3116 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
3117 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), | |
3118 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), | |
3119 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), | |
3120 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), | |
972c5427 RN |
3121 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), |
3122 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), | |
3123 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), | |
3124 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), | |
3125 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), | |
3126 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), | |
3127 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), | |
3128 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), | |
3129 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), | |
3130 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), | |
3131 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), | |
3132 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), | |
972c5427 RN |
3133 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), |
3134 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), | |
3135 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), | |
3136 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), | |
3137 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), | |
30c95692 | 3138 | CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), |
972c5427 RN |
3139 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), |
3140 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), | |
de474535 | 3141 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), |
972c5427 RN |
3142 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), |
3143 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), | |
3144 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), | |
54776050 RN |
3145 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
3146 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), | |
3147 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), | |
1c03f42f | 3148 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), |
257d643d | 3149 | CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), |
54776050 | 3150 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
257d643d | 3151 | CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), |
972c5427 | 3152 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
54776050 | 3153 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
0e433271 | 3154 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), |
3a23aafc TV |
3155 | CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), |
3156 | CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), | |
3157 | CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), | |
3158 | CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), | |
6ea74cb9 | 3159 | CLK(NULL, "dss_fck", &dss_fck, CK_443X), |
2df122f5 | 3160 | CLK("omapdss_dss", "ick", &dss_fck, CK_443X), |
0e433271 BC |
3161 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), |
3162 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), | |
3163 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), | |
54776050 | 3164 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
0e433271 | 3165 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
b399bca8 | 3166 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), |
54776050 | 3167 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
b399bca8 | 3168 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), |
54776050 | 3169 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
b399bca8 | 3170 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), |
54776050 | 3171 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
b399bca8 | 3172 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), |
54776050 | 3173 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
b399bca8 | 3174 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), |
54776050 | 3175 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
b399bca8 | 3176 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), |
54776050 RN |
3177 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
3178 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), | |
0e433271 | 3179 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
bf1e0776 | 3180 | CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X), |
0e433271 | 3181 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
bf1e0776 BC |
3182 | CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X), |
3183 | CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), | |
3184 | CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), | |
3185 | CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), | |
0e433271 | 3186 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
1c03f42f | 3187 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
54776050 | 3188 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
0e433271 BC |
3189 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), |
3190 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), | |
3191 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), | |
3192 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), | |
972c5427 | 3193 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
54776050 | 3194 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
972c5427 | 3195 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
bf1e0776 | 3196 | CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), |
972c5427 | 3197 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
bf1e0776 | 3198 | CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), |
972c5427 | 3199 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
bf1e0776 | 3200 | CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), |
972c5427 | 3201 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
bf1e0776 | 3202 | CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), |
0e433271 | 3203 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), |
bf1e0776 BC |
3204 | CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), |
3205 | CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X), | |
3206 | CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X), | |
3207 | CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X), | |
3208 | CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X), | |
3209 | CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X), | |
3210 | CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X), | |
3211 | CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X), | |
3212 | CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X), | |
1c03f42f | 3213 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), |
0edc9e85 | 3214 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), |
0e433271 | 3215 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), |
6ea74cb9 | 3216 | CLK(NULL, "rng_ick", &rng_ick, CK_443X), |
54776050 | 3217 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
0e433271 BC |
3218 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
3219 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), | |
1c03f42f BC |
3220 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
3221 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), | |
3222 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), | |
3223 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), | |
54776050 | 3224 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
1c03f42f BC |
3225 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), |
3226 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), | |
3227 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), | |
54776050 | 3228 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
0e433271 BC |
3229 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), |
3230 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), | |
3231 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), | |
ae6df418 TKD |
3232 | CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), |
3233 | CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), | |
3234 | CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), | |
3235 | CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), | |
3236 | CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), | |
3237 | CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), | |
3238 | CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), | |
3239 | CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), | |
3240 | CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), | |
3241 | CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), | |
3242 | CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), | |
54776050 RN |
3243 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
3244 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), | |
3245 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), | |
3246 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), | |
a6d3a662 | 3247 | CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), |
6ea74cb9 | 3248 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
1c03f42f BC |
3249 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
3250 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), | |
3251 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), | |
3252 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), | |
032b5a7e | 3253 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), |
1c03f42f | 3254 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
032b5a7e TG |
3255 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), |
3256 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), | |
1c03f42f BC |
3257 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
3258 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), | |
6ea74cb9 | 3259 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
a6d3a662 | 3260 | CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X), |
1c03f42f BC |
3261 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
3262 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), | |
6ea74cb9 | 3263 | CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X), |
03491761 | 3264 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), |
0edc9e85 | 3265 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
1c03f42f BC |
3266 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
3267 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), | |
3268 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), | |
6ea74cb9 | 3269 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
a6d3a662 | 3270 | CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X), |
8fde3afb | 3271 | CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), |
0edc9e85 BC |
3272 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
3273 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), | |
0e433271 | 3274 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
bf1e0776 | 3275 | CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X), |
0e433271 | 3276 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), |
972c5427 RN |
3277 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
3278 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), | |
ad03f1cb | 3279 | CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X), |
7ecd4228 | 3280 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), |
7ecd4228 | 3281 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), |
ad03f1cb RN |
3282 | CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X), |
3283 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), | |
7ecd4228 | 3284 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), |
ad03f1cb RN |
3285 | CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X), |
3286 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), | |
7ecd4228 | 3287 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), |
ad03f1cb RN |
3288 | CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X), |
3289 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), | |
7ecd4228 | 3290 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), |
ad03f1cb RN |
3291 | CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X), |
3292 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), | |
7ecd4228 | 3293 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), |
ad03f1cb RN |
3294 | CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X), |
3295 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), | |
7ecd4228 | 3296 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), |
7c43d547 | 3297 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), |
f7bb0d9a BC |
3298 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
3299 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), | |
3300 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), | |
3301 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), | |
7ecd4228 | 3302 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), |
0005ae73 KK |
3303 | CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), |
3304 | CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), | |
3305 | CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), | |
3306 | CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), | |
3307 | CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3308 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), |
3309 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), | |
3310 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), | |
3311 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), | |
0e433271 BC |
3312 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), |
3313 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), | |
3314 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), | |
3315 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), | |
7c43d547 SS |
3316 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), |
3317 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), | |
3318 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), | |
3319 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), | |
a6d3a662 KM |
3320 | CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X), |
3321 | CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X), | |
8fde3afb | 3322 | CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X), |
7c43d547 | 3323 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), |
c59b537d | 3324 | CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X), |
fabcf41f | 3325 | /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */ |
c59b537d JH |
3326 | CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
3327 | CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3328 | CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3329 | CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3330 | CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3331 | CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3332 | CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3333 | CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3334 | CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3335 | CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3336 | CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
fabcf41f JH |
3337 | CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), |
3338 | CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3339 | CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3340 | CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3341 | CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3342 | CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3343 | CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X), | |
3344 | CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3345 | CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3346 | CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
3347 | CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X), | |
c810fde2 | 3348 | CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), |
972c5427 RN |
3349 | }; |
3350 | ||
e80a9729 | 3351 | int __init omap4xxx_clk_init(void) |
972c5427 | 3352 | { |
972c5427 | 3353 | struct omap_clk *c; |
972c5427 RN |
3354 | u32 cpu_clkflg; |
3355 | ||
52a3a4d4 | 3356 | if (cpu_is_omap443x()) { |
972c5427 RN |
3357 | cpu_mask = RATE_IN_4430; |
3358 | cpu_clkflg = CK_443X; | |
e90b833e | 3359 | } else if (cpu_is_omap446x() || cpu_is_omap447x()) { |
52a3a4d4 PW |
3360 | cpu_mask = RATE_IN_4460 | RATE_IN_4430; |
3361 | cpu_clkflg = CK_446X | CK_443X; | |
e90b833e JH |
3362 | |
3363 | if (cpu_is_omap447x()) | |
3364 | pr_warn("WARNING: OMAP4470 clock data incomplete!\n"); | |
450a37d2 PW |
3365 | } else { |
3366 | return 0; | |
972c5427 RN |
3367 | } |
3368 | ||
3369 | clk_init(&omap2_clk_functions); | |
9c5f5601 PW |
3370 | |
3371 | /* | |
3372 | * Must stay commented until all OMAP SoC drivers are | |
3373 | * converted to runtime PM, or drivers may start crashing | |
3374 | * | |
3375 | * omap2_clk_disable_clkdm_control(); | |
3376 | */ | |
972c5427 RN |
3377 | |
3378 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3379 | c++) | |
3380 | clk_preinit(c->lk.clk); | |
3381 | ||
3382 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); | |
3383 | c++) | |
3384 | if (c->cpu & cpu_clkflg) { | |
3385 | clkdev_add(&c->lk); | |
3386 | clk_register(c->lk.clk); | |
972c5427 | 3387 | omap2_init_clk_clkdm(c->lk.clk); |
972c5427 RN |
3388 | } |
3389 | ||
c6461f5c PW |
3390 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
3391 | omap_clk_disable_autoidle_all(); | |
3392 | ||
972c5427 RN |
3393 | recalculate_root_clocks(); |
3394 | ||
3395 | /* | |
3396 | * Only enable those clocks we will need, let the drivers | |
3397 | * enable other clocks as necessary | |
3398 | */ | |
3399 | clk_enable_init_clocks(); | |
3400 | ||
3401 | return 0; | |
3402 | } |