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a64459c4 AM |
1 | /* |
2 | * TI81XX Clock Domain data. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ | |
5 | * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H | |
18 | #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/io.h> | |
22 | ||
23 | #include "clockdomain.h" | |
24 | #include "cm81xx.h" | |
25 | ||
26 | /* | |
27 | * Note that 814x seems to have HWSUP_SWSUP for many clockdomains | |
28 | * while 816x does not. According to the TRM, 816x only has HWSUP | |
29 | * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h | |
30 | * seems to have the related ifdef the wrong way around claiming | |
31 | * 816x supports HWSUP while 814x does not. For now, we only set | |
32 | * HWSUP for ALWON_L3_FAST as that seems to be supported for both | |
33 | * dm814x and dm816x. | |
34 | */ | |
35 | ||
36 | /* Common for 81xx */ | |
37 | ||
38 | static struct clockdomain alwon_l3_slow_81xx_clkdm = { | |
39 | .name = "alwon_l3s_clkdm", | |
40 | .pwrdm = { .name = "alwon_pwrdm" }, | |
41 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
42 | .clkdm_offs = TI81XX_CM_ALWON_L3_SLOW_CLKDM, | |
43 | .flags = CLKDM_CAN_SWSUP, | |
44 | }; | |
45 | ||
46 | static struct clockdomain alwon_l3_med_81xx_clkdm = { | |
47 | .name = "alwon_l3_med_clkdm", | |
48 | .pwrdm = { .name = "alwon_pwrdm" }, | |
49 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
50 | .clkdm_offs = TI81XX_CM_ALWON_L3_MED_CLKDM, | |
51 | .flags = CLKDM_CAN_SWSUP, | |
52 | }; | |
53 | ||
54 | static struct clockdomain alwon_l3_fast_81xx_clkdm = { | |
55 | .name = "alwon_l3_fast_clkdm", | |
56 | .pwrdm = { .name = "alwon_pwrdm" }, | |
57 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
58 | .clkdm_offs = TI81XX_CM_ALWON_L3_FAST_CLKDM, | |
59 | .flags = CLKDM_CAN_HWSUP_SWSUP, | |
60 | }; | |
61 | ||
62 | static struct clockdomain alwon_ethernet_81xx_clkdm = { | |
63 | .name = "alwon_ethernet_clkdm", | |
64 | .pwrdm = { .name = "alwon_pwrdm" }, | |
65 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
66 | .clkdm_offs = TI81XX_CM_ETHERNET_CLKDM, | |
67 | .flags = CLKDM_CAN_SWSUP, | |
68 | }; | |
69 | ||
70 | static struct clockdomain mmu_81xx_clkdm = { | |
71 | .name = "mmu_clkdm", | |
72 | .pwrdm = { .name = "alwon_pwrdm" }, | |
73 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
74 | .clkdm_offs = TI81XX_CM_MMU_CLKDM, | |
75 | .flags = CLKDM_CAN_SWSUP, | |
76 | }; | |
77 | ||
78 | static struct clockdomain mmu_cfg_81xx_clkdm = { | |
79 | .name = "mmu_cfg_clkdm", | |
80 | .pwrdm = { .name = "alwon_pwrdm" }, | |
81 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
82 | .clkdm_offs = TI81XX_CM_MMUCFG_CLKDM, | |
83 | .flags = CLKDM_CAN_SWSUP, | |
84 | }; | |
85 | ||
86 | /* 816x only */ | |
87 | ||
88 | static struct clockdomain alwon_mpu_816x_clkdm = { | |
89 | .name = "alwon_mpu_clkdm", | |
90 | .pwrdm = { .name = "alwon_pwrdm" }, | |
91 | .cm_inst = TI81XX_CM_ALWON_MOD, | |
92 | .clkdm_offs = TI81XX_CM_ALWON_MPU_CLKDM, | |
93 | .flags = CLKDM_CAN_SWSUP, | |
94 | }; | |
95 | ||
96 | static struct clockdomain active_gem_816x_clkdm = { | |
97 | .name = "active_gem_clkdm", | |
98 | .pwrdm = { .name = "active_pwrdm" }, | |
99 | .cm_inst = TI816X_CM_ACTIVE_MOD, | |
100 | .clkdm_offs = TI816X_CM_ACTIVE_GEM_CLKDM, | |
101 | .flags = CLKDM_CAN_SWSUP, | |
102 | }; | |
103 | ||
104 | static struct clockdomain ivahd0_816x_clkdm = { | |
105 | .name = "ivahd0_clkdm", | |
106 | .pwrdm = { .name = "ivahd0_pwrdm" }, | |
107 | .cm_inst = TI816X_CM_IVAHD0_MOD, | |
108 | .clkdm_offs = TI816X_CM_IVAHD0_CLKDM, | |
109 | .flags = CLKDM_CAN_SWSUP, | |
110 | }; | |
111 | ||
112 | static struct clockdomain ivahd1_816x_clkdm = { | |
113 | .name = "ivahd1_clkdm", | |
114 | .pwrdm = { .name = "ivahd1_pwrdm" }, | |
115 | .cm_inst = TI816X_CM_IVAHD1_MOD, | |
116 | .clkdm_offs = TI816X_CM_IVAHD1_CLKDM, | |
117 | .flags = CLKDM_CAN_SWSUP, | |
118 | }; | |
119 | ||
120 | static struct clockdomain ivahd2_816x_clkdm = { | |
121 | .name = "ivahd2_clkdm", | |
122 | .pwrdm = { .name = "ivahd2_pwrdm" }, | |
123 | .cm_inst = TI816X_CM_IVAHD2_MOD, | |
124 | .clkdm_offs = TI816X_CM_IVAHD2_CLKDM, | |
125 | .flags = CLKDM_CAN_SWSUP, | |
126 | }; | |
127 | ||
128 | static struct clockdomain sgx_816x_clkdm = { | |
129 | .name = "sgx_clkdm", | |
130 | .pwrdm = { .name = "sgx_pwrdm" }, | |
131 | .cm_inst = TI816X_CM_SGX_MOD, | |
132 | .clkdm_offs = TI816X_CM_SGX_CLKDM, | |
133 | .flags = CLKDM_CAN_SWSUP, | |
134 | }; | |
135 | ||
136 | static struct clockdomain default_l3_med_816x_clkdm = { | |
137 | .name = "default_l3_med_clkdm", | |
138 | .pwrdm = { .name = "default_pwrdm" }, | |
139 | .cm_inst = TI816X_CM_DEFAULT_MOD, | |
140 | .clkdm_offs = TI816X_CM_DEFAULT_L3_MED_CLKDM, | |
141 | .flags = CLKDM_CAN_SWSUP, | |
142 | }; | |
143 | ||
144 | static struct clockdomain default_ducati_816x_clkdm = { | |
145 | .name = "default_ducati_clkdm", | |
146 | .pwrdm = { .name = "default_pwrdm" }, | |
147 | .cm_inst = TI816X_CM_DEFAULT_MOD, | |
148 | .clkdm_offs = TI816X_CM_DEFAULT_DUCATI_CLKDM, | |
149 | .flags = CLKDM_CAN_SWSUP, | |
150 | }; | |
151 | ||
152 | static struct clockdomain default_pci_816x_clkdm = { | |
153 | .name = "default_pci_clkdm", | |
154 | .pwrdm = { .name = "default_pwrdm" }, | |
155 | .cm_inst = TI816X_CM_DEFAULT_MOD, | |
156 | .clkdm_offs = TI816X_CM_DEFAULT_PCI_CLKDM, | |
157 | .flags = CLKDM_CAN_SWSUP, | |
158 | }; | |
159 | ||
160 | static struct clockdomain default_l3_slow_816x_clkdm = { | |
161 | .name = "default_l3_slow_clkdm", | |
162 | .pwrdm = { .name = "default_pwrdm" }, | |
163 | .cm_inst = TI816X_CM_DEFAULT_MOD, | |
164 | .clkdm_offs = TI816X_CM_DEFAULT_L3_SLOW_CLKDM, | |
165 | .flags = CLKDM_CAN_SWSUP, | |
166 | }; | |
167 | ||
168 | static struct clockdomain *clockdomains_ti81xx[] __initdata = { | |
169 | &alwon_mpu_816x_clkdm, | |
170 | &alwon_l3_slow_81xx_clkdm, | |
171 | &alwon_l3_med_81xx_clkdm, | |
172 | &alwon_l3_fast_81xx_clkdm, | |
173 | &alwon_ethernet_81xx_clkdm, | |
174 | &mmu_81xx_clkdm, | |
175 | &mmu_cfg_81xx_clkdm, | |
176 | &active_gem_816x_clkdm, | |
177 | &ivahd0_816x_clkdm, | |
178 | &ivahd1_816x_clkdm, | |
179 | &ivahd2_816x_clkdm, | |
180 | &sgx_816x_clkdm, | |
181 | &default_l3_med_816x_clkdm, | |
182 | &default_ducati_816x_clkdm, | |
183 | &default_pci_816x_clkdm, | |
184 | &default_l3_slow_816x_clkdm, | |
185 | NULL, | |
186 | }; | |
187 | ||
188 | void __init ti81xx_clockdomains_init(void) | |
189 | { | |
190 | clkdm_register_platform_funcs(&am33xx_clkdm_operations); | |
191 | clkdm_register_clkdms(clockdomains_ti81xx); | |
192 | clkdm_complete_init(); | |
193 | } | |
194 | #endif |