[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / cm.h

#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
#define __ARCH_ASM_MACH_OMAP2_CM_H

/*
 * OMAP2/3 Clock Management (CM) register definitions
 *
 * Copyright (C) 2007-2009 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "prcm-common.h"

#define OMAP2420_CM_REGADDR(module, reg)				\
			OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg)				\
			OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg)				\
			OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))


#include "cm44xx.h"

/*
 * Architecture-specific global CM registers
 * Use cm_{read,write}_reg() with these registers.
 * These registers appear once per CM module.
 */

#define OMAP3430_CM_REVISION		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG		OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL		OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)

#define OMAP3_CM_CLKOUT_CTRL_OFFSET	0x0070
#define OMAP3430_CM_CLKOUT_CTRL		OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)

/*
 * Module specific CM registers from CM_BASE + domain offset
 * Use cm_{read,write}_mod_reg() with these registers.
 * These register offsets generally appear in more than one PRCM submodule.
 */

/* Common between 24xx and 34xx */

#define CM_FCLKEN					0x0000
#define CM_FCLKEN1					CM_FCLKEN
#define CM_CLKEN					CM_FCLKEN
#define CM_ICLKEN					0x0010
#define CM_ICLKEN1					CM_ICLKEN
#define CM_ICLKEN2					0x0014
#define CM_ICLKEN3					0x0018
#define CM_IDLEST					0x0020
#define CM_IDLEST1					CM_IDLEST
#define CM_IDLEST2					0x0024
#define CM_AUTOIDLE					0x0030
#define CM_AUTOIDLE1					CM_AUTOIDLE
#define CM_AUTOIDLE2					0x0034
#define CM_AUTOIDLE3					0x0038
#define CM_CLKSEL					0x0040
#define CM_CLKSEL1					CM_CLKSEL
#define CM_CLKSEL2					0x0044
#define OMAP2_CM_CLKSTCTRL				0x0048
#define OMAP4_CM_CLKSTCTRL				0x0000


/* Architecture-specific registers */

#define OMAP24XX_CM_FCLKEN2				0x0004
#define OMAP24XX_CM_ICLKEN4				0x001c
#define OMAP24XX_CM_AUTOIDLE4				0x003c

#define OMAP2430_CM_IDLEST3				0x0028

#define OMAP3430_CM_CLKEN_PLL				0x0004
#define OMAP3430ES2_CM_CLKEN2				0x0004
#define OMAP3430ES2_CM_FCLKEN3				0x0008
#define OMAP3430_CM_IDLEST_PLL				CM_IDLEST2
#define OMAP3430_CM_AUTOIDLE_PLL			CM_AUTOIDLE2
#define OMAP3430ES2_CM_AUTOIDLE2_PLL			CM_AUTOIDLE2
#define OMAP3430_CM_CLKSEL1				CM_CLKSEL
#define OMAP3430_CM_CLKSEL1_PLL				CM_CLKSEL
#define OMAP3430_CM_CLKSEL2_PLL				CM_CLKSEL2
#define OMAP3430_CM_SLEEPDEP				CM_CLKSEL2
#define OMAP3430_CM_CLKSEL3				OMAP2_CM_CLKSTCTRL
#define OMAP3430_CM_CLKSTST				0x004c
#define OMAP3430ES2_CM_CLKSEL4				0x004c
#define OMAP3430ES2_CM_CLKSEL5				0x0050
#define OMAP3430_CM_CLKSEL2_EMU				0x0050
#define OMAP3430_CM_CLKSEL3_EMU				0x0054

/* CM2.CEFUSE_CM2 register offsets */

/* OMAP4 modulemode control */
#define OMAP4430_MODULEMODE_HWCTRL			0
#define OMAP4430_MODULEMODE_SWCTRL			1

/* Clock management domain register get/set */

#ifndef __ASSEMBLER__

extern u32 cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);

extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
				      u8 idlest_shift);
extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);

static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return cm_rmw_mod_reg_bits(bits, bits, module, idx);
}

static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}

#endif

/* CM register bits shared between 24XX and 3430 */

/* CM_CLKSEL_GFX */
#define OMAP_CLKSEL_GFX_SHIFT				0
#define OMAP_CLKSEL_GFX_MASK				(0x7 << 0)

/* CM_ICLKEN_GFX */
#define OMAP_EN_GFX_SHIFT				0
#define OMAP_EN_GFX_MASK				(1 << 0)

/* CM_IDLEST_GFX */
#define OMAP_ST_GFX_MASK				(1 << 0)


/* CM_IDLEST indicator */
#define OMAP24XX_CM_IDLEST_VAL		0
#define OMAP34XX_CM_IDLEST_VAL		1

/*
 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
 * PRCM to request that a module exit the inactive state in the case of
 * OMAP2 & 3.
 * In the case of OMAP4 this is the max duration in microseconds for the
 * module to reach the functionnal state from an inactive state.
 */
#define MAX_MODULE_READY_TIME		2000

#endif
Commit	Line	Data
69d88a00 PW	1	#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
	2	#define __ARCH_ASM_MACH_OMAP2_CM_H
	3
	4	/*
	5	* OMAP2/3 Clock Management (CM) register definitions
	6	*
9b47267f RN	7	* Copyright (C) 2007-2009 Texas Instruments, Inc.
9b47267f RN	8	* Copyright (C) 2007-2009 Nokia Corporation
69d88a00 PW	9	*
	10	* Written by Paul Walmsley
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include "prcm-common.h"
	18
69d88a00	19	#define OMAP2420_CM_REGADDR(module, reg) \
233fd64e	20	OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
69d88a00	21	#define OMAP2430_CM_REGADDR(module, reg) \
233fd64e	22	OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
69d88a00	23	#define OMAP34XX_CM_REGADDR(module, reg) \
233fd64e	24	OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
d198b514	25
9b47267f RN	26
9b47267f RN	27	#include "cm44xx.h"
69d88a00 PW	28
	29	/*
	30	* Architecture-specific global CM registers
	31	* Use cm_{read,write}_reg() with these registers.
	32	* These registers appear once per CM module.
	33	*/
	34
364dd474 KH	35	#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
	36	#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
	37	#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
69d88a00	38
8e3bd351	39	#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
69d88a00 PW	40	#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
	41
	42	/*
	43	* Module specific CM registers from CM_BASE + domain offset
	44	* Use cm_{read,write}_mod_reg() with these registers.
	45	* These register offsets generally appear in more than one PRCM submodule.
	46	*/
	47
	48	/* Common between 24xx and 34xx */
	49
	50	#define CM_FCLKEN 0x0000
	51	#define CM_FCLKEN1 CM_FCLKEN
	52	#define CM_CLKEN CM_FCLKEN
	53	#define CM_ICLKEN 0x0010
	54	#define CM_ICLKEN1 CM_ICLKEN
	55	#define CM_ICLKEN2 0x0014
	56	#define CM_ICLKEN3 0x0018
	57	#define CM_IDLEST 0x0020
	58	#define CM_IDLEST1 CM_IDLEST
	59	#define CM_IDLEST2 0x0024
	60	#define CM_AUTOIDLE 0x0030
	61	#define CM_AUTOIDLE1 CM_AUTOIDLE
	62	#define CM_AUTOIDLE2 0x0034
	63	#define CM_AUTOIDLE3 0x0038
	64	#define CM_CLKSEL 0x0040
	65	#define CM_CLKSEL1 CM_CLKSEL
	66	#define CM_CLKSEL2 0x0044
84c0c39a AP	67	#define OMAP2_CM_CLKSTCTRL 0x0048
84c0c39a AP	68	#define OMAP4_CM_CLKSTCTRL 0x0000
69d88a00 PW	69
	70
	71	/* Architecture-specific registers */
	72
	73	#define OMAP24XX_CM_FCLKEN2 0x0004
	74	#define OMAP24XX_CM_ICLKEN4 0x001c
	75	#define OMAP24XX_CM_AUTOIDLE4 0x003c
	76
	77	#define OMAP2430_CM_IDLEST3 0x0028
	78
	79	#define OMAP3430_CM_CLKEN_PLL 0x0004
	80	#define OMAP3430ES2_CM_CLKEN2 0x0004
	81	#define OMAP3430ES2_CM_FCLKEN3 0x0008
	82	#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
	83	#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
542313cc	84	#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
69d88a00 PW	85	#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
	86	#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
	87	#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
	88	#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
84c0c39a	89	#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
69d88a00 PW	90	#define OMAP3430_CM_CLKSTST 0x004c
	91	#define OMAP3430ES2_CM_CLKSEL4 0x004c
	92	#define OMAP3430ES2_CM_CLKSEL5 0x0050
	93	#define OMAP3430_CM_CLKSEL2_EMU 0x0050
	94	#define OMAP3430_CM_CLKSEL3_EMU 0x0054
	95
9b47267f	96	/* CM2.CEFUSE_CM2 register offsets */
69d88a00	97
d79b1267 RN	98	/* OMAP4 modulemode control */
	99	#define OMAP4430_MODULEMODE_HWCTRL 0
	100	#define OMAP4430_MODULEMODE_SWCTRL 1
	101
69d88a00 PW	102	/* Clock management domain register get/set */
	103
	104	#ifndef __ASSEMBLER__
a58caad1 TL	105
	106	extern u32 cm_read_mod_reg(s16 module, u16 idx);
	107	extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
ff00fcc9 TL	108	extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
ff00fcc9 TL	109
71348bca PW	110	extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
71348bca PW	111	u8 idlest_shift);
9a23dfe1	112	extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
71348bca	113
ff00fcc9 TL	114	static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
	115	{
	116	return cm_rmw_mod_reg_bits(bits, bits, module, idx);
	117	}
	118
	119	static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
	120	{
	121	return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
	122	}
a58caad1	123
69d88a00 PW	124	#endif
	125
	126	/* CM register bits shared between 24XX and 3430 */
	127
	128	/* CM_CLKSEL_GFX */
	129	#define OMAP_CLKSEL_GFX_SHIFT 0
	130	#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
	131
	132	/* CM_ICLKEN_GFX */
	133	#define OMAP_EN_GFX_SHIFT 0
2fd0f75c	134	#define OMAP_EN_GFX_MASK (1 << 0)
69d88a00 PW	135
69d88a00 PW	136	/* CM_IDLEST_GFX */
2fd0f75c PW	137	#define OMAP_ST_GFX_MASK (1 << 0)
2fd0f75c PW	138
69d88a00	139
419cc97d RL	140	/* CM_IDLEST indicator */
	141	#define OMAP24XX_CM_IDLEST_VAL 0
	142	#define OMAP34XX_CM_IDLEST_VAL 1
69d88a00	143
d9e6625c BC	144	/*
	145	* MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
	146	* PRCM to request that a module exit the inactive state in the case of
	147	* OMAP2 & 3.
	148	* In the case of OMAP4 this is the max duration in microseconds for the
	149	* module to reach the functionnal state from an inactive state.
	150	*/
	151	#define MAX_MODULE_READY_TIME 2000
	152
69d88a00	153	#endif