projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9b47267f RN |
1 | /* |
| 2 | * OMAP44xx CM1 & CM2 instance offset macros | |
| 3 | * | |
| a610855c BC |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | |
| 9b47267f RN |
6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H | |
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM44XX_H | |
| 24 | ||
| 25 | ||
| 26 | /* CM1 */ | |
| 27 | ||
| 9b47267f | 28 | /* CM1.OCP_SOCKET_CM1 register offsets */ |
| fe894d56 | 29 | #define OMAP4_REVISION_CM1_OFFSET 0x0000 |
| 9b47267f | 30 | #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000) |
| fe894d56 | 31 | #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 |
| 9b47267f RN |
32 | #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040) |
| 33 | ||
| 34 | /* CM1.CKGEN_CM1 register offsets */ | |
| fe894d56 | 35 | #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 |
| 9b47267f | 36 | #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000) |
| fe894d56 | 37 | #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 |
| 9b47267f | 38 | #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008) |
| fe894d56 | 39 | #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 |
| 9b47267f | 40 | #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010) |
| fe894d56 | 41 | #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 |
| 9b47267f | 42 | #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020) |
| fe894d56 | 43 | #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 |
| 9b47267f | 44 | #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024) |
| fe894d56 | 45 | #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 |
| 9b47267f | 46 | #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028) |
| fe894d56 | 47 | #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c |
| 9b47267f | 48 | #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c) |
| fe894d56 | 49 | #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 |
| 9b47267f | 50 | #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030) |
| fe894d56 | 51 | #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 |
| 9b47267f | 52 | #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034) |
| fe894d56 | 53 | #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 |
| 9b47267f | 54 | #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038) |
| fe894d56 | 55 | #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c |
| 9b47267f | 56 | #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c) |
| fe894d56 | 57 | #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 |
| 9b47267f | 58 | #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040) |
| fe894d56 | 59 | #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 |
| 9b47267f | 60 | #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044) |
| fe894d56 | 61 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 |
| 9b47267f | 62 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048) |
| fe894d56 | 63 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c |
| 9b47267f | 64 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c) |
| fe894d56 | 65 | #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 |
| 9b47267f | 66 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050) |
| fe894d56 | 67 | #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 |
| 9b47267f | 68 | #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060) |
| fe894d56 | 69 | #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 |
| 9b47267f | 70 | #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064) |
| fe894d56 | 71 | #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 |
| 9b47267f | 72 | #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068) |
| fe894d56 | 73 | #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c |
| 9b47267f | 74 | #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c) |
| fe894d56 | 75 | #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 |
| 9b47267f | 76 | #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070) |
| fe894d56 | 77 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 |
| 9b47267f | 78 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088) |
| fe894d56 | 79 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c |
| 9b47267f | 80 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c) |
| fe894d56 | 81 | #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c |
| 9b47267f | 82 | #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c) |
| fe894d56 | 83 | #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 |
| 9b47267f | 84 | #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0) |
| fe894d56 | 85 | #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 |
| 9b47267f | 86 | #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4) |
| fe894d56 | 87 | #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 |
| 9b47267f | 88 | #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8) |
| fe894d56 | 89 | #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac |
| 9b47267f | 90 | #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac) |
| fe894d56 | 91 | #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 |
| 9b47267f | 92 | #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8) |
| fe894d56 | 93 | #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc |
| 9b47267f | 94 | #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc) |
| fe894d56 | 95 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 |
| 9b47267f | 96 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8) |
| fe894d56 | 97 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc |
| 9b47267f | 98 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc) |
| fe894d56 | 99 | #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc |
| 9b47267f | 100 | #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc) |
| fe894d56 | 101 | #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 |
| 9b47267f | 102 | #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0) |
| fe894d56 | 103 | #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 |
| 9b47267f | 104 | #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4) |
| fe894d56 | 105 | #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 |
| 9b47267f | 106 | #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8) |
| fe894d56 | 107 | #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec |
| 9b47267f | 108 | #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec) |
| fe894d56 | 109 | #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 |
| 9b47267f | 110 | #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0) |
| fe894d56 | 111 | #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 |
| 9b47267f | 112 | #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4) |
| fe894d56 | 113 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 |
| 9b47267f | 114 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108) |
| fe894d56 | 115 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c |
| 9b47267f | 116 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c) |
| fe894d56 | 117 | #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 |
| 9b47267f | 118 | #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120) |
| fe894d56 | 119 | #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 |
| 9b47267f | 120 | #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124) |
| fe894d56 | 121 | #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 |
| 9b47267f | 122 | #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128) |
| fe894d56 | 123 | #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c |
| 9b47267f | 124 | #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c) |
| fe894d56 | 125 | #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 |
| 9b47267f | 126 | #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130) |
| fe894d56 | 127 | #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 |
| 9b47267f | 128 | #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138) |
| fe894d56 | 129 | #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c |
| 9b47267f | 130 | #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c) |
| fe894d56 | 131 | #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 |
| 9b47267f | 132 | #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140) |
| fe894d56 | 133 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 |
| 9b47267f | 134 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148) |
| fe894d56 | 135 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c |
| 9b47267f | 136 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c) |
| fe894d56 | 137 | #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 |
| 9b47267f | 138 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160) |
| fe894d56 | 139 | #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 |
| 9b47267f | 140 | #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164) |
| fe894d56 | 141 | #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 |
| 9b47267f | 142 | #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170) |
| fe894d56 | 143 | #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 |
| 9b47267f RN |
144 | #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180) |
| 145 | ||
| 146 | /* CM1.MPU_CM1 register offsets */ | |
| fe894d56 | 147 | #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 148 | #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000) |
| fe894d56 | 149 | #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 150 | #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004) |
| fe894d56 | 151 | #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 152 | #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008) |
| fe894d56 | 153 | #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 |
| 9b47267f RN |
154 | #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020) |
| 155 | ||
| 156 | /* CM1.TESLA_CM1 register offsets */ | |
| fe894d56 | 157 | #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 158 | #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000) |
| fe894d56 | 159 | #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 160 | #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004) |
| fe894d56 | 161 | #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 162 | #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008) |
| fe894d56 | 163 | #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 |
| 9b47267f RN |
164 | #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020) |
| 165 | ||
| 166 | /* CM1.ABE_CM1 register offsets */ | |
| fe894d56 | 167 | #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 168 | #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000) |
| fe894d56 | 169 | #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 170 | #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020) |
| fe894d56 | 171 | #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 |
| 9b47267f | 172 | #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028) |
| fe894d56 | 173 | #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 |
| 9b47267f | 174 | #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030) |
| fe894d56 | 175 | #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 |
| 9b47267f | 176 | #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038) |
| fe894d56 | 177 | #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 |
| 9b47267f | 178 | #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040) |
| fe894d56 | 179 | #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 |
| 9b47267f | 180 | #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048) |
| fe894d56 | 181 | #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 |
| 9b47267f | 182 | #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050) |
| fe894d56 | 183 | #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 |
| 9b47267f | 184 | #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058) |
| fe894d56 | 185 | #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 |
| 9b47267f | 186 | #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060) |
| fe894d56 | 187 | #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 |
| 9b47267f | 188 | #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068) |
| fe894d56 | 189 | #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 |
| 9b47267f | 190 | #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070) |
| fe894d56 | 191 | #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 |
| 9b47267f | 192 | #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078) |
| fe894d56 | 193 | #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 |
| 9b47267f | 194 | #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080) |
| fe894d56 | 195 | #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 |
| 9b47267f RN |
196 | #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) |
| 197 | ||
| 9b47267f RN |
198 | /* CM2 */ |
| 199 | ||
| 9b47267f | 200 | /* CM2.OCP_SOCKET_CM2 register offsets */ |
| fe894d56 | 201 | #define OMAP4_REVISION_CM2_OFFSET 0x0000 |
| 9b47267f | 202 | #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000) |
| fe894d56 | 203 | #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 |
| 9b47267f RN |
204 | #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040) |
| 205 | ||
| 206 | /* CM2.CKGEN_CM2 register offsets */ | |
| fe894d56 | 207 | #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 |
| 9b47267f | 208 | #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000) |
| fe894d56 | 209 | #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 |
| 9b47267f | 210 | #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004) |
| fe894d56 | 211 | #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 |
| 9b47267f | 212 | #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008) |
| fe894d56 | 213 | #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 |
| 9b47267f | 214 | #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010) |
| fe894d56 | 215 | #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 |
| 9b47267f | 216 | #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014) |
| fe894d56 | 217 | #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 |
| 9b47267f | 218 | #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018) |
| fe894d56 | 219 | #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c |
| 9b47267f | 220 | #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c) |
| fe894d56 | 221 | #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 |
| 9b47267f | 222 | #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024) |
| fe894d56 | 223 | #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 |
| 9b47267f | 224 | #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028) |
| fe894d56 | 225 | #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c |
| 9b47267f | 226 | #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c) |
| fe894d56 | 227 | #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 |
| 9b47267f | 228 | #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030) |
| fe894d56 | 229 | #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 |
| 9b47267f | 230 | #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038) |
| fe894d56 | 231 | #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 |
| 9b47267f | 232 | #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040) |
| fe894d56 | 233 | #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 |
| 9b47267f | 234 | #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044) |
| fe894d56 | 235 | #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 |
| 9b47267f | 236 | #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048) |
| fe894d56 | 237 | #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c |
| 9b47267f | 238 | #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c) |
| fe894d56 | 239 | #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 |
| 9b47267f | 240 | #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050) |
| fe894d56 | 241 | #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 |
| 9b47267f | 242 | #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054) |
| fe894d56 | 243 | #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 |
| 9b47267f | 244 | #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058) |
| fe894d56 | 245 | #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c |
| 9b47267f | 246 | #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c) |
| fe894d56 | 247 | #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 |
| 9b47267f | 248 | #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060) |
| fe894d56 | 249 | #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 |
| 9b47267f | 250 | #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064) |
| fe894d56 | 251 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 |
| 9b47267f | 252 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) |
| fe894d56 | 253 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c |
| 9b47267f | 254 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) |
| fe894d56 | 255 | #define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070 |
| 9b47267f | 256 | #define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070) |
| fe894d56 | 257 | #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 |
| 9b47267f | 258 | #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) |
| fe894d56 | 259 | #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 |
| 9b47267f | 260 | #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084) |
| fe894d56 | 261 | #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 |
| 9b47267f | 262 | #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088) |
| fe894d56 | 263 | #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c |
| 9b47267f | 264 | #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c) |
| fe894d56 | 265 | #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 |
| 9b47267f | 266 | #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090) |
| fe894d56 | 267 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 |
| 9b47267f | 268 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8) |
| fe894d56 | 269 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac |
| 9b47267f | 270 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac) |
| fe894d56 | 271 | #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 |
| 9b47267f | 272 | #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4) |
| fe894d56 | 273 | #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 |
| 9b47267f | 274 | #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0) |
| fe894d56 | 275 | #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 |
| 9b47267f | 276 | #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4) |
| fe894d56 | 277 | #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 |
| 9b47267f | 278 | #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8) |
| fe894d56 | 279 | #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc |
| 9b47267f | 280 | #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc) |
| fe894d56 | 281 | #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 |
| 9b47267f | 282 | #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0) |
| fe894d56 | 283 | #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 |
| 9b47267f | 284 | #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8) |
| fe894d56 | 285 | #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec |
| 9b47267f RN |
286 | #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec) |
| 287 | ||
| 288 | /* CM2.ALWAYS_ON_CM2 register offsets */ | |
| fe894d56 | 289 | #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 290 | #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000) |
| fe894d56 | 291 | #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 292 | #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020) |
| fe894d56 | 293 | #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 |
| 9b47267f | 294 | #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028) |
| fe894d56 | 295 | #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 |
| 9b47267f | 296 | #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) |
| fe894d56 | 297 | #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 |
| 9b47267f RN |
298 | #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) |
| 299 | ||
| 300 | /* CM2.CORE_CM2 register offsets */ | |
| fe894d56 | 301 | #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 302 | #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000) |
| fe894d56 | 303 | #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 304 | #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008) |
| fe894d56 | 305 | #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 306 | #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020) |
| fe894d56 | 307 | #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 |
| 9b47267f | 308 | #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100) |
| fe894d56 | 309 | #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 |
| 9b47267f | 310 | #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108) |
| fe894d56 | 311 | #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 |
| 9b47267f | 312 | #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120) |
| fe894d56 | 313 | #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 |
| 9b47267f | 314 | #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128) |
| fe894d56 | 315 | #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 |
| 9b47267f | 316 | #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130) |
| fe894d56 | 317 | #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 |
| 9b47267f | 318 | #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200) |
| fe894d56 | 319 | #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 |
| 9b47267f | 320 | #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204) |
| fe894d56 | 321 | #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 |
| 9b47267f | 322 | #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208) |
| fe894d56 | 323 | #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 |
| 9b47267f | 324 | #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220) |
| fe894d56 | 325 | #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 |
| 9b47267f | 326 | #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300) |
| fe894d56 | 327 | #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 |
| 9b47267f | 328 | #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304) |
| fe894d56 | 329 | #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 |
| 9b47267f | 330 | #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308) |
| fe894d56 | 331 | #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 |
| 9b47267f | 332 | #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320) |
| fe894d56 | 333 | #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 |
| 9b47267f | 334 | #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400) |
| fe894d56 | 335 | #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 |
| 9b47267f | 336 | #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420) |
| fe894d56 | 337 | #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 |
| 9b47267f | 338 | #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428) |
| fe894d56 | 339 | #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 |
| 9b47267f | 340 | #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430) |
| fe894d56 | 341 | #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 |
| 9b47267f | 342 | #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438) |
| fe894d56 | 343 | #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 |
| 9b47267f | 344 | #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440) |
| fe894d56 | 345 | #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 |
| 9b47267f | 346 | #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450) |
| fe894d56 | 347 | #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 |
| 9b47267f | 348 | #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458) |
| fe894d56 | 349 | #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 |
| 9b47267f | 350 | #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460) |
| fe894d56 | 351 | #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 |
| 9b47267f | 352 | #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500) |
| fe894d56 | 353 | #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 |
| 9b47267f | 354 | #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504) |
| fe894d56 | 355 | #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 |
| 9b47267f | 356 | #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508) |
| fe894d56 | 357 | #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 |
| 9b47267f | 358 | #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520) |
| fe894d56 | 359 | #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 |
| 9b47267f | 360 | #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528) |
| fe894d56 | 361 | #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 |
| 9b47267f | 362 | #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530) |
| fe894d56 | 363 | #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 |
| 9b47267f | 364 | #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600) |
| fe894d56 | 365 | #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 |
| 9b47267f | 366 | #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608) |
| fe894d56 | 367 | #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 |
| 9b47267f | 368 | #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620) |
| fe894d56 | 369 | #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 |
| 9b47267f | 370 | #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628) |
| fe894d56 | 371 | #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 |
| 9b47267f | 372 | #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630) |
| fe894d56 | 373 | #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 |
| 9b47267f | 374 | #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638) |
| fe894d56 | 375 | #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 |
| 9b47267f | 376 | #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700) |
| fe894d56 | 377 | #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 |
| 9b47267f | 378 | #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720) |
| fe894d56 | 379 | #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 |
| 9b47267f | 380 | #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728) |
| fe894d56 | 381 | #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 |
| 9b47267f RN |
382 | #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740) |
| 383 | ||
| 384 | /* CM2.IVAHD_CM2 register offsets */ | |
| fe894d56 | 385 | #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 386 | #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000) |
| fe894d56 | 387 | #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 388 | #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004) |
| fe894d56 | 389 | #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 390 | #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008) |
| fe894d56 | 391 | #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 392 | #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020) |
| fe894d56 | 393 | #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 |
| 9b47267f RN |
394 | #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028) |
| 395 | ||
| 396 | /* CM2.CAM_CM2 register offsets */ | |
| fe894d56 | 397 | #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 398 | #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000) |
| fe894d56 | 399 | #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 400 | #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004) |
| fe894d56 | 401 | #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 402 | #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008) |
| fe894d56 | 403 | #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 404 | #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020) |
| fe894d56 | 405 | #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 |
| 9b47267f RN |
406 | #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028) |
| 407 | ||
| 408 | /* CM2.DSS_CM2 register offsets */ | |
| fe894d56 | 409 | #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 410 | #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000) |
| fe894d56 | 411 | #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 412 | #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004) |
| fe894d56 | 413 | #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 414 | #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008) |
| fe894d56 | 415 | #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 416 | #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020) |
| fe894d56 | 417 | #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 |
| 9b47267f RN |
418 | #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028) |
| 419 | ||
| 420 | /* CM2.GFX_CM2 register offsets */ | |
| fe894d56 | 421 | #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 422 | #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000) |
| fe894d56 | 423 | #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 424 | #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004) |
| fe894d56 | 425 | #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 426 | #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008) |
| fe894d56 | 427 | #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 |
| 9b47267f RN |
428 | #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020) |
| 429 | ||
| 430 | /* CM2.L3INIT_CM2 register offsets */ | |
| fe894d56 | 431 | #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 432 | #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000) |
| fe894d56 | 433 | #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 |
| 9b47267f | 434 | #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004) |
| fe894d56 | 435 | #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 436 | #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008) |
| fe894d56 | 437 | #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 |
| 9b47267f | 438 | #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028) |
| fe894d56 | 439 | #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 |
| 9b47267f | 440 | #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030) |
| fe894d56 | 441 | #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 |
| 9b47267f | 442 | #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038) |
| fe894d56 | 443 | #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 |
| 9b47267f | 444 | #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040) |
| fe894d56 | 445 | #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 |
| 9b47267f | 446 | #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058) |
| fe894d56 | 447 | #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 |
| 9b47267f | 448 | #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060) |
| fe894d56 | 449 | #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 |
| 9b47267f | 450 | #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068) |
| fe894d56 | 451 | #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 |
| 9b47267f | 452 | #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078) |
| fe894d56 | 453 | #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 |
| 9b47267f | 454 | #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080) |
| fe894d56 | 455 | #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 |
| 9b47267f | 456 | #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088) |
| fe894d56 | 457 | #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 |
| 9b47267f | 458 | #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090) |
| fe894d56 | 459 | #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 |
| 9b47267f | 460 | #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098) |
| fe894d56 | 461 | #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 |
| 9b47267f | 462 | #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8) |
| fe894d56 | 463 | #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 |
| 9b47267f | 464 | #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0) |
| fe894d56 | 465 | #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 |
| 9b47267f | 466 | #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8) |
| fe894d56 | 467 | #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 |
| 9b47267f | 468 | #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0) |
| fe894d56 | 469 | #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 |
| 9b47267f RN |
470 | #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0) |
| 471 | ||
| 472 | /* CM2.L4PER_CM2 register offsets */ | |
| fe894d56 | 473 | #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 474 | #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000) |
| fe894d56 | 475 | #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 |
| 9b47267f | 476 | #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008) |
| fe894d56 | 477 | #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 478 | #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020) |
| fe894d56 | 479 | #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 |
| 9b47267f | 480 | #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028) |
| fe894d56 | 481 | #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 |
| 9b47267f | 482 | #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030) |
| fe894d56 | 483 | #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 |
| 9b47267f | 484 | #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038) |
| fe894d56 | 485 | #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 |
| 9b47267f | 486 | #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040) |
| fe894d56 | 487 | #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 |
| 9b47267f | 488 | #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048) |
| fe894d56 | 489 | #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 |
| 9b47267f | 490 | #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050) |
| fe894d56 | 491 | #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 |
| 9b47267f | 492 | #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058) |
| fe894d56 | 493 | #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 |
| 9b47267f | 494 | #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060) |
| fe894d56 | 495 | #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 |
| 9b47267f | 496 | #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068) |
| fe894d56 | 497 | #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 |
| 9b47267f | 498 | #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070) |
| fe894d56 | 499 | #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 |
| 9b47267f | 500 | #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078) |
| fe894d56 | 501 | #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 |
| 9b47267f | 502 | #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080) |
| fe894d56 | 503 | #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 |
| 9b47267f | 504 | #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088) |
| fe894d56 | 505 | #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 |
| 9b47267f | 506 | #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090) |
| fe894d56 | 507 | #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 |
| 9b47267f | 508 | #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098) |
| fe894d56 | 509 | #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 |
| 9b47267f | 510 | #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0) |
| fe894d56 | 511 | #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 |
| 9b47267f | 512 | #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8) |
| fe894d56 | 513 | #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 |
| 9b47267f | 514 | #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0) |
| fe894d56 | 515 | #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 |
| 9b47267f | 516 | #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8) |
| fe894d56 | 517 | #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 |
| 9b47267f | 518 | #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0) |
| fe894d56 | 519 | #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 |
| 9b47267f | 520 | #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0) |
| fe894d56 | 521 | #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 |
| 9b47267f | 522 | #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8) |
| fe894d56 | 523 | #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 |
| 9b47267f | 524 | #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0) |
| fe894d56 | 525 | #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 |
| 9b47267f | 526 | #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8) |
| fe894d56 | 527 | #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 |
| 9b47267f | 528 | #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0) |
| fe894d56 | 529 | #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 |
| 9b47267f | 530 | #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8) |
| fe894d56 | 531 | #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 |
| 9b47267f | 532 | #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100) |
| fe894d56 | 533 | #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 |
| 9b47267f | 534 | #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108) |
| fe894d56 | 535 | #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 |
| 9b47267f | 536 | #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120) |
| fe894d56 | 537 | #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 |
| 9b47267f | 538 | #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128) |
| fe894d56 | 539 | #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 |
| 9b47267f | 540 | #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130) |
| fe894d56 | 541 | #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 |
| 9b47267f | 542 | #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138) |
| fe894d56 | 543 | #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 |
| 9b47267f | 544 | #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140) |
| fe894d56 | 545 | #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 |
| 9b47267f | 546 | #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148) |
| fe894d56 | 547 | #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 |
| 9b47267f | 548 | #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150) |
| fe894d56 | 549 | #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 |
| 9b47267f | 550 | #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158) |
| fe894d56 | 551 | #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 |
| 9b47267f | 552 | #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160) |
| fe894d56 | 553 | #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 |
| 9b47267f | 554 | #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168) |
| fe894d56 | 555 | #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 |
| 9b47267f | 556 | #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180) |
| fe894d56 | 557 | #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 |
| 9b47267f | 558 | #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184) |
| fe894d56 | 559 | #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 |
| 9b47267f | 560 | #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188) |
| fe894d56 | 561 | #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 |
| 9b47267f | 562 | #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0) |
| fe894d56 | 563 | #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 |
| 9b47267f | 564 | #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8) |
| fe894d56 | 565 | #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 |
| 9b47267f | 566 | #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0) |
| fe894d56 | 567 | #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 |
| 9b47267f | 568 | #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8) |
| fe894d56 | 569 | #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 |
| 9b47267f | 570 | #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0) |
| fe894d56 | 571 | #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 |
| 9b47267f | 572 | #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8) |
| fe894d56 | 573 | #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 |
| 9b47267f RN |
574 | #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8) |
| 575 | ||
| 576 | /* CM2.CEFUSE_CM2 register offsets */ | |
| fe894d56 | 577 | #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 |
| 9b47267f | 578 | #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) |
| fe894d56 | 579 | #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 |
| 9b47267f | 580 | #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) |
| 9b47267f | 581 | #endif |