[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-omap2 / control.c

/*
 * OMAP2/3 System Control Module register access
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/io.h>

#include <plat/common.h>
#include <plat/control.h>
#include <plat/sdrc.h>
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "prm.h"
#include "sdrc.h"

static void __iomem *omap2_ctrl_base;

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
struct omap3_scratchpad {
	u32 boot_config_ptr;
	u32 public_restore_ptr;
	u32 secure_ram_restore_ptr;
	u32 sdrc_module_semaphore;
	u32 prcm_block_offset;
	u32 sdrc_block_offset;
};

struct omap3_scratchpad_prcm_block {
	u32 prm_clksrc_ctrl;
	u32 prm_clksel;
	u32 cm_clksel_core;
	u32 cm_clksel_wkup;
	u32 cm_clken_pll;
	u32 cm_autoidle_pll;
	u32 cm_clksel1_pll;
	u32 cm_clksel2_pll;
	u32 cm_clksel3_pll;
	u32 cm_clken_pll_mpu;
	u32 cm_autoidle_pll_mpu;
	u32 cm_clksel1_pll_mpu;
	u32 cm_clksel2_pll_mpu;
	u32 prcm_block_size;
};

struct omap3_scratchpad_sdrc_block {
	u16 sysconfig;
	u16 cs_cfg;
	u16 sharing;
	u16 err_type;
	u32 dll_a_ctrl;
	u32 dll_b_ctrl;
	u32 power;
	u32 cs_0;
	u32 mcfg_0;
	u16 mr_0;
	u16 emr_1_0;
	u16 emr_2_0;
	u16 emr_3_0;
	u32 actim_ctrla_0;
	u32 actim_ctrlb_0;
	u32 rfr_ctrl_0;
	u32 cs_1;
	u32 mcfg_1;
	u16 mr_1;
	u16 emr_1_1;
	u16 emr_2_1;
	u16 emr_3_1;
	u32 actim_ctrla_1;
	u32 actim_ctrlb_1;
	u32 rfr_ctrl_1;
	u16 dcdl_1_ctrl;
	u16 dcdl_2_ctrl;
	u32 flags;
	u32 block_size;
};

void *omap3_secure_ram_storage;

/*
 * This is used to store ARM registers in SDRAM before attempting
 * an MPU OFF. The save and restore happens from the SRAM sleep code.
 * The address is stored in scratchpad, so that it can be used
 * during the restore path.
 */
u32 omap3_arm_context[128];

struct omap3_control_regs {
	u32 sysconfig;
	u32 devconf0;
	u32 mem_dftrw0;
	u32 mem_dftrw1;
	u32 msuspendmux_0;
	u32 msuspendmux_1;
	u32 msuspendmux_2;
	u32 msuspendmux_3;
	u32 msuspendmux_4;
	u32 msuspendmux_5;
	u32 sec_ctrl;
	u32 devconf1;
	u32 csirxfe;
	u32 iva2_bootaddr;
	u32 iva2_bootmod;
	u32 debobs_0;
	u32 debobs_1;
	u32 debobs_2;
	u32 debobs_3;
	u32 debobs_4;
	u32 debobs_5;
	u32 debobs_6;
	u32 debobs_7;
	u32 debobs_8;
	u32 prog_io0;
	u32 prog_io1;
	u32 dss_dpll_spreading;
	u32 core_dpll_spreading;
	u32 per_dpll_spreading;
	u32 usbhost_dpll_spreading;
	u32 pbias_lite;
	u32 temp_sensor;
	u32 sramldo4;
	u32 sramldo5;
	u32 csi;
};

static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */

#define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))

void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
	/* Static mapping, never released */
	if (omap2_globals->ctrl) {
		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
		WARN_ON(!omap2_ctrl_base);
	}
}

void __iomem *omap_ctrl_base_get(void)
{
	return omap2_ctrl_base;
}

u8 omap_ctrl_readb(u16 offset)
{
	return __raw_readb(OMAP_CTRL_REGADDR(offset));
}

u16 omap_ctrl_readw(u16 offset)
{
	return __raw_readw(OMAP_CTRL_REGADDR(offset));
}

u32 omap_ctrl_readl(u16 offset)
{
	return __raw_readl(OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writeb(u8 val, u16 offset)
{
	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writew(u16 val, u16 offset)
{
	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writel(u32 val, u16 offset)
{
	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
/*
 * Clears the scratchpad contents in case of cold boot-
 * called during bootup
 */
void omap3_clear_scratchpad_contents(void)
{
	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
	u32 *v_addr;
	u32 offset = 0;
	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
	    OMAP3430_GLOBAL_COLD_RST_MASK) {
		for ( ; offset <= max_offset; offset += 0x4)
			__raw_writel(0x0, (v_addr + offset));
		prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
				     OMAP3430_GR_MOD,
				     OMAP3_PRM_RSTST_OFFSET);
	}
}

/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
	void * __iomem scratchpad_address;
	u32 arm_context_addr;
	struct omap3_scratchpad scratchpad_contents;
	struct omap3_scratchpad_prcm_block prcm_block_contents;
	struct omap3_scratchpad_sdrc_block sdrc_block_contents;

	/* Populate the Scratchpad contents */
	scratchpad_contents.boot_config_ptr = 0x0;
	if (omap_rev() != OMAP3430_REV_ES3_0 &&
					omap_rev() != OMAP3430_REV_ES3_1)
		scratchpad_contents.public_restore_ptr =
			virt_to_phys(get_restore_pointer());
	else
		scratchpad_contents.public_restore_ptr =
			virt_to_phys(get_es3_restore_pointer());
	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
		scratchpad_contents.secure_ram_restore_ptr = 0x0;
	else
		scratchpad_contents.secure_ram_restore_ptr =
			(u32) __pa(omap3_secure_ram_storage);
	scratchpad_contents.sdrc_module_semaphore = 0x0;
	scratchpad_contents.prcm_block_offset = 0x2C;
	scratchpad_contents.sdrc_block_offset = 0x64;

	/* Populate the PRCM block contents */
	prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
			OMAP3_PRM_CLKSRC_CTRL_OFFSET);
	prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
			OMAP3_PRM_CLKSEL_OFFSET);
	prcm_block_contents.cm_clksel_core =
			cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
	prcm_block_contents.cm_clksel_wkup =
			cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
	prcm_block_contents.cm_clken_pll =
			cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	prcm_block_contents.cm_autoidle_pll =
			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	prcm_block_contents.cm_clksel1_pll =
			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
	prcm_block_contents.cm_clksel2_pll =
			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
	prcm_block_contents.cm_clksel3_pll =
			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
	prcm_block_contents.cm_clken_pll_mpu =
			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
	prcm_block_contents.cm_autoidle_pll_mpu =
			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	prcm_block_contents.cm_clksel1_pll_mpu =
			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
	prcm_block_contents.cm_clksel2_pll_mpu =
			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
	prcm_block_contents.prcm_block_size = 0x0;

	/* Populate the SDRC block contents */
	sdrc_block_contents.sysconfig =
			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
	sdrc_block_contents.cs_cfg =
			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
	sdrc_block_contents.sharing =
			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
	sdrc_block_contents.err_type =
			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
	sdrc_block_contents.dll_b_ctrl = 0x0;
	/*
	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
	 * be programed to issue automatic self refresh on timeout
	 * of AUTO_CNT = 1 prior to any transition to OFF mode.
	 */
	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
			&& (omap_rev() >= OMAP3430_REV_ES3_0))
		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
				~(SDRC_POWER_AUTOCOUNT_MASK|
				SDRC_POWER_CLKCTRL_MASK)) |
				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
				SDRC_SELF_REFRESH_ON_AUTOCOUNT;
	else
		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);

	sdrc_block_contents.cs_0 = 0x0;
	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
	sdrc_block_contents.emr_1_0 = 0x0;
	sdrc_block_contents.emr_2_0 = 0x0;
	sdrc_block_contents.emr_3_0 = 0x0;
	sdrc_block_contents.actim_ctrla_0 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
	sdrc_block_contents.actim_ctrlb_0 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
	sdrc_block_contents.rfr_ctrl_0 =
			sdrc_read_reg(SDRC_RFR_CTRL_0);
	sdrc_block_contents.cs_1 = 0x0;
	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
	sdrc_block_contents.emr_1_1 = 0x0;
	sdrc_block_contents.emr_2_1 = 0x0;
	sdrc_block_contents.emr_3_1 = 0x0;
	sdrc_block_contents.actim_ctrla_1 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
	sdrc_block_contents.actim_ctrlb_1 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
	sdrc_block_contents.rfr_ctrl_1 =
			sdrc_read_reg(SDRC_RFR_CTRL_1);
	sdrc_block_contents.dcdl_1_ctrl = 0x0;
	sdrc_block_contents.dcdl_2_ctrl = 0x0;
	sdrc_block_contents.flags = 0x0;
	sdrc_block_contents.block_size = 0x0;

	arm_context_addr = virt_to_phys(omap3_arm_context);

	/* Copy all the contents to the scratchpad location */
	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
	memcpy_toio(scratchpad_address, &scratchpad_contents,
		 sizeof(scratchpad_contents));
	/* Scratchpad contents being 32 bits, a divide by 4 done here */
	memcpy_toio(scratchpad_address +
		scratchpad_contents.prcm_block_offset,
		&prcm_block_contents, sizeof(prcm_block_contents));
	memcpy_toio(scratchpad_address +
		scratchpad_contents.sdrc_block_offset,
		&sdrc_block_contents, sizeof(sdrc_block_contents));
	/*
	 * Copies the address of the location in SDRAM where ARM
	 * registers get saved during a MPU OFF transition.
	 */
	memcpy_toio(scratchpad_address +
		scratchpad_contents.sdrc_block_offset +
		sizeof(sdrc_block_contents), &arm_context_addr, 4);
}

void omap3_control_save_context(void)
{
	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	control_context.mem_dftrw0 =
			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
	control_context.mem_dftrw1 =
			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
	control_context.msuspendmux_0 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
	control_context.msuspendmux_1 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
	control_context.msuspendmux_2 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
	control_context.msuspendmux_3 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
	control_context.msuspendmux_4 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
	control_context.msuspendmux_5 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
	control_context.iva2_bootaddr =
			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
	control_context.iva2_bootmod =
			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	control_context.dss_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	control_context.core_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	control_context.per_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
	control_context.usbhost_dpll_spreading =
		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	control_context.pbias_lite =
			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
	control_context.temp_sensor =
			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
	return;
}

void omap3_control_restore_context(void)
{
	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
	omap_ctrl_writel(control_context.mem_dftrw0,
					OMAP343X_CONTROL_MEM_DFTRW0);
	omap_ctrl_writel(control_context.mem_dftrw1,
					OMAP343X_CONTROL_MEM_DFTRW1);
	omap_ctrl_writel(control_context.msuspendmux_0,
					OMAP2_CONTROL_MSUSPENDMUX_0);
	omap_ctrl_writel(control_context.msuspendmux_1,
					OMAP2_CONTROL_MSUSPENDMUX_1);
	omap_ctrl_writel(control_context.msuspendmux_2,
					OMAP2_CONTROL_MSUSPENDMUX_2);
	omap_ctrl_writel(control_context.msuspendmux_3,
					OMAP2_CONTROL_MSUSPENDMUX_3);
	omap_ctrl_writel(control_context.msuspendmux_4,
					OMAP2_CONTROL_MSUSPENDMUX_4);
	omap_ctrl_writel(control_context.msuspendmux_5,
					OMAP2_CONTROL_MSUSPENDMUX_5);
	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
	omap_ctrl_writel(control_context.iva2_bootaddr,
					OMAP343X_CONTROL_IVA2_BOOTADDR);
	omap_ctrl_writel(control_context.iva2_bootmod,
					OMAP343X_CONTROL_IVA2_BOOTMOD);
	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
	omap_ctrl_writel(control_context.dss_dpll_spreading,
					OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	omap_ctrl_writel(control_context.core_dpll_spreading,
					OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	omap_ctrl_writel(control_context.per_dpll_spreading,
					OMAP343X_CONTROL_PER_DPLL_SPREADING);
	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	omap_ctrl_writel(control_context.pbias_lite,
					OMAP343X_CONTROL_PBIAS_LITE);
	omap_ctrl_writel(control_context.temp_sensor,
					OMAP343X_CONTROL_TEMP_SENSOR);
	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
	return;
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
Commit	Line	Data
69d88a00 PW	1	/*
	2	* OMAP2/3 System Control Module register access
	3	*
	4	* Copyright (C) 2007 Texas Instruments, Inc.
	5	* Copyright (C) 2007 Nokia Corporation
	6	*
	7	* Written by Paul Walmsley
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#undef DEBUG
	14
	15	#include <linux/kernel.h>
a58caad1	16	#include <linux/io.h>
69d88a00	17
ce491cf8 TL	18	#include <plat/common.h>
ce491cf8 TL	19	#include <plat/control.h>
80140786 RN	20	#include <plat/sdrc.h>
	21	#include "cm-regbits-34xx.h"
	22	#include "prm-regbits-34xx.h"
	23	#include "cm.h"
	24	#include "prm.h"
	25	#include "sdrc.h"
69d88a00	26
a58caad1	27	static void __iomem *omap2_ctrl_base;
69d88a00	28
c96631e1	29	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786 RN	30	struct omap3_scratchpad {
	31	u32 boot_config_ptr;
	32	u32 public_restore_ptr;
	33	u32 secure_ram_restore_ptr;
	34	u32 sdrc_module_semaphore;
	35	u32 prcm_block_offset;
	36	u32 sdrc_block_offset;
	37	};
	38
	39	struct omap3_scratchpad_prcm_block {
	40	u32 prm_clksrc_ctrl;
	41	u32 prm_clksel;
	42	u32 cm_clksel_core;
	43	u32 cm_clksel_wkup;
	44	u32 cm_clken_pll;
	45	u32 cm_autoidle_pll;
	46	u32 cm_clksel1_pll;
	47	u32 cm_clksel2_pll;
	48	u32 cm_clksel3_pll;
	49	u32 cm_clken_pll_mpu;
	50	u32 cm_autoidle_pll_mpu;
	51	u32 cm_clksel1_pll_mpu;
	52	u32 cm_clksel2_pll_mpu;
	53	u32 prcm_block_size;
	54	};
	55
	56	struct omap3_scratchpad_sdrc_block {
	57	u16 sysconfig;
	58	u16 cs_cfg;
	59	u16 sharing;
	60	u16 err_type;
	61	u32 dll_a_ctrl;
	62	u32 dll_b_ctrl;
	63	u32 power;
	64	u32 cs_0;
	65	u32 mcfg_0;
	66	u16 mr_0;
	67	u16 emr_1_0;
	68	u16 emr_2_0;
	69	u16 emr_3_0;
	70	u32 actim_ctrla_0;
	71	u32 actim_ctrlb_0;
	72	u32 rfr_ctrl_0;
	73	u32 cs_1;
	74	u32 mcfg_1;
	75	u16 mr_1;
	76	u16 emr_1_1;
	77	u16 emr_2_1;
	78	u16 emr_3_1;
	79	u32 actim_ctrla_1;
	80	u32 actim_ctrlb_1;
	81	u32 rfr_ctrl_1;
	82	u16 dcdl_1_ctrl;
	83	u16 dcdl_2_ctrl;
	84	u32 flags;
	85	u32 block_size;
	86	};
	87
27d59a4a TK	88	void *omap3_secure_ram_storage;
27d59a4a TK	89
80140786 RN	90	/*
	91	* This is used to store ARM registers in SDRAM before attempting
	92	* an MPU OFF. The save and restore happens from the SRAM sleep code.
	93	* The address is stored in scratchpad, so that it can be used
	94	* during the restore path.
	95	*/
	96	u32 omap3_arm_context[128];
	97
c96631e1 RN	98	struct omap3_control_regs {
	99	u32 sysconfig;
	100	u32 devconf0;
	101	u32 mem_dftrw0;
	102	u32 mem_dftrw1;
	103	u32 msuspendmux_0;
	104	u32 msuspendmux_1;
	105	u32 msuspendmux_2;
	106	u32 msuspendmux_3;
	107	u32 msuspendmux_4;
	108	u32 msuspendmux_5;
	109	u32 sec_ctrl;
	110	u32 devconf1;
	111	u32 csirxfe;
	112	u32 iva2_bootaddr;
	113	u32 iva2_bootmod;
	114	u32 debobs_0;
	115	u32 debobs_1;
	116	u32 debobs_2;
	117	u32 debobs_3;
	118	u32 debobs_4;
	119	u32 debobs_5;
	120	u32 debobs_6;
	121	u32 debobs_7;
	122	u32 debobs_8;
	123	u32 prog_io0;
	124	u32 prog_io1;
	125	u32 dss_dpll_spreading;
	126	u32 core_dpll_spreading;
	127	u32 per_dpll_spreading;
	128	u32 usbhost_dpll_spreading;
	129	u32 pbias_lite;
	130	u32 temp_sensor;
	131	u32 sramldo4;
	132	u32 sramldo5;
	133	u32 csi;
	134	};
	135
	136	static struct omap3_control_regs control_context;
	137	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
	138
a58caad1	139	#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
69d88a00	140
a58caad1	141	void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
69d88a00	142	{
b7ebb10b SS	143	/* Static mapping, never released */
	144	if (omap2_globals->ctrl) {
	145	omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
	146	WARN_ON(!omap2_ctrl_base);
	147	}
69d88a00 PW	148	}
69d88a00 PW	149
a58caad1	150	void __iomem *omap_ctrl_base_get(void)
69d88a00 PW	151	{
	152	return omap2_ctrl_base;
	153	}
	154
	155	u8 omap_ctrl_readb(u16 offset)
	156	{
	157	return __raw_readb(OMAP_CTRL_REGADDR(offset));
	158	}
	159
	160	u16 omap_ctrl_readw(u16 offset)
	161	{
	162	return __raw_readw(OMAP_CTRL_REGADDR(offset));
	163	}
	164
	165	u32 omap_ctrl_readl(u16 offset)
	166	{
	167	return __raw_readl(OMAP_CTRL_REGADDR(offset));
	168	}
	169
	170	void omap_ctrl_writeb(u8 val, u16 offset)
	171	{
69d88a00 PW	172	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
	173	}
	174
	175	void omap_ctrl_writew(u16 val, u16 offset)
	176	{
69d88a00 PW	177	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
	178	}
	179
	180	void omap_ctrl_writel(u32 val, u16 offset)
	181	{
69d88a00 PW	182	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
	183	}
	184
c96631e1	185	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786 RN	186	/*
	187	* Clears the scratchpad contents in case of cold boot-
	188	* called during bootup
	189	*/
	190	void omap3_clear_scratchpad_contents(void)
	191	{
	192	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
	193	u32 *v_addr;
	194	u32 offset = 0;
	195	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
	196	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
2bc4ef71	197	OMAP3430_GLOBAL_COLD_RST_MASK) {
80140786 RN	198	for ( ; offset <= max_offset; offset += 0x4)
80140786 RN	199	__raw_writel(0x0, (v_addr + offset));
2bc4ef71 PW	200	prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
	201	OMAP3430_GR_MOD,
	202	OMAP3_PRM_RSTST_OFFSET);
80140786 RN	203	}
	204	}
	205
	206	/* Populate the scratchpad structure with restore structure */
	207	void omap3_save_scratchpad_contents(void)
	208	{
	209	void * __iomem scratchpad_address;
	210	u32 arm_context_addr;
	211	struct omap3_scratchpad scratchpad_contents;
	212	struct omap3_scratchpad_prcm_block prcm_block_contents;
	213	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
	214
	215	/* Populate the Scratchpad contents */
	216	scratchpad_contents.boot_config_ptr = 0x0;
0795a75a TK	217	if (omap_rev() != OMAP3430_REV_ES3_0 &&
	218	omap_rev() != OMAP3430_REV_ES3_1)
	219	scratchpad_contents.public_restore_ptr =
	220	virt_to_phys(get_restore_pointer());
	221	else
	222	scratchpad_contents.public_restore_ptr =
	223	virt_to_phys(get_es3_restore_pointer());
27d59a4a TK	224	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
	225	scratchpad_contents.secure_ram_restore_ptr = 0x0;
	226	else
	227	scratchpad_contents.secure_ram_restore_ptr =
	228	(u32) __pa(omap3_secure_ram_storage);
80140786 RN	229	scratchpad_contents.sdrc_module_semaphore = 0x0;
	230	scratchpad_contents.prcm_block_offset = 0x2C;
	231	scratchpad_contents.sdrc_block_offset = 0x64;
	232
	233	/* Populate the PRCM block contents */
	234	prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
	235	OMAP3_PRM_CLKSRC_CTRL_OFFSET);
	236	prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
	237	OMAP3_PRM_CLKSEL_OFFSET);
	238	prcm_block_contents.cm_clksel_core =
	239	cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
	240	prcm_block_contents.cm_clksel_wkup =
	241	cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
	242	prcm_block_contents.cm_clken_pll =
cb0cb2b8	243	cm_read_mod_reg(PLL_MOD, CM_CLKEN);
80140786 RN	244	prcm_block_contents.cm_autoidle_pll =
	245	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	246	prcm_block_contents.cm_clksel1_pll =
	247	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
	248	prcm_block_contents.cm_clksel2_pll =
	249	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
	250	prcm_block_contents.cm_clksel3_pll =
	251	cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
	252	prcm_block_contents.cm_clken_pll_mpu =
	253	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
	254	prcm_block_contents.cm_autoidle_pll_mpu =
	255	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	256	prcm_block_contents.cm_clksel1_pll_mpu =
	257	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
	258	prcm_block_contents.cm_clksel2_pll_mpu =
	259	cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
	260	prcm_block_contents.prcm_block_size = 0x0;
	261
	262	/* Populate the SDRC block contents */
	263	sdrc_block_contents.sysconfig =
	264	(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
	265	sdrc_block_contents.cs_cfg =
	266	(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
	267	sdrc_block_contents.sharing =
	268	(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
	269	sdrc_block_contents.err_type =
	270	(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
	271	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
	272	sdrc_block_contents.dll_b_ctrl = 0x0;
f265dc4c RN	273	/*
	274	* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
	275	* be programed to issue automatic self refresh on timeout
	276	* of AUTO_CNT = 1 prior to any transition to OFF mode.
	277	*/
	278	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
	279	&& (omap_rev() >= OMAP3430_REV_ES3_0))
	280	sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
	281	~(SDRC_POWER_AUTOCOUNT_MASK\|
	282	SDRC_POWER_CLKCTRL_MASK)) \|
	283	(1 << SDRC_POWER_AUTOCOUNT_SHIFT) \|
	284	SDRC_SELF_REFRESH_ON_AUTOCOUNT;
	285	else
	286	sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
	287
80140786 RN	288	sdrc_block_contents.cs_0 = 0x0;
	289	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
	290	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
	291	sdrc_block_contents.emr_1_0 = 0x0;
	292	sdrc_block_contents.emr_2_0 = 0x0;
	293	sdrc_block_contents.emr_3_0 = 0x0;
	294	sdrc_block_contents.actim_ctrla_0 =
	295	sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
	296	sdrc_block_contents.actim_ctrlb_0 =
	297	sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
	298	sdrc_block_contents.rfr_ctrl_0 =
	299	sdrc_read_reg(SDRC_RFR_CTRL_0);
	300	sdrc_block_contents.cs_1 = 0x0;
	301	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
	302	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
	303	sdrc_block_contents.emr_1_1 = 0x0;
	304	sdrc_block_contents.emr_2_1 = 0x0;
	305	sdrc_block_contents.emr_3_1 = 0x0;
	306	sdrc_block_contents.actim_ctrla_1 =
	307	sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
	308	sdrc_block_contents.actim_ctrlb_1 =
	309	sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
	310	sdrc_block_contents.rfr_ctrl_1 =
	311	sdrc_read_reg(SDRC_RFR_CTRL_1);
	312	sdrc_block_contents.dcdl_1_ctrl = 0x0;
	313	sdrc_block_contents.dcdl_2_ctrl = 0x0;
	314	sdrc_block_contents.flags = 0x0;
	315	sdrc_block_contents.block_size = 0x0;
	316
	317	arm_context_addr = virt_to_phys(omap3_arm_context);
	318
	319	/* Copy all the contents to the scratchpad location */
	320	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
	321	memcpy_toio(scratchpad_address, &scratchpad_contents,
	322	sizeof(scratchpad_contents));
	323	/* Scratchpad contents being 32 bits, a divide by 4 done here */
	324	memcpy_toio(scratchpad_address +
	325	scratchpad_contents.prcm_block_offset,
	326	&prcm_block_contents, sizeof(prcm_block_contents));
	327	memcpy_toio(scratchpad_address +
	328	scratchpad_contents.sdrc_block_offset,
	329	&sdrc_block_contents, sizeof(sdrc_block_contents));
	330	/*
	331	* Copies the address of the location in SDRAM where ARM
	332	* registers get saved during a MPU OFF transition.
	333	*/
	334	memcpy_toio(scratchpad_address +
	335	scratchpad_contents.sdrc_block_offset +
	336	sizeof(sdrc_block_contents), &arm_context_addr, 4);
	337	}
	338
c96631e1 RN	339	void omap3_control_save_context(void)
	340	{
	341	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
	342	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	343	control_context.mem_dftrw0 =
	344	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
	345	control_context.mem_dftrw1 =
	346	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
	347	control_context.msuspendmux_0 =
	348	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
	349	control_context.msuspendmux_1 =
	350	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
	351	control_context.msuspendmux_2 =
	352	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
	353	control_context.msuspendmux_3 =
	354	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
	355	control_context.msuspendmux_4 =
	356	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
	357	control_context.msuspendmux_5 =
	358	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
	359	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
	360	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
	361	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
	362	control_context.iva2_bootaddr =
	363	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
	364	control_context.iva2_bootmod =
	365	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
	366	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
	367	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
	368	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
	369	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
	370	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
	371	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
	372	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
	373	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
	374	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
	375	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
	376	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	377	control_context.dss_dpll_spreading =
	378	omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	379	control_context.core_dpll_spreading =
	380	omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	381	control_context.per_dpll_spreading =
	382	omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
	383	control_context.usbhost_dpll_spreading =
	384	omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	385	control_context.pbias_lite =
	386	omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
	387	control_context.temp_sensor =
	388	omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
	389	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
	390	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
	391	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
	392	return;
	393	}
	394
	395	void omap3_control_restore_context(void)
	396	{
	397	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
	398	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
	399	omap_ctrl_writel(control_context.mem_dftrw0,
	400	OMAP343X_CONTROL_MEM_DFTRW0);
	401	omap_ctrl_writel(control_context.mem_dftrw1,
	402	OMAP343X_CONTROL_MEM_DFTRW1);
403	omap_ctrl_writel(control_context.msuspendmux_0,
404	OMAP2_CONTROL_MSUSPENDMUX_0);
405	omap_ctrl_writel(control_context.msuspendmux_1,
406	OMAP2_CONTROL_MSUSPENDMUX_1);
407	omap_ctrl_writel(control_context.msuspendmux_2,
408	OMAP2_CONTROL_MSUSPENDMUX_2);
409	omap_ctrl_writel(control_context.msuspendmux_3,
410	OMAP2_CONTROL_MSUSPENDMUX_3);
411	omap_ctrl_writel(control_context.msuspendmux_4,
412	OMAP2_CONTROL_MSUSPENDMUX_4);
413	omap_ctrl_writel(control_context.msuspendmux_5,
414	OMAP2_CONTROL_MSUSPENDMUX_5);
415	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
416	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
417	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
418	omap_ctrl_writel(control_context.iva2_bootaddr,
419	OMAP343X_CONTROL_IVA2_BOOTADDR);
420	omap_ctrl_writel(control_context.iva2_bootmod,
421	OMAP343X_CONTROL_IVA2_BOOTMOD);
422	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
423	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
424	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
425	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
426	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
427	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
428	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
429	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
430	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
431	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
432	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
433	omap_ctrl_writel(control_context.dss_dpll_spreading,
434	OMAP343X_CONTROL_DSS_DPLL_SPREADING);
435	omap_ctrl_writel(control_context.core_dpll_spreading,
436	OMAP343X_CONTROL_CORE_DPLL_SPREADING);
437	omap_ctrl_writel(control_context.per_dpll_spreading,
438	OMAP343X_CONTROL_PER_DPLL_SPREADING);
439	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
440	OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
441	omap_ctrl_writel(control_context.pbias_lite,
442	OMAP343X_CONTROL_PBIAS_LITE);
443	omap_ctrl_writel(control_context.temp_sensor,
444	OMAP343X_CONTROL_TEMP_SENSOR);
445	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
446	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
447	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
448	return;
449	}
450	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */