[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / control.c

/*
 * OMAP2/3 System Control Module register access
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/io.h>

#include <plat/common.h>
#include <plat/sdrc.h>

#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"

static void __iomem *omap2_ctrl_base;
static void __iomem *omap4_ctrl_pad_base;

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
struct omap3_scratchpad {
	u32 boot_config_ptr;
	u32 public_restore_ptr;
	u32 secure_ram_restore_ptr;
	u32 sdrc_module_semaphore;
	u32 prcm_block_offset;
	u32 sdrc_block_offset;
};

struct omap3_scratchpad_prcm_block {
	u32 prm_clksrc_ctrl;
	u32 prm_clksel;
	u32 cm_clksel_core;
	u32 cm_clksel_wkup;
	u32 cm_clken_pll;
	u32 cm_autoidle_pll;
	u32 cm_clksel1_pll;
	u32 cm_clksel2_pll;
	u32 cm_clksel3_pll;
	u32 cm_clken_pll_mpu;
	u32 cm_autoidle_pll_mpu;
	u32 cm_clksel1_pll_mpu;
	u32 cm_clksel2_pll_mpu;
	u32 prcm_block_size;
};

struct omap3_scratchpad_sdrc_block {
	u16 sysconfig;
	u16 cs_cfg;
	u16 sharing;
	u16 err_type;
	u32 dll_a_ctrl;
	u32 dll_b_ctrl;
	u32 power;
	u32 cs_0;
	u32 mcfg_0;
	u16 mr_0;
	u16 emr_1_0;
	u16 emr_2_0;
	u16 emr_3_0;
	u32 actim_ctrla_0;
	u32 actim_ctrlb_0;
	u32 rfr_ctrl_0;
	u32 cs_1;
	u32 mcfg_1;
	u16 mr_1;
	u16 emr_1_1;
	u16 emr_2_1;
	u16 emr_3_1;
	u32 actim_ctrla_1;
	u32 actim_ctrlb_1;
	u32 rfr_ctrl_1;
	u16 dcdl_1_ctrl;
	u16 dcdl_2_ctrl;
	u32 flags;
	u32 block_size;
};

void *omap3_secure_ram_storage;

/*
 * This is used to store ARM registers in SDRAM before attempting
 * an MPU OFF. The save and restore happens from the SRAM sleep code.
 * The address is stored in scratchpad, so that it can be used
 * during the restore path.
 */
u32 omap3_arm_context[128];

struct omap3_control_regs {
	u32 sysconfig;
	u32 devconf0;
	u32 mem_dftrw0;
	u32 mem_dftrw1;
	u32 msuspendmux_0;
	u32 msuspendmux_1;
	u32 msuspendmux_2;
	u32 msuspendmux_3;
	u32 msuspendmux_4;
	u32 msuspendmux_5;
	u32 sec_ctrl;
	u32 devconf1;
	u32 csirxfe;
	u32 iva2_bootaddr;
	u32 iva2_bootmod;
	u32 debobs_0;
	u32 debobs_1;
	u32 debobs_2;
	u32 debobs_3;
	u32 debobs_4;
	u32 debobs_5;
	u32 debobs_6;
	u32 debobs_7;
	u32 debobs_8;
	u32 prog_io0;
	u32 prog_io1;
	u32 dss_dpll_spreading;
	u32 core_dpll_spreading;
	u32 per_dpll_spreading;
	u32 usbhost_dpll_spreading;
	u32 pbias_lite;
	u32 temp_sensor;
	u32 sramldo4;
	u32 sramldo5;
	u32 csi;
	u32 padconf_sys_nirq;
};

static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */

#define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))
#define OMAP4_CTRL_PAD_REGADDR(reg)	(omap4_ctrl_pad_base + (reg))

void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
{
	/* Static mapping, never released */
	if (omap2_globals->ctrl) {
		omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
		WARN_ON(!omap2_ctrl_base);
	}

	/* Static mapping, never released */
	if (omap2_globals->ctrl_pad) {
		omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
		WARN_ON(!omap4_ctrl_pad_base);
	}
}

void __iomem *omap_ctrl_base_get(void)
{
	return omap2_ctrl_base;
}

u8 omap_ctrl_readb(u16 offset)
{
	return __raw_readb(OMAP_CTRL_REGADDR(offset));
}

u16 omap_ctrl_readw(u16 offset)
{
	return __raw_readw(OMAP_CTRL_REGADDR(offset));
}

u32 omap_ctrl_readl(u16 offset)
{
	return __raw_readl(OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writeb(u8 val, u16 offset)
{
	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writew(u16 val, u16 offset)
{
	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
}

void omap_ctrl_writel(u32 val, u16 offset)
{
	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
}

/*
 * On OMAP4 control pad are not addressable from control
 * core base. So the common omap_ctrl_read/write APIs breaks
 * Hence export separate APIs to manage the omap4 pad control
 * registers. This APIs will work only for OMAP4
 */

u32 omap4_ctrl_pad_readl(u16 offset)
{
	return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
}

void omap4_ctrl_pad_writel(u32 val, u16 offset)
{
	__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
}

#ifdef CONFIG_ARCH_OMAP3

/**
 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 * @bootmode: 8-bit value to pass to some boot code
 *
 * Set the bootmode in the scratchpad RAM.  This is used after the
 * system restarts.  Not sure what actually uses this - it may be the
 * bootloader, rather than the boot ROM - contrary to the preserved
 * comment below.  No return value.
 */
void omap3_ctrl_write_boot_mode(u8 bootmode)
{
	u32 l;

	l = ('B' << 24) | ('M' << 16) | bootmode;

	/*
	 * Reserve the first word in scratchpad for communicating
	 * with the boot ROM. A pointer to a data structure
	 * describing the boot process can be stored there,
	 * cf. OMAP34xx TRM, Initialization / Software Booting
	 * Configuration.
	 *
	 * XXX This should use some omap_ctrl_writel()-type function
	 */
	__raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
}

#endif

#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
/*
 * Clears the scratchpad contents in case of cold boot-
 * called during bootup
 */
void omap3_clear_scratchpad_contents(void)
{
	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
	void __iomem *v_addr;
	u32 offset = 0;
	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
	if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
	    OMAP3430_GLOBAL_COLD_RST_MASK) {
		for ( ; offset <= max_offset; offset += 0x4)
			__raw_writel(0x0, (v_addr + offset));
		omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
					   OMAP3430_GR_MOD,
					   OMAP3_PRM_RSTST_OFFSET);
	}
}

/* Populate the scratchpad structure with restore structure */
void omap3_save_scratchpad_contents(void)
{
	void  __iomem *scratchpad_address;
	u32 arm_context_addr;
	struct omap3_scratchpad scratchpad_contents;
	struct omap3_scratchpad_prcm_block prcm_block_contents;
	struct omap3_scratchpad_sdrc_block sdrc_block_contents;

	/*
	 * Populate the Scratchpad contents
	 *
	 * The "get_*restore_pointer" functions are used to provide a
	 * physical restore address where the ROM code jumps while waking
	 * up from MPU OFF/OSWR state.
	 * The restore pointer is stored into the scratchpad.
	 */
	scratchpad_contents.boot_config_ptr = 0x0;
	if (cpu_is_omap3630())
		scratchpad_contents.public_restore_ptr =
			virt_to_phys(get_omap3630_restore_pointer());
	else if (omap_rev() != OMAP3430_REV_ES3_0 &&
					omap_rev() != OMAP3430_REV_ES3_1)
		scratchpad_contents.public_restore_ptr =
			virt_to_phys(get_restore_pointer());
	else
		scratchpad_contents.public_restore_ptr =
			virt_to_phys(get_es3_restore_pointer());
	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
		scratchpad_contents.secure_ram_restore_ptr = 0x0;
	else
		scratchpad_contents.secure_ram_restore_ptr =
			(u32) __pa(omap3_secure_ram_storage);
	scratchpad_contents.sdrc_module_semaphore = 0x0;
	scratchpad_contents.prcm_block_offset = 0x2C;
	scratchpad_contents.sdrc_block_offset = 0x64;

	/* Populate the PRCM block contents */
	prcm_block_contents.prm_clksrc_ctrl =
		omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
				       OMAP3_PRM_CLKSRC_CTRL_OFFSET);
	prcm_block_contents.prm_clksel =
		omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
				       OMAP3_PRM_CLKSEL_OFFSET);
	prcm_block_contents.cm_clksel_core =
			omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
	prcm_block_contents.cm_clksel_wkup =
			omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
	prcm_block_contents.cm_clken_pll =
			omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
	prcm_block_contents.cm_autoidle_pll =
			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	prcm_block_contents.cm_clksel1_pll =
			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
	prcm_block_contents.cm_clksel2_pll =
			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
	prcm_block_contents.cm_clksel3_pll =
			omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
	prcm_block_contents.cm_clken_pll_mpu =
			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
	prcm_block_contents.cm_autoidle_pll_mpu =
			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
	prcm_block_contents.cm_clksel1_pll_mpu =
			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
	prcm_block_contents.cm_clksel2_pll_mpu =
			omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
	prcm_block_contents.prcm_block_size = 0x0;

	/* Populate the SDRC block contents */
	sdrc_block_contents.sysconfig =
			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
	sdrc_block_contents.cs_cfg =
			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
	sdrc_block_contents.sharing =
			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
	sdrc_block_contents.err_type =
			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
	sdrc_block_contents.dll_b_ctrl = 0x0;
	/*
	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
	 * be programed to issue automatic self refresh on timeout
	 * of AUTO_CNT = 1 prior to any transition to OFF mode.
	 */
	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
			&& (omap_rev() >= OMAP3430_REV_ES3_0))
		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
				~(SDRC_POWER_AUTOCOUNT_MASK|
				SDRC_POWER_CLKCTRL_MASK)) |
				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
				SDRC_SELF_REFRESH_ON_AUTOCOUNT;
	else
		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);

	sdrc_block_contents.cs_0 = 0x0;
	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
	sdrc_block_contents.emr_1_0 = 0x0;
	sdrc_block_contents.emr_2_0 = 0x0;
	sdrc_block_contents.emr_3_0 = 0x0;
	sdrc_block_contents.actim_ctrla_0 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
	sdrc_block_contents.actim_ctrlb_0 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
	sdrc_block_contents.rfr_ctrl_0 =
			sdrc_read_reg(SDRC_RFR_CTRL_0);
	sdrc_block_contents.cs_1 = 0x0;
	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
	sdrc_block_contents.emr_1_1 = 0x0;
	sdrc_block_contents.emr_2_1 = 0x0;
	sdrc_block_contents.emr_3_1 = 0x0;
	sdrc_block_contents.actim_ctrla_1 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
	sdrc_block_contents.actim_ctrlb_1 =
			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
	sdrc_block_contents.rfr_ctrl_1 =
			sdrc_read_reg(SDRC_RFR_CTRL_1);
	sdrc_block_contents.dcdl_1_ctrl = 0x0;
	sdrc_block_contents.dcdl_2_ctrl = 0x0;
	sdrc_block_contents.flags = 0x0;
	sdrc_block_contents.block_size = 0x0;

	arm_context_addr = virt_to_phys(omap3_arm_context);

	/* Copy all the contents to the scratchpad location */
	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
	memcpy_toio(scratchpad_address, &scratchpad_contents,
		 sizeof(scratchpad_contents));
	/* Scratchpad contents being 32 bits, a divide by 4 done here */
	memcpy_toio(scratchpad_address +
		scratchpad_contents.prcm_block_offset,
		&prcm_block_contents, sizeof(prcm_block_contents));
	memcpy_toio(scratchpad_address +
		scratchpad_contents.sdrc_block_offset,
		&sdrc_block_contents, sizeof(sdrc_block_contents));
	/*
	 * Copies the address of the location in SDRAM where ARM
	 * registers get saved during a MPU OFF transition.
	 */
	memcpy_toio(scratchpad_address +
		scratchpad_contents.sdrc_block_offset +
		sizeof(sdrc_block_contents), &arm_context_addr, 4);
}

void omap3_control_save_context(void)
{
	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	control_context.mem_dftrw0 =
			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
	control_context.mem_dftrw1 =
			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
	control_context.msuspendmux_0 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
	control_context.msuspendmux_1 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
	control_context.msuspendmux_2 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
	control_context.msuspendmux_3 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
	control_context.msuspendmux_4 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
	control_context.msuspendmux_5 =
			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
	control_context.iva2_bootaddr =
			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
	control_context.iva2_bootmod =
			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	control_context.dss_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	control_context.core_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	control_context.per_dpll_spreading =
			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
	control_context.usbhost_dpll_spreading =
		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	control_context.pbias_lite =
			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
	control_context.temp_sensor =
			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
	control_context.padconf_sys_nirq =
		omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
	return;
}

void omap3_control_restore_context(void)
{
	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
	omap_ctrl_writel(control_context.mem_dftrw0,
					OMAP343X_CONTROL_MEM_DFTRW0);
	omap_ctrl_writel(control_context.mem_dftrw1,
					OMAP343X_CONTROL_MEM_DFTRW1);
	omap_ctrl_writel(control_context.msuspendmux_0,
					OMAP2_CONTROL_MSUSPENDMUX_0);
	omap_ctrl_writel(control_context.msuspendmux_1,
					OMAP2_CONTROL_MSUSPENDMUX_1);
	omap_ctrl_writel(control_context.msuspendmux_2,
					OMAP2_CONTROL_MSUSPENDMUX_2);
	omap_ctrl_writel(control_context.msuspendmux_3,
					OMAP2_CONTROL_MSUSPENDMUX_3);
	omap_ctrl_writel(control_context.msuspendmux_4,
					OMAP2_CONTROL_MSUSPENDMUX_4);
	omap_ctrl_writel(control_context.msuspendmux_5,
					OMAP2_CONTROL_MSUSPENDMUX_5);
	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
	omap_ctrl_writel(control_context.iva2_bootaddr,
					OMAP343X_CONTROL_IVA2_BOOTADDR);
	omap_ctrl_writel(control_context.iva2_bootmod,
					OMAP343X_CONTROL_IVA2_BOOTMOD);
	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
	omap_ctrl_writel(control_context.dss_dpll_spreading,
					OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	omap_ctrl_writel(control_context.core_dpll_spreading,
					OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	omap_ctrl_writel(control_context.per_dpll_spreading,
					OMAP343X_CONTROL_PER_DPLL_SPREADING);
	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	omap_ctrl_writel(control_context.pbias_lite,
					OMAP343X_CONTROL_PBIAS_LITE);
	omap_ctrl_writel(control_context.temp_sensor,
					OMAP343X_CONTROL_TEMP_SENSOR);
	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
	omap_ctrl_writel(control_context.padconf_sys_nirq,
			 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
	return;
}

void omap3630_ctrl_disable_rta(void)
{
	if (!cpu_is_omap3630())
		return;
	omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
}

#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
Commit	Line	Data
69d88a00 PW	1	/*
	2	* OMAP2/3 System Control Module register access
	3	*
	4	* Copyright (C) 2007 Texas Instruments, Inc.
	5	* Copyright (C) 2007 Nokia Corporation
	6	*
	7	* Written by Paul Walmsley
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13	#undef DEBUG
	14
	15	#include <linux/kernel.h>
a58caad1	16	#include <linux/io.h>
69d88a00	17
ce491cf8	18	#include <plat/common.h>
80140786	19	#include <plat/sdrc.h>
4814ced5	20
80140786 RN	21	#include "cm-regbits-34xx.h"
80140786 RN	22	#include "prm-regbits-34xx.h"
59fb659b PW	23	#include "prm2xxx_3xxx.h"
59fb659b PW	24	#include "cm2xxx_3xxx.h"
80140786	25	#include "sdrc.h"
38815733	26	#include "pm.h"
4814ced5	27	#include "control.h"
69d88a00	28
a58caad1	29	static void __iomem *omap2_ctrl_base;
0c349246	30	static void __iomem *omap4_ctrl_pad_base;
69d88a00	31
c96631e1	32	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786 RN	33	struct omap3_scratchpad {
	34	u32 boot_config_ptr;
	35	u32 public_restore_ptr;
	36	u32 secure_ram_restore_ptr;
	37	u32 sdrc_module_semaphore;
	38	u32 prcm_block_offset;
	39	u32 sdrc_block_offset;
	40	};
	41
	42	struct omap3_scratchpad_prcm_block {
	43	u32 prm_clksrc_ctrl;
	44	u32 prm_clksel;
	45	u32 cm_clksel_core;
	46	u32 cm_clksel_wkup;
	47	u32 cm_clken_pll;
	48	u32 cm_autoidle_pll;
	49	u32 cm_clksel1_pll;
	50	u32 cm_clksel2_pll;
	51	u32 cm_clksel3_pll;
	52	u32 cm_clken_pll_mpu;
	53	u32 cm_autoidle_pll_mpu;
	54	u32 cm_clksel1_pll_mpu;
	55	u32 cm_clksel2_pll_mpu;
	56	u32 prcm_block_size;
	57	};
	58
	59	struct omap3_scratchpad_sdrc_block {
	60	u16 sysconfig;
	61	u16 cs_cfg;
	62	u16 sharing;
	63	u16 err_type;
	64	u32 dll_a_ctrl;
	65	u32 dll_b_ctrl;
	66	u32 power;
	67	u32 cs_0;
	68	u32 mcfg_0;
	69	u16 mr_0;
	70	u16 emr_1_0;
	71	u16 emr_2_0;
	72	u16 emr_3_0;
	73	u32 actim_ctrla_0;
	74	u32 actim_ctrlb_0;
	75	u32 rfr_ctrl_0;
	76	u32 cs_1;
	77	u32 mcfg_1;
	78	u16 mr_1;
	79	u16 emr_1_1;
	80	u16 emr_2_1;
	81	u16 emr_3_1;
	82	u32 actim_ctrla_1;
	83	u32 actim_ctrlb_1;
	84	u32 rfr_ctrl_1;
	85	u16 dcdl_1_ctrl;
	86	u16 dcdl_2_ctrl;
	87	u32 flags;
	88	u32 block_size;
	89	};
	90
27d59a4a TK	91	void *omap3_secure_ram_storage;
27d59a4a TK	92
80140786 RN	93	/*
	94	* This is used to store ARM registers in SDRAM before attempting
	95	* an MPU OFF. The save and restore happens from the SRAM sleep code.
	96	* The address is stored in scratchpad, so that it can be used
	97	* during the restore path.
	98	*/
	99	u32 omap3_arm_context[128];
	100
c96631e1 RN	101	struct omap3_control_regs {
	102	u32 sysconfig;
	103	u32 devconf0;
	104	u32 mem_dftrw0;
	105	u32 mem_dftrw1;
	106	u32 msuspendmux_0;
	107	u32 msuspendmux_1;
	108	u32 msuspendmux_2;
	109	u32 msuspendmux_3;
	110	u32 msuspendmux_4;
	111	u32 msuspendmux_5;
	112	u32 sec_ctrl;
	113	u32 devconf1;
	114	u32 csirxfe;
	115	u32 iva2_bootaddr;
	116	u32 iva2_bootmod;
	117	u32 debobs_0;
	118	u32 debobs_1;
	119	u32 debobs_2;
	120	u32 debobs_3;
	121	u32 debobs_4;
	122	u32 debobs_5;
	123	u32 debobs_6;
	124	u32 debobs_7;
	125	u32 debobs_8;
	126	u32 prog_io0;
	127	u32 prog_io1;
	128	u32 dss_dpll_spreading;
	129	u32 core_dpll_spreading;
	130	u32 per_dpll_spreading;
	131	u32 usbhost_dpll_spreading;
	132	u32 pbias_lite;
	133	u32 temp_sensor;
	134	u32 sramldo4;
	135	u32 sramldo5;
	136	u32 csi;
f5f9d132	137	u32 padconf_sys_nirq;
c96631e1 RN	138	};
	139
	140	static struct omap3_control_regs control_context;
	141	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
	142
a58caad1	143	#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
70ba71a2	144	#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
69d88a00	145
a58caad1	146	void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
69d88a00	147	{
b7ebb10b SS	148	/* Static mapping, never released */
	149	if (omap2_globals->ctrl) {
	150	omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
	151	WARN_ON(!omap2_ctrl_base);
	152	}
0c349246 SS	153
	154	/* Static mapping, never released */
	155	if (omap2_globals->ctrl_pad) {
	156	omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
	157	WARN_ON(!omap4_ctrl_pad_base);
	158	}
69d88a00 PW	159	}
69d88a00 PW	160
a58caad1	161	void __iomem *omap_ctrl_base_get(void)
69d88a00 PW	162	{
	163	return omap2_ctrl_base;
	164	}
	165
	166	u8 omap_ctrl_readb(u16 offset)
	167	{
	168	return __raw_readb(OMAP_CTRL_REGADDR(offset));
	169	}
	170
	171	u16 omap_ctrl_readw(u16 offset)
	172	{
	173	return __raw_readw(OMAP_CTRL_REGADDR(offset));
	174	}
	175
	176	u32 omap_ctrl_readl(u16 offset)
	177	{
	178	return __raw_readl(OMAP_CTRL_REGADDR(offset));
	179	}
	180
	181	void omap_ctrl_writeb(u8 val, u16 offset)
	182	{
69d88a00 PW	183	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
	184	}
	185
	186	void omap_ctrl_writew(u16 val, u16 offset)
	187	{
69d88a00 PW	188	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
	189	}
	190
	191	void omap_ctrl_writel(u32 val, u16 offset)
	192	{
69d88a00 PW	193	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
	194	}
	195
70ba71a2 SS	196	/*
	197	* On OMAP4 control pad are not addressable from control
	198	* core base. So the common omap_ctrl_read/write APIs breaks
	199	* Hence export separate APIs to manage the omap4 pad control
	200	* registers. This APIs will work only for OMAP4
	201	*/
	202
	203	u32 omap4_ctrl_pad_readl(u16 offset)
	204	{
	205	return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
	206	}
	207
	208	void omap4_ctrl_pad_writel(u32 val, u16 offset)
	209	{
	210	__raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
	211	}
	212
166353bd PW	213	#ifdef CONFIG_ARCH_OMAP3
	214
	215	/**
	216	* omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
	217	* @bootmode: 8-bit value to pass to some boot code
	218	*
	219	* Set the bootmode in the scratchpad RAM. This is used after the
	220	* system restarts. Not sure what actually uses this - it may be the
	221	* bootloader, rather than the boot ROM - contrary to the preserved
	222	* comment below. No return value.
	223	*/
	224	void omap3_ctrl_write_boot_mode(u8 bootmode)
	225	{
	226	u32 l;
	227
	228	l = ('B' << 24) \| ('M' << 16) \| bootmode;
	229
	230	/*
	231	* Reserve the first word in scratchpad for communicating
	232	* with the boot ROM. A pointer to a data structure
	233	* describing the boot process can be stored there,
	234	* cf. OMAP34xx TRM, Initialization / Software Booting
	235	* Configuration.
	236	*
	237	* XXX This should use some omap_ctrl_writel()-type function
	238	*/
	239	__raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
	240	}
	241
	242	#endif
	243
c96631e1	244	#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
80140786 RN	245	/*
	246	* Clears the scratchpad contents in case of cold boot-
	247	* called during bootup
	248	*/
	249	void omap3_clear_scratchpad_contents(void)
	250	{
	251	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
4d63bc1d	252	void __iomem *v_addr;
80140786 RN	253	u32 offset = 0;
80140786 RN	254	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
c4d7e58f	255	if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
2bc4ef71	256	OMAP3430_GLOBAL_COLD_RST_MASK) {
80140786 RN	257	for ( ; offset <= max_offset; offset += 0x4)
80140786 RN	258	__raw_writel(0x0, (v_addr + offset));
c4d7e58f PW	259	omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
	260	OMAP3430_GR_MOD,
	261	OMAP3_PRM_RSTST_OFFSET);
80140786 RN	262	}
	263	}
	264
	265	/* Populate the scratchpad structure with restore structure */
	266	void omap3_save_scratchpad_contents(void)
	267	{
4d63bc1d	268	void __iomem *scratchpad_address;
80140786 RN	269	u32 arm_context_addr;
	270	struct omap3_scratchpad scratchpad_contents;
	271	struct omap3_scratchpad_prcm_block prcm_block_contents;
	272	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
	273
f7dfe3d8 JP	274	/*
	275	* Populate the Scratchpad contents
	276	*
	277	* The "get_*restore_pointer" functions are used to provide a
	278	* physical restore address where the ROM code jumps while waking
	279	* up from MPU OFF/OSWR state.
	280	* The restore pointer is stored into the scratchpad.
	281	*/
80140786	282	scratchpad_contents.boot_config_ptr = 0x0;
458e999e NM	283	if (cpu_is_omap3630())
	284	scratchpad_contents.public_restore_ptr =
	285	virt_to_phys(get_omap3630_restore_pointer());
	286	else if (omap_rev() != OMAP3430_REV_ES3_0 &&
0795a75a TK	287	omap_rev() != OMAP3430_REV_ES3_1)
	288	scratchpad_contents.public_restore_ptr =
	289	virt_to_phys(get_restore_pointer());
	290	else
	291	scratchpad_contents.public_restore_ptr =
	292	virt_to_phys(get_es3_restore_pointer());
27d59a4a TK	293	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
	294	scratchpad_contents.secure_ram_restore_ptr = 0x0;
	295	else
	296	scratchpad_contents.secure_ram_restore_ptr =
	297	(u32) __pa(omap3_secure_ram_storage);
80140786 RN	298	scratchpad_contents.sdrc_module_semaphore = 0x0;
	299	scratchpad_contents.prcm_block_offset = 0x2C;
	300	scratchpad_contents.sdrc_block_offset = 0x64;
	301
	302	/* Populate the PRCM block contents */
c4d7e58f PW	303	prcm_block_contents.prm_clksrc_ctrl =
	304	omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
	305	OMAP3_PRM_CLKSRC_CTRL_OFFSET);
	306	prcm_block_contents.prm_clksel =
	307	omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
	308	OMAP3_PRM_CLKSEL_OFFSET);
80140786	309	prcm_block_contents.cm_clksel_core =
c4d7e58f	310	omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
80140786	311	prcm_block_contents.cm_clksel_wkup =
c4d7e58f	312	omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
80140786	313	prcm_block_contents.cm_clken_pll =
c4d7e58f	314	omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
80140786	315	prcm_block_contents.cm_autoidle_pll =
c4d7e58f	316	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
80140786	317	prcm_block_contents.cm_clksel1_pll =
c4d7e58f	318	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
80140786	319	prcm_block_contents.cm_clksel2_pll =
c4d7e58f	320	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
80140786	321	prcm_block_contents.cm_clksel3_pll =
c4d7e58f	322	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
80140786	323	prcm_block_contents.cm_clken_pll_mpu =
c4d7e58f	324	omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
80140786	325	prcm_block_contents.cm_autoidle_pll_mpu =
c4d7e58f	326	omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
80140786	327	prcm_block_contents.cm_clksel1_pll_mpu =
c4d7e58f	328	omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
80140786	329	prcm_block_contents.cm_clksel2_pll_mpu =
c4d7e58f	330	omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
80140786 RN	331	prcm_block_contents.prcm_block_size = 0x0;
	332
	333	/* Populate the SDRC block contents */
	334	sdrc_block_contents.sysconfig =
	335	(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
	336	sdrc_block_contents.cs_cfg =
	337	(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
	338	sdrc_block_contents.sharing =
	339	(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
	340	sdrc_block_contents.err_type =
	341	(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
	342	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
	343	sdrc_block_contents.dll_b_ctrl = 0x0;
f265dc4c RN	344	/*
	345	* Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
	346	* be programed to issue automatic self refresh on timeout
	347	* of AUTO_CNT = 1 prior to any transition to OFF mode.
	348	*/
	349	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
	350	&& (omap_rev() >= OMAP3430_REV_ES3_0))
	351	sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
	352	~(SDRC_POWER_AUTOCOUNT_MASK\|
	353	SDRC_POWER_CLKCTRL_MASK)) \|
	354	(1 << SDRC_POWER_AUTOCOUNT_SHIFT) \|
	355	SDRC_SELF_REFRESH_ON_AUTOCOUNT;
	356	else
	357	sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
	358
80140786 RN	359	sdrc_block_contents.cs_0 = 0x0;
	360	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
	361	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
	362	sdrc_block_contents.emr_1_0 = 0x0;
	363	sdrc_block_contents.emr_2_0 = 0x0;
	364	sdrc_block_contents.emr_3_0 = 0x0;
	365	sdrc_block_contents.actim_ctrla_0 =
	366	sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
	367	sdrc_block_contents.actim_ctrlb_0 =
	368	sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
	369	sdrc_block_contents.rfr_ctrl_0 =
	370	sdrc_read_reg(SDRC_RFR_CTRL_0);
	371	sdrc_block_contents.cs_1 = 0x0;
	372	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
	373	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
	374	sdrc_block_contents.emr_1_1 = 0x0;
	375	sdrc_block_contents.emr_2_1 = 0x0;
	376	sdrc_block_contents.emr_3_1 = 0x0;
	377	sdrc_block_contents.actim_ctrla_1 =
	378	sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
	379	sdrc_block_contents.actim_ctrlb_1 =
	380	sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
	381	sdrc_block_contents.rfr_ctrl_1 =
	382	sdrc_read_reg(SDRC_RFR_CTRL_1);
	383	sdrc_block_contents.dcdl_1_ctrl = 0x0;
	384	sdrc_block_contents.dcdl_2_ctrl = 0x0;
	385	sdrc_block_contents.flags = 0x0;
	386	sdrc_block_contents.block_size = 0x0;
	387
	388	arm_context_addr = virt_to_phys(omap3_arm_context);
	389
	390	/* Copy all the contents to the scratchpad location */
	391	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
	392	memcpy_toio(scratchpad_address, &scratchpad_contents,
	393	sizeof(scratchpad_contents));
	394	/* Scratchpad contents being 32 bits, a divide by 4 done here */
	395	memcpy_toio(scratchpad_address +
	396	scratchpad_contents.prcm_block_offset,
	397	&prcm_block_contents, sizeof(prcm_block_contents));
	398	memcpy_toio(scratchpad_address +
	399	scratchpad_contents.sdrc_block_offset,
	400	&sdrc_block_contents, sizeof(sdrc_block_contents));
	401	/*
	402	* Copies the address of the location in SDRAM where ARM
	403	* registers get saved during a MPU OFF transition.
	404	*/
	405	memcpy_toio(scratchpad_address +
	406	scratchpad_contents.sdrc_block_offset +
	407	sizeof(sdrc_block_contents), &arm_context_addr, 4);
	408	}
	409
c96631e1 RN	410	void omap3_control_save_context(void)
	411	{
	412	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
	413	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
	414	control_context.mem_dftrw0 =
	415	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
	416	control_context.mem_dftrw1 =
	417	omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
	418	control_context.msuspendmux_0 =
	419	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
	420	control_context.msuspendmux_1 =
	421	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
	422	control_context.msuspendmux_2 =
	423	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
	424	control_context.msuspendmux_3 =
	425	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
	426	control_context.msuspendmux_4 =
	427	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
	428	control_context.msuspendmux_5 =
	429	omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
	430	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
	431	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
	432	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
	433	control_context.iva2_bootaddr =
	434	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
	435	control_context.iva2_bootmod =
	436	omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
	437	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
	438	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
	439	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
	440	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
	441	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
	442	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
	443	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
	444	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
	445	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
	446	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
	447	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
	448	control_context.dss_dpll_spreading =
	449	omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	450	control_context.core_dpll_spreading =
	451	omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	452	control_context.per_dpll_spreading =
	453	omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
	454	control_context.usbhost_dpll_spreading =
	455	omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	456	control_context.pbias_lite =
	457	omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
	458	control_context.temp_sensor =
	459	omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
	460	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
	461	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
	462	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
f5f9d132 PW	463	control_context.padconf_sys_nirq =
f5f9d132 PW	464	omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
c96631e1 RN	465	return;
	466	}
	467
	468	void omap3_control_restore_context(void)
	469	{
	470	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
	471	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
	472	omap_ctrl_writel(control_context.mem_dftrw0,
	473	OMAP343X_CONTROL_MEM_DFTRW0);
	474	omap_ctrl_writel(control_context.mem_dftrw1,
	475	OMAP343X_CONTROL_MEM_DFTRW1);
	476	omap_ctrl_writel(control_context.msuspendmux_0,
	477	OMAP2_CONTROL_MSUSPENDMUX_0);
	478	omap_ctrl_writel(control_context.msuspendmux_1,
	479	OMAP2_CONTROL_MSUSPENDMUX_1);
	480	omap_ctrl_writel(control_context.msuspendmux_2,
	481	OMAP2_CONTROL_MSUSPENDMUX_2);
	482	omap_ctrl_writel(control_context.msuspendmux_3,
	483	OMAP2_CONTROL_MSUSPENDMUX_3);
	484	omap_ctrl_writel(control_context.msuspendmux_4,
	485	OMAP2_CONTROL_MSUSPENDMUX_4);
	486	omap_ctrl_writel(control_context.msuspendmux_5,
	487	OMAP2_CONTROL_MSUSPENDMUX_5);
	488	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
	489	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
	490	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
	491	omap_ctrl_writel(control_context.iva2_bootaddr,
	492	OMAP343X_CONTROL_IVA2_BOOTADDR);
	493	omap_ctrl_writel(control_context.iva2_bootmod,
	494	OMAP343X_CONTROL_IVA2_BOOTMOD);
	495	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
	496	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
	497	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
	498	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
	499	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
	500	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
	501	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
	502	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
	503	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
	504	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
	505	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
	506	omap_ctrl_writel(control_context.dss_dpll_spreading,
	507	OMAP343X_CONTROL_DSS_DPLL_SPREADING);
	508	omap_ctrl_writel(control_context.core_dpll_spreading,
	509	OMAP343X_CONTROL_CORE_DPLL_SPREADING);
	510	omap_ctrl_writel(control_context.per_dpll_spreading,
	511	OMAP343X_CONTROL_PER_DPLL_SPREADING);
	512	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
	513	OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
	514	omap_ctrl_writel(control_context.pbias_lite,
	515	OMAP343X_CONTROL_PBIAS_LITE);
	516	omap_ctrl_writel(control_context.temp_sensor,
	517	OMAP343X_CONTROL_TEMP_SENSOR);
	518	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
	519	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
	520	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
f5f9d132 PW	521	omap_ctrl_writel(control_context.padconf_sys_nirq,
f5f9d132 PW	522	OMAP343X_CONTROL_PADCONF_SYSNIRQ);
c96631e1 RN	523	return;
c96631e1 RN	524	}
458e999e NM	525
	526	void omap3630_ctrl_disable_rta(void)
	527	{
	528	if (!cpu_is_omap3630())
	529	return;
	530	omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
	531	}
	532
c96631e1	533	#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */