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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/kernel.h> |
13 | #include <linux/init.h> | |
14 | #include <linux/platform_device.h> | |
fced80c7 | 15 | #include <linux/io.h> |
917fa280 | 16 | #include <linux/clk.h> |
f2ce6231 | 17 | #include <linux/err.h> |
1a5d8190 | 18 | #include <linux/slab.h> |
1dbae815 | 19 | |
a09e64fb | 20 | #include <mach/hardware.h> |
88341334 | 21 | #include <mach/irqs.h> |
1dbae815 TL |
22 | #include <asm/mach-types.h> |
23 | #include <asm/mach/map.h> | |
88341334 | 24 | #include <asm/pmu.h> |
1dbae815 | 25 | |
ce491cf8 TL |
26 | #include <plat/tc.h> |
27 | #include <plat/board.h> | |
a09f73fa | 28 | #include <plat/mcbsp.h> |
a09e64fb | 29 | #include <mach/gpio.h> |
ce491cf8 | 30 | #include <plat/mmc.h> |
ee5500c4 | 31 | #include <plat/dma.h> |
f2ce6231 VC |
32 | #include <plat/omap_hwmod.h> |
33 | #include <plat/omap_device.h> | |
59556765 | 34 | #include <plat/omap4-keypad.h> |
1dbae815 | 35 | |
4896e394 | 36 | #include "mux.h" |
4814ced5 | 37 | #include "control.h" |
a11f6706 | 38 | #include "devices.h" |
4896e394 | 39 | |
0abcf618 | 40 | #define L3_MODULES_MAX_LEN 12 |
a4dc616a | 41 | #define L3_MODULES 3 |
0abcf618 | 42 | |
43 | static int __init omap3_l3_init(void) | |
44 | { | |
45 | int l; | |
46 | struct omap_hwmod *oh; | |
47 | struct omap_device *od; | |
48 | char oh_name[L3_MODULES_MAX_LEN]; | |
49 | ||
50 | /* | |
51 | * To avoid code running on other OMAPs in | |
52 | * multi-omap builds | |
53 | */ | |
54 | if (!(cpu_is_omap34xx())) | |
55 | return -ENODEV; | |
56 | ||
57 | l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main"); | |
58 | ||
59 | oh = omap_hwmod_lookup(oh_name); | |
60 | ||
61 | if (!oh) | |
62 | pr_err("could not look up %s\n", oh_name); | |
63 | ||
64 | od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, | |
65 | NULL, 0, 0); | |
66 | ||
67 | WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); | |
68 | ||
36133869 | 69 | return IS_ERR(od) ? PTR_ERR(od) : 0; |
0abcf618 | 70 | } |
71 | postcore_initcall(omap3_l3_init); | |
72 | ||
a4dc616a | 73 | static int __init omap4_l3_init(void) |
74 | { | |
75 | int l, i; | |
76 | struct omap_hwmod *oh[3]; | |
77 | struct omap_device *od; | |
78 | char oh_name[L3_MODULES_MAX_LEN]; | |
79 | ||
80 | /* | |
81 | * To avoid code running on other OMAPs in | |
82 | * multi-omap builds | |
83 | */ | |
84 | if (!(cpu_is_omap44xx())) | |
85 | return -ENODEV; | |
86 | ||
87 | for (i = 0; i < L3_MODULES; i++) { | |
88 | l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1); | |
89 | ||
90 | oh[i] = omap_hwmod_lookup(oh_name); | |
91 | if (!(oh[i])) | |
92 | pr_err("could not look up %s\n", oh_name); | |
93 | } | |
94 | ||
95 | od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, | |
96 | 0, NULL, 0, 0); | |
97 | ||
98 | WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name); | |
99 | ||
100 | return PTR_ERR(od); | |
101 | } | |
102 | postcore_initcall(omap4_l3_init); | |
103 | ||
828c707e | 104 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 105 | |
cfe2cde6 | 106 | static struct resource omap2cam_resources[] = { |
c40fae95 | 107 | { |
828c707e TL |
108 | .start = OMAP24XX_CAMERA_BASE, |
109 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
110 | .flags = IORESOURCE_MEM, | |
111 | }, | |
112 | { | |
113 | .start = INT_24XX_CAM_IRQ, | |
114 | .flags = IORESOURCE_IRQ, | |
115 | } | |
116 | }; | |
117 | ||
cfe2cde6 | 118 | static struct platform_device omap2cam_device = { |
828c707e TL |
119 | .name = "omap24xxcam", |
120 | .id = -1, | |
cfe2cde6 SA |
121 | .num_resources = ARRAY_SIZE(omap2cam_resources), |
122 | .resource = omap2cam_resources, | |
828c707e | 123 | }; |
a11f6706 | 124 | #endif |
828c707e TL |
125 | |
126 | static struct resource omap3isp_resources[] = { | |
127 | { | |
128 | .start = OMAP3430_ISP_BASE, | |
129 | .end = OMAP3430_ISP_END, | |
130 | .flags = IORESOURCE_MEM, | |
131 | }, | |
828c707e TL |
132 | { |
133 | .start = OMAP3430_ISP_CCP2_BASE, | |
134 | .end = OMAP3430_ISP_CCP2_END, | |
135 | .flags = IORESOURCE_MEM, | |
136 | }, | |
137 | { | |
138 | .start = OMAP3430_ISP_CCDC_BASE, | |
139 | .end = OMAP3430_ISP_CCDC_END, | |
140 | .flags = IORESOURCE_MEM, | |
141 | }, | |
142 | { | |
143 | .start = OMAP3430_ISP_HIST_BASE, | |
144 | .end = OMAP3430_ISP_HIST_END, | |
145 | .flags = IORESOURCE_MEM, | |
146 | }, | |
147 | { | |
148 | .start = OMAP3430_ISP_H3A_BASE, | |
149 | .end = OMAP3430_ISP_H3A_END, | |
150 | .flags = IORESOURCE_MEM, | |
151 | }, | |
152 | { | |
153 | .start = OMAP3430_ISP_PREV_BASE, | |
154 | .end = OMAP3430_ISP_PREV_END, | |
155 | .flags = IORESOURCE_MEM, | |
156 | }, | |
157 | { | |
158 | .start = OMAP3430_ISP_RESZ_BASE, | |
159 | .end = OMAP3430_ISP_RESZ_END, | |
160 | .flags = IORESOURCE_MEM, | |
161 | }, | |
162 | { | |
163 | .start = OMAP3430_ISP_SBL_BASE, | |
164 | .end = OMAP3430_ISP_SBL_END, | |
165 | .flags = IORESOURCE_MEM, | |
166 | }, | |
167 | { | |
6817a69a TT |
168 | .start = OMAP3430_ISP_CSI2A_REGS1_BASE, |
169 | .end = OMAP3430_ISP_CSI2A_REGS1_END, | |
828c707e TL |
170 | .flags = IORESOURCE_MEM, |
171 | }, | |
172 | { | |
6817a69a TT |
173 | .start = OMAP3430_ISP_CSIPHY2_BASE, |
174 | .end = OMAP3430_ISP_CSIPHY2_END, | |
175 | .flags = IORESOURCE_MEM, | |
176 | }, | |
177 | { | |
178 | .start = OMAP3630_ISP_CSI2A_REGS2_BASE, | |
179 | .end = OMAP3630_ISP_CSI2A_REGS2_END, | |
828c707e TL |
180 | .flags = IORESOURCE_MEM, |
181 | }, | |
182 | { | |
6817a69a TT |
183 | .start = OMAP3630_ISP_CSI2C_REGS1_BASE, |
184 | .end = OMAP3630_ISP_CSI2C_REGS1_END, | |
185 | .flags = IORESOURCE_MEM, | |
186 | }, | |
187 | { | |
188 | .start = OMAP3630_ISP_CSIPHY1_BASE, | |
189 | .end = OMAP3630_ISP_CSIPHY1_END, | |
190 | .flags = IORESOURCE_MEM, | |
191 | }, | |
192 | { | |
193 | .start = OMAP3630_ISP_CSI2C_REGS2_BASE, | |
194 | .end = OMAP3630_ISP_CSI2C_REGS2_END, | |
828c707e TL |
195 | .flags = IORESOURCE_MEM, |
196 | }, | |
197 | { | |
198 | .start = INT_34XX_CAM_IRQ, | |
199 | .flags = IORESOURCE_IRQ, | |
200 | } | |
201 | }; | |
202 | ||
203 | static struct platform_device omap3isp_device = { | |
204 | .name = "omap3isp", | |
205 | .id = -1, | |
206 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
207 | .resource = omap3isp_resources, | |
208 | }; | |
209 | ||
a11f6706 | 210 | int omap3_init_camera(struct isp_platform_data *pdata) |
828c707e | 211 | { |
a11f6706 LP |
212 | omap3isp_device.dev.platform_data = pdata; |
213 | return platform_device_register(&omap3isp_device); | |
828c707e | 214 | } |
828c707e | 215 | |
828c707e TL |
216 | static inline void omap_init_camera(void) |
217 | { | |
cfe2cde6 SA |
218 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
219 | if (cpu_is_omap24xx()) | |
220 | platform_device_register(&omap2cam_device); | |
828c707e | 221 | #endif |
cfe2cde6 | 222 | } |
828c707e | 223 | |
59556765 SR |
224 | struct omap_device_pm_latency omap_keyboard_latency[] = { |
225 | { | |
226 | .deactivate_func = omap_device_idle_hwmods, | |
227 | .activate_func = omap_device_enable_hwmods, | |
228 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
229 | }, | |
230 | }; | |
231 | ||
232 | int __init omap4_keyboard_init(struct omap4_keypad_platform_data | |
233 | *sdp4430_keypad_data) | |
234 | { | |
235 | struct omap_device *od; | |
236 | struct omap_hwmod *oh; | |
237 | struct omap4_keypad_platform_data *keypad_data; | |
238 | unsigned int id = -1; | |
239 | char *oh_name = "kbd"; | |
240 | char *name = "omap4-keypad"; | |
241 | ||
242 | oh = omap_hwmod_lookup(oh_name); | |
243 | if (!oh) { | |
244 | pr_err("Could not look up %s\n", oh_name); | |
245 | return -ENODEV; | |
246 | } | |
247 | ||
248 | keypad_data = sdp4430_keypad_data; | |
249 | ||
250 | od = omap_device_build(name, id, oh, keypad_data, | |
251 | sizeof(struct omap4_keypad_platform_data), | |
252 | omap_keyboard_latency, | |
253 | ARRAY_SIZE(omap_keyboard_latency), 0); | |
254 | ||
255 | if (IS_ERR(od)) { | |
256 | WARN(1, "Cant build omap_device for %s:%s.\n", | |
257 | name, oh->name); | |
258 | return PTR_ERR(od); | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
6c20a683 | 264 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
69dbf857 FC |
265 | static struct omap_device_pm_latency mbox_latencies[] = { |
266 | [0] = { | |
267 | .activate_func = omap_device_enable_hwmods, | |
268 | .deactivate_func = omap_device_idle_hwmods, | |
269 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
454bf340 S |
270 | }, |
271 | }; | |
c40fae95 TL |
272 | |
273 | static inline void omap_init_mbox(void) | |
274 | { | |
69dbf857 FC |
275 | struct omap_hwmod *oh; |
276 | struct omap_device *od; | |
277 | ||
278 | oh = omap_hwmod_lookup("mailbox"); | |
279 | if (!oh) { | |
280 | pr_err("%s: unable to find hwmod\n", __func__); | |
6c20a683 HD |
281 | return; |
282 | } | |
69dbf857 FC |
283 | |
284 | od = omap_device_build("omap-mailbox", -1, oh, NULL, 0, | |
285 | mbox_latencies, ARRAY_SIZE(mbox_latencies), 0); | |
286 | WARN(IS_ERR(od), "%s: could not build device, err %ld\n", | |
287 | __func__, PTR_ERR(od)); | |
c40fae95 TL |
288 | } |
289 | #else | |
290 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 291 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 292 | |
9b6553cd | 293 | static inline void omap_init_sti(void) {} |
9b6553cd | 294 | |
f0fba2ad LG |
295 | #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) |
296 | ||
297 | static struct platform_device omap_pcm = { | |
298 | .name = "omap-pcm-audio", | |
299 | .id = -1, | |
300 | }; | |
301 | ||
302 | /* | |
303 | * OMAP2420 has 2 McBSP ports | |
304 | * OMAP2430 has 5 McBSP ports | |
305 | * OMAP3 has 5 McBSP ports | |
306 | * OMAP4 has 4 McBSP ports | |
307 | */ | |
308 | OMAP_MCBSP_PLATFORM_DEVICE(1); | |
309 | OMAP_MCBSP_PLATFORM_DEVICE(2); | |
310 | OMAP_MCBSP_PLATFORM_DEVICE(3); | |
311 | OMAP_MCBSP_PLATFORM_DEVICE(4); | |
312 | OMAP_MCBSP_PLATFORM_DEVICE(5); | |
313 | ||
314 | static void omap_init_audio(void) | |
315 | { | |
316 | platform_device_register(&omap_mcbsp1); | |
317 | platform_device_register(&omap_mcbsp2); | |
318 | if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { | |
319 | platform_device_register(&omap_mcbsp3); | |
320 | platform_device_register(&omap_mcbsp4); | |
321 | } | |
322 | if (cpu_is_omap243x() || cpu_is_omap34xx()) | |
323 | platform_device_register(&omap_mcbsp5); | |
324 | ||
325 | platform_device_register(&omap_pcm); | |
326 | } | |
327 | ||
328 | #else | |
329 | static inline void omap_init_audio(void) {} | |
330 | #endif | |
331 | ||
646e3ed1 | 332 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 333 | |
ce491cf8 | 334 | #include <plat/mcspi.h> |
ed7eb9d9 | 335 | |
1a5d8190 C |
336 | struct omap_device_pm_latency omap_mcspi_latency[] = { |
337 | [0] = { | |
338 | .deactivate_func = omap_device_idle_hwmods, | |
339 | .activate_func = omap_device_enable_hwmods, | |
340 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
646e3ed1 TL |
341 | }, |
342 | }; | |
646e3ed1 | 343 | |
1a5d8190 | 344 | static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) |
af41a12f | 345 | { |
1a5d8190 C |
346 | struct omap_device *od; |
347 | char *name = "omap2_mcspi"; | |
348 | struct omap2_mcspi_platform_config *pdata; | |
349 | static int spi_num; | |
350 | struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; | |
351 | ||
352 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | |
353 | if (!pdata) { | |
354 | pr_err("Memory allocation for McSPI device failed\n"); | |
355 | return -ENOMEM; | |
356 | } | |
af41a12f | 357 | |
1a5d8190 C |
358 | pdata->num_cs = mcspi_attrib->num_chipselect; |
359 | switch (oh->class->rev) { | |
360 | case OMAP2_MCSPI_REV: | |
361 | case OMAP3_MCSPI_REV: | |
362 | pdata->regs_offset = 0; | |
363 | break; | |
364 | case OMAP4_MCSPI_REV: | |
365 | pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; | |
366 | break; | |
367 | default: | |
368 | pr_err("Invalid McSPI Revision value\n"); | |
369 | return -EINVAL; | |
370 | } | |
af41a12f | 371 | |
1a5d8190 C |
372 | spi_num++; |
373 | od = omap_device_build(name, spi_num, oh, pdata, | |
374 | sizeof(*pdata), omap_mcspi_latency, | |
375 | ARRAY_SIZE(omap_mcspi_latency), 0); | |
376 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", | |
377 | name, oh->name); | |
378 | kfree(pdata); | |
379 | return 0; | |
af41a12f | 380 | } |
af41a12f TL |
381 | |
382 | static void omap_init_mcspi(void) | |
383 | { | |
1a5d8190 | 384 | omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); |
ed7eb9d9 JY |
385 | } |
386 | ||
387 | #else | |
388 | static inline void omap_init_mcspi(void) {} | |
389 | #endif | |
390 | ||
88341334 WD |
391 | static struct resource omap2_pmu_resource = { |
392 | .start = 3, | |
393 | .end = 3, | |
394 | .flags = IORESOURCE_IRQ, | |
395 | }; | |
396 | ||
397 | static struct resource omap3_pmu_resource = { | |
398 | .start = INT_34XX_BENCH_MPU_EMUL, | |
399 | .end = INT_34XX_BENCH_MPU_EMUL, | |
400 | .flags = IORESOURCE_IRQ, | |
401 | }; | |
402 | ||
403 | static struct platform_device omap_pmu_device = { | |
404 | .name = "arm-pmu", | |
405 | .id = ARM_PMU_DEVICE_CPU, | |
406 | .num_resources = 1, | |
407 | }; | |
408 | ||
409 | static void omap_init_pmu(void) | |
410 | { | |
411 | if (cpu_is_omap24xx()) | |
412 | omap_pmu_device.resource = &omap2_pmu_resource; | |
413 | else if (cpu_is_omap34xx()) | |
414 | omap_pmu_device.resource = &omap3_pmu_resource; | |
415 | else | |
416 | return; | |
417 | ||
418 | platform_device_register(&omap_pmu_device); | |
419 | } | |
420 | ||
421 | ||
ee5500c4 DK |
422 | #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE) |
423 | ||
edc774ed | 424 | #ifdef CONFIG_ARCH_OMAP2 |
ee5500c4 | 425 | static struct resource omap2_sham_resources[] = { |
646e3ed1 TL |
426 | { |
427 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
428 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
429 | .flags = IORESOURCE_MEM, | |
430 | }, | |
431 | { | |
432 | .start = INT_24XX_SHA1MD5, | |
433 | .flags = IORESOURCE_IRQ, | |
434 | } | |
435 | }; | |
ee5500c4 DK |
436 | static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources); |
437 | #else | |
438 | #define omap2_sham_resources NULL | |
439 | #define omap2_sham_resources_sz 0 | |
440 | #endif | |
646e3ed1 | 441 | |
edc774ed | 442 | #ifdef CONFIG_ARCH_OMAP3 |
ee5500c4 DK |
443 | static struct resource omap3_sham_resources[] = { |
444 | { | |
445 | .start = OMAP34XX_SEC_SHA1MD5_BASE, | |
446 | .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64, | |
447 | .flags = IORESOURCE_MEM, | |
448 | }, | |
449 | { | |
450 | .start = INT_34XX_SHA1MD52_IRQ, | |
451 | .flags = IORESOURCE_IRQ, | |
452 | }, | |
453 | { | |
454 | .start = OMAP34XX_DMA_SHA1MD5_RX, | |
455 | .flags = IORESOURCE_DMA, | |
456 | } | |
457 | }; | |
458 | static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources); | |
459 | #else | |
460 | #define omap3_sham_resources NULL | |
461 | #define omap3_sham_resources_sz 0 | |
462 | #endif | |
463 | ||
464 | static struct platform_device sham_device = { | |
465 | .name = "omap-sham", | |
646e3ed1 | 466 | .id = -1, |
646e3ed1 TL |
467 | }; |
468 | ||
ee5500c4 | 469 | static void omap_init_sham(void) |
646e3ed1 | 470 | { |
ee5500c4 DK |
471 | if (cpu_is_omap24xx()) { |
472 | sham_device.resource = omap2_sham_resources; | |
473 | sham_device.num_resources = omap2_sham_resources_sz; | |
474 | } else if (cpu_is_omap34xx()) { | |
475 | sham_device.resource = omap3_sham_resources; | |
476 | sham_device.num_resources = omap3_sham_resources_sz; | |
477 | } else { | |
478 | pr_err("%s: platform not supported\n", __func__); | |
479 | return; | |
480 | } | |
481 | platform_device_register(&sham_device); | |
646e3ed1 TL |
482 | } |
483 | #else | |
ee5500c4 | 484 | static inline void omap_init_sham(void) { } |
646e3ed1 TL |
485 | #endif |
486 | ||
b744c679 DK |
487 | #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE) |
488 | ||
82a0c149 | 489 | #ifdef CONFIG_ARCH_OMAP2 |
b744c679 DK |
490 | static struct resource omap2_aes_resources[] = { |
491 | { | |
492 | .start = OMAP24XX_SEC_AES_BASE, | |
493 | .end = OMAP24XX_SEC_AES_BASE + 0x4C, | |
494 | .flags = IORESOURCE_MEM, | |
495 | }, | |
496 | { | |
497 | .start = OMAP24XX_DMA_AES_TX, | |
498 | .flags = IORESOURCE_DMA, | |
499 | }, | |
500 | { | |
501 | .start = OMAP24XX_DMA_AES_RX, | |
502 | .flags = IORESOURCE_DMA, | |
503 | } | |
504 | }; | |
505 | static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources); | |
506 | #else | |
507 | #define omap2_aes_resources NULL | |
508 | #define omap2_aes_resources_sz 0 | |
509 | #endif | |
510 | ||
82a0c149 | 511 | #ifdef CONFIG_ARCH_OMAP3 |
b744c679 DK |
512 | static struct resource omap3_aes_resources[] = { |
513 | { | |
514 | .start = OMAP34XX_SEC_AES_BASE, | |
515 | .end = OMAP34XX_SEC_AES_BASE + 0x4C, | |
516 | .flags = IORESOURCE_MEM, | |
517 | }, | |
518 | { | |
519 | .start = OMAP34XX_DMA_AES2_TX, | |
520 | .flags = IORESOURCE_DMA, | |
521 | }, | |
522 | { | |
523 | .start = OMAP34XX_DMA_AES2_RX, | |
524 | .flags = IORESOURCE_DMA, | |
525 | } | |
526 | }; | |
527 | static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources); | |
528 | #else | |
529 | #define omap3_aes_resources NULL | |
530 | #define omap3_aes_resources_sz 0 | |
531 | #endif | |
532 | ||
533 | static struct platform_device aes_device = { | |
534 | .name = "omap-aes", | |
535 | .id = -1, | |
536 | }; | |
537 | ||
538 | static void omap_init_aes(void) | |
539 | { | |
540 | if (cpu_is_omap24xx()) { | |
541 | aes_device.resource = omap2_aes_resources; | |
542 | aes_device.num_resources = omap2_aes_resources_sz; | |
543 | } else if (cpu_is_omap34xx()) { | |
544 | aes_device.resource = omap3_aes_resources; | |
545 | aes_device.num_resources = omap3_aes_resources_sz; | |
546 | } else { | |
547 | pr_err("%s: platform not supported\n", __func__); | |
548 | return; | |
549 | } | |
550 | platform_device_register(&aes_device); | |
551 | } | |
552 | ||
553 | #else | |
554 | static inline void omap_init_aes(void) { } | |
555 | #endif | |
556 | ||
d8874665 TL |
557 | /*-------------------------------------------------------------------------*/ |
558 | ||
e08016d0 | 559 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
917fa280 | 560 | |
e08016d0 AG |
561 | static inline void omap242x_mmc_mux(struct omap_mmc_platform_data |
562 | *mmc_controller) | |
d8874665 | 563 | { |
ed8303fc | 564 | if ((mmc_controller->slots[0].switch_pin > 0) && \ |
565 | (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) | |
566 | omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, | |
567 | OMAP_PIN_INPUT_PULLUP); | |
568 | if ((mmc_controller->slots[0].gpio_wp > 0) && \ | |
569 | (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) | |
570 | omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, | |
571 | OMAP_PIN_INPUT_PULLUP); | |
572 | ||
e08016d0 AG |
573 | omap_mux_init_signal("sdmmc_cmd", 0); |
574 | omap_mux_init_signal("sdmmc_clki", 0); | |
575 | omap_mux_init_signal("sdmmc_clko", 0); | |
576 | omap_mux_init_signal("sdmmc_dat0", 0); | |
577 | omap_mux_init_signal("sdmmc_dat_dir0", 0); | |
578 | omap_mux_init_signal("sdmmc_cmd_dir", 0); | |
579 | if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { | |
580 | omap_mux_init_signal("sdmmc_dat1", 0); | |
581 | omap_mux_init_signal("sdmmc_dat2", 0); | |
582 | omap_mux_init_signal("sdmmc_dat3", 0); | |
583 | omap_mux_init_signal("sdmmc_dat_dir1", 0); | |
584 | omap_mux_init_signal("sdmmc_dat_dir2", 0); | |
585 | omap_mux_init_signal("sdmmc_dat_dir3", 0); | |
d8874665 | 586 | } |
57b9daa0 | 587 | |
e08016d0 AG |
588 | /* |
589 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
590 | * selection | |
591 | */ | |
592 | if (mmc_controller->slots[0].internal_clock) { | |
593 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
594 | v |= (1 << 24); | |
595 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
57b9daa0 | 596 | } |
d8874665 TL |
597 | } |
598 | ||
e08016d0 | 599 | void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) |
d8874665 | 600 | { |
e08016d0 | 601 | char *name = "mmci-omap"; |
d8874665 | 602 | |
e08016d0 AG |
603 | if (!mmc_data[0]) { |
604 | pr_err("%s fails: Incomplete platform data\n", __func__); | |
605 | return; | |
606 | } | |
d8874665 | 607 | |
e08016d0 AG |
608 | omap242x_mmc_mux(mmc_data[0]); |
609 | omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, | |
610 | INT_24XX_MMC_IRQ, mmc_data[0]); | |
d8874665 TL |
611 | } |
612 | ||
613 | #endif | |
614 | ||
615 | /*-------------------------------------------------------------------------*/ | |
616 | ||
646e3ed1 | 617 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
59b479e0 | 618 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) |
646e3ed1 TL |
619 | #define OMAP_HDQ_BASE 0x480B2000 |
620 | #endif | |
621 | static struct resource omap_hdq_resources[] = { | |
622 | { | |
623 | .start = OMAP_HDQ_BASE, | |
624 | .end = OMAP_HDQ_BASE + 0x1C, | |
625 | .flags = IORESOURCE_MEM, | |
626 | }, | |
627 | { | |
628 | .start = INT_24XX_HDQ_IRQ, | |
629 | .flags = IORESOURCE_IRQ, | |
630 | }, | |
631 | }; | |
632 | static struct platform_device omap_hdq_dev = { | |
633 | .name = "omap_hdq", | |
634 | .id = 0, | |
635 | .dev = { | |
636 | .platform_data = NULL, | |
637 | }, | |
638 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
639 | .resource = omap_hdq_resources, | |
640 | }; | |
641 | static inline void omap_hdq_init(void) | |
642 | { | |
643 | (void) platform_device_register(&omap_hdq_dev); | |
644 | } | |
645 | #else | |
646 | static inline void omap_hdq_init(void) {} | |
647 | #endif | |
648 | ||
b227358d VH |
649 | /*---------------------------------------------------------------------------*/ |
650 | ||
651 | #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \ | |
652 | defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE) | |
653 | #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) | |
654 | static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = { | |
655 | }; | |
656 | #else | |
657 | static struct resource omap_vout_resource[2] = { | |
658 | }; | |
659 | #endif | |
660 | ||
661 | static struct platform_device omap_vout_device = { | |
662 | .name = "omap_vout", | |
663 | .num_resources = ARRAY_SIZE(omap_vout_resource), | |
664 | .resource = &omap_vout_resource[0], | |
665 | .id = -1, | |
666 | }; | |
667 | static void omap_init_vout(void) | |
668 | { | |
669 | if (platform_device_register(&omap_vout_device) < 0) | |
670 | printk(KERN_ERR "Unable to register OMAP-VOUT device\n"); | |
671 | } | |
672 | #else | |
673 | static inline void omap_init_vout(void) {} | |
674 | #endif | |
675 | ||
1dbae815 TL |
676 | /*-------------------------------------------------------------------------*/ |
677 | ||
678 | static int __init omap2_init_devices(void) | |
679 | { | |
81fbc5ef PW |
680 | /* |
681 | * please keep these calls, and their implementations above, | |
1dbae815 TL |
682 | * in alphabetical order so they're easier to sort through. |
683 | */ | |
f0fba2ad | 684 | omap_init_audio(); |
828c707e | 685 | omap_init_camera(); |
c40fae95 | 686 | omap_init_mbox(); |
ed7eb9d9 | 687 | omap_init_mcspi(); |
88341334 | 688 | omap_init_pmu(); |
646e3ed1 | 689 | omap_hdq_init(); |
9b6553cd | 690 | omap_init_sti(); |
ee5500c4 | 691 | omap_init_sham(); |
b744c679 | 692 | omap_init_aes(); |
b227358d | 693 | omap_init_vout(); |
1dbae815 TL |
694 | |
695 | return 0; | |
696 | } | |
697 | arch_initcall(omap2_init_devices); | |
f2ce6231 VC |
698 | |
699 | #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) | |
a9b365bd | 700 | static struct omap_device_pm_latency omap_wdt_latency[] = { |
f2ce6231 VC |
701 | [0] = { |
702 | .deactivate_func = omap_device_idle_hwmods, | |
703 | .activate_func = omap_device_enable_hwmods, | |
704 | .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, | |
705 | }, | |
706 | }; | |
707 | ||
708 | static int __init omap_init_wdt(void) | |
709 | { | |
710 | int id = -1; | |
711 | struct omap_device *od; | |
712 | struct omap_hwmod *oh; | |
713 | char *oh_name = "wd_timer2"; | |
714 | char *dev_name = "omap_wdt"; | |
715 | ||
716 | if (!cpu_class_is_omap2()) | |
717 | return 0; | |
718 | ||
719 | oh = omap_hwmod_lookup(oh_name); | |
720 | if (!oh) { | |
721 | pr_err("Could not look up wd_timer%d hwmod\n", id); | |
722 | return -EINVAL; | |
723 | } | |
724 | ||
725 | od = omap_device_build(dev_name, id, oh, NULL, 0, | |
726 | omap_wdt_latency, | |
727 | ARRAY_SIZE(omap_wdt_latency), 0); | |
728 | WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n", | |
729 | dev_name, oh->name); | |
730 | return 0; | |
731 | } | |
732 | subsys_initcall(omap_init_wdt); | |
733 | #endif |