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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/devices.c | |
3 | * | |
4 | * OMAP2 platform device setup/initialization | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
1dbae815 TL |
12 | #include <linux/module.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/platform_device.h> | |
fced80c7 | 16 | #include <linux/io.h> |
917fa280 | 17 | #include <linux/clk.h> |
1dbae815 | 18 | |
a09e64fb | 19 | #include <mach/hardware.h> |
1dbae815 TL |
20 | #include <asm/mach-types.h> |
21 | #include <asm/mach/map.h> | |
22 | ||
ce491cf8 TL |
23 | #include <plat/control.h> |
24 | #include <plat/tc.h> | |
25 | #include <plat/board.h> | |
26 | #include <plat/mux.h> | |
a09e64fb | 27 | #include <mach/gpio.h> |
ce491cf8 | 28 | #include <plat/mmc.h> |
1dbae815 | 29 | |
828c707e | 30 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
c40fae95 | 31 | |
828c707e | 32 | static struct resource cam_resources[] = { |
c40fae95 | 33 | { |
828c707e TL |
34 | .start = OMAP24XX_CAMERA_BASE, |
35 | .end = OMAP24XX_CAMERA_BASE + 0xfff, | |
36 | .flags = IORESOURCE_MEM, | |
37 | }, | |
38 | { | |
39 | .start = INT_24XX_CAM_IRQ, | |
40 | .flags = IORESOURCE_IRQ, | |
41 | } | |
42 | }; | |
43 | ||
44 | static struct platform_device omap_cam_device = { | |
45 | .name = "omap24xxcam", | |
46 | .id = -1, | |
47 | .num_resources = ARRAY_SIZE(cam_resources), | |
48 | .resource = cam_resources, | |
49 | }; | |
50 | ||
51 | static inline void omap_init_camera(void) | |
52 | { | |
53 | platform_device_register(&omap_cam_device); | |
54 | } | |
55 | ||
56 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | |
57 | ||
58 | static struct resource omap3isp_resources[] = { | |
59 | { | |
60 | .start = OMAP3430_ISP_BASE, | |
61 | .end = OMAP3430_ISP_END, | |
62 | .flags = IORESOURCE_MEM, | |
63 | }, | |
64 | { | |
65 | .start = OMAP3430_ISP_CBUFF_BASE, | |
66 | .end = OMAP3430_ISP_CBUFF_END, | |
67 | .flags = IORESOURCE_MEM, | |
68 | }, | |
69 | { | |
70 | .start = OMAP3430_ISP_CCP2_BASE, | |
71 | .end = OMAP3430_ISP_CCP2_END, | |
72 | .flags = IORESOURCE_MEM, | |
73 | }, | |
74 | { | |
75 | .start = OMAP3430_ISP_CCDC_BASE, | |
76 | .end = OMAP3430_ISP_CCDC_END, | |
77 | .flags = IORESOURCE_MEM, | |
78 | }, | |
79 | { | |
80 | .start = OMAP3430_ISP_HIST_BASE, | |
81 | .end = OMAP3430_ISP_HIST_END, | |
82 | .flags = IORESOURCE_MEM, | |
83 | }, | |
84 | { | |
85 | .start = OMAP3430_ISP_H3A_BASE, | |
86 | .end = OMAP3430_ISP_H3A_END, | |
87 | .flags = IORESOURCE_MEM, | |
88 | }, | |
89 | { | |
90 | .start = OMAP3430_ISP_PREV_BASE, | |
91 | .end = OMAP3430_ISP_PREV_END, | |
92 | .flags = IORESOURCE_MEM, | |
93 | }, | |
94 | { | |
95 | .start = OMAP3430_ISP_RESZ_BASE, | |
96 | .end = OMAP3430_ISP_RESZ_END, | |
97 | .flags = IORESOURCE_MEM, | |
98 | }, | |
99 | { | |
100 | .start = OMAP3430_ISP_SBL_BASE, | |
101 | .end = OMAP3430_ISP_SBL_END, | |
102 | .flags = IORESOURCE_MEM, | |
103 | }, | |
104 | { | |
105 | .start = OMAP3430_ISP_CSI2A_BASE, | |
106 | .end = OMAP3430_ISP_CSI2A_END, | |
107 | .flags = IORESOURCE_MEM, | |
108 | }, | |
109 | { | |
110 | .start = OMAP3430_ISP_CSI2PHY_BASE, | |
111 | .end = OMAP3430_ISP_CSI2PHY_END, | |
112 | .flags = IORESOURCE_MEM, | |
113 | }, | |
114 | { | |
115 | .start = INT_34XX_CAM_IRQ, | |
116 | .flags = IORESOURCE_IRQ, | |
117 | } | |
118 | }; | |
119 | ||
120 | static struct platform_device omap3isp_device = { | |
121 | .name = "omap3isp", | |
122 | .id = -1, | |
123 | .num_resources = ARRAY_SIZE(omap3isp_resources), | |
124 | .resource = omap3isp_resources, | |
125 | }; | |
126 | ||
127 | static inline void omap_init_camera(void) | |
128 | { | |
129 | platform_device_register(&omap3isp_device); | |
130 | } | |
131 | #else | |
132 | static inline void omap_init_camera(void) | |
133 | { | |
134 | } | |
135 | #endif | |
136 | ||
6c20a683 | 137 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) |
c40fae95 | 138 | |
6c20a683 HD |
139 | #define MBOX_REG_SIZE 0x120 |
140 | ||
141 | static struct resource omap2_mbox_resources[] = { | |
c40fae95 | 142 | { |
6c20a683 HD |
143 | .start = OMAP24XX_MAILBOX_BASE, |
144 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
c40fae95 TL |
145 | .flags = IORESOURCE_MEM, |
146 | }, | |
147 | { | |
148 | .start = INT_24XX_MAIL_U0_MPU, | |
149 | .flags = IORESOURCE_IRQ, | |
150 | }, | |
151 | { | |
152 | .start = INT_24XX_MAIL_U3_MPU, | |
153 | .flags = IORESOURCE_IRQ, | |
154 | }, | |
155 | }; | |
156 | ||
6c20a683 HD |
157 | static struct resource omap3_mbox_resources[] = { |
158 | { | |
159 | .start = OMAP34XX_MAILBOX_BASE, | |
160 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | |
161 | .flags = IORESOURCE_MEM, | |
162 | }, | |
163 | { | |
164 | .start = INT_24XX_MAIL_U0_MPU, | |
165 | .flags = IORESOURCE_IRQ, | |
166 | }, | |
167 | }; | |
168 | ||
c40fae95 | 169 | static struct platform_device mbox_device = { |
da8cfe03 | 170 | .name = "omap2-mailbox", |
c40fae95 | 171 | .id = -1, |
c40fae95 TL |
172 | }; |
173 | ||
174 | static inline void omap_init_mbox(void) | |
175 | { | |
6c20a683 HD |
176 | if (cpu_is_omap2420()) { |
177 | mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources); | |
178 | mbox_device.resource = omap2_mbox_resources; | |
179 | } else if (cpu_is_omap3430()) { | |
180 | mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources); | |
181 | mbox_device.resource = omap3_mbox_resources; | |
182 | } else { | |
183 | pr_err("%s: platform not supported\n", __func__); | |
184 | return; | |
185 | } | |
c40fae95 TL |
186 | platform_device_register(&mbox_device); |
187 | } | |
188 | #else | |
189 | static inline void omap_init_mbox(void) { } | |
6c20a683 | 190 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
c40fae95 | 191 | |
9b6553cd TL |
192 | #if defined(CONFIG_OMAP_STI) |
193 | ||
646e3ed1 TL |
194 | #if defined(CONFIG_ARCH_OMAP2) |
195 | ||
196 | #define OMAP2_STI_BASE 0x48068000 | |
9b6553cd TL |
197 | #define OMAP2_STI_CHANNEL_BASE 0x54000000 |
198 | #define OMAP2_STI_IRQ 4 | |
199 | ||
200 | static struct resource sti_resources[] = { | |
201 | { | |
202 | .start = OMAP2_STI_BASE, | |
203 | .end = OMAP2_STI_BASE + 0x7ff, | |
204 | .flags = IORESOURCE_MEM, | |
205 | }, | |
206 | { | |
207 | .start = OMAP2_STI_CHANNEL_BASE, | |
208 | .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1, | |
209 | .flags = IORESOURCE_MEM, | |
210 | }, | |
211 | { | |
212 | .start = OMAP2_STI_IRQ, | |
213 | .flags = IORESOURCE_IRQ, | |
214 | } | |
215 | }; | |
646e3ed1 TL |
216 | #elif defined(CONFIG_ARCH_OMAP3) |
217 | ||
218 | #define OMAP3_SDTI_BASE 0x54500000 | |
219 | #define OMAP3_SDTI_CHANNEL_BASE 0x54600000 | |
220 | ||
221 | static struct resource sti_resources[] = { | |
222 | { | |
223 | .start = OMAP3_SDTI_BASE, | |
224 | .end = OMAP3_SDTI_BASE + 0xFFF, | |
225 | .flags = IORESOURCE_MEM, | |
226 | }, | |
227 | { | |
228 | .start = OMAP3_SDTI_CHANNEL_BASE, | |
229 | .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1, | |
230 | .flags = IORESOURCE_MEM, | |
231 | } | |
232 | }; | |
233 | ||
234 | #endif | |
9b6553cd TL |
235 | |
236 | static struct platform_device sti_device = { | |
237 | .name = "sti", | |
238 | .id = -1, | |
9b6553cd TL |
239 | .num_resources = ARRAY_SIZE(sti_resources), |
240 | .resource = sti_resources, | |
241 | }; | |
242 | ||
243 | static inline void omap_init_sti(void) | |
244 | { | |
245 | platform_device_register(&sti_device); | |
246 | } | |
247 | #else | |
248 | static inline void omap_init_sti(void) {} | |
249 | #endif | |
250 | ||
646e3ed1 | 251 | #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE) |
ed7eb9d9 | 252 | |
ce491cf8 | 253 | #include <plat/mcspi.h> |
ed7eb9d9 JY |
254 | |
255 | #define OMAP2_MCSPI1_BASE 0x48098000 | |
256 | #define OMAP2_MCSPI2_BASE 0x4809a000 | |
646e3ed1 TL |
257 | #define OMAP2_MCSPI3_BASE 0x480b8000 |
258 | #define OMAP2_MCSPI4_BASE 0x480ba000 | |
ed7eb9d9 | 259 | |
7869c0b9 SR |
260 | #define OMAP4_MCSPI1_BASE 0x48098100 |
261 | #define OMAP4_MCSPI2_BASE 0x4809a100 | |
262 | #define OMAP4_MCSPI3_BASE 0x480b8100 | |
263 | #define OMAP4_MCSPI4_BASE 0x480ba100 | |
264 | ||
ed7eb9d9 | 265 | static struct omap2_mcspi_platform_config omap2_mcspi1_config = { |
ed7eb9d9 JY |
266 | .num_cs = 4, |
267 | }; | |
268 | ||
c40fae95 TL |
269 | static struct resource omap2_mcspi1_resources[] = { |
270 | { | |
271 | .start = OMAP2_MCSPI1_BASE, | |
272 | .end = OMAP2_MCSPI1_BASE + 0xff, | |
273 | .flags = IORESOURCE_MEM, | |
274 | }, | |
275 | }; | |
276 | ||
646e3ed1 | 277 | static struct platform_device omap2_mcspi1 = { |
ed7eb9d9 JY |
278 | .name = "omap2_mcspi", |
279 | .id = 1, | |
c40fae95 TL |
280 | .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), |
281 | .resource = omap2_mcspi1_resources, | |
ed7eb9d9 JY |
282 | .dev = { |
283 | .platform_data = &omap2_mcspi1_config, | |
284 | }, | |
285 | }; | |
286 | ||
287 | static struct omap2_mcspi_platform_config omap2_mcspi2_config = { | |
ed7eb9d9 JY |
288 | .num_cs = 2, |
289 | }; | |
290 | ||
c40fae95 TL |
291 | static struct resource omap2_mcspi2_resources[] = { |
292 | { | |
293 | .start = OMAP2_MCSPI2_BASE, | |
294 | .end = OMAP2_MCSPI2_BASE + 0xff, | |
295 | .flags = IORESOURCE_MEM, | |
296 | }, | |
297 | }; | |
298 | ||
646e3ed1 | 299 | static struct platform_device omap2_mcspi2 = { |
ed7eb9d9 JY |
300 | .name = "omap2_mcspi", |
301 | .id = 2, | |
c40fae95 TL |
302 | .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), |
303 | .resource = omap2_mcspi2_resources, | |
ed7eb9d9 JY |
304 | .dev = { |
305 | .platform_data = &omap2_mcspi2_config, | |
306 | }, | |
307 | }; | |
308 | ||
7869c0b9 SR |
309 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
310 | defined(CONFIG_ARCH_OMAP4) | |
646e3ed1 TL |
311 | static struct omap2_mcspi_platform_config omap2_mcspi3_config = { |
312 | .num_cs = 2, | |
313 | }; | |
314 | ||
315 | static struct resource omap2_mcspi3_resources[] = { | |
316 | { | |
317 | .start = OMAP2_MCSPI3_BASE, | |
318 | .end = OMAP2_MCSPI3_BASE + 0xff, | |
319 | .flags = IORESOURCE_MEM, | |
320 | }, | |
321 | }; | |
322 | ||
323 | static struct platform_device omap2_mcspi3 = { | |
324 | .name = "omap2_mcspi", | |
325 | .id = 3, | |
326 | .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), | |
327 | .resource = omap2_mcspi3_resources, | |
328 | .dev = { | |
329 | .platform_data = &omap2_mcspi3_config, | |
330 | }, | |
331 | }; | |
332 | #endif | |
333 | ||
7869c0b9 | 334 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
646e3ed1 TL |
335 | static struct omap2_mcspi_platform_config omap2_mcspi4_config = { |
336 | .num_cs = 1, | |
337 | }; | |
338 | ||
339 | static struct resource omap2_mcspi4_resources[] = { | |
340 | { | |
341 | .start = OMAP2_MCSPI4_BASE, | |
342 | .end = OMAP2_MCSPI4_BASE + 0xff, | |
343 | .flags = IORESOURCE_MEM, | |
344 | }, | |
345 | }; | |
346 | ||
347 | static struct platform_device omap2_mcspi4 = { | |
348 | .name = "omap2_mcspi", | |
349 | .id = 4, | |
350 | .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), | |
351 | .resource = omap2_mcspi4_resources, | |
352 | .dev = { | |
353 | .platform_data = &omap2_mcspi4_config, | |
354 | }, | |
355 | }; | |
356 | #endif | |
357 | ||
af41a12f TL |
358 | #ifdef CONFIG_ARCH_OMAP4 |
359 | static inline void omap4_mcspi_fixup(void) | |
ed7eb9d9 | 360 | { |
af41a12f TL |
361 | omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; |
362 | omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; | |
363 | omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; | |
364 | omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; | |
365 | omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; | |
366 | omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; | |
367 | omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; | |
368 | omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; | |
369 | } | |
370 | #else | |
371 | static inline void omap4_mcspi_fixup(void) | |
372 | { | |
373 | } | |
374 | #endif | |
375 | ||
7869c0b9 SR |
376 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ |
377 | defined(CONFIG_ARCH_OMAP4) | |
af41a12f TL |
378 | static inline void omap2_mcspi3_init(void) |
379 | { | |
380 | platform_device_register(&omap2_mcspi3); | |
381 | } | |
382 | #else | |
383 | static inline void omap2_mcspi3_init(void) | |
384 | { | |
385 | } | |
646e3ed1 | 386 | #endif |
af41a12f | 387 | |
7869c0b9 | 388 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
af41a12f TL |
389 | static inline void omap2_mcspi4_init(void) |
390 | { | |
391 | platform_device_register(&omap2_mcspi4); | |
392 | } | |
393 | #else | |
394 | static inline void omap2_mcspi4_init(void) | |
395 | { | |
396 | } | |
646e3ed1 | 397 | #endif |
af41a12f TL |
398 | |
399 | static void omap_init_mcspi(void) | |
400 | { | |
401 | if (cpu_is_omap44xx()) | |
402 | omap4_mcspi_fixup(); | |
403 | ||
404 | platform_device_register(&omap2_mcspi1); | |
405 | platform_device_register(&omap2_mcspi2); | |
406 | ||
407 | if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) | |
408 | omap2_mcspi3_init(); | |
409 | ||
410 | if (cpu_is_omap343x() || cpu_is_omap44xx()) | |
411 | omap2_mcspi4_init(); | |
ed7eb9d9 JY |
412 | } |
413 | ||
414 | #else | |
415 | static inline void omap_init_mcspi(void) {} | |
416 | #endif | |
417 | ||
646e3ed1 TL |
418 | #ifdef CONFIG_OMAP_SHA1_MD5 |
419 | static struct resource sha1_md5_resources[] = { | |
420 | { | |
421 | .start = OMAP24XX_SEC_SHA1MD5_BASE, | |
422 | .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64, | |
423 | .flags = IORESOURCE_MEM, | |
424 | }, | |
425 | { | |
426 | .start = INT_24XX_SHA1MD5, | |
427 | .flags = IORESOURCE_IRQ, | |
428 | } | |
429 | }; | |
430 | ||
431 | static struct platform_device sha1_md5_device = { | |
432 | .name = "OMAP SHA1/MD5", | |
433 | .id = -1, | |
434 | .num_resources = ARRAY_SIZE(sha1_md5_resources), | |
435 | .resource = sha1_md5_resources, | |
436 | }; | |
437 | ||
438 | static void omap_init_sha1_md5(void) | |
439 | { | |
440 | platform_device_register(&sha1_md5_device); | |
441 | } | |
442 | #else | |
443 | static inline void omap_init_sha1_md5(void) { } | |
444 | #endif | |
445 | ||
d8874665 TL |
446 | /*-------------------------------------------------------------------------*/ |
447 | ||
82cf818d | 448 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
917fa280 KH |
449 | |
450 | #define MMCHS_SYSCONFIG 0x0010 | |
451 | #define MMCHS_SYSCONFIG_SWRESET (1 << 1) | |
452 | #define MMCHS_SYSSTATUS 0x0014 | |
453 | #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) | |
454 | ||
455 | static struct platform_device dummy_pdev = { | |
456 | .dev = { | |
457 | .bus = &platform_bus_type, | |
458 | }, | |
459 | }; | |
460 | ||
461 | /** | |
462 | * omap_hsmmc_reset() - Full reset of each HS-MMC controller | |
463 | * | |
464 | * Ensure that each MMC controller is fully reset. Controllers | |
465 | * left in an unknown state (by bootloader) may prevent retention | |
466 | * or OFF-mode. This is especially important in cases where the | |
467 | * MMC driver is not enabled, _or_ built as a module. | |
468 | * | |
469 | * In order for reset to work, interface, functional and debounce | |
470 | * clocks must be enabled. The debounce clock comes from func_32k_clk | |
471 | * and is not under SW control, so we only enable i- and f-clocks. | |
472 | **/ | |
473 | static void __init omap_hsmmc_reset(void) | |
474 | { | |
82cf818d | 475 | u32 i, nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : |
476 | (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); | |
917fa280 KH |
477 | |
478 | for (i = 0; i < nr_controllers; i++) { | |
479 | u32 v, base = 0; | |
480 | struct clk *iclk, *fclk; | |
481 | struct device *dev = &dummy_pdev.dev; | |
482 | ||
483 | switch (i) { | |
484 | case 0: | |
485 | base = OMAP2_MMC1_BASE; | |
486 | break; | |
487 | case 1: | |
488 | base = OMAP2_MMC2_BASE; | |
489 | break; | |
490 | case 2: | |
491 | base = OMAP3_MMC3_BASE; | |
492 | break; | |
82cf818d | 493 | case 3: |
494 | if (!cpu_is_omap44xx()) | |
495 | return; | |
496 | base = OMAP4_MMC4_BASE; | |
497 | break; | |
498 | case 4: | |
499 | if (!cpu_is_omap44xx()) | |
500 | return; | |
501 | base = OMAP4_MMC5_BASE; | |
502 | break; | |
917fa280 KH |
503 | } |
504 | ||
82cf818d | 505 | if (cpu_is_omap44xx()) |
506 | base += OMAP4_MMC_REG_OFFSET; | |
507 | ||
917fa280 | 508 | dummy_pdev.id = i; |
1e98ffa8 | 509 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
6f7607cc | 510 | iclk = clk_get(dev, "ick"); |
917fa280 KH |
511 | if (iclk && clk_enable(iclk)) |
512 | iclk = NULL; | |
513 | ||
6f7607cc | 514 | fclk = clk_get(dev, "fck"); |
917fa280 KH |
515 | if (fclk && clk_enable(fclk)) |
516 | fclk = NULL; | |
517 | ||
518 | if (!iclk || !fclk) { | |
519 | printk(KERN_WARNING | |
520 | "%s: Unable to enable clocks for MMC%d, " | |
521 | "cannot reset.\n", __func__, i); | |
522 | break; | |
523 | } | |
524 | ||
525 | omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); | |
526 | v = omap_readl(base + MMCHS_SYSSTATUS); | |
527 | while (!(omap_readl(base + MMCHS_SYSSTATUS) & | |
528 | MMCHS_SYSSTATUS_RESETDONE)) | |
529 | cpu_relax(); | |
530 | ||
531 | if (fclk) { | |
532 | clk_disable(fclk); | |
533 | clk_put(fclk); | |
534 | } | |
535 | if (iclk) { | |
536 | clk_disable(iclk); | |
537 | clk_put(iclk); | |
538 | } | |
539 | } | |
540 | } | |
541 | #else | |
542 | static inline void omap_hsmmc_reset(void) {} | |
543 | #endif | |
544 | ||
d8874665 TL |
545 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
546 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | |
547 | ||
548 | static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, | |
549 | int controller_nr) | |
550 | { | |
551 | if (cpu_is_omap2420() && controller_nr == 0) { | |
552 | omap_cfg_reg(H18_24XX_MMC_CMD); | |
553 | omap_cfg_reg(H15_24XX_MMC_CLKI); | |
554 | omap_cfg_reg(G19_24XX_MMC_CLKO); | |
555 | omap_cfg_reg(F20_24XX_MMC_DAT0); | |
556 | omap_cfg_reg(F19_24XX_MMC_DAT_DIR0); | |
557 | omap_cfg_reg(G18_24XX_MMC_CMD_DIR); | |
90c62bf0 | 558 | if (mmc_controller->slots[0].wires == 4) { |
d8874665 TL |
559 | omap_cfg_reg(H14_24XX_MMC_DAT1); |
560 | omap_cfg_reg(E19_24XX_MMC_DAT2); | |
561 | omap_cfg_reg(D19_24XX_MMC_DAT3); | |
562 | omap_cfg_reg(E20_24XX_MMC_DAT_DIR1); | |
563 | omap_cfg_reg(F18_24XX_MMC_DAT_DIR2); | |
564 | omap_cfg_reg(E18_24XX_MMC_DAT_DIR3); | |
565 | } | |
566 | ||
567 | /* | |
568 | * Use internal loop-back in MMC/SDIO Module Input Clock | |
569 | * selection | |
570 | */ | |
571 | if (mmc_controller->slots[0].internal_clock) { | |
572 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
573 | v |= (1 << 24); | |
574 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | |
575 | } | |
576 | } | |
57b9daa0 VP |
577 | |
578 | if (cpu_is_omap3430()) { | |
579 | if (controller_nr == 0) { | |
580 | omap_cfg_reg(N28_3430_MMC1_CLK); | |
581 | omap_cfg_reg(M27_3430_MMC1_CMD); | |
582 | omap_cfg_reg(N27_3430_MMC1_DAT0); | |
583 | if (mmc_controller->slots[0].wires == 4 || | |
584 | mmc_controller->slots[0].wires == 8) { | |
585 | omap_cfg_reg(N26_3430_MMC1_DAT1); | |
586 | omap_cfg_reg(N25_3430_MMC1_DAT2); | |
587 | omap_cfg_reg(P28_3430_MMC1_DAT3); | |
588 | } | |
589 | if (mmc_controller->slots[0].wires == 8) { | |
590 | omap_cfg_reg(P27_3430_MMC1_DAT4); | |
591 | omap_cfg_reg(P26_3430_MMC1_DAT5); | |
592 | omap_cfg_reg(R27_3430_MMC1_DAT6); | |
593 | omap_cfg_reg(R25_3430_MMC1_DAT7); | |
594 | } | |
595 | } | |
596 | if (controller_nr == 1) { | |
597 | /* MMC2 */ | |
598 | omap_cfg_reg(AE2_3430_MMC2_CLK); | |
599 | omap_cfg_reg(AG5_3430_MMC2_CMD); | |
600 | omap_cfg_reg(AH5_3430_MMC2_DAT0); | |
601 | ||
602 | /* | |
603 | * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed | |
604 | * in the board-*.c files | |
605 | */ | |
606 | if (mmc_controller->slots[0].wires == 4 || | |
607 | mmc_controller->slots[0].wires == 8) { | |
608 | omap_cfg_reg(AH4_3430_MMC2_DAT1); | |
609 | omap_cfg_reg(AG4_3430_MMC2_DAT2); | |
610 | omap_cfg_reg(AF4_3430_MMC2_DAT3); | |
611 | } | |
612 | } | |
613 | ||
614 | /* | |
615 | * For MMC3 the pins need to be muxed in the board-*.c files | |
616 | */ | |
617 | } | |
d8874665 TL |
618 | } |
619 | ||
620 | void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |
621 | int nr_controllers) | |
622 | { | |
623 | int i; | |
0dffb5c5 | 624 | char *name; |
d8874665 TL |
625 | |
626 | for (i = 0; i < nr_controllers; i++) { | |
627 | unsigned long base, size; | |
628 | unsigned int irq = 0; | |
629 | ||
630 | if (!mmc_data[i]) | |
631 | continue; | |
632 | ||
633 | omap2_mmc_mux(mmc_data[i], i); | |
634 | ||
635 | switch (i) { | |
636 | case 0: | |
637 | base = OMAP2_MMC1_BASE; | |
638 | irq = INT_24XX_MMC_IRQ; | |
639 | break; | |
640 | case 1: | |
641 | base = OMAP2_MMC2_BASE; | |
642 | irq = INT_24XX_MMC2_IRQ; | |
643 | break; | |
644 | case 2: | |
82cf818d | 645 | if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) |
d8874665 TL |
646 | return; |
647 | base = OMAP3_MMC3_BASE; | |
648 | irq = INT_34XX_MMC3_IRQ; | |
649 | break; | |
82cf818d | 650 | case 3: |
651 | if (!cpu_is_omap44xx()) | |
652 | return; | |
653 | base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; | |
654 | irq = INT_44XX_MMC4_IRQ; | |
655 | break; | |
656 | case 4: | |
657 | if (!cpu_is_omap44xx()) | |
658 | return; | |
659 | base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; | |
660 | irq = INT_44XX_MMC5_IRQ; | |
661 | break; | |
d8874665 TL |
662 | default: |
663 | continue; | |
664 | } | |
665 | ||
0dffb5c5 | 666 | if (cpu_is_omap2420()) { |
d8874665 | 667 | size = OMAP2420_MMC_SIZE; |
0dffb5c5 | 668 | name = "mmci-omap"; |
82cf818d | 669 | } else if (cpu_is_omap44xx()) { |
670 | if (i < 3) { | |
671 | base += OMAP4_MMC_REG_OFFSET; | |
672 | irq += IRQ_GIC_START; | |
673 | } | |
674 | size = OMAP4_HSMMC_SIZE; | |
675 | name = "mmci-omap-hs"; | |
0dffb5c5 | 676 | } else { |
82cf818d | 677 | size = OMAP3_HSMMC_SIZE; |
0dffb5c5 TL |
678 | name = "mmci-omap-hs"; |
679 | } | |
680 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | |
d8874665 TL |
681 | }; |
682 | } | |
683 | ||
684 | #endif | |
685 | ||
686 | /*-------------------------------------------------------------------------*/ | |
687 | ||
646e3ed1 TL |
688 | #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) |
689 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) | |
690 | #define OMAP_HDQ_BASE 0x480B2000 | |
691 | #endif | |
692 | static struct resource omap_hdq_resources[] = { | |
693 | { | |
694 | .start = OMAP_HDQ_BASE, | |
695 | .end = OMAP_HDQ_BASE + 0x1C, | |
696 | .flags = IORESOURCE_MEM, | |
697 | }, | |
698 | { | |
699 | .start = INT_24XX_HDQ_IRQ, | |
700 | .flags = IORESOURCE_IRQ, | |
701 | }, | |
702 | }; | |
703 | static struct platform_device omap_hdq_dev = { | |
704 | .name = "omap_hdq", | |
705 | .id = 0, | |
706 | .dev = { | |
707 | .platform_data = NULL, | |
708 | }, | |
709 | .num_resources = ARRAY_SIZE(omap_hdq_resources), | |
710 | .resource = omap_hdq_resources, | |
711 | }; | |
712 | static inline void omap_hdq_init(void) | |
713 | { | |
714 | (void) platform_device_register(&omap_hdq_dev); | |
715 | } | |
716 | #else | |
717 | static inline void omap_hdq_init(void) {} | |
718 | #endif | |
719 | ||
1dbae815 TL |
720 | /*-------------------------------------------------------------------------*/ |
721 | ||
722 | static int __init omap2_init_devices(void) | |
723 | { | |
724 | /* please keep these calls, and their implementations above, | |
725 | * in alphabetical order so they're easier to sort through. | |
726 | */ | |
917fa280 | 727 | omap_hsmmc_reset(); |
828c707e | 728 | omap_init_camera(); |
c40fae95 | 729 | omap_init_mbox(); |
ed7eb9d9 | 730 | omap_init_mcspi(); |
646e3ed1 | 731 | omap_hdq_init(); |
9b6553cd | 732 | omap_init_sti(); |
646e3ed1 | 733 | omap_init_sha1_md5(); |
1dbae815 TL |
734 | |
735 | return 0; | |
736 | } | |
737 | arch_initcall(omap2_init_devices); |