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Commit | Line | Data |
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97f67898 RN |
1 | /* |
2 | * OMAP4-specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Rajendra Nayak | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/bitops.h> | |
17 | ||
97f67898 | 18 | #include "clock.h" |
97f67898 | 19 | |
3ff51ed8 JH |
20 | /* |
21 | * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that | |
22 | * can supported when using the DPLL low-power mode. Frequencies are | |
23 | * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, | |
24 | * Status, and Low-Power Operation Mode". | |
25 | */ | |
26 | #define OMAP4_DPLL_LP_FINT_MAX 1000000 | |
27 | #define OMAP4_DPLL_LP_FOUT_MAX 100000000 | |
28 | ||
44b65e76 TK |
29 | /* |
30 | * Bitfield declarations | |
31 | */ | |
32 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | |
33 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) | |
34 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) | |
35 | ||
36 | /* Static rate multiplier for OMAP4 REGM4XEN clocks */ | |
37 | #define OMAP4430_REGM4XEN_MULT 4 | |
38 | ||
32cc0021 | 39 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
40 | { |
41 | u32 v; | |
42 | u32 mask; | |
43 | ||
74b9b62b | 44 | if (!clk || !clk->clksel_reg) |
97f67898 RN |
45 | return; |
46 | ||
47 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
48 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
49 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
50 | ||
519ab8b2 | 51 | v = omap2_clk_readl(clk, clk->clksel_reg); |
97f67898 RN |
52 | /* Clear the bit to allow gatectrl */ |
53 | v &= ~mask; | |
519ab8b2 | 54 | omap2_clk_writel(v, clk, clk->clksel_reg); |
97f67898 RN |
55 | } |
56 | ||
32cc0021 | 57 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
58 | { |
59 | u32 v; | |
60 | u32 mask; | |
61 | ||
74b9b62b | 62 | if (!clk || !clk->clksel_reg) |
97f67898 RN |
63 | return; |
64 | ||
65 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
66 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
67 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
68 | ||
519ab8b2 | 69 | v = omap2_clk_readl(clk, clk->clksel_reg); |
97f67898 RN |
70 | /* Set the bit to deny gatectrl */ |
71 | v |= mask; | |
519ab8b2 | 72 | omap2_clk_writel(v, clk, clk->clksel_reg); |
97f67898 | 73 | } |
70db8a62 | 74 | |
32cc0021 MT |
75 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { |
76 | .allow_idle = omap4_dpllmx_allow_gatectrl, | |
77 | .deny_idle = omap4_dpllmx_deny_gatectrl, | |
78 | }; | |
70db8a62 | 79 | |
3ff51ed8 JH |
80 | /** |
81 | * omap4_dpll_lpmode_recalc - compute DPLL low-power setting | |
82 | * @dd: pointer to the dpll data structure | |
83 | * | |
84 | * Calculates if low-power mode can be enabled based upon the last | |
85 | * multiplier and divider values calculated. If low-power mode can be | |
86 | * enabled, then the bit to enable low-power mode is stored in the | |
87 | * last_rounded_lpmode variable. This implementation is based upon the | |
88 | * criteria for enabling low-power mode as described in the OMAP4430/60 | |
89 | * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power | |
90 | * Operation Mode". | |
91 | */ | |
92 | static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) | |
93 | { | |
94 | long fint, fout; | |
95 | ||
96 | fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); | |
97 | fout = fint * dd->last_rounded_m; | |
98 | ||
99 | if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) | |
100 | dd->last_rounded_lpmode = 1; | |
101 | else | |
102 | dd->last_rounded_lpmode = 0; | |
103 | } | |
104 | ||
a1900f2e MT |
105 | /** |
106 | * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit | |
107 | * @clk: struct clk * of the DPLL to compute the rate for | |
108 | * | |
109 | * Compute the output rate for the OMAP4 DPLL represented by @clk. | |
110 | * Takes the REGM4XEN bit into consideration, which is needed for the | |
111 | * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) | |
112 | * upon success, or 0 upon error. | |
113 | */ | |
32cc0021 MT |
114 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
115 | unsigned long parent_rate) | |
116 | { | |
117 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
118 | u32 v; |
119 | unsigned long rate; | |
120 | struct dpll_data *dd; | |
121 | ||
122 | if (!clk || !clk->dpll_data) | |
123 | return 0; | |
124 | ||
125 | dd = clk->dpll_data; | |
126 | ||
127 | rate = omap2_get_dpll_rate(clk); | |
128 | ||
129 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | |
519ab8b2 | 130 | v = omap2_clk_readl(clk, dd->control_reg); |
a1900f2e MT |
131 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) |
132 | rate *= OMAP4430_REGM4XEN_MULT; | |
133 | ||
134 | return rate; | |
135 | } | |
136 | ||
137 | /** | |
138 | * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit | |
139 | * @clk: struct clk * of the DPLL to round a rate for | |
140 | * @target_rate: the desired rate of the DPLL | |
141 | * | |
142 | * Compute the rate that would be programmed into the DPLL hardware | |
143 | * for @clk if set_rate() were to be provided with the rate | |
144 | * @target_rate. Takes the REGM4XEN bit into consideration, which is | |
145 | * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before | |
146 | * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or | |
147 | * ~0 if an error occurred in omap2_dpll_round_rate(). | |
148 | */ | |
32cc0021 MT |
149 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
150 | unsigned long target_rate, | |
151 | unsigned long *parent_rate) | |
152 | { | |
153 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
154 | struct dpll_data *dd; |
155 | long r; | |
156 | ||
157 | if (!clk || !clk->dpll_data) | |
158 | return -EINVAL; | |
159 | ||
160 | dd = clk->dpll_data; | |
161 | ||
3ff51ed8 | 162 | dd->last_rounded_m4xen = 0; |
a1900f2e | 163 | |
3ff51ed8 JH |
164 | /* |
165 | * First try to compute the DPLL configuration for | |
166 | * target rate without using the 4X multiplier. | |
167 | */ | |
32cc0021 | 168 | r = omap2_dpll_round_rate(hw, target_rate, NULL); |
3ff51ed8 JH |
169 | if (r != ~0) |
170 | goto out; | |
171 | ||
172 | /* | |
173 | * If we did not find a valid DPLL configuration, try again, but | |
174 | * this time see if using the 4X multiplier can help. Enabling the | |
175 | * 4X multiplier is equivalent to dividing the target rate by 4. | |
176 | */ | |
177 | r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, | |
178 | NULL); | |
a1900f2e MT |
179 | if (r == ~0) |
180 | return r; | |
181 | ||
3ff51ed8 JH |
182 | dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; |
183 | dd->last_rounded_m4xen = 1; | |
184 | ||
185 | out: | |
186 | omap4_dpll_lpmode_recalc(dd); | |
a1900f2e | 187 | |
3ff51ed8 | 188 | return dd->last_rounded_rate; |
a1900f2e | 189 | } |
83501ff0 TK |
190 | |
191 | /** | |
192 | * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL | |
193 | * @hw: pointer to the clock to determine rate for | |
0817b62c | 194 | * @req: target rate request |
83501ff0 TK |
195 | * |
196 | * Determines which DPLL mode to use for reaching a desired rate. | |
197 | * Checks whether the DPLL shall be in bypass or locked mode, and if | |
198 | * locked, calculates the M,N values for the DPLL via round-rate. | |
0817b62c | 199 | * Returns 0 on success and a negative error value otherwise. |
83501ff0 | 200 | */ |
0817b62c BB |
201 | int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, |
202 | struct clk_rate_request *req) | |
83501ff0 TK |
203 | { |
204 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
205 | struct dpll_data *dd; | |
206 | ||
0817b62c | 207 | if (!req->rate) |
83501ff0 TK |
208 | return -EINVAL; |
209 | ||
210 | dd = clk->dpll_data; | |
211 | if (!dd) | |
212 | return -EINVAL; | |
213 | ||
0817b62c | 214 | if (__clk_get_rate(dd->clk_bypass) == req->rate && |
83501ff0 | 215 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
0817b62c | 216 | req->best_parent_hw = __clk_get_hw(dd->clk_bypass); |
83501ff0 | 217 | } else { |
0817b62c BB |
218 | req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate, |
219 | &req->best_parent_rate); | |
220 | req->best_parent_hw = __clk_get_hw(dd->clk_ref); | |
83501ff0 TK |
221 | } |
222 | ||
0817b62c | 223 | req->best_parent_rate = req->rate; |
83501ff0 | 224 | |
0817b62c | 225 | return 0; |
83501ff0 | 226 | } |