[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / gpmc-onenand.c

/*
 * linux/arch/arm/mach-omap2/gpmc-onenand.c
 *
 * Copyright (C) 2006 - 2009 Nokia Corporation
 * Contacts:	Juha Yrjola
 *		Tony Lindgren
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/onenand_regs.h>
#include <linux/io.h>
#include <linux/platform_data/mtd-onenand-omap2.h>
#include <linux/err.h>

#include <asm/mach/flash.h>

#include "gpmc.h"
#include "soc.h"
#include "gpmc-onenand.h"

#define	ONENAND_IO_SIZE	SZ_128K

#define	ONENAND_FLAG_SYNCREAD	(1 << 0)
#define	ONENAND_FLAG_SYNCWRITE	(1 << 1)
#define	ONENAND_FLAG_HF		(1 << 2)
#define	ONENAND_FLAG_VHF	(1 << 3)

static unsigned onenand_flags;
static unsigned latency;

static struct omap_onenand_platform_data *gpmc_onenand_data;

static struct resource gpmc_onenand_resource = {
	.flags		= IORESOURCE_MEM,
};

static struct platform_device gpmc_onenand_device = {
	.name		= "omap2-onenand",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &gpmc_onenand_resource,
};

static struct gpmc_settings onenand_async = {
	.device_width	= GPMC_DEVWIDTH_16BIT,
	.mux_add_data	= GPMC_MUX_AD,
};

static struct gpmc_settings onenand_sync = {
	.burst_read	= true,
	.burst_wrap	= true,
	.burst_len	= GPMC_BURST_16,
	.device_width	= GPMC_DEVWIDTH_16BIT,
	.mux_add_data	= GPMC_MUX_AD,
	.wait_pin	= 0,
};

static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
{
	struct gpmc_device_timings dev_t;
	const int t_cer = 15;
	const int t_avdp = 12;
	const int t_aavdh = 7;
	const int t_ce = 76;
	const int t_aa = 76;
	const int t_oe = 20;
	const int t_cez = 20; /* max of t_cez, t_oez */
	const int t_wpl = 40;
	const int t_wph = 30;

	memset(&dev_t, 0, sizeof(dev_t));

	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
	dev_t.t_avdp_w = dev_t.t_avdp_r;
	dev_t.t_aavdh = t_aavdh * 1000;
	dev_t.t_aa = t_aa * 1000;
	dev_t.t_ce = t_ce * 1000;
	dev_t.t_oe = t_oe * 1000;
	dev_t.t_cez_r = t_cez * 1000;
	dev_t.t_cez_w = dev_t.t_cez_r;
	dev_t.t_wpl = t_wpl * 1000;
	dev_t.t_wph = t_wph * 1000;

	gpmc_calc_timings(t, &onenand_async, &dev_t);
}

static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
{
	u32 reg;

	/* Ensure sync read and sync write are disabled */
	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}

static void set_onenand_cfg(void __iomem *onenand_base)
{
	u32 reg;

	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
	reg |=	(latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
		ONENAND_SYS_CFG1_BL_16;
	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
		reg |= ONENAND_SYS_CFG1_SYNC_READ;
	else
		reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
		reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
	else
		reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
	if (onenand_flags & ONENAND_FLAG_HF)
		reg |= ONENAND_SYS_CFG1_HF;
	else
		reg &= ~ONENAND_SYS_CFG1_HF;
	if (onenand_flags & ONENAND_FLAG_VHF)
		reg |= ONENAND_SYS_CFG1_VHF;
	else
		reg &= ~ONENAND_SYS_CFG1_VHF;
	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
}

static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
				  void __iomem *onenand_base)
{
	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
	int freq;

	switch ((ver >> 4) & 0xf) {
	case 0:
		freq = 40;
		break;
	case 1:
		freq = 54;
		break;
	case 2:
		freq = 66;
		break;
	case 3:
		freq = 83;
		break;
	case 4:
		freq = 104;
		break;
	default:
		freq = 54;
		break;
	}

	return freq;
}

static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
					    unsigned int flags,
					    int freq)
{
	struct gpmc_device_timings dev_t;
	const int t_cer  = 15;
	const int t_avdp = 12;
	const int t_cez  = 20; /* max of t_cez, t_oez */
	const int t_wpl  = 40;
	const int t_wph  = 30;
	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
	int div, gpmc_clk_ns;

	if (flags & ONENAND_SYNC_READ)
		onenand_flags = ONENAND_FLAG_SYNCREAD;
	else if (flags & ONENAND_SYNC_READWRITE)
		onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;

	switch (freq) {
	case 104:
		min_gpmc_clk_period = 9600; /* 104 MHz */
		t_ces   = 3;
		t_avds  = 4;
		t_avdh  = 2;
		t_ach   = 3;
		t_aavdh = 6;
		t_rdyo  = 6;
		break;
	case 83:
		min_gpmc_clk_period = 12000; /* 83 MHz */
		t_ces   = 5;
		t_avds  = 4;
		t_avdh  = 2;
		t_ach   = 6;
		t_aavdh = 6;
		t_rdyo  = 9;
		break;
	case 66:
		min_gpmc_clk_period = 15000; /* 66 MHz */
		t_ces   = 6;
		t_avds  = 5;
		t_avdh  = 2;
		t_ach   = 6;
		t_aavdh = 6;
		t_rdyo  = 11;
		break;
	default:
		min_gpmc_clk_period = 18500; /* 54 MHz */
		t_ces   = 7;
		t_avds  = 7;
		t_avdh  = 7;
		t_ach   = 9;
		t_aavdh = 7;
		t_rdyo  = 15;
		onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
		break;
	}

	div = gpmc_calc_divider(min_gpmc_clk_period);
	gpmc_clk_ns = gpmc_ticks_to_ns(div);
	if (gpmc_clk_ns < 15) /* >66Mhz */
		onenand_flags |= ONENAND_FLAG_HF;
	else
		onenand_flags &= ~ONENAND_FLAG_HF;
	if (gpmc_clk_ns < 12) /* >83Mhz */
		onenand_flags |= ONENAND_FLAG_VHF;
	else
		onenand_flags &= ~ONENAND_FLAG_VHF;
	if (onenand_flags & ONENAND_FLAG_VHF)
		latency = 8;
	else if (onenand_flags & ONENAND_FLAG_HF)
		latency = 6;
	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
		latency = 3;
	else
		latency = 4;

	/* Set synchronous read timings */
	memset(&dev_t, 0, sizeof(dev_t));

	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
		onenand_sync.sync_read = true;
	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
		onenand_sync.sync_write = true;
		onenand_sync.burst_write = true;
	} else {
		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
		dev_t.t_wpl = t_wpl * 1000;
		dev_t.t_wph = t_wph * 1000;
		dev_t.t_aavdh = t_aavdh * 1000;
	}
	dev_t.ce_xdelay = true;
	dev_t.avd_xdelay = true;
	dev_t.oe_xdelay = true;
	dev_t.we_xdelay = true;
	dev_t.clk = min_gpmc_clk_period;
	dev_t.t_bacc = dev_t.clk;
	dev_t.t_ces = t_ces * 1000;
	dev_t.t_avds = t_avds * 1000;
	dev_t.t_avdh = t_avdh * 1000;
	dev_t.t_ach = t_ach * 1000;
	dev_t.cyc_iaa = (latency + 1);
	dev_t.t_cez_r = t_cez * 1000;
	dev_t.t_cez_w = dev_t.t_cez_r;
	dev_t.cyc_aavdh_oe = 1;
	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;

	gpmc_calc_timings(t, &onenand_sync, &dev_t);
}

static int omap2_onenand_setup_async(void __iomem *onenand_base)
{
	struct gpmc_timings t;
	int ret;

	if (gpmc_onenand_data->of_node) {
		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
				      &onenand_async);
		if (onenand_async.sync_read || onenand_async.sync_write) {
			if (onenand_async.sync_write)
				gpmc_onenand_data->flags |=
					ONENAND_SYNC_READWRITE;
			else
				gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
			onenand_async.sync_read = false;
			onenand_async.sync_write = false;
		}
	}

	omap2_onenand_set_async_mode(onenand_base);

	omap2_onenand_calc_async_timings(&t);

	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
	if (ret < 0)
		return ret;

	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
	if (ret < 0)
		return ret;

	omap2_onenand_set_async_mode(onenand_base);

	return 0;
}

static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
{
	int ret, freq = *freq_ptr;
	struct gpmc_timings t;

	if (!freq) {
		/* Very first call freq is not known */
		freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
		set_onenand_cfg(onenand_base);
	}

	if (gpmc_onenand_data->of_node) {
		gpmc_read_settings_dt(gpmc_onenand_data->of_node,
				      &onenand_sync);
	} else {
		/*
		 * FIXME: Appears to be legacy code from initial ONENAND commit.
		 * Unclear what boards this is for and if this can be removed.
		 */
		if (!cpu_is_omap34xx())
			onenand_sync.wait_on_read = true;
	}

	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);

	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
	if (ret < 0)
		return ret;

	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
	if (ret < 0)
		return ret;

	set_onenand_cfg(onenand_base);

	*freq_ptr = freq;

	return 0;
}

static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
{
	struct device *dev = &gpmc_onenand_device.dev;
	unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
	int ret;

	ret = omap2_onenand_setup_async(onenand_base);
	if (ret) {
		dev_err(dev, "unable to set to async mode\n");
		return ret;
	}

	if (!(gpmc_onenand_data->flags & l))
		return 0;

	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
	if (ret)
		dev_err(dev, "unable to set to sync mode\n");
	return ret;
}

void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
{
	int err;
	struct device *dev = &gpmc_onenand_device.dev;

	gpmc_onenand_data = _onenand_data;
	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;

	if (cpu_is_omap24xx() &&
			(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
		dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
		gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
		gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
	}

	if (cpu_is_omap34xx())
		gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
	else
		gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;

	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
				(unsigned long *)&gpmc_onenand_resource.start);
	if (err < 0) {
		dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
			gpmc_onenand_data->cs, err);
		return;
	}

	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
							ONENAND_IO_SIZE - 1;

	if (platform_device_register(&gpmc_onenand_device) < 0) {
		dev_err(dev, "Unable to register OneNAND device\n");
		gpmc_cs_free(gpmc_onenand_data->cs);
		return;
	}
}
Commit	Line	Data
aa62e90f JY	1	/*
	2	* linux/arch/arm/mach-omap2/gpmc-onenand.c
	3	*
	4	* Copyright (C) 2006 - 2009 Nokia Corporation
	5	* Contacts: Juha Yrjola
	6	* Tony Lindgren
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
d44b28c4	13	#include <linux/string.h>
aa62e90f JY	14	#include <linux/kernel.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/mtd/onenand_regs.h>
	17	#include <linux/io.h>
2203747c	18	#include <linux/platform_data/mtd-onenand-omap2.h>
46376884	19	#include <linux/err.h>
aa62e90f JY	20
	21	#include <asm/mach/flash.h>
	22
3ef5d007	23	#include "gpmc.h"
dbc04161	24	#include "soc.h"
b6ab13e7	25	#include "gpmc-onenand.h"
dbc04161	26
681988ba AM	27	#define ONENAND_IO_SIZE SZ_128K
681988ba AM	28
46376884 AM	29	#define ONENAND_FLAG_SYNCREAD (1 << 0)
	30	#define ONENAND_FLAG_SYNCWRITE (1 << 1)
	31	#define ONENAND_FLAG_HF (1 << 2)
	32	#define ONENAND_FLAG_VHF (1 << 3)
	33
	34	static unsigned onenand_flags;
	35	static unsigned latency;
46376884	36
aa62e90f JY	37	static struct omap_onenand_platform_data *gpmc_onenand_data;
aa62e90f JY	38
681988ba AM	39	static struct resource gpmc_onenand_resource = {
	40	.flags = IORESOURCE_MEM,
	41	};
	42
aa62e90f JY	43	static struct platform_device gpmc_onenand_device = {
	44	.name = "omap2-onenand",
	45	.id = -1,
681988ba AM	46	.num_resources = 1,
681988ba AM	47	.resource = &gpmc_onenand_resource,
aa62e90f JY	48	};
aa62e90f JY	49
c3be5b45	50	static struct gpmc_settings onenand_async = {
3aef65ee	51	.device_width = GPMC_DEVWIDTH_16BIT,
c3be5b45 JH	52	.mux_add_data = GPMC_MUX_AD,
	53	};
	54
	55	static struct gpmc_settings onenand_sync = {
	56	.burst_read = true,
3aef65ee JH	57	.burst_wrap = true,
	58	.burst_len = GPMC_BURST_16,
	59	.device_width = GPMC_DEVWIDTH_16BIT,
c3be5b45	60	.mux_add_data = GPMC_MUX_AD,
3aef65ee	61	.wait_pin = 0,
c3be5b45 JH	62	};
c3be5b45 JH	63
be9f10c0	64	static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
aa62e90f	65	{
4f4426f9	66	struct gpmc_device_timings dev_t;
aa62e90f JY	67	const int t_cer = 15;
	68	const int t_avdp = 12;
	69	const int t_aavdh = 7;
	70	const int t_ce = 76;
	71	const int t_aa = 76;
	72	const int t_oe = 20;
	73	const int t_cez = 20; /* max of t_cez, t_oez */
aa62e90f JY	74	const int t_wpl = 40;
	75	const int t_wph = 30;
	76
4f4426f9 AM	77	memset(&dev_t, 0, sizeof(dev_t));
4f4426f9 AM	78
4f4426f9 AM	79	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
	80	dev_t.t_avdp_w = dev_t.t_avdp_r;
	81	dev_t.t_aavdh = t_aavdh * 1000;
	82	dev_t.t_aa = t_aa * 1000;
	83	dev_t.t_ce = t_ce * 1000;
	84	dev_t.t_oe = t_oe * 1000;
	85	dev_t.t_cez_r = t_cez * 1000;
	86	dev_t.t_cez_w = dev_t.t_cez_r;
	87	dev_t.t_wpl = t_wpl * 1000;
	88	dev_t.t_wph = t_wph * 1000;
	89
c3be5b45	90	gpmc_calc_timings(t, &onenand_async, &dev_t);
46376884 AM	91	}
46376884 AM	92
46376884 AM	93	static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
	94	{
	95	u32 reg;
6d453e84 AH	96
	97	/* Ensure sync read and sync write are disabled */
	98	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	99	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
	100	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
aa62e90f JY	101	}
aa62e90f JY	102
46376884	103	static void set_onenand_cfg(void __iomem *onenand_base)
aa62e90f JY	104	{
	105	u32 reg;
	106
	107	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
	108	reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) \| (0x7 << 9));
	109	reg \|= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) \|
	110	ONENAND_SYS_CFG1_BL_16;
46376884	111	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
aa62e90f JY	112	reg \|= ONENAND_SYS_CFG1_SYNC_READ;
	113	else
	114	reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
46376884	115	if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
aa62e90f JY	116	reg \|= ONENAND_SYS_CFG1_SYNC_WRITE;
	117	else
	118	reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
46376884	119	if (onenand_flags & ONENAND_FLAG_HF)
aa62e90f JY	120	reg \|= ONENAND_SYS_CFG1_HF;
	121	else
	122	reg &= ~ONENAND_SYS_CFG1_HF;
46376884	123	if (onenand_flags & ONENAND_FLAG_VHF)
1435ca0f AH	124	reg \|= ONENAND_SYS_CFG1_VHF;
	125	else
	126	reg &= ~ONENAND_SYS_CFG1_VHF;
aa62e90f JY	127	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
	128	}
	129
5714b7ed	130	static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
757ef791	131	void __iomem *onenand_base)
5714b7ed AH	132	{
5714b7ed AH	133	u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
757ef791	134	int freq;
5714b7ed AH	135
	136	switch ((ver >> 4) & 0xf) {
	137	case 0:
	138	freq = 40;
	139	break;
	140	case 1:
	141	freq = 54;
	142	break;
	143	case 2:
	144	freq = 66;
	145	break;
	146	case 3:
	147	freq = 83;
	148	break;
	149	case 4:
	150	freq = 104;
	151	break;
	152	default:
	153	freq = 54;
	154	break;
	155	}
	156
	157	return freq;
	158	}
	159
be9f10c0 JH	160	static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
	161	unsigned int flags,
	162	int freq)
aa62e90f	163	{
4f4426f9	164	struct gpmc_device_timings dev_t;
aa62e90f JY	165	const int t_cer = 15;
	166	const int t_avdp = 12;
	167	const int t_cez = 20; /* max of t_cez, t_oez */
aa62e90f JY	168	const int t_wpl = 40;
	169	const int t_wph = 30;
	170	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
4f4426f9	171	int div, gpmc_clk_ns;
aa62e90f	172
be9f10c0	173	if (flags & ONENAND_SYNC_READ)
46376884	174	onenand_flags = ONENAND_FLAG_SYNCREAD;
be9f10c0	175	else if (flags & ONENAND_SYNC_READWRITE)
46376884	176	onenand_flags = ONENAND_FLAG_SYNCREAD \| ONENAND_FLAG_SYNCWRITE;
aa62e90f JY	177
aa62e90f JY	178	switch (freq) {
4931445b AH	179	case 104:
	180	min_gpmc_clk_period = 9600; /* 104 MHz */
	181	t_ces = 3;
	182	t_avds = 4;
	183	t_avdh = 2;
	184	t_ach = 3;
	185	t_aavdh = 6;
1435ca0f	186	t_rdyo = 6;
4931445b	187	break;
aa62e90f	188	case 83:
a3551f5b	189	min_gpmc_clk_period = 12000; /* 83 MHz */
aa62e90f JY	190	t_ces = 5;
	191	t_avds = 4;
	192	t_avdh = 2;
	193	t_ach = 6;
	194	t_aavdh = 6;
	195	t_rdyo = 9;
	196	break;
	197	case 66:
a3551f5b	198	min_gpmc_clk_period = 15000; /* 66 MHz */
aa62e90f JY	199	t_ces = 6;
	200	t_avds = 5;
	201	t_avdh = 2;
	202	t_ach = 6;
	203	t_aavdh = 6;
	204	t_rdyo = 11;
	205	break;
	206	default:
a3551f5b	207	min_gpmc_clk_period = 18500; /* 54 MHz */
aa62e90f JY	208	t_ces = 7;
	209	t_avds = 7;
	210	t_avdh = 7;
	211	t_ach = 9;
	212	t_aavdh = 7;
	213	t_rdyo = 15;
46376884	214	onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
aa62e90f JY	215	break;
	216	}
	217
1b47ca1a	218	div = gpmc_calc_divider(min_gpmc_clk_period);
aa62e90f JY	219	gpmc_clk_ns = gpmc_ticks_to_ns(div);
aa62e90f JY	220	if (gpmc_clk_ns < 15) /* >66Mhz */
46376884 AM	221	onenand_flags \|= ONENAND_FLAG_HF;
	222	else
	223	onenand_flags &= ~ONENAND_FLAG_HF;
1435ca0f	224	if (gpmc_clk_ns < 12) /* >83Mhz */
46376884 AM	225	onenand_flags \|= ONENAND_FLAG_VHF;
	226	else
	227	onenand_flags &= ~ONENAND_FLAG_VHF;
	228	if (onenand_flags & ONENAND_FLAG_VHF)
1435ca0f	229	latency = 8;
46376884	230	else if (onenand_flags & ONENAND_FLAG_HF)
aa62e90f JY	231	latency = 6;
	232	else if (gpmc_clk_ns >= 25) /* 40 MHz*/
	233	latency = 3;
	234	else
	235	latency = 4;
	236
46376884	237	/* Set synchronous read timings */
4f4426f9	238	memset(&dev_t, 0, sizeof(dev_t));
aa62e90f	239
3aef65ee JH	240	if (onenand_flags & ONENAND_FLAG_SYNCREAD)
3aef65ee JH	241	onenand_sync.sync_read = true;
46376884	242	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
c3be5b45	243	onenand_sync.sync_write = true;
3aef65ee	244	onenand_sync.burst_write = true;
aa62e90f	245	} else {
4f4426f9 AM	246	dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
	247	dev_t.t_wpl = t_wpl * 1000;
	248	dev_t.t_wph = t_wph * 1000;
	249	dev_t.t_aavdh = t_aavdh * 1000;
aa62e90f	250	}
4f4426f9 AM	251	dev_t.ce_xdelay = true;
	252	dev_t.avd_xdelay = true;
	253	dev_t.oe_xdelay = true;
	254	dev_t.we_xdelay = true;
	255	dev_t.clk = min_gpmc_clk_period;
	256	dev_t.t_bacc = dev_t.clk;
	257	dev_t.t_ces = t_ces * 1000;
	258	dev_t.t_avds = t_avds * 1000;
	259	dev_t.t_avdh = t_avdh * 1000;
	260	dev_t.t_ach = t_ach * 1000;
	261	dev_t.cyc_iaa = (latency + 1);
	262	dev_t.t_cez_r = t_cez * 1000;
	263	dev_t.t_cez_w = dev_t.t_cez_r;
	264	dev_t.cyc_aavdh_oe = 1;
	265	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
	266
c3be5b45	267	gpmc_calc_timings(t, &onenand_sync, &dev_t);
46376884 AM	268	}
46376884 AM	269
46376884 AM	270	static int omap2_onenand_setup_async(void __iomem *onenand_base)
	271	{
	272	struct gpmc_timings t;
	273	int ret;
	274
1dc1c338	275	if (gpmc_onenand_data->of_node) {
32cde0b5 JH	276	gpmc_read_settings_dt(gpmc_onenand_data->of_node,
32cde0b5 JH	277	&onenand_async);
1dc1c338 AK	278	if (onenand_async.sync_read \|\| onenand_async.sync_write) {
	279	if (onenand_async.sync_write)
	280	gpmc_onenand_data->flags \|=
	281	ONENAND_SYNC_READWRITE;
	282	else
	283	gpmc_onenand_data->flags \|= ONENAND_SYNC_READ;
	284	onenand_async.sync_read = false;
	285	onenand_async.sync_write = false;
	286	}
	287	}
32cde0b5	288
46376884 AM	289	omap2_onenand_set_async_mode(onenand_base);
46376884 AM	290
be9f10c0	291	omap2_onenand_calc_async_timings(&t);
46376884	292
3aef65ee JH	293	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
	294	if (ret < 0)
	295	return ret;
	296
	297	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
71856843	298	if (ret < 0)
46376884 AM	299	return ret;
	300
	301	omap2_onenand_set_async_mode(onenand_base);
	302
	303	return 0;
	304	}
	305
	306	static int omap2_onenand_setup_sync(void __iomem onenand_base, int freq_ptr)
	307	{
	308	int ret, freq = *freq_ptr;
	309	struct gpmc_timings t;
46376884 AM	310
	311	if (!freq) {
	312	/* Very first call freq is not known */
757ef791	313	freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
46376884 AM	314	set_onenand_cfg(onenand_base);
	315	}
	316
32cde0b5 JH	317	if (gpmc_onenand_data->of_node) {
	318	gpmc_read_settings_dt(gpmc_onenand_data->of_node,
	319	&onenand_sync);
	320	} else {
	321	/*
	322	* FIXME: Appears to be legacy code from initial ONENAND commit.
	323	* Unclear what boards this is for and if this can be removed.
	324	*/
	325	if (!cpu_is_omap34xx())
	326	onenand_sync.wait_on_read = true;
	327	}
3aef65ee	328
be9f10c0	329	omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
aa62e90f	330
3aef65ee JH	331	ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
	332	if (ret < 0)
	333	return ret;
	334
	335	ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
71856843	336	if (ret < 0)
46376884 AM	337	return ret;
	338
	339	set_onenand_cfg(onenand_base);
aa62e90f	340
3ad2d861 AH	341	*freq_ptr = freq;
3ad2d861 AH	342
aa62e90f JY	343	return 0;
	344	}
	345
3ad2d861	346	static int gpmc_onenand_setup(void __iomem onenand_base, int freq_ptr)
aa62e90f JY	347	{
aa62e90f JY	348	struct device *dev = &gpmc_onenand_device.dev;
46376884 AM	349	unsigned l = ONENAND_SYNC_READ \| ONENAND_SYNC_READWRITE;
46376884 AM	350	int ret;
aa62e90f	351
46376884 AM	352	ret = omap2_onenand_setup_async(onenand_base);
	353	if (ret) {
	354	dev_err(dev, "unable to set to async mode\n");
	355	return ret;
aa62e90f JY	356	}
aa62e90f JY	357
46376884 AM	358	if (!(gpmc_onenand_data->flags & l))
	359	return 0;
	360
	361	ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
	362	if (ret)
	363	dev_err(dev, "unable to set to sync mode\n");
	364	return ret;
aa62e90f JY	365	}
aa62e90f JY	366
faf5d2ff	367	void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
aa62e90f	368	{
681988ba	369	int err;
df25cb46	370	struct device *dev = &gpmc_onenand_device.dev;
681988ba	371
aa62e90f JY	372	gpmc_onenand_data = _onenand_data;
	373	gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
	374	gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
	375
	376	if (cpu_is_omap24xx() &&
	377	(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
7ab91596	378	dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
aa62e90f JY	379	gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
	380	gpmc_onenand_data->flags \|= ONENAND_SYNC_READ;
	381	}
	382
eb77b6a7 AM	383	if (cpu_is_omap34xx())
	384	gpmc_onenand_data->flags \|= ONENAND_IN_OMAP34XX;
	385	else
	386	gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
	387
681988ba AM	388	err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
	389	(unsigned long *)&gpmc_onenand_resource.start);
	390	if (err < 0) {
df25cb46 EG	391	dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
df25cb46 EG	392	gpmc_onenand_data->cs, err);
681988ba AM	393	return;
	394	}
	395
	396	gpmc_onenand_resource.end = gpmc_onenand_resource.start +
	397	ONENAND_IO_SIZE - 1;
	398
aa62e90f	399	if (platform_device_register(&gpmc_onenand_device) < 0) {
df25cb46	400	dev_err(dev, "Unable to register OneNAND device\n");
681988ba	401	gpmc_cs_free(gpmc_onenand_data->cs);
aa62e90f JY	402	return;
	403	}
	404	}