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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
1dbae815 TL |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | ||
18 | #include <asm/io.h> | |
19 | ||
a09e64fb RK |
20 | #include <mach/control.h> |
21 | #include <mach/cpu.h> | |
72d0f1c3 | 22 | |
097c584c PW |
23 | #if defined(CONFIG_ARCH_OMAP2420) |
24 | #define TAP_BASE io_p2v(0x48014000) | |
25 | #elif defined(CONFIG_ARCH_OMAP2430) | |
26 | #define TAP_BASE io_p2v(0x4900A000) | |
27 | #elif defined(CONFIG_ARCH_OMAP34XX) | |
28 | #define TAP_BASE io_p2v(0x4830A000) | |
72d0f1c3 | 29 | #endif |
1dbae815 TL |
30 | |
31 | #define OMAP_TAP_IDCODE 0x0204 | |
097c584c PW |
32 | #if defined(CONFIG_ARCH_OMAP34XX) |
33 | #define OMAP_TAP_PROD_ID 0x0210 | |
34 | #else | |
1dbae815 | 35 | #define OMAP_TAP_PROD_ID 0x0208 |
097c584c | 36 | #endif |
1dbae815 TL |
37 | |
38 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
39 | #define OMAP_TAP_DIE_ID_1 0x021C | |
40 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
41 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
42 | ||
43 | /* system_rev fields for OMAP2 processors: | |
44 | * CPU id bits [31:16], | |
45 | * CPU device type [15:12], (unprg,normal,POP) | |
46 | * CPU revision [11:08] | |
47 | * CPU class bits [07:00] | |
48 | */ | |
49 | ||
50 | struct omap_id { | |
51 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
52 | u8 dev; /* Device type from production_id reg */ | |
53 | u32 type; /* combined type id copied to system_rev */ | |
54 | }; | |
55 | ||
56 | /* Register values to detect the OMAP version */ | |
57 | static struct omap_id omap_ids[] __initdata = { | |
58 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 }, | |
59 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 }, | |
60 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 }, | |
61 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 }, | |
62 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 }, | |
63 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 }, | |
64 | }; | |
65 | ||
097c584c PW |
66 | static struct omap_chip_id omap_chip; |
67 | ||
68 | /** | |
69 | * omap_chip_is - test whether currently running OMAP matches a chip type | |
70 | * @oc: omap_chip_t to test against | |
71 | * | |
72 | * Test whether the currently-running OMAP chip matches the supplied | |
73 | * chip type 'oc'. Returns 1 upon a match; 0 upon failure. | |
74 | */ | |
75 | int omap_chip_is(struct omap_chip_id oci) | |
76 | { | |
77 | return (oci.oc & omap_chip.oc) ? 1 : 0; | |
78 | } | |
79 | EXPORT_SYMBOL(omap_chip_is); | |
80 | ||
1dbae815 TL |
81 | static u32 __init read_tap_reg(int reg) |
82 | { | |
097c584c PW |
83 | unsigned int regval = 0; |
84 | u32 cpuid; | |
85 | ||
86 | /* Reading the IDCODE register on 3430 ES1 results in a | |
87 | * data abort as the register is not exposed on the OCP | |
88 | * Hence reading the Cortex Rev | |
89 | */ | |
90 | cpuid = read_cpuid(CPUID_ID); | |
91 | ||
92 | /* If the processor type is Cortex-A8 and the revision is 0x0 | |
93 | * it means its Cortex r0p0 which is 3430 ES1 | |
94 | */ | |
95 | if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { | |
96 | switch (reg) { | |
97 | case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; | |
98 | /* Making DevType as 0xF in ES1 to differ from ES2 */ | |
99 | case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break; | |
100 | case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; | |
101 | case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; | |
102 | case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; | |
103 | case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; | |
104 | } | |
105 | } else | |
106 | regval = __raw_readl(TAP_BASE + reg); | |
107 | ||
108 | return regval; | |
109 | ||
110 | } | |
111 | ||
112 | /* | |
113 | * _set_system_rev - set the system_rev global based on current OMAP chip type | |
114 | * | |
115 | * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx() | |
116 | * macros. | |
117 | */ | |
118 | static void __init _set_system_rev(u32 type, u8 rev) | |
119 | { | |
120 | u32 i, ctrl_status; | |
121 | ||
122 | /* | |
123 | * system_rev encoding is as follows | |
124 | * system_rev & 0xff000000 -> Omap Class (24xx/34xx) | |
125 | * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x) | |
126 | * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430) | |
127 | * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 ) | |
128 | * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD ) | |
129 | * system_rev & 0x000000c0 -> IDCODE revision[6:7] | |
130 | * system_rev & 0x0000003f -> sys_boot[0:5] | |
131 | */ | |
132 | /* Embedding the ES revision info in type field */ | |
133 | system_rev = type; | |
134 | /* Also add IDCODE revision info only two lower bits */ | |
135 | system_rev |= ((rev & 0x3) << 6); | |
136 | ||
137 | /* Add in the device type and sys_boot fields (see above) */ | |
138 | if (cpu_is_omap24xx()) { | |
139 | i = OMAP24XX_CONTROL_STATUS; | |
140 | } else if (cpu_is_omap343x()) { | |
141 | i = OMAP343X_CONTROL_STATUS; | |
142 | } else { | |
143 | printk(KERN_ERR "id: unknown CPU type\n"); | |
144 | BUG(); | |
145 | } | |
146 | ctrl_status = omap_ctrl_readl(i); | |
147 | system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK | | |
148 | OMAP2_SYSBOOT_4_MASK | | |
149 | OMAP2_SYSBOOT_3_MASK | | |
150 | OMAP2_SYSBOOT_2_MASK | | |
151 | OMAP2_SYSBOOT_1_MASK | | |
152 | OMAP2_SYSBOOT_0_MASK)); | |
153 | system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK); | |
154 | } | |
155 | ||
156 | ||
157 | /* | |
158 | * _set_omap_chip - set the omap_chip global based on OMAP chip type | |
159 | * | |
160 | * Build the omap_chip bits. This variable is used by powerdomain and | |
161 | * clockdomain code to indicate whether structures are applicable for | |
162 | * the current OMAP chip type by ANDing it against a 'platform' bitfield | |
163 | * in the structure. | |
164 | */ | |
165 | static void __init _set_omap_chip(void) | |
166 | { | |
167 | if (cpu_is_omap343x()) { | |
168 | ||
169 | omap_chip.oc = CHIP_IS_OMAP3430; | |
170 | if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) | |
171 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; | |
172 | else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) | |
173 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; | |
174 | ||
175 | } else if (cpu_is_omap243x()) { | |
176 | ||
177 | /* Currently only supports 2430ES2.1 and 2430-all */ | |
178 | omap_chip.oc |= CHIP_IS_OMAP2430; | |
179 | ||
180 | } else if (cpu_is_omap242x()) { | |
181 | ||
182 | /* Currently only supports 2420ES2.1.1 and 2420-all */ | |
183 | omap_chip.oc |= CHIP_IS_OMAP2420; | |
184 | ||
185 | } else { | |
186 | ||
187 | /* Current CPU not supported by this code. */ | |
188 | printk(KERN_WARNING "OMAP chip type code does not yet support " | |
189 | "this CPU type.\n"); | |
190 | WARN_ON(1); | |
191 | ||
192 | } | |
193 | ||
1dbae815 TL |
194 | } |
195 | ||
196 | void __init omap2_check_revision(void) | |
197 | { | |
198 | int i, j; | |
199 | u32 idcode; | |
200 | u32 prod_id; | |
201 | u16 hawkeye; | |
202 | u8 dev_type; | |
203 | u8 rev; | |
204 | ||
205 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
206 | prod_id = read_tap_reg(OMAP_TAP_PROD_ID); | |
207 | hawkeye = (idcode >> 12) & 0xffff; | |
208 | rev = (idcode >> 28) & 0x0f; | |
209 | dev_type = (prod_id >> 16) & 0x0f; | |
210 | ||
097c584c PW |
211 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
212 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
213 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", | |
214 | read_tap_reg(OMAP_TAP_DIE_ID_0)); | |
215 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", | |
216 | read_tap_reg(OMAP_TAP_DIE_ID_1), | |
217 | (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); | |
218 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", | |
219 | read_tap_reg(OMAP_TAP_DIE_ID_2)); | |
220 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", | |
221 | read_tap_reg(OMAP_TAP_DIE_ID_3)); | |
222 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", | |
223 | prod_id, dev_type); | |
224 | ||
225 | /* | |
226 | * Detection for 34xx ES2.0 and above can be done with just | |
227 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
228 | * Note that rev cannot be used directly as ES1.0 uses value 0. | |
229 | */ | |
230 | if (hawkeye == 0xb7ae) { | |
231 | system_rev = 0x34300000 | ((1 + rev) << 12); | |
232 | pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev); | |
233 | _set_omap_chip(); | |
234 | return; | |
235 | } | |
1dbae815 TL |
236 | |
237 | /* Check hawkeye ids */ | |
238 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
239 | if (hawkeye == omap_ids[i].hawkeye) | |
240 | break; | |
241 | } | |
242 | ||
243 | if (i == ARRAY_SIZE(omap_ids)) { | |
244 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
245 | return; | |
246 | } | |
247 | ||
248 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
249 | if (dev_type == omap_ids[j].dev) | |
250 | break; | |
251 | } | |
252 | ||
253 | if (j == ARRAY_SIZE(omap_ids)) { | |
254 | printk(KERN_ERR "Unknown OMAP device type. " | |
255 | "Handling it as OMAP%04x\n", | |
256 | omap_ids[i].type >> 16); | |
257 | j = i; | |
258 | } | |
1dbae815 | 259 | |
097c584c | 260 | _set_system_rev(omap_ids[j].type, rev); |
1dbae815 | 261 | |
097c584c | 262 | _set_omap_chip(); |
1dbae815 TL |
263 | |
264 | pr_info("OMAP%04x", system_rev >> 16); | |
265 | if ((system_rev >> 8) & 0x0f) | |
097c584c PW |
266 | pr_info("ES%x", (system_rev >> 12) & 0xf); |
267 | pr_info("\n"); | |
268 | ||
1dbae815 TL |
269 | } |
270 |