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Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
de26804b | 21 | #include <linux/random.h> |
6770b211 RB |
22 | #include <linux/slab.h> |
23 | ||
24 | #ifdef CONFIG_SOC_BUS | |
25 | #include <linux/sys_soc.h> | |
26 | #endif | |
1dbae815 | 27 | |
0ba8b9b2 | 28 | #include <asm/cputype.h> |
1dbae815 | 29 | |
4e65331c | 30 | #include "common.h" |
72d0f1c3 | 31 | |
4952af43 | 32 | #include "id.h" |
2e130fc3 | 33 | |
dbc04161 | 34 | #include "soc.h" |
4814ced5 PW |
35 | #include "control.h" |
36 | ||
42a1cc9c IK |
37 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
38 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | |
39 | ||
f9d41eef RB |
40 | #define OMAP_SOC_MAX_NAME_LENGTH 16 |
41 | ||
84a34344 | 42 | static unsigned int omap_revision; |
f9d41eef RB |
43 | static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; |
44 | static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; | |
cc0170b2 | 45 | u32 omap_features; |
84a34344 LL |
46 | |
47 | unsigned int omap_rev(void) | |
48 | { | |
49 | return omap_revision; | |
50 | } | |
51 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 52 | |
8e25ad96 KH |
53 | int omap_type(void) |
54 | { | |
23d240d6 TK |
55 | static u32 val = OMAP2_DEVICETYPE_MASK; |
56 | ||
57 | if (val < OMAP2_DEVICETYPE_MASK) | |
58 | return val; | |
8e25ad96 | 59 | |
3ea4a182 | 60 | if (soc_is_omap24xx()) { |
8e25ad96 | 61 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
3ea4a182 | 62 | } else if (soc_is_ti81xx()) { |
e226ebe9 | 63 | val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); |
49cc485d | 64 | } else if (soc_is_am33xx() || soc_is_am43xx()) { |
fb3cfb1f | 65 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
3ea4a182 | 66 | } else if (soc_is_omap34xx()) { |
8e25ad96 | 67 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
3ea4a182 | 68 | } else if (soc_is_omap44xx()) { |
dcf5ef3f | 69 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
6852215a | 70 | } else if (soc_is_omap54xx() || soc_is_dra7xx()) { |
b13e80a8 S |
71 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); |
72 | val &= OMAP5_DEVICETYPE_MASK; | |
73 | val >>= 6; | |
74 | goto out; | |
edeae658 | 75 | } else { |
8e25ad96 KH |
76 | pr_err("Cannot detect omap type!\n"); |
77 | goto out; | |
78 | } | |
79 | ||
80 | val &= OMAP2_DEVICETYPE_MASK; | |
81 | val >>= 8; | |
82 | ||
83 | out: | |
84 | return val; | |
85 | } | |
86 | EXPORT_SYMBOL(omap_type); | |
87 | ||
88 | ||
a8823143 | 89 | /*----------------------------------------------------------------------------*/ |
097c584c | 90 | |
a8823143 TL |
91 | #define OMAP_TAP_IDCODE 0x0204 |
92 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
93 | #define OMAP_TAP_DIE_ID_1 0x021C | |
94 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
95 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 96 | |
b235e007 AG |
97 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
98 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
99 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
100 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
101 | ||
edfaf05c | 102 | #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) |
097c584c | 103 | |
a8823143 TL |
104 | struct omap_id { |
105 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
106 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 107 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 108 | }; |
097c584c | 109 | |
a8823143 TL |
110 | /* Register values to detect the OMAP version */ |
111 | static struct omap_id omap_ids[] __initdata = { | |
112 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
113 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
114 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
115 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
116 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
117 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
118 | }; | |
097c584c | 119 | |
a8823143 TL |
120 | static void __iomem *tap_base; |
121 | static u16 tap_prod_id; | |
1dbae815 | 122 | |
2e130fc3 KRC |
123 | void omap_get_die_id(struct omap_die_id *odi) |
124 | { | |
3ea4a182 | 125 | if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
b235e007 AG |
126 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
127 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
128 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
129 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
130 | ||
131 | return; | |
132 | } | |
2e130fc3 KRC |
133 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
134 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
135 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
136 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
137 | } | |
138 | ||
de26804b LW |
139 | static int __init omap_feed_randpool(void) |
140 | { | |
141 | struct omap_die_id odi; | |
142 | ||
143 | /* Throw the die ID into the entropy pool at boot */ | |
144 | omap_get_die_id(&odi); | |
145 | add_device_randomness(&odi, sizeof(odi)); | |
146 | return 0; | |
147 | } | |
148 | omap_device_initcall(omap_feed_randpool); | |
149 | ||
4de34f35 | 150 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
151 | { |
152 | int i, j; | |
a8823143 | 153 | u32 idcode, prod_id; |
1dbae815 | 154 | u16 hawkeye; |
a8823143 | 155 | u8 dev_type, rev; |
c46732bb | 156 | struct omap_die_id odi; |
1dbae815 TL |
157 | |
158 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 159 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
160 | hawkeye = (idcode >> 12) & 0xffff; |
161 | rev = (idcode >> 28) & 0x0f; | |
162 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 163 | omap_get_die_id(&odi); |
1dbae815 | 164 | |
097c584c PW |
165 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
166 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 167 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 168 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
169 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
170 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
171 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
172 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
173 | prod_id, dev_type); | |
174 | ||
1dbae815 TL |
175 | /* Check hawkeye ids */ |
176 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
177 | if (hawkeye == omap_ids[i].hawkeye) | |
178 | break; | |
179 | } | |
180 | ||
181 | if (i == ARRAY_SIZE(omap_ids)) { | |
182 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
183 | return; | |
184 | } | |
185 | ||
186 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
187 | if (dev_type == omap_ids[j].dev) | |
188 | break; | |
189 | } | |
190 | ||
191 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
192 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
193 | omap_ids[i].type >> 16); | |
1dbae815 TL |
194 | j = i; |
195 | } | |
1dbae815 | 196 | |
f9d41eef RB |
197 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
198 | sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); | |
199 | ||
200 | pr_info("%s", soc_name); | |
84a34344 | 201 | if ((omap_rev() >> 8) & 0x0f) |
f9d41eef | 202 | pr_info("%s", soc_rev); |
097c584c | 203 | pr_info("\n"); |
a8823143 TL |
204 | } |
205 | ||
50a01e64 VH |
206 | #define OMAP3_SHOW_FEATURE(feat) \ |
207 | if (omap3_has_ ##feat()) \ | |
85566ca6 | 208 | n += scnprintf(buf + n, sizeof(buf) - n, #feat " "); |
50a01e64 VH |
209 | |
210 | static void __init omap3_cpuinfo(void) | |
211 | { | |
212 | const char *cpu_name; | |
85566ca6 TL |
213 | char buf[64]; |
214 | int n = 0; | |
215 | ||
216 | memset(buf, 0, sizeof(buf)); | |
50a01e64 VH |
217 | |
218 | /* | |
219 | * OMAP3430 and OMAP3530 are assumed to be same. | |
220 | * | |
221 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
222 | * on available features. Upon detection, update the CPU id | |
223 | * and CPU class bits. | |
224 | */ | |
3ea4a182 | 225 | if (soc_is_omap3630()) { |
631af44c AF |
226 | if (omap3_has_iva() && omap3_has_sgx()) { |
227 | cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621"; | |
228 | } else if (omap3_has_iva()) { | |
229 | cpu_name = "DM3725"; | |
230 | } else if (omap3_has_sgx()) { | |
231 | cpu_name = "OMAP3615/AM3715"; | |
232 | } else { | |
233 | cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611"; | |
234 | } | |
68a88b98 | 235 | } else if (soc_is_am35xx()) { |
50a01e64 | 236 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
3ea4a182 | 237 | } else if (soc_is_ti816x()) { |
50a01e64 | 238 | cpu_name = "TI816X"; |
971b8a9c | 239 | } else if (soc_is_am335x()) { |
50a01e64 | 240 | cpu_name = "AM335X"; |
c04bbaa4 AM |
241 | } else if (soc_is_am437x()) { |
242 | cpu_name = "AM437x"; | |
3ea4a182 | 243 | } else if (soc_is_ti814x()) { |
50a01e64 VH |
244 | cpu_name = "TI814X"; |
245 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
246 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
247 | cpu_name = "OMAP3430/3530"; | |
248 | } else if (omap3_has_iva()) { | |
249 | cpu_name = "OMAP3525"; | |
250 | } else if (omap3_has_sgx()) { | |
251 | cpu_name = "OMAP3515"; | |
252 | } else { | |
253 | cpu_name = "OMAP3503"; | |
254 | } | |
255 | ||
85566ca6 | 256 | scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name); |
f9d41eef | 257 | |
50a01e64 | 258 | /* Print verbose information */ |
85566ca6 | 259 | n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev); |
50a01e64 VH |
260 | |
261 | OMAP3_SHOW_FEATURE(l2cache); | |
262 | OMAP3_SHOW_FEATURE(iva); | |
263 | OMAP3_SHOW_FEATURE(sgx); | |
264 | OMAP3_SHOW_FEATURE(neon); | |
265 | OMAP3_SHOW_FEATURE(isp); | |
266 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
85566ca6 TL |
267 | if (*(buf + n - 1) == ' ') |
268 | n--; | |
269 | n += scnprintf(buf + n, sizeof(buf) - n, ")\n"); | |
270 | pr_info("%s", buf); | |
50a01e64 VH |
271 | } |
272 | ||
8384ce07 SP |
273 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
274 | if (((status & OMAP3_ ##feat## _MASK) \ | |
275 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 276 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
277 | } |
278 | ||
4de34f35 | 279 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
280 | { |
281 | u32 status; | |
282 | ||
cc0170b2 | 283 | omap_features = 0; |
8384ce07 SP |
284 | |
285 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
286 | ||
287 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
288 | OMAP3_CHECK_FEATURE(status, IVA); | |
289 | OMAP3_CHECK_FEATURE(status, SGX); | |
290 | OMAP3_CHECK_FEATURE(status, NEON); | |
291 | OMAP3_CHECK_FEATURE(status, ISP); | |
3ea4a182 | 292 | if (soc_is_omap3630()) |
cc0170b2 | 293 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
3ea4a182 | 294 | if (soc_is_omap3430() || soc_is_omap3630()) |
cc0170b2 | 295 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
3ea4a182 | 296 | if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
b02b9172 PW |
297 | omap_rev() == OMAP3430_REV_ES3_1_2) |
298 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 299 | |
cc0170b2 | 300 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 301 | |
1ce02996 MG |
302 | /* |
303 | * am35x fixups: | |
304 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
305 | * reserved and therefore return 0 when read. Unfortunately, | |
306 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
307 | * mean that a feature is present even though it isn't so clear | |
308 | * the incorrectly set feature bits. | |
309 | */ | |
310 | if (soc_is_am35xx()) | |
311 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
312 | ||
8384ce07 SP |
313 | /* |
314 | * TODO: Get additional info (where applicable) | |
315 | * e.g. Size of L2 cache. | |
316 | */ | |
4de34f35 VH |
317 | |
318 | omap3_cpuinfo(); | |
8384ce07 SP |
319 | } |
320 | ||
4de34f35 | 321 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
322 | { |
323 | u32 si_type; | |
324 | ||
42a1cc9c IK |
325 | si_type = |
326 | (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; | |
cc0170b2 | 327 | |
42a1cc9c IK |
328 | if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) |
329 | omap_features = OMAP4_HAS_PERF_SILICON; | |
cc0170b2 A |
330 | } |
331 | ||
4de34f35 | 332 | void __init ti81xx_check_features(void) |
01001712 | 333 | { |
cc0170b2 | 334 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 335 | omap3_cpuinfo(); |
01001712 HP |
336 | } |
337 | ||
7bcad170 VH |
338 | void __init am33xx_check_features(void) |
339 | { | |
340 | u32 status; | |
341 | ||
342 | omap_features = OMAP3_HAS_NEON; | |
343 | ||
344 | status = omap_ctrl_readl(AM33XX_DEV_FEATURE); | |
345 | if (status & AM33XX_SGX_MASK) | |
346 | omap_features |= OMAP3_HAS_SGX; | |
347 | ||
348 | omap3_cpuinfo(); | |
349 | } | |
350 | ||
4de34f35 | 351 | void __init omap3xxx_check_revision(void) |
a8823143 | 352 | { |
f9d41eef | 353 | const char *cpu_rev; |
a8823143 TL |
354 | u32 cpuid, idcode; |
355 | u16 hawkeye; | |
356 | u8 rev; | |
a8823143 TL |
357 | |
358 | /* | |
359 | * We cannot access revision registers on ES1.0. | |
360 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
361 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
362 | */ | |
ac52e83f | 363 | cpuid = read_cpuid_id(); |
a8823143 | 364 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { |
84a34344 | 365 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 366 | cpu_rev = "1.0"; |
048f4bd7 | 367 | return; |
a8823143 TL |
368 | } |
369 | ||
370 | /* | |
371 | * Detection for 34xx ES2.0 and above can be done with just | |
372 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
373 | * Note that rev does not map directly to our defined processor | |
374 | * revision numbers as ES1.0 uses value 0. | |
375 | */ | |
376 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
377 | hawkeye = (idcode >> 12) & 0xffff; | |
378 | rev = (idcode >> 28) & 0xff; | |
097c584c | 379 | |
2456a10f NM |
380 | switch (hawkeye) { |
381 | case 0xb7ae: | |
382 | /* Handle 34xx/35xx devices */ | |
a8823143 | 383 | switch (rev) { |
048f4bd7 SP |
384 | case 0: /* Take care of early samples */ |
385 | case 1: | |
84a34344 | 386 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 387 | cpu_rev = "2.0"; |
a8823143 TL |
388 | break; |
389 | case 2: | |
84a34344 | 390 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 391 | cpu_rev = "2.1"; |
a8823143 TL |
392 | break; |
393 | case 3: | |
84a34344 | 394 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 395 | cpu_rev = "3.0"; |
a8823143 | 396 | break; |
187e688d | 397 | case 4: |
e9acb9b6 | 398 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 399 | cpu_rev = "3.1"; |
e9acb9b6 TL |
400 | break; |
401 | case 7: | |
edeae658 | 402 | /* FALLTHROUGH */ |
a8823143 TL |
403 | default: |
404 | /* Use the latest known revision as default */ | |
e9acb9b6 | 405 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 406 | cpu_rev = "3.1.2"; |
a8823143 | 407 | } |
2456a10f | 408 | break; |
4cac6018 | 409 | case 0xb868: |
1f1b0353 PW |
410 | /* |
411 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 412 | * |
1f1b0353 | 413 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
414 | * is identified later based on the features. |
415 | */ | |
9ed2ba7a PW |
416 | switch (rev) { |
417 | case 0: | |
68a88b98 | 418 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 419 | cpu_rev = "1.0"; |
9ed2ba7a PW |
420 | break; |
421 | case 1: | |
422 | /* FALLTHROUGH */ | |
423 | default: | |
68a88b98 | 424 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 425 | cpu_rev = "1.1"; |
9ed2ba7a | 426 | } |
4cac6018 | 427 | break; |
edeae658 | 428 | case 0xb891: |
b0a1a6ce | 429 | /* Handle 36xx devices */ |
b0a1a6ce AG |
430 | |
431 | switch(rev) { | |
432 | case 0: /* Take care of early samples */ | |
433 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 434 | cpu_rev = "1.0"; |
b0a1a6ce AG |
435 | break; |
436 | case 1: | |
437 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 438 | cpu_rev = "1.1"; |
b0a1a6ce AG |
439 | break; |
440 | case 2: | |
51ec811a | 441 | /* FALLTHROUGH */ |
b0a1a6ce | 442 | default: |
51ec811a | 443 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 444 | cpu_rev = "1.2"; |
b0a1a6ce | 445 | } |
77c0870c | 446 | break; |
01001712 | 447 | case 0xb81e: |
01001712 HP |
448 | switch (rev) { |
449 | case 0: | |
450 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 451 | cpu_rev = "1.0"; |
01001712 HP |
452 | break; |
453 | case 1: | |
51ec811a | 454 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 455 | cpu_rev = "1.1"; |
3b32b7d6 | 456 | break; |
a5f93d9d AM |
457 | case 2: |
458 | omap_revision = TI8168_REV_ES2_0; | |
459 | cpu_rev = "2.0"; | |
460 | break; | |
461 | case 3: | |
462 | /* FALLTHROUGH */ | |
463 | default: | |
464 | omap_revision = TI8168_REV_ES2_1; | |
465 | cpu_rev = "2.1"; | |
01001712 HP |
466 | } |
467 | break; | |
1e6cb146 | 468 | case 0xb944: |
5af044f4 AC |
469 | switch (rev) { |
470 | case 0: | |
471 | omap_revision = AM335X_REV_ES1_0; | |
472 | cpu_rev = "1.0"; | |
473 | break; | |
474 | case 1: | |
5af044f4 AC |
475 | omap_revision = AM335X_REV_ES2_0; |
476 | cpu_rev = "2.0"; | |
477 | break; | |
d240ef30 VH |
478 | case 2: |
479 | /* FALLTHROUGH */ | |
480 | default: | |
481 | omap_revision = AM335X_REV_ES2_1; | |
482 | cpu_rev = "2.1"; | |
483 | break; | |
5af044f4 | 484 | } |
c2d13554 | 485 | break; |
c04bbaa4 | 486 | case 0xb98c: |
4a2ed4c0 LV |
487 | switch (rev) { |
488 | case 0: | |
489 | omap_revision = AM437X_REV_ES1_0; | |
490 | cpu_rev = "1.0"; | |
491 | break; | |
492 | case 1: | |
4a2ed4c0 LV |
493 | omap_revision = AM437X_REV_ES1_1; |
494 | cpu_rev = "1.1"; | |
495 | break; | |
4fdd54f0 LV |
496 | case 2: |
497 | /* FALLTHROUGH */ | |
498 | default: | |
499 | omap_revision = AM437X_REV_ES1_2; | |
500 | cpu_rev = "1.2"; | |
501 | break; | |
4a2ed4c0 | 502 | } |
c04bbaa4 | 503 | break; |
4390f5b2 | 504 | case 0xb8f2: |
68b813bf | 505 | case 0xb968: |
4390f5b2 HP |
506 | switch (rev) { |
507 | case 0: | |
508 | /* FALLTHROUGH */ | |
509 | case 1: | |
510 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 511 | cpu_rev = "1.0"; |
4390f5b2 HP |
512 | break; |
513 | case 2: | |
514 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 515 | cpu_rev = "2.0"; |
4390f5b2 HP |
516 | break; |
517 | case 3: | |
518 | /* FALLTHROUGH */ | |
519 | default: | |
520 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 521 | cpu_rev = "2.1"; |
4390f5b2 HP |
522 | break; |
523 | } | |
1e6cb146 | 524 | break; |
2456a10f | 525 | default: |
51ec811a | 526 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 527 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 528 | cpu_rev = "1.2"; |
68b813bf TL |
529 | pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n", |
530 | hawkeye); | |
a8823143 | 531 | } |
f9d41eef | 532 | sprintf(soc_rev, "ES%s", cpu_rev); |
1dbae815 TL |
533 | } |
534 | ||
4de34f35 | 535 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
536 | { |
537 | u32 idcode; | |
538 | u16 hawkeye; | |
539 | u8 rev; | |
b570e0ec SS |
540 | |
541 | /* | |
542 | * The IC rev detection is done with hawkeye and rev. | |
543 | * Note that rev does not map directly to defined processor | |
544 | * revision numbers as ES1.0 uses value 0. | |
545 | */ | |
546 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
547 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 548 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 549 | |
ed6be0ba | 550 | /* |
fa54dccd | 551 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
552 | * Use ARM register to detect the correct ES version |
553 | */ | |
ec023e46 | 554 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ac52e83f | 555 | idcode = read_cpuid_id(); |
ed6be0ba SS |
556 | rev = (idcode & 0xf) - 1; |
557 | } | |
558 | ||
559 | switch (hawkeye) { | |
560 | case 0xb852: | |
561 | switch (rev) { | |
562 | case 0: | |
563 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
564 | break; |
565 | case 1: | |
e49c4d27 | 566 | default: |
ed6be0ba | 567 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
568 | } |
569 | break; | |
570 | case 0xb95c: | |
571 | switch (rev) { | |
572 | case 3: | |
573 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 574 | break; |
e49c4d27 | 575 | case 4: |
e49c4d27 | 576 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
577 | break; |
578 | case 6: | |
579 | default: | |
580 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
581 | } |
582 | break; | |
fa54dccd A |
583 | case 0xb94e: |
584 | switch (rev) { | |
585 | case 0: | |
fa54dccd | 586 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 587 | break; |
33ee0db5 CL |
588 | case 2: |
589 | default: | |
590 | omap_revision = OMAP4460_REV_ES1_1; | |
591 | break; | |
fa54dccd A |
592 | } |
593 | break; | |
ec023e46 LI |
594 | case 0xb975: |
595 | switch (rev) { | |
596 | case 0: | |
597 | default: | |
598 | omap_revision = OMAP4470_REV_ES1_0; | |
599 | break; | |
600 | } | |
601 | break; | |
ed6be0ba | 602 | default: |
e49c4d27 | 603 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 604 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
605 | } |
606 | ||
f9d41eef RB |
607 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
608 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
609 | (omap_rev() >> 8) & 0xf); | |
610 | pr_info("%s %s\n", soc_name, soc_rev); | |
b570e0ec SS |
611 | } |
612 | ||
b13e80a8 S |
613 | void __init omap5xxx_check_revision(void) |
614 | { | |
615 | u32 idcode; | |
616 | u16 hawkeye; | |
617 | u8 rev; | |
618 | ||
619 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
620 | hawkeye = (idcode >> 12) & 0xffff; | |
621 | rev = (idcode >> 28) & 0xff; | |
622 | switch (hawkeye) { | |
623 | case 0xb942: | |
624 | switch (rev) { | |
625 | case 0: | |
aa2f4b16 NM |
626 | /* No support for ES1.0 Test chip */ |
627 | BUG(); | |
5a898a78 SS |
628 | case 1: |
629 | default: | |
630 | omap_revision = OMAP5430_REV_ES2_0; | |
b13e80a8 S |
631 | } |
632 | break; | |
633 | ||
634 | case 0xb998: | |
635 | switch (rev) { | |
636 | case 0: | |
aa2f4b16 NM |
637 | /* No support for ES1.0 Test chip */ |
638 | BUG(); | |
5a898a78 SS |
639 | case 1: |
640 | default: | |
641 | omap_revision = OMAP5432_REV_ES2_0; | |
b13e80a8 S |
642 | } |
643 | break; | |
644 | ||
645 | default: | |
646 | /* Unknown default to latest silicon rev as default*/ | |
5a898a78 | 647 | omap_revision = OMAP5430_REV_ES2_0; |
b13e80a8 S |
648 | } |
649 | ||
f9d41eef RB |
650 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
651 | sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); | |
652 | ||
653 | pr_info("%s %s\n", soc_name, soc_rev); | |
b13e80a8 S |
654 | } |
655 | ||
733d20ee NM |
656 | void __init dra7xxx_check_revision(void) |
657 | { | |
658 | u32 idcode; | |
659 | u16 hawkeye; | |
660 | u8 rev; | |
661 | ||
662 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
663 | hawkeye = (idcode >> 12) & 0xffff; | |
664 | rev = (idcode >> 28) & 0xff; | |
665 | switch (hawkeye) { | |
c15ab996 LV |
666 | case 0xbb50: |
667 | switch (rev) { | |
668 | case 0: | |
669 | default: | |
670 | omap_revision = DRA762_REV_ES1_0; | |
671 | break; | |
672 | } | |
673 | break; | |
674 | ||
733d20ee NM |
675 | case 0xb990: |
676 | switch (rev) { | |
677 | case 0: | |
678 | omap_revision = DRA752_REV_ES1_0; | |
679 | break; | |
680 | case 1: | |
733d20ee | 681 | omap_revision = DRA752_REV_ES1_1; |
81032e34 VM |
682 | break; |
683 | case 2: | |
684 | default: | |
685 | omap_revision = DRA752_REV_ES2_0; | |
686 | break; | |
733d20ee NM |
687 | } |
688 | break; | |
689 | ||
73d20280 NM |
690 | case 0xb9bc: |
691 | switch (rev) { | |
692 | case 0: | |
693 | omap_revision = DRA722_REV_ES1_0; | |
694 | break; | |
6b532c4a | 695 | case 1: |
6b532c4a | 696 | omap_revision = DRA722_REV_ES2_0; |
73d20280 | 697 | break; |
cf14dd05 VM |
698 | case 2: |
699 | default: | |
700 | omap_revision = DRA722_REV_ES2_1; | |
701 | break; | |
73d20280 NM |
702 | } |
703 | break; | |
704 | ||
733d20ee NM |
705 | default: |
706 | /* Unknown default to latest silicon rev as default*/ | |
6953faf9 | 707 | pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", |
733d20ee | 708 | __func__, idcode, hawkeye, rev); |
81032e34 | 709 | omap_revision = DRA752_REV_ES2_0; |
733d20ee NM |
710 | } |
711 | ||
712 | sprintf(soc_name, "DRA%03x", omap_rev() >> 16); | |
713 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
714 | (omap_rev() >> 8) & 0xf); | |
715 | ||
716 | pr_info("%s %s\n", soc_name, soc_rev); | |
717 | } | |
718 | ||
a8823143 TL |
719 | /* |
720 | * Set up things for map_io and processor detection later on. Gets called | |
721 | * pretty much first thing from board init. For multi-omap, this gets | |
722 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
723 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
724 | * is done. | |
725 | */ | |
b6a4226c | 726 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap) |
0e564848 | 727 | { |
b6a4226c PW |
728 | omap_revision = class; |
729 | tap_base = tap; | |
0e564848 | 730 | |
b6a4226c | 731 | /* XXX What is this intended to do? */ |
3ea4a182 | 732 | if (soc_is_omap34xx()) |
0e564848 TL |
733 | tap_prod_id = 0x0210; |
734 | else | |
735 | tap_prod_id = 0x0208; | |
736 | } | |
6770b211 RB |
737 | |
738 | #ifdef CONFIG_SOC_BUS | |
739 | ||
415ab328 | 740 | static const char * const omap_types[] = { |
6770b211 RB |
741 | [OMAP2_DEVICE_TYPE_TEST] = "TST", |
742 | [OMAP2_DEVICE_TYPE_EMU] = "EMU", | |
743 | [OMAP2_DEVICE_TYPE_SEC] = "HS", | |
744 | [OMAP2_DEVICE_TYPE_GP] = "GP", | |
745 | [OMAP2_DEVICE_TYPE_BAD] = "BAD", | |
746 | }; | |
747 | ||
748 | static const char * __init omap_get_family(void) | |
749 | { | |
3ea4a182 | 750 | if (soc_is_omap24xx()) |
6770b211 | 751 | return kasprintf(GFP_KERNEL, "OMAP2"); |
3ea4a182 | 752 | else if (soc_is_omap34xx()) |
6770b211 | 753 | return kasprintf(GFP_KERNEL, "OMAP3"); |
3ea4a182 | 754 | else if (soc_is_omap44xx()) |
6770b211 RB |
755 | return kasprintf(GFP_KERNEL, "OMAP4"); |
756 | else if (soc_is_omap54xx()) | |
757 | return kasprintf(GFP_KERNEL, "OMAP5"); | |
e5ed5b60 SA |
758 | else if (soc_is_am33xx() || soc_is_am335x()) |
759 | return kasprintf(GFP_KERNEL, "AM33xx"); | |
7a2e0513 AM |
760 | else if (soc_is_am43xx()) |
761 | return kasprintf(GFP_KERNEL, "AM43xx"); | |
733d20ee NM |
762 | else if (soc_is_dra7xx()) |
763 | return kasprintf(GFP_KERNEL, "DRA7"); | |
6770b211 RB |
764 | else |
765 | return kasprintf(GFP_KERNEL, "Unknown"); | |
766 | } | |
767 | ||
768 | static ssize_t omap_get_type(struct device *dev, | |
769 | struct device_attribute *attr, | |
770 | char *buf) | |
771 | { | |
772 | return sprintf(buf, "%s\n", omap_types[omap_type()]); | |
773 | } | |
774 | ||
775 | static struct device_attribute omap_soc_attr = | |
776 | __ATTR(type, S_IRUGO, omap_get_type, NULL); | |
777 | ||
778 | void __init omap_soc_device_init(void) | |
779 | { | |
780 | struct device *parent; | |
781 | struct soc_device *soc_dev; | |
782 | struct soc_device_attribute *soc_dev_attr; | |
783 | ||
784 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
785 | if (!soc_dev_attr) | |
786 | return; | |
787 | ||
788 | soc_dev_attr->machine = soc_name; | |
789 | soc_dev_attr->family = omap_get_family(); | |
790 | soc_dev_attr->revision = soc_rev; | |
791 | ||
792 | soc_dev = soc_device_register(soc_dev_attr); | |
b1dd11d6 | 793 | if (IS_ERR(soc_dev)) { |
6770b211 RB |
794 | kfree(soc_dev_attr); |
795 | return; | |
796 | } | |
797 | ||
798 | parent = soc_device_to_device(soc_dev); | |
b1dd11d6 | 799 | device_create_file(parent, &omap_soc_attr); |
6770b211 RB |
800 | } |
801 | #endif /* CONFIG_SOC_BUS */ |