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Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/id.c | |
3 | * | |
4 | * OMAP2 CPU identification code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Written by Tony Lindgren <tony@atomide.com> | |
8 | * | |
e49c4d27 | 9 | * Copyright (C) 2009-11 Texas Instruments |
44169075 SS |
10 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
11 | * | |
1dbae815 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
1dbae815 TL |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
fced80c7 | 20 | #include <linux/io.h> |
de26804b | 21 | #include <linux/random.h> |
6770b211 RB |
22 | #include <linux/slab.h> |
23 | ||
24 | #ifdef CONFIG_SOC_BUS | |
25 | #include <linux/sys_soc.h> | |
26 | #endif | |
1dbae815 | 27 | |
0ba8b9b2 | 28 | #include <asm/cputype.h> |
1dbae815 | 29 | |
4e65331c | 30 | #include "common.h" |
72d0f1c3 | 31 | |
4952af43 | 32 | #include "id.h" |
2e130fc3 | 33 | |
dbc04161 | 34 | #include "soc.h" |
4814ced5 PW |
35 | #include "control.h" |
36 | ||
42a1cc9c IK |
37 | #define OMAP4_SILICON_TYPE_STANDARD 0x01 |
38 | #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 | |
39 | ||
f9d41eef RB |
40 | #define OMAP_SOC_MAX_NAME_LENGTH 16 |
41 | ||
84a34344 | 42 | static unsigned int omap_revision; |
f9d41eef RB |
43 | static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; |
44 | static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; | |
cc0170b2 | 45 | u32 omap_features; |
84a34344 LL |
46 | |
47 | unsigned int omap_rev(void) | |
48 | { | |
49 | return omap_revision; | |
50 | } | |
51 | EXPORT_SYMBOL(omap_rev); | |
097c584c | 52 | |
8e25ad96 KH |
53 | int omap_type(void) |
54 | { | |
23d240d6 TK |
55 | static u32 val = OMAP2_DEVICETYPE_MASK; |
56 | ||
57 | if (val < OMAP2_DEVICETYPE_MASK) | |
58 | return val; | |
8e25ad96 | 59 | |
3ea4a182 | 60 | if (soc_is_omap24xx()) { |
8e25ad96 | 61 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
3ea4a182 | 62 | } else if (soc_is_ti81xx()) { |
e226ebe9 | 63 | val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); |
49cc485d | 64 | } else if (soc_is_am33xx() || soc_is_am43xx()) { |
fb3cfb1f | 65 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
3ea4a182 | 66 | } else if (soc_is_omap34xx()) { |
8e25ad96 | 67 | val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); |
3ea4a182 | 68 | } else if (soc_is_omap44xx()) { |
dcf5ef3f | 69 | val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); |
6852215a | 70 | } else if (soc_is_omap54xx() || soc_is_dra7xx()) { |
b13e80a8 S |
71 | val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); |
72 | val &= OMAP5_DEVICETYPE_MASK; | |
73 | val >>= 6; | |
74 | goto out; | |
edeae658 | 75 | } else { |
8e25ad96 KH |
76 | pr_err("Cannot detect omap type!\n"); |
77 | goto out; | |
78 | } | |
79 | ||
80 | val &= OMAP2_DEVICETYPE_MASK; | |
81 | val >>= 8; | |
82 | ||
83 | out: | |
84 | return val; | |
85 | } | |
86 | EXPORT_SYMBOL(omap_type); | |
87 | ||
88 | ||
a8823143 | 89 | /*----------------------------------------------------------------------------*/ |
097c584c | 90 | |
a8823143 TL |
91 | #define OMAP_TAP_IDCODE 0x0204 |
92 | #define OMAP_TAP_DIE_ID_0 0x0218 | |
93 | #define OMAP_TAP_DIE_ID_1 0x021C | |
94 | #define OMAP_TAP_DIE_ID_2 0x0220 | |
95 | #define OMAP_TAP_DIE_ID_3 0x0224 | |
097c584c | 96 | |
b235e007 AG |
97 | #define OMAP_TAP_DIE_ID_44XX_0 0x0200 |
98 | #define OMAP_TAP_DIE_ID_44XX_1 0x0208 | |
99 | #define OMAP_TAP_DIE_ID_44XX_2 0x020c | |
100 | #define OMAP_TAP_DIE_ID_44XX_3 0x0210 | |
101 | ||
edfaf05c | 102 | #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) |
097c584c | 103 | |
a8823143 TL |
104 | struct omap_id { |
105 | u16 hawkeye; /* Silicon type (Hawkeye id) */ | |
106 | u8 dev; /* Device type from production_id reg */ | |
84a34344 | 107 | u32 type; /* Combined type id copied to omap_revision */ |
a8823143 | 108 | }; |
097c584c | 109 | |
a8823143 TL |
110 | /* Register values to detect the OMAP version */ |
111 | static struct omap_id omap_ids[] __initdata = { | |
112 | { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, | |
113 | { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, | |
114 | { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, | |
115 | { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, | |
116 | { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, | |
117 | { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, | |
118 | }; | |
097c584c | 119 | |
a8823143 TL |
120 | static void __iomem *tap_base; |
121 | static u16 tap_prod_id; | |
1dbae815 | 122 | |
2e130fc3 KRC |
123 | void omap_get_die_id(struct omap_die_id *odi) |
124 | { | |
3ea4a182 | 125 | if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
b235e007 AG |
126 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); |
127 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); | |
128 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); | |
129 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); | |
130 | ||
131 | return; | |
132 | } | |
2e130fc3 KRC |
133 | odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); |
134 | odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); | |
135 | odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); | |
136 | odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); | |
137 | } | |
138 | ||
de26804b LW |
139 | static int __init omap_feed_randpool(void) |
140 | { | |
141 | struct omap_die_id odi; | |
142 | ||
143 | /* Throw the die ID into the entropy pool at boot */ | |
144 | omap_get_die_id(&odi); | |
145 | add_device_randomness(&odi, sizeof(odi)); | |
146 | return 0; | |
147 | } | |
148 | omap_device_initcall(omap_feed_randpool); | |
149 | ||
4de34f35 | 150 | void __init omap2xxx_check_revision(void) |
1dbae815 TL |
151 | { |
152 | int i, j; | |
a8823143 | 153 | u32 idcode, prod_id; |
1dbae815 | 154 | u16 hawkeye; |
a8823143 | 155 | u8 dev_type, rev; |
c46732bb | 156 | struct omap_die_id odi; |
1dbae815 TL |
157 | |
158 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
0e564848 | 159 | prod_id = read_tap_reg(tap_prod_id); |
1dbae815 TL |
160 | hawkeye = (idcode >> 12) & 0xffff; |
161 | rev = (idcode >> 28) & 0x0f; | |
162 | dev_type = (prod_id >> 16) & 0x0f; | |
c46732bb | 163 | omap_get_die_id(&odi); |
1dbae815 | 164 | |
097c584c PW |
165 | pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", |
166 | idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); | |
c46732bb | 167 | pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); |
097c584c | 168 | pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", |
c46732bb KRC |
169 | odi.id_1, (odi.id_1 >> 28) & 0xf); |
170 | pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); | |
171 | pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); | |
097c584c PW |
172 | pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", |
173 | prod_id, dev_type); | |
174 | ||
1dbae815 TL |
175 | /* Check hawkeye ids */ |
176 | for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { | |
177 | if (hawkeye == omap_ids[i].hawkeye) | |
178 | break; | |
179 | } | |
180 | ||
181 | if (i == ARRAY_SIZE(omap_ids)) { | |
182 | printk(KERN_ERR "Unknown OMAP CPU id\n"); | |
183 | return; | |
184 | } | |
185 | ||
186 | for (j = i; j < ARRAY_SIZE(omap_ids); j++) { | |
187 | if (dev_type == omap_ids[j].dev) | |
188 | break; | |
189 | } | |
190 | ||
191 | if (j == ARRAY_SIZE(omap_ids)) { | |
7852ec05 PW |
192 | pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", |
193 | omap_ids[i].type >> 16); | |
1dbae815 TL |
194 | j = i; |
195 | } | |
1dbae815 | 196 | |
f9d41eef RB |
197 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
198 | sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); | |
199 | ||
200 | pr_info("%s", soc_name); | |
84a34344 | 201 | if ((omap_rev() >> 8) & 0x0f) |
f9d41eef | 202 | pr_info("%s", soc_rev); |
097c584c | 203 | pr_info("\n"); |
a8823143 TL |
204 | } |
205 | ||
50a01e64 VH |
206 | #define OMAP3_SHOW_FEATURE(feat) \ |
207 | if (omap3_has_ ##feat()) \ | |
85566ca6 | 208 | n += scnprintf(buf + n, sizeof(buf) - n, #feat " "); |
50a01e64 VH |
209 | |
210 | static void __init omap3_cpuinfo(void) | |
211 | { | |
212 | const char *cpu_name; | |
85566ca6 TL |
213 | char buf[64]; |
214 | int n = 0; | |
215 | ||
216 | memset(buf, 0, sizeof(buf)); | |
50a01e64 VH |
217 | |
218 | /* | |
219 | * OMAP3430 and OMAP3530 are assumed to be same. | |
220 | * | |
221 | * OMAP3525, OMAP3515 and OMAP3503 can be detected only based | |
222 | * on available features. Upon detection, update the CPU id | |
223 | * and CPU class bits. | |
224 | */ | |
3ea4a182 | 225 | if (soc_is_omap3630()) { |
50a01e64 | 226 | cpu_name = "OMAP3630"; |
68a88b98 | 227 | } else if (soc_is_am35xx()) { |
50a01e64 | 228 | cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; |
3ea4a182 | 229 | } else if (soc_is_ti816x()) { |
50a01e64 | 230 | cpu_name = "TI816X"; |
971b8a9c | 231 | } else if (soc_is_am335x()) { |
50a01e64 | 232 | cpu_name = "AM335X"; |
c04bbaa4 AM |
233 | } else if (soc_is_am437x()) { |
234 | cpu_name = "AM437x"; | |
3ea4a182 | 235 | } else if (soc_is_ti814x()) { |
50a01e64 VH |
236 | cpu_name = "TI814X"; |
237 | } else if (omap3_has_iva() && omap3_has_sgx()) { | |
238 | /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ | |
239 | cpu_name = "OMAP3430/3530"; | |
240 | } else if (omap3_has_iva()) { | |
241 | cpu_name = "OMAP3525"; | |
242 | } else if (omap3_has_sgx()) { | |
243 | cpu_name = "OMAP3515"; | |
244 | } else { | |
245 | cpu_name = "OMAP3503"; | |
246 | } | |
247 | ||
85566ca6 | 248 | scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name); |
f9d41eef | 249 | |
50a01e64 | 250 | /* Print verbose information */ |
85566ca6 | 251 | n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev); |
50a01e64 VH |
252 | |
253 | OMAP3_SHOW_FEATURE(l2cache); | |
254 | OMAP3_SHOW_FEATURE(iva); | |
255 | OMAP3_SHOW_FEATURE(sgx); | |
256 | OMAP3_SHOW_FEATURE(neon); | |
257 | OMAP3_SHOW_FEATURE(isp); | |
258 | OMAP3_SHOW_FEATURE(192mhz_clk); | |
85566ca6 TL |
259 | if (*(buf + n - 1) == ' ') |
260 | n--; | |
261 | n += scnprintf(buf + n, sizeof(buf) - n, ")\n"); | |
262 | pr_info("%s", buf); | |
50a01e64 VH |
263 | } |
264 | ||
8384ce07 SP |
265 | #define OMAP3_CHECK_FEATURE(status,feat) \ |
266 | if (((status & OMAP3_ ##feat## _MASK) \ | |
267 | >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ | |
cc0170b2 | 268 | omap_features |= OMAP3_HAS_ ##feat; \ |
8384ce07 SP |
269 | } |
270 | ||
4de34f35 | 271 | void __init omap3xxx_check_features(void) |
8384ce07 SP |
272 | { |
273 | u32 status; | |
274 | ||
cc0170b2 | 275 | omap_features = 0; |
8384ce07 SP |
276 | |
277 | status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); | |
278 | ||
279 | OMAP3_CHECK_FEATURE(status, L2CACHE); | |
280 | OMAP3_CHECK_FEATURE(status, IVA); | |
281 | OMAP3_CHECK_FEATURE(status, SGX); | |
282 | OMAP3_CHECK_FEATURE(status, NEON); | |
283 | OMAP3_CHECK_FEATURE(status, ISP); | |
3ea4a182 | 284 | if (soc_is_omap3630()) |
cc0170b2 | 285 | omap_features |= OMAP3_HAS_192MHZ_CLK; |
3ea4a182 | 286 | if (soc_is_omap3430() || soc_is_omap3630()) |
cc0170b2 | 287 | omap_features |= OMAP3_HAS_IO_WAKEUP; |
3ea4a182 | 288 | if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || |
b02b9172 PW |
289 | omap_rev() == OMAP3430_REV_ES3_1_2) |
290 | omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; | |
8384ce07 | 291 | |
cc0170b2 | 292 | omap_features |= OMAP3_HAS_SDRC; |
01001712 | 293 | |
1ce02996 MG |
294 | /* |
295 | * am35x fixups: | |
296 | * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as | |
297 | * reserved and therefore return 0 when read. Unfortunately, | |
298 | * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to | |
299 | * mean that a feature is present even though it isn't so clear | |
300 | * the incorrectly set feature bits. | |
301 | */ | |
302 | if (soc_is_am35xx()) | |
303 | omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); | |
304 | ||
8384ce07 SP |
305 | /* |
306 | * TODO: Get additional info (where applicable) | |
307 | * e.g. Size of L2 cache. | |
308 | */ | |
4de34f35 VH |
309 | |
310 | omap3_cpuinfo(); | |
8384ce07 SP |
311 | } |
312 | ||
4de34f35 | 313 | void __init omap4xxx_check_features(void) |
cc0170b2 A |
314 | { |
315 | u32 si_type; | |
316 | ||
42a1cc9c IK |
317 | si_type = |
318 | (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; | |
cc0170b2 | 319 | |
42a1cc9c IK |
320 | if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) |
321 | omap_features = OMAP4_HAS_PERF_SILICON; | |
cc0170b2 A |
322 | } |
323 | ||
4de34f35 | 324 | void __init ti81xx_check_features(void) |
01001712 | 325 | { |
cc0170b2 | 326 | omap_features = OMAP3_HAS_NEON; |
4de34f35 | 327 | omap3_cpuinfo(); |
01001712 HP |
328 | } |
329 | ||
7bcad170 VH |
330 | void __init am33xx_check_features(void) |
331 | { | |
332 | u32 status; | |
333 | ||
334 | omap_features = OMAP3_HAS_NEON; | |
335 | ||
336 | status = omap_ctrl_readl(AM33XX_DEV_FEATURE); | |
337 | if (status & AM33XX_SGX_MASK) | |
338 | omap_features |= OMAP3_HAS_SGX; | |
339 | ||
340 | omap3_cpuinfo(); | |
341 | } | |
342 | ||
4de34f35 | 343 | void __init omap3xxx_check_revision(void) |
a8823143 | 344 | { |
f9d41eef | 345 | const char *cpu_rev; |
a8823143 TL |
346 | u32 cpuid, idcode; |
347 | u16 hawkeye; | |
348 | u8 rev; | |
a8823143 TL |
349 | |
350 | /* | |
351 | * We cannot access revision registers on ES1.0. | |
352 | * If the processor type is Cortex-A8 and the revision is 0x0 | |
353 | * it means its Cortex r0p0 which is 3430 ES1.0. | |
354 | */ | |
ac52e83f | 355 | cpuid = read_cpuid_id(); |
a8823143 | 356 | if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { |
84a34344 | 357 | omap_revision = OMAP3430_REV_ES1_0; |
50a01e64 | 358 | cpu_rev = "1.0"; |
048f4bd7 | 359 | return; |
a8823143 TL |
360 | } |
361 | ||
362 | /* | |
363 | * Detection for 34xx ES2.0 and above can be done with just | |
364 | * hawkeye and rev. See TRM 1.5.2 Device Identification. | |
365 | * Note that rev does not map directly to our defined processor | |
366 | * revision numbers as ES1.0 uses value 0. | |
367 | */ | |
368 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
369 | hawkeye = (idcode >> 12) & 0xffff; | |
370 | rev = (idcode >> 28) & 0xff; | |
097c584c | 371 | |
2456a10f NM |
372 | switch (hawkeye) { |
373 | case 0xb7ae: | |
374 | /* Handle 34xx/35xx devices */ | |
a8823143 | 375 | switch (rev) { |
048f4bd7 SP |
376 | case 0: /* Take care of early samples */ |
377 | case 1: | |
84a34344 | 378 | omap_revision = OMAP3430_REV_ES2_0; |
50a01e64 | 379 | cpu_rev = "2.0"; |
a8823143 TL |
380 | break; |
381 | case 2: | |
84a34344 | 382 | omap_revision = OMAP3430_REV_ES2_1; |
50a01e64 | 383 | cpu_rev = "2.1"; |
a8823143 TL |
384 | break; |
385 | case 3: | |
84a34344 | 386 | omap_revision = OMAP3430_REV_ES3_0; |
50a01e64 | 387 | cpu_rev = "3.0"; |
a8823143 | 388 | break; |
187e688d | 389 | case 4: |
e9acb9b6 | 390 | omap_revision = OMAP3430_REV_ES3_1; |
50a01e64 | 391 | cpu_rev = "3.1"; |
e9acb9b6 TL |
392 | break; |
393 | case 7: | |
edeae658 | 394 | /* FALLTHROUGH */ |
a8823143 TL |
395 | default: |
396 | /* Use the latest known revision as default */ | |
e9acb9b6 | 397 | omap_revision = OMAP3430_REV_ES3_1_2; |
50a01e64 | 398 | cpu_rev = "3.1.2"; |
a8823143 | 399 | } |
2456a10f | 400 | break; |
4cac6018 | 401 | case 0xb868: |
1f1b0353 PW |
402 | /* |
403 | * Handle OMAP/AM 3505/3517 devices | |
4cac6018 | 404 | * |
1f1b0353 | 405 | * Set the device to be OMAP3517 here. Actual device |
4cac6018 SP |
406 | * is identified later based on the features. |
407 | */ | |
9ed2ba7a PW |
408 | switch (rev) { |
409 | case 0: | |
68a88b98 | 410 | omap_revision = AM35XX_REV_ES1_0; |
50a01e64 | 411 | cpu_rev = "1.0"; |
9ed2ba7a PW |
412 | break; |
413 | case 1: | |
414 | /* FALLTHROUGH */ | |
415 | default: | |
68a88b98 | 416 | omap_revision = AM35XX_REV_ES1_1; |
50a01e64 | 417 | cpu_rev = "1.1"; |
9ed2ba7a | 418 | } |
4cac6018 | 419 | break; |
edeae658 | 420 | case 0xb891: |
b0a1a6ce | 421 | /* Handle 36xx devices */ |
b0a1a6ce AG |
422 | |
423 | switch(rev) { | |
424 | case 0: /* Take care of early samples */ | |
425 | omap_revision = OMAP3630_REV_ES1_0; | |
50a01e64 | 426 | cpu_rev = "1.0"; |
b0a1a6ce AG |
427 | break; |
428 | case 1: | |
429 | omap_revision = OMAP3630_REV_ES1_1; | |
50a01e64 | 430 | cpu_rev = "1.1"; |
b0a1a6ce AG |
431 | break; |
432 | case 2: | |
51ec811a | 433 | /* FALLTHROUGH */ |
b0a1a6ce | 434 | default: |
51ec811a | 435 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 436 | cpu_rev = "1.2"; |
b0a1a6ce | 437 | } |
77c0870c | 438 | break; |
01001712 | 439 | case 0xb81e: |
01001712 HP |
440 | switch (rev) { |
441 | case 0: | |
442 | omap_revision = TI8168_REV_ES1_0; | |
50a01e64 | 443 | cpu_rev = "1.0"; |
01001712 HP |
444 | break; |
445 | case 1: | |
51ec811a | 446 | omap_revision = TI8168_REV_ES1_1; |
50a01e64 | 447 | cpu_rev = "1.1"; |
3b32b7d6 | 448 | break; |
a5f93d9d AM |
449 | case 2: |
450 | omap_revision = TI8168_REV_ES2_0; | |
451 | cpu_rev = "2.0"; | |
452 | break; | |
453 | case 3: | |
454 | /* FALLTHROUGH */ | |
455 | default: | |
456 | omap_revision = TI8168_REV_ES2_1; | |
457 | cpu_rev = "2.1"; | |
01001712 HP |
458 | } |
459 | break; | |
1e6cb146 | 460 | case 0xb944: |
5af044f4 AC |
461 | switch (rev) { |
462 | case 0: | |
463 | omap_revision = AM335X_REV_ES1_0; | |
464 | cpu_rev = "1.0"; | |
465 | break; | |
466 | case 1: | |
5af044f4 AC |
467 | omap_revision = AM335X_REV_ES2_0; |
468 | cpu_rev = "2.0"; | |
469 | break; | |
d240ef30 VH |
470 | case 2: |
471 | /* FALLTHROUGH */ | |
472 | default: | |
473 | omap_revision = AM335X_REV_ES2_1; | |
474 | cpu_rev = "2.1"; | |
475 | break; | |
5af044f4 | 476 | } |
c2d13554 | 477 | break; |
c04bbaa4 | 478 | case 0xb98c: |
4a2ed4c0 LV |
479 | switch (rev) { |
480 | case 0: | |
481 | omap_revision = AM437X_REV_ES1_0; | |
482 | cpu_rev = "1.0"; | |
483 | break; | |
484 | case 1: | |
4a2ed4c0 LV |
485 | omap_revision = AM437X_REV_ES1_1; |
486 | cpu_rev = "1.1"; | |
487 | break; | |
4fdd54f0 LV |
488 | case 2: |
489 | /* FALLTHROUGH */ | |
490 | default: | |
491 | omap_revision = AM437X_REV_ES1_2; | |
492 | cpu_rev = "1.2"; | |
493 | break; | |
4a2ed4c0 | 494 | } |
c04bbaa4 | 495 | break; |
4390f5b2 | 496 | case 0xb8f2: |
68b813bf | 497 | case 0xb968: |
4390f5b2 HP |
498 | switch (rev) { |
499 | case 0: | |
500 | /* FALLTHROUGH */ | |
501 | case 1: | |
502 | omap_revision = TI8148_REV_ES1_0; | |
50a01e64 | 503 | cpu_rev = "1.0"; |
4390f5b2 HP |
504 | break; |
505 | case 2: | |
506 | omap_revision = TI8148_REV_ES2_0; | |
50a01e64 | 507 | cpu_rev = "2.0"; |
4390f5b2 HP |
508 | break; |
509 | case 3: | |
510 | /* FALLTHROUGH */ | |
511 | default: | |
512 | omap_revision = TI8148_REV_ES2_1; | |
50a01e64 | 513 | cpu_rev = "2.1"; |
4390f5b2 HP |
514 | break; |
515 | } | |
1e6cb146 | 516 | break; |
2456a10f | 517 | default: |
51ec811a | 518 | /* Unknown default to latest silicon rev as default */ |
3b32b7d6 | 519 | omap_revision = OMAP3630_REV_ES1_2; |
50a01e64 | 520 | cpu_rev = "1.2"; |
68b813bf TL |
521 | pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n", |
522 | hawkeye); | |
a8823143 | 523 | } |
f9d41eef | 524 | sprintf(soc_rev, "ES%s", cpu_rev); |
1dbae815 TL |
525 | } |
526 | ||
4de34f35 | 527 | void __init omap4xxx_check_revision(void) |
b570e0ec SS |
528 | { |
529 | u32 idcode; | |
530 | u16 hawkeye; | |
531 | u8 rev; | |
b570e0ec SS |
532 | |
533 | /* | |
534 | * The IC rev detection is done with hawkeye and rev. | |
535 | * Note that rev does not map directly to defined processor | |
536 | * revision numbers as ES1.0 uses value 0. | |
537 | */ | |
538 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
539 | hawkeye = (idcode >> 12) & 0xffff; | |
e49c4d27 | 540 | rev = (idcode >> 28) & 0xf; |
b570e0ec | 541 | |
ed6be0ba | 542 | /* |
fa54dccd | 543 | * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 |
ed6be0ba SS |
544 | * Use ARM register to detect the correct ES version |
545 | */ | |
ec023e46 | 546 | if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { |
ac52e83f | 547 | idcode = read_cpuid_id(); |
ed6be0ba SS |
548 | rev = (idcode & 0xf) - 1; |
549 | } | |
550 | ||
551 | switch (hawkeye) { | |
552 | case 0xb852: | |
553 | switch (rev) { | |
554 | case 0: | |
555 | omap_revision = OMAP4430_REV_ES1_0; | |
ed6be0ba SS |
556 | break; |
557 | case 1: | |
e49c4d27 | 558 | default: |
ed6be0ba | 559 | omap_revision = OMAP4430_REV_ES2_0; |
e49c4d27 NK |
560 | } |
561 | break; | |
562 | case 0xb95c: | |
563 | switch (rev) { | |
564 | case 3: | |
565 | omap_revision = OMAP4430_REV_ES2_1; | |
ed6be0ba | 566 | break; |
e49c4d27 | 567 | case 4: |
e49c4d27 | 568 | omap_revision = OMAP4430_REV_ES2_2; |
55035c15 DA |
569 | break; |
570 | case 6: | |
571 | default: | |
572 | omap_revision = OMAP4430_REV_ES2_3; | |
e49c4d27 NK |
573 | } |
574 | break; | |
fa54dccd A |
575 | case 0xb94e: |
576 | switch (rev) { | |
577 | case 0: | |
fa54dccd | 578 | omap_revision = OMAP4460_REV_ES1_0; |
fa54dccd | 579 | break; |
33ee0db5 CL |
580 | case 2: |
581 | default: | |
582 | omap_revision = OMAP4460_REV_ES1_1; | |
583 | break; | |
fa54dccd A |
584 | } |
585 | break; | |
ec023e46 LI |
586 | case 0xb975: |
587 | switch (rev) { | |
588 | case 0: | |
589 | default: | |
590 | omap_revision = OMAP4470_REV_ES1_0; | |
591 | break; | |
592 | } | |
593 | break; | |
ed6be0ba | 594 | default: |
e49c4d27 | 595 | /* Unknown default to latest silicon rev as default */ |
55035c15 | 596 | omap_revision = OMAP4430_REV_ES2_3; |
b570e0ec SS |
597 | } |
598 | ||
f9d41eef RB |
599 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
600 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
601 | (omap_rev() >> 8) & 0xf); | |
602 | pr_info("%s %s\n", soc_name, soc_rev); | |
b570e0ec SS |
603 | } |
604 | ||
b13e80a8 S |
605 | void __init omap5xxx_check_revision(void) |
606 | { | |
607 | u32 idcode; | |
608 | u16 hawkeye; | |
609 | u8 rev; | |
610 | ||
611 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
612 | hawkeye = (idcode >> 12) & 0xffff; | |
613 | rev = (idcode >> 28) & 0xff; | |
614 | switch (hawkeye) { | |
615 | case 0xb942: | |
616 | switch (rev) { | |
617 | case 0: | |
aa2f4b16 NM |
618 | /* No support for ES1.0 Test chip */ |
619 | BUG(); | |
5a898a78 SS |
620 | case 1: |
621 | default: | |
622 | omap_revision = OMAP5430_REV_ES2_0; | |
b13e80a8 S |
623 | } |
624 | break; | |
625 | ||
626 | case 0xb998: | |
627 | switch (rev) { | |
628 | case 0: | |
aa2f4b16 NM |
629 | /* No support for ES1.0 Test chip */ |
630 | BUG(); | |
5a898a78 SS |
631 | case 1: |
632 | default: | |
633 | omap_revision = OMAP5432_REV_ES2_0; | |
b13e80a8 S |
634 | } |
635 | break; | |
636 | ||
637 | default: | |
638 | /* Unknown default to latest silicon rev as default*/ | |
5a898a78 | 639 | omap_revision = OMAP5430_REV_ES2_0; |
b13e80a8 S |
640 | } |
641 | ||
f9d41eef RB |
642 | sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); |
643 | sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); | |
644 | ||
645 | pr_info("%s %s\n", soc_name, soc_rev); | |
b13e80a8 S |
646 | } |
647 | ||
733d20ee NM |
648 | void __init dra7xxx_check_revision(void) |
649 | { | |
650 | u32 idcode; | |
651 | u16 hawkeye; | |
652 | u8 rev; | |
653 | ||
654 | idcode = read_tap_reg(OMAP_TAP_IDCODE); | |
655 | hawkeye = (idcode >> 12) & 0xffff; | |
656 | rev = (idcode >> 28) & 0xff; | |
657 | switch (hawkeye) { | |
658 | case 0xb990: | |
659 | switch (rev) { | |
660 | case 0: | |
661 | omap_revision = DRA752_REV_ES1_0; | |
662 | break; | |
663 | case 1: | |
733d20ee | 664 | omap_revision = DRA752_REV_ES1_1; |
81032e34 VM |
665 | break; |
666 | case 2: | |
667 | default: | |
668 | omap_revision = DRA752_REV_ES2_0; | |
669 | break; | |
733d20ee NM |
670 | } |
671 | break; | |
672 | ||
73d20280 NM |
673 | case 0xb9bc: |
674 | switch (rev) { | |
675 | case 0: | |
676 | omap_revision = DRA722_REV_ES1_0; | |
677 | break; | |
6b532c4a | 678 | case 1: |
73d20280 | 679 | default: |
6b532c4a | 680 | omap_revision = DRA722_REV_ES2_0; |
73d20280 NM |
681 | break; |
682 | } | |
683 | break; | |
684 | ||
733d20ee NM |
685 | default: |
686 | /* Unknown default to latest silicon rev as default*/ | |
6953faf9 | 687 | pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", |
733d20ee | 688 | __func__, idcode, hawkeye, rev); |
81032e34 | 689 | omap_revision = DRA752_REV_ES2_0; |
733d20ee NM |
690 | } |
691 | ||
692 | sprintf(soc_name, "DRA%03x", omap_rev() >> 16); | |
693 | sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, | |
694 | (omap_rev() >> 8) & 0xf); | |
695 | ||
696 | pr_info("%s %s\n", soc_name, soc_rev); | |
697 | } | |
698 | ||
a8823143 TL |
699 | /* |
700 | * Set up things for map_io and processor detection later on. Gets called | |
701 | * pretty much first thing from board init. For multi-omap, this gets | |
702 | * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to | |
703 | * detect the exact revision later on in omap2_detect_revision() once map_io | |
704 | * is done. | |
705 | */ | |
b6a4226c | 706 | void __init omap2_set_globals_tap(u32 class, void __iomem *tap) |
0e564848 | 707 | { |
b6a4226c PW |
708 | omap_revision = class; |
709 | tap_base = tap; | |
0e564848 | 710 | |
b6a4226c | 711 | /* XXX What is this intended to do? */ |
3ea4a182 | 712 | if (soc_is_omap34xx()) |
0e564848 TL |
713 | tap_prod_id = 0x0210; |
714 | else | |
715 | tap_prod_id = 0x0208; | |
716 | } | |
6770b211 RB |
717 | |
718 | #ifdef CONFIG_SOC_BUS | |
719 | ||
415ab328 | 720 | static const char * const omap_types[] = { |
6770b211 RB |
721 | [OMAP2_DEVICE_TYPE_TEST] = "TST", |
722 | [OMAP2_DEVICE_TYPE_EMU] = "EMU", | |
723 | [OMAP2_DEVICE_TYPE_SEC] = "HS", | |
724 | [OMAP2_DEVICE_TYPE_GP] = "GP", | |
725 | [OMAP2_DEVICE_TYPE_BAD] = "BAD", | |
726 | }; | |
727 | ||
728 | static const char * __init omap_get_family(void) | |
729 | { | |
3ea4a182 | 730 | if (soc_is_omap24xx()) |
6770b211 | 731 | return kasprintf(GFP_KERNEL, "OMAP2"); |
3ea4a182 | 732 | else if (soc_is_omap34xx()) |
6770b211 | 733 | return kasprintf(GFP_KERNEL, "OMAP3"); |
3ea4a182 | 734 | else if (soc_is_omap44xx()) |
6770b211 RB |
735 | return kasprintf(GFP_KERNEL, "OMAP4"); |
736 | else if (soc_is_omap54xx()) | |
737 | return kasprintf(GFP_KERNEL, "OMAP5"); | |
e5ed5b60 SA |
738 | else if (soc_is_am33xx() || soc_is_am335x()) |
739 | return kasprintf(GFP_KERNEL, "AM33xx"); | |
7a2e0513 AM |
740 | else if (soc_is_am43xx()) |
741 | return kasprintf(GFP_KERNEL, "AM43xx"); | |
733d20ee NM |
742 | else if (soc_is_dra7xx()) |
743 | return kasprintf(GFP_KERNEL, "DRA7"); | |
6770b211 RB |
744 | else |
745 | return kasprintf(GFP_KERNEL, "Unknown"); | |
746 | } | |
747 | ||
748 | static ssize_t omap_get_type(struct device *dev, | |
749 | struct device_attribute *attr, | |
750 | char *buf) | |
751 | { | |
752 | return sprintf(buf, "%s\n", omap_types[omap_type()]); | |
753 | } | |
754 | ||
755 | static struct device_attribute omap_soc_attr = | |
756 | __ATTR(type, S_IRUGO, omap_get_type, NULL); | |
757 | ||
758 | void __init omap_soc_device_init(void) | |
759 | { | |
760 | struct device *parent; | |
761 | struct soc_device *soc_dev; | |
762 | struct soc_device_attribute *soc_dev_attr; | |
763 | ||
764 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
765 | if (!soc_dev_attr) | |
766 | return; | |
767 | ||
768 | soc_dev_attr->machine = soc_name; | |
769 | soc_dev_attr->family = omap_get_family(); | |
770 | soc_dev_attr->revision = soc_rev; | |
771 | ||
772 | soc_dev = soc_device_register(soc_dev_attr); | |
b1dd11d6 | 773 | if (IS_ERR(soc_dev)) { |
6770b211 RB |
774 | kfree(soc_dev_attr); |
775 | return; | |
776 | } | |
777 | ||
778 | parent = soc_device_to_device(soc_dev); | |
b1dd11d6 | 779 | device_create_file(parent, &omap_soc_attr); |
6770b211 RB |
780 | } |
781 | #endif /* CONFIG_SOC_BUS */ |