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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
45c3eb7d | 28 | #include <linux/omap-dma.h> |
ee0839c2 | 29 | |
dc843280 | 30 | #include "omap_hwmod.h" |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
81a60482 | 33 | #include "voltage.h" |
72e06d08 | 34 | #include "powerdomain.h" |
1540f214 | 35 | #include "clockdomain.h" |
4e65331c | 36 | #include "common.h" |
e30384ab | 37 | #include "clock.h" |
ee0839c2 TL |
38 | #include "clock2xxx.h" |
39 | #include "clock3xxx.h" | |
40 | #include "clock44xx.h" | |
1d5aef49 | 41 | #include "omap-pm.h" |
3e6ece13 | 42 | #include "sdrc.h" |
b6a4226c | 43 | #include "control.h" |
3d82cbbb | 44 | #include "serial.h" |
bf027ca1 | 45 | #include "sram.h" |
c4ceedcb PW |
46 | #include "cm2xxx.h" |
47 | #include "cm3xxx.h" | |
d9a16f9a PW |
48 | #include "prm.h" |
49 | #include "cm.h" | |
50 | #include "prcm_mpu44xx.h" | |
51 | #include "prminst44xx.h" | |
52 | #include "cminst44xx.h" | |
63a293e0 PW |
53 | #include "prm2xxx.h" |
54 | #include "prm3xxx.h" | |
55 | #include "prm44xx.h" | |
02bfc030 | 56 | |
1dbae815 TL |
57 | /* |
58 | * The machine specific code may provide the extra mapping besides the | |
59 | * default mapping provided here. | |
60 | */ | |
cc26b3b0 | 61 | |
e48f814e | 62 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 63 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
64 | { |
65 | .virtual = L3_24XX_VIRT, | |
66 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
67 | .length = L3_24XX_SIZE, | |
68 | .type = MT_DEVICE | |
69 | }, | |
09f21ed4 | 70 | { |
cc26b3b0 SMK |
71 | .virtual = L4_24XX_VIRT, |
72 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
73 | .length = L4_24XX_SIZE, | |
74 | .type = MT_DEVICE | |
09f21ed4 | 75 | }, |
cc26b3b0 SMK |
76 | }; |
77 | ||
59b479e0 | 78 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
79 | static struct map_desc omap242x_io_desc[] __initdata = { |
80 | { | |
7adb9987 PW |
81 | .virtual = DSP_MEM_2420_VIRT, |
82 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
83 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
84 | .type = MT_DEVICE |
85 | }, | |
86 | { | |
7adb9987 PW |
87 | .virtual = DSP_IPI_2420_VIRT, |
88 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
89 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 90 | .type = MT_DEVICE |
09f21ed4 | 91 | }, |
cc26b3b0 | 92 | { |
7adb9987 PW |
93 | .virtual = DSP_MMU_2420_VIRT, |
94 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
95 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
96 | .type = MT_DEVICE |
97 | }, | |
98 | }; | |
99 | ||
100 | #endif | |
101 | ||
59b479e0 | 102 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 103 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
104 | { |
105 | .virtual = L4_WK_243X_VIRT, | |
106 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
107 | .length = L4_WK_243X_SIZE, | |
108 | .type = MT_DEVICE | |
109 | }, | |
110 | { | |
111 | .virtual = OMAP243X_GPMC_VIRT, | |
112 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
113 | .length = OMAP243X_GPMC_SIZE, | |
114 | .type = MT_DEVICE | |
115 | }, | |
cc26b3b0 SMK |
116 | { |
117 | .virtual = OMAP243X_SDRC_VIRT, | |
118 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
119 | .length = OMAP243X_SDRC_SIZE, | |
120 | .type = MT_DEVICE | |
121 | }, | |
122 | { | |
123 | .virtual = OMAP243X_SMS_VIRT, | |
124 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
125 | .length = OMAP243X_SMS_SIZE, | |
126 | .type = MT_DEVICE | |
127 | }, | |
128 | }; | |
72d0f1c3 | 129 | #endif |
72d0f1c3 | 130 | #endif |
cc26b3b0 | 131 | |
a8eb7ca0 | 132 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 133 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 134 | { |
cc26b3b0 SMK |
135 | .virtual = L3_34XX_VIRT, |
136 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
137 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
138 | .type = MT_DEVICE |
139 | }, | |
140 | { | |
cc26b3b0 SMK |
141 | .virtual = L4_34XX_VIRT, |
142 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
143 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
144 | .type = MT_DEVICE |
145 | }, | |
cc26b3b0 SMK |
146 | { |
147 | .virtual = OMAP34XX_GPMC_VIRT, | |
148 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
149 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 150 | .type = MT_DEVICE |
cc26b3b0 SMK |
151 | }, |
152 | { | |
153 | .virtual = OMAP343X_SMS_VIRT, | |
154 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
155 | .length = OMAP343X_SMS_SIZE, | |
156 | .type = MT_DEVICE | |
157 | }, | |
158 | { | |
159 | .virtual = OMAP343X_SDRC_VIRT, | |
160 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
161 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 162 | .type = MT_DEVICE |
cc26b3b0 SMK |
163 | }, |
164 | { | |
165 | .virtual = L4_PER_34XX_VIRT, | |
166 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
167 | .length = L4_PER_34XX_SIZE, | |
168 | .type = MT_DEVICE | |
169 | }, | |
170 | { | |
171 | .virtual = L4_EMU_34XX_VIRT, | |
172 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
173 | .length = L4_EMU_34XX_SIZE, | |
174 | .type = MT_DEVICE | |
175 | }, | |
a4f57b81 TL |
176 | #if defined(CONFIG_DEBUG_LL) && \ |
177 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
178 | { | |
179 | .virtual = ZOOM_UART_VIRT, | |
180 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
181 | .length = SZ_1M, | |
182 | .type = MT_DEVICE | |
183 | }, | |
184 | #endif | |
1dbae815 | 185 | }; |
cc26b3b0 | 186 | #endif |
01001712 | 187 | |
33959553 | 188 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 189 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
190 | { |
191 | .virtual = L4_34XX_VIRT, | |
192 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
193 | .length = L4_34XX_SIZE, | |
194 | .type = MT_DEVICE | |
195 | } | |
196 | }; | |
197 | #endif | |
198 | ||
bb6abcf4 | 199 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 200 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
201 | { |
202 | .virtual = L4_34XX_VIRT, | |
203 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
204 | .length = L4_34XX_SIZE, | |
205 | .type = MT_DEVICE | |
206 | }, | |
1e6cb146 AM |
207 | { |
208 | .virtual = L4_WK_AM33XX_VIRT, | |
209 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
210 | .length = L4_WK_AM33XX_SIZE, | |
211 | .type = MT_DEVICE | |
212 | } | |
01001712 HP |
213 | }; |
214 | #endif | |
215 | ||
44169075 SS |
216 | #ifdef CONFIG_ARCH_OMAP4 |
217 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
218 | { | |
219 | .virtual = L3_44XX_VIRT, | |
220 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
221 | .length = L3_44XX_SIZE, | |
222 | .type = MT_DEVICE, | |
223 | }, | |
224 | { | |
225 | .virtual = L4_44XX_VIRT, | |
226 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
227 | .length = L4_44XX_SIZE, | |
228 | .type = MT_DEVICE, | |
229 | }, | |
44169075 SS |
230 | { |
231 | .virtual = L4_PER_44XX_VIRT, | |
232 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
233 | .length = L4_PER_44XX_SIZE, | |
234 | .type = MT_DEVICE, | |
235 | }, | |
137d105d SS |
236 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
237 | { | |
238 | .virtual = OMAP4_SRAM_VA, | |
239 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | |
240 | .length = PAGE_SIZE, | |
241 | .type = MT_MEMORY_SO, | |
242 | }, | |
243 | #endif | |
244 | ||
44169075 SS |
245 | }; |
246 | #endif | |
1dbae815 | 247 | |
05e152c7 S |
248 | #ifdef CONFIG_SOC_OMAP5 |
249 | static struct map_desc omap54xx_io_desc[] __initdata = { | |
250 | { | |
251 | .virtual = L3_54XX_VIRT, | |
252 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
253 | .length = L3_54XX_SIZE, | |
254 | .type = MT_DEVICE, | |
255 | }, | |
256 | { | |
257 | .virtual = L4_54XX_VIRT, | |
258 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
259 | .length = L4_54XX_SIZE, | |
260 | .type = MT_DEVICE, | |
261 | }, | |
262 | { | |
263 | .virtual = L4_WK_54XX_VIRT, | |
264 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
265 | .length = L4_WK_54XX_SIZE, | |
266 | .type = MT_DEVICE, | |
267 | }, | |
268 | { | |
269 | .virtual = L4_PER_54XX_VIRT, | |
270 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
271 | .length = L4_PER_54XX_SIZE, | |
272 | .type = MT_DEVICE, | |
273 | }, | |
274 | }; | |
275 | #endif | |
276 | ||
59b479e0 | 277 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 278 | void __init omap242x_map_io(void) |
1dbae815 | 279 | { |
cc26b3b0 SMK |
280 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
281 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 282 | } |
cc26b3b0 SMK |
283 | #endif |
284 | ||
59b479e0 | 285 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 286 | void __init omap243x_map_io(void) |
6fbd55d0 | 287 | { |
cc26b3b0 SMK |
288 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
289 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 290 | } |
cc26b3b0 SMK |
291 | #endif |
292 | ||
a8eb7ca0 | 293 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 294 | void __init omap3_map_io(void) |
6fbd55d0 | 295 | { |
cc26b3b0 | 296 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 297 | } |
cc26b3b0 | 298 | #endif |
120db2cb | 299 | |
33959553 | 300 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 301 | void __init ti81xx_map_io(void) |
01001712 | 302 | { |
a920360f | 303 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
304 | } |
305 | #endif | |
306 | ||
bb6abcf4 | 307 | #ifdef CONFIG_SOC_AM33XX |
b6a4226c | 308 | void __init am33xx_map_io(void) |
01001712 | 309 | { |
1e6cb146 | 310 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
311 | } |
312 | #endif | |
313 | ||
6fbd55d0 | 314 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 315 | void __init omap4_map_io(void) |
6fbd55d0 | 316 | { |
44169075 | 317 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 318 | omap_barriers_init(); |
120db2cb | 319 | } |
6fbd55d0 | 320 | #endif |
120db2cb | 321 | |
05e152c7 | 322 | #ifdef CONFIG_SOC_OMAP5 |
b6a4226c | 323 | void __init omap5_map_io(void) |
05e152c7 S |
324 | { |
325 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
326 | } | |
327 | #endif | |
2f135eaf PW |
328 | /* |
329 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
330 | * | |
331 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
332 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
333 | * registers to the values currently defined by the kernel. Currently | |
334 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
335 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
336 | * or passes along the return value of clk_set_rate(). | |
337 | */ | |
338 | static int __init _omap2_init_reprogram_sdrc(void) | |
339 | { | |
340 | struct clk *dpll3_m2_ck; | |
341 | int v = -EINVAL; | |
342 | long rate; | |
343 | ||
344 | if (!cpu_is_omap34xx()) | |
345 | return 0; | |
346 | ||
347 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 348 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
349 | return -EINVAL; |
350 | ||
351 | rate = clk_get_rate(dpll3_m2_ck); | |
352 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
353 | v = clk_set_rate(dpll3_m2_ck, rate); | |
354 | if (v) | |
355 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
356 | ||
357 | clk_put(dpll3_m2_ck); | |
358 | ||
359 | return v; | |
360 | } | |
361 | ||
2092e5cc PW |
362 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
363 | { | |
364 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
365 | } | |
366 | ||
7b250aff TL |
367 | static void __init omap_hwmod_init_postsetup(void) |
368 | { | |
369 | u8 postsetup_state; | |
2092e5cc PW |
370 | |
371 | /* Set the default postsetup state for all hwmods */ | |
372 | #ifdef CONFIG_PM_RUNTIME | |
373 | postsetup_state = _HWMOD_STATE_IDLE; | |
374 | #else | |
375 | postsetup_state = _HWMOD_STATE_ENABLED; | |
376 | #endif | |
377 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 378 | |
53da4ce2 | 379 | omap_pm_if_early_init(); |
4805734b PW |
380 | } |
381 | ||
16110798 | 382 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
383 | void __init omap2420_init_early(void) |
384 | { | |
b6a4226c PW |
385 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
386 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
387 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
388 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), | |
389 | NULL); | |
d9a16f9a PW |
390 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); |
391 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); | |
4de34f35 | 392 | omap2xxx_check_revision(); |
63a293e0 | 393 | omap2xxx_prm_init(); |
c4ceedcb | 394 | omap2xxx_cm_init(); |
7b250aff TL |
395 | omap2xxx_voltagedomains_init(); |
396 | omap242x_powerdomains_init(); | |
397 | omap242x_clockdomains_init(); | |
398 | omap2420_hwmod_init(); | |
399 | omap_hwmod_init_postsetup(); | |
400 | omap2420_clk_init(); | |
8f5b5a41 | 401 | } |
bbd707ac SG |
402 | |
403 | void __init omap2420_init_late(void) | |
404 | { | |
405 | omap_mux_late_init(); | |
406 | omap2_common_pm_late_init(); | |
407 | omap2_pm_init(); | |
23fb8ba3 | 408 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 409 | } |
16110798 | 410 | #endif |
8f5b5a41 | 411 | |
16110798 | 412 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
413 | void __init omap2430_init_early(void) |
414 | { | |
b6a4226c PW |
415 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
416 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
417 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
418 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | |
419 | NULL); | |
d9a16f9a PW |
420 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); |
421 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); | |
4de34f35 | 422 | omap2xxx_check_revision(); |
63a293e0 | 423 | omap2xxx_prm_init(); |
c4ceedcb | 424 | omap2xxx_cm_init(); |
7b250aff TL |
425 | omap2xxx_voltagedomains_init(); |
426 | omap243x_powerdomains_init(); | |
427 | omap243x_clockdomains_init(); | |
428 | omap2430_hwmod_init(); | |
429 | omap_hwmod_init_postsetup(); | |
430 | omap2430_clk_init(); | |
431 | } | |
bbd707ac SG |
432 | |
433 | void __init omap2430_init_late(void) | |
434 | { | |
435 | omap_mux_late_init(); | |
436 | omap2_common_pm_late_init(); | |
437 | omap2_pm_init(); | |
23fb8ba3 | 438 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 439 | } |
c4e2d245 | 440 | #endif |
7b250aff TL |
441 | |
442 | /* | |
443 | * Currently only board-omap3beagle.c should call this because of the | |
444 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
445 | */ | |
c4e2d245 | 446 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
447 | void __init omap3_init_early(void) |
448 | { | |
b6a4226c PW |
449 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
450 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
451 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
452 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | |
453 | NULL); | |
d9a16f9a PW |
454 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
455 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); | |
4de34f35 VH |
456 | omap3xxx_check_revision(); |
457 | omap3xxx_check_features(); | |
63a293e0 | 458 | omap3xxx_prm_init(); |
c4ceedcb | 459 | omap3xxx_cm_init(); |
7b250aff TL |
460 | omap3xxx_voltagedomains_init(); |
461 | omap3xxx_powerdomains_init(); | |
462 | omap3xxx_clockdomains_init(); | |
463 | omap3xxx_hwmod_init(); | |
464 | omap_hwmod_init_postsetup(); | |
465 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
466 | } |
467 | ||
468 | void __init omap3430_init_early(void) | |
469 | { | |
7b250aff | 470 | omap3_init_early(); |
8f5b5a41 TL |
471 | } |
472 | ||
473 | void __init omap35xx_init_early(void) | |
474 | { | |
7b250aff | 475 | omap3_init_early(); |
8f5b5a41 TL |
476 | } |
477 | ||
478 | void __init omap3630_init_early(void) | |
479 | { | |
7b250aff | 480 | omap3_init_early(); |
8f5b5a41 TL |
481 | } |
482 | ||
483 | void __init am35xx_init_early(void) | |
484 | { | |
7b250aff | 485 | omap3_init_early(); |
8f5b5a41 TL |
486 | } |
487 | ||
a920360f | 488 | void __init ti81xx_init_early(void) |
8f5b5a41 | 489 | { |
b6a4226c PW |
490 | omap2_set_globals_tap(OMAP343X_CLASS, |
491 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
492 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), | |
493 | NULL); | |
d9a16f9a PW |
494 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); |
495 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); | |
4de34f35 VH |
496 | omap3xxx_check_revision(); |
497 | ti81xx_check_features(); | |
4c3cf901 TL |
498 | omap3xxx_voltagedomains_init(); |
499 | omap3xxx_powerdomains_init(); | |
500 | omap3xxx_clockdomains_init(); | |
501 | omap3xxx_hwmod_init(); | |
502 | omap_hwmod_init_postsetup(); | |
503 | omap3xxx_clk_init(); | |
8f5b5a41 | 504 | } |
bbd707ac SG |
505 | |
506 | void __init omap3_init_late(void) | |
507 | { | |
508 | omap_mux_late_init(); | |
509 | omap2_common_pm_late_init(); | |
510 | omap3_pm_init(); | |
23fb8ba3 | 511 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
512 | } |
513 | ||
514 | void __init omap3430_init_late(void) | |
515 | { | |
516 | omap_mux_late_init(); | |
517 | omap2_common_pm_late_init(); | |
518 | omap3_pm_init(); | |
23fb8ba3 | 519 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
520 | } |
521 | ||
522 | void __init omap35xx_init_late(void) | |
523 | { | |
524 | omap_mux_late_init(); | |
525 | omap2_common_pm_late_init(); | |
526 | omap3_pm_init(); | |
23fb8ba3 | 527 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
528 | } |
529 | ||
530 | void __init omap3630_init_late(void) | |
531 | { | |
532 | omap_mux_late_init(); | |
533 | omap2_common_pm_late_init(); | |
534 | omap3_pm_init(); | |
23fb8ba3 | 535 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
536 | } |
537 | ||
538 | void __init am35xx_init_late(void) | |
539 | { | |
540 | omap_mux_late_init(); | |
541 | omap2_common_pm_late_init(); | |
542 | omap3_pm_init(); | |
23fb8ba3 | 543 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
544 | } |
545 | ||
546 | void __init ti81xx_init_late(void) | |
547 | { | |
548 | omap_mux_late_init(); | |
549 | omap2_common_pm_late_init(); | |
550 | omap3_pm_init(); | |
23fb8ba3 | 551 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 552 | } |
c4e2d245 | 553 | #endif |
8f5b5a41 | 554 | |
08f30989 AM |
555 | #ifdef CONFIG_SOC_AM33XX |
556 | void __init am33xx_init_early(void) | |
557 | { | |
b6a4226c PW |
558 | omap2_set_globals_tap(AM335X_CLASS, |
559 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
560 | omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), | |
561 | NULL); | |
d9a16f9a PW |
562 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); |
563 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); | |
08f30989 AM |
564 | omap3xxx_check_revision(); |
565 | ti81xx_check_features(); | |
ce3fc89a | 566 | am33xx_voltagedomains_init(); |
3f0ea764 | 567 | am33xx_powerdomains_init(); |
9c80f3aa | 568 | am33xx_clockdomains_init(); |
a2cfc509 VH |
569 | am33xx_hwmod_init(); |
570 | omap_hwmod_init_postsetup(); | |
e30384ab | 571 | am33xx_clk_init(); |
08f30989 AM |
572 | } |
573 | #endif | |
574 | ||
c4e2d245 | 575 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
576 | void __init omap4430_init_early(void) |
577 | { | |
b6a4226c PW |
578 | omap2_set_globals_tap(OMAP443X_CLASS, |
579 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
580 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), | |
581 | OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); | |
d9a16f9a PW |
582 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); |
583 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | |
584 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); | |
585 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); | |
586 | omap_prm_base_init(); | |
587 | omap_cm_base_init(); | |
4de34f35 VH |
588 | omap4xxx_check_revision(); |
589 | omap4xxx_check_features(); | |
63a293e0 | 590 | omap44xx_prm_init(); |
7b250aff TL |
591 | omap44xx_voltagedomains_init(); |
592 | omap44xx_powerdomains_init(); | |
593 | omap44xx_clockdomains_init(); | |
594 | omap44xx_hwmod_init(); | |
595 | omap_hwmod_init_postsetup(); | |
596 | omap4xxx_clk_init(); | |
8f5b5a41 | 597 | } |
bbd707ac SG |
598 | |
599 | void __init omap4430_init_late(void) | |
600 | { | |
601 | omap_mux_late_init(); | |
602 | omap2_common_pm_late_init(); | |
603 | omap4_pm_init(); | |
23fb8ba3 | 604 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 605 | } |
c4e2d245 | 606 | #endif |
8f5b5a41 | 607 | |
05e152c7 S |
608 | #ifdef CONFIG_SOC_OMAP5 |
609 | void __init omap5_init_early(void) | |
610 | { | |
b6a4226c PW |
611 | omap2_set_globals_tap(OMAP54XX_CLASS, |
612 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
613 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | |
614 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); | |
d9a16f9a PW |
615 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); |
616 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), | |
617 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | |
618 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | |
619 | omap_prm_base_init(); | |
620 | omap_cm_base_init(); | |
05e152c7 | 621 | omap5xxx_check_revision(); |
05e152c7 S |
622 | } |
623 | #endif | |
624 | ||
a4ca9dbe | 625 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
626 | struct omap_sdrc_params *sdrc_cs1) |
627 | { | |
a66cb345 TL |
628 | omap_sram_init(); |
629 | ||
01001712 | 630 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
631 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
632 | _omap2_init_reprogram_sdrc(); | |
633 | } | |
1dbae815 | 634 | } |