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ARM: DRA7: PRM: add voltage processor check behind a prm_feature flag
[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
1d5aef49 41#include "omap-pm.h"
3e6ece13 42#include "sdrc.h"
b6a4226c 43#include "control.h"
3d82cbbb 44#include "serial.h"
bf027ca1 45#include "sram.h"
c4ceedcb
PW		 46#include "cm2xxx.h"
47#include "cm3xxx.h"
d9a16f9a
PW		 48#include "prm.h"
49#include "cm.h"
50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
63a293e0
PW		 53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
69a1e7a1 56#include "opp2xxx.h"
02bfc030 57
ff931c82 58/*
cfa9667d 59 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 60 * clock initializations
61 */
cfa9667d 62static int (*omap_clk_soc_init)(void);
ff931c82 63
1dbae815
TL		 64/*
65 * The machine specific code may provide the extra mapping besides the
66 * default mapping provided here.
67 */
cc26b3b0 68
e48f814e 69#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 70static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 71 {
72 .virtual = L3_24XX_VIRT,
73 .pfn = __phys_to_pfn(L3_24XX_PHYS),
74 .length = L3_24XX_SIZE,
75 .type = MT_DEVICE
76 },
09f21ed4 77 {
cc26b3b0
SMK		 78 .virtual = L4_24XX_VIRT,
79 .pfn = __phys_to_pfn(L4_24XX_PHYS),
80 .length = L4_24XX_SIZE,
81 .type = MT_DEVICE
09f21ed4 82 },
cc26b3b0
SMK		 83};
84
59b479e0 85#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 86static struct map_desc omap242x_io_desc[] __initdata = {
87 {
7adb9987
PW		 88 .virtual = DSP_MEM_2420_VIRT,
89 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
90 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 91 .type = MT_DEVICE
92 },
93 {
7adb9987
PW		 94 .virtual = DSP_IPI_2420_VIRT,
95 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
96 .length = DSP_IPI_2420_SIZE,
cc26b3b0 97 .type = MT_DEVICE
09f21ed4 98 },
cc26b3b0 99 {
7adb9987
PW		 100 .virtual = DSP_MMU_2420_VIRT,
101 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
102 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 103 .type = MT_DEVICE
104 },
105};
106
107#endif
108
59b479e0 109#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 110static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 111 {
112 .virtual = L4_WK_243X_VIRT,
113 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
114 .length = L4_WK_243X_SIZE,
115 .type = MT_DEVICE
116 },
117 {
118 .virtual = OMAP243X_GPMC_VIRT,
119 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
120 .length = OMAP243X_GPMC_SIZE,
121 .type = MT_DEVICE
122 },
cc26b3b0
SMK		 123 {
124 .virtual = OMAP243X_SDRC_VIRT,
125 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
126 .length = OMAP243X_SDRC_SIZE,
127 .type = MT_DEVICE
128 },
129 {
130 .virtual = OMAP243X_SMS_VIRT,
131 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
132 .length = OMAP243X_SMS_SIZE,
133 .type = MT_DEVICE
134 },
135};
72d0f1c3 136#endif
72d0f1c3 137#endif
cc26b3b0 138
a8eb7ca0 139#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 140static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 141 {
cc26b3b0
SMK		 142 .virtual = L3_34XX_VIRT,
143 .pfn = __phys_to_pfn(L3_34XX_PHYS),
144 .length = L3_34XX_SIZE,
c40fae95
TL		 145 .type = MT_DEVICE
146 },
147 {
cc26b3b0
SMK		 148 .virtual = L4_34XX_VIRT,
149 .pfn = __phys_to_pfn(L4_34XX_PHYS),
150 .length = L4_34XX_SIZE,
c40fae95
TL		 151 .type = MT_DEVICE
152 },
cc26b3b0
SMK		 153 {
154 .virtual = OMAP34XX_GPMC_VIRT,
155 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
156 .length = OMAP34XX_GPMC_SIZE,
1dbae815 157 .type = MT_DEVICE
cc26b3b0
SMK		 158 },
159 {
160 .virtual = OMAP343X_SMS_VIRT,
161 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
162 .length = OMAP343X_SMS_SIZE,
163 .type = MT_DEVICE
164 },
165 {
166 .virtual = OMAP343X_SDRC_VIRT,
167 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
168 .length = OMAP343X_SDRC_SIZE,
1dbae815 169 .type = MT_DEVICE
cc26b3b0
SMK		 170 },
171 {
172 .virtual = L4_PER_34XX_VIRT,
173 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
174 .length = L4_PER_34XX_SIZE,
175 .type = MT_DEVICE
176 },
177 {
178 .virtual = L4_EMU_34XX_VIRT,
179 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
180 .length = L4_EMU_34XX_SIZE,
181 .type = MT_DEVICE
182 },
1dbae815 183};
cc26b3b0 184#endif
01001712 185
33959553 186#ifdef CONFIG_SOC_TI81XX
a920360f 187static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 188 {
189 .virtual = L4_34XX_VIRT,
190 .pfn = __phys_to_pfn(L4_34XX_PHYS),
191 .length = L4_34XX_SIZE,
192 .type = MT_DEVICE
193 }
194};
195#endif
196
addb154a 197#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 198static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 199 {
200 .virtual = L4_34XX_VIRT,
201 .pfn = __phys_to_pfn(L4_34XX_PHYS),
202 .length = L4_34XX_SIZE,
203 .type = MT_DEVICE
204 },
1e6cb146
AM		 205 {
206 .virtual = L4_WK_AM33XX_VIRT,
207 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
208 .length = L4_WK_AM33XX_SIZE,
209 .type = MT_DEVICE
210 }
01001712
HP		 211};
212#endif
213
44169075
SS		 214#ifdef CONFIG_ARCH_OMAP4
215static struct map_desc omap44xx_io_desc[] __initdata = {
216 {
217 .virtual = L3_44XX_VIRT,
218 .pfn = __phys_to_pfn(L3_44XX_PHYS),
219 .length = L3_44XX_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
223 .virtual = L4_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_44XX_PHYS),
225 .length = L4_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
44169075
SS		 228 {
229 .virtual = L4_PER_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
231 .length = L4_PER_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
44169075
SS		 234};
235#endif
1dbae815 236
a3a9384a 237#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
05e152c7
S		 238static struct map_desc omap54xx_io_desc[] __initdata = {
239 {
240 .virtual = L3_54XX_VIRT,
241 .pfn = __phys_to_pfn(L3_54XX_PHYS),
242 .length = L3_54XX_SIZE,
243 .type = MT_DEVICE,
244 },
245 {
246 .virtual = L4_54XX_VIRT,
247 .pfn = __phys_to_pfn(L4_54XX_PHYS),
248 .length = L4_54XX_SIZE,
249 .type = MT_DEVICE,
250 },
251 {
252 .virtual = L4_WK_54XX_VIRT,
253 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
254 .length = L4_WK_54XX_SIZE,
255 .type = MT_DEVICE,
256 },
257 {
258 .virtual = L4_PER_54XX_VIRT,
259 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
260 .length = L4_PER_54XX_SIZE,
261 .type = MT_DEVICE,
262 },
263};
264#endif
265
59b479e0 266#ifdef CONFIG_SOC_OMAP2420
b6a4226c 267void __init omap242x_map_io(void)
1dbae815 268{
cc26b3b0
SMK		 269 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
270 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 271}
cc26b3b0
SMK		 272#endif
273
59b479e0 274#ifdef CONFIG_SOC_OMAP2430
b6a4226c 275void __init omap243x_map_io(void)
6fbd55d0 276{
cc26b3b0
SMK		 277 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
278 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 279}
cc26b3b0
SMK		 280#endif
281
a8eb7ca0 282#ifdef CONFIG_ARCH_OMAP3
b6a4226c 283void __init omap3_map_io(void)
6fbd55d0 284{
cc26b3b0 285 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 286}
cc26b3b0 287#endif
120db2cb 288
33959553 289#ifdef CONFIG_SOC_TI81XX
b6a4226c 290void __init ti81xx_map_io(void)
01001712 291{
a920360f 292 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 293}
294#endif
295
addb154a 296#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 297void __init am33xx_map_io(void)
01001712 298{
1e6cb146 299 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 300}
301#endif
302
6fbd55d0 303#ifdef CONFIG_ARCH_OMAP4
b6a4226c 304void __init omap4_map_io(void)
6fbd55d0 305{
44169075 306 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 307 omap_barriers_init();
120db2cb 308}
6fbd55d0 309#endif
120db2cb 310
a3a9384a 311#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
b6a4226c 312void __init omap5_map_io(void)
05e152c7
S		 313{
314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
1348bbf9 315 omap_barriers_init();
05e152c7
S		 316}
317#endif
2f135eaf
PW		 318/*
319 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
320 *
321 * Sets the CORE DPLL3 M2 divider to the same value that it's at
322 * currently. This has the effect of setting the SDRC SDRAM AC timing
323 * registers to the values currently defined by the kernel. Currently
324 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
325 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
326 * or passes along the return value of clk_set_rate().
327 */
328static int __init _omap2_init_reprogram_sdrc(void)
329{
330 struct clk *dpll3_m2_ck;
331 int v = -EINVAL;
332 long rate;
333
334 if (!cpu_is_omap34xx())
335 return 0;
336
337 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 338 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 339 return -EINVAL;
340
341 rate = clk_get_rate(dpll3_m2_ck);
342 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
343 v = clk_set_rate(dpll3_m2_ck, rate);
344 if (v)
345 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
346
347 clk_put(dpll3_m2_ck);
348
349 return v;
350}
351
2092e5cc
PW		 352static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
353{
354 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
355}
356
7b250aff
TL		 357static void __init omap_hwmod_init_postsetup(void)
358{
359 u8 postsetup_state;
2092e5cc
PW		 360
361 /* Set the default postsetup state for all hwmods */
362#ifdef CONFIG_PM_RUNTIME
363 postsetup_state = _HWMOD_STATE_IDLE;
364#else
365 postsetup_state = _HWMOD_STATE_ENABLED;
366#endif
367 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 368
53da4ce2 369 omap_pm_if_early_init();
4805734b
PW		 370}
371
069d0a78 372static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 373{
374 omap_mux_late_init();
375 omap2_common_pm_late_init();
6770b211 376 omap_soc_device_init();
4ed12be0
RB		 377}
378
16110798 379#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 380void __init omap2420_init_early(void)
381{
b6a4226c
PW		 382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
385 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
386 NULL);
d9a16f9a
PW		 387 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
388 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
4de34f35 389 omap2xxx_check_revision();
63a293e0 390 omap2xxx_prm_init();
c4ceedcb 391 omap2xxx_cm_init();
7b250aff
TL		 392 omap2xxx_voltagedomains_init();
393 omap242x_powerdomains_init();
394 omap242x_clockdomains_init();
395 omap2420_hwmod_init();
396 omap_hwmod_init_postsetup();
6a194a6e
TK		 397 omap_clk_soc_init = omap2420_dt_clk_init;
398 rate_table = omap2420_rate_table;
8f5b5a41 399}
bbd707ac
SG		 400
401void __init omap2420_init_late(void)
402{
4ed12be0 403 omap_common_late_init();
bbd707ac 404 omap2_pm_init();
23fb8ba3 405 omap2_clk_enable_autoidle_all();
bbd707ac 406}
16110798 407#endif
8f5b5a41 408
16110798 409#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 410void __init omap2430_init_early(void)
411{
b6a4226c
PW		 412 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
413 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
414 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
415 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
416 NULL);
d9a16f9a
PW		 417 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
418 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
4de34f35 419 omap2xxx_check_revision();
63a293e0 420 omap2xxx_prm_init();
c4ceedcb 421 omap2xxx_cm_init();
7b250aff
TL		 422 omap2xxx_voltagedomains_init();
423 omap243x_powerdomains_init();
424 omap243x_clockdomains_init();
425 omap2430_hwmod_init();
426 omap_hwmod_init_postsetup();
6a194a6e
TK		 427 omap_clk_soc_init = omap2430_dt_clk_init;
428 rate_table = omap2430_rate_table;
7b250aff 429}
bbd707ac
SG		 430
431void __init omap2430_init_late(void)
432{
4ed12be0 433 omap_common_late_init();
bbd707ac 434 omap2_pm_init();
23fb8ba3 435 omap2_clk_enable_autoidle_all();
bbd707ac 436}
c4e2d245 437#endif
7b250aff
TL		 438
439/*
440 * Currently only board-omap3beagle.c should call this because of the
441 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
442 */
c4e2d245 443#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 444void __init omap3_init_early(void)
445{
b6a4226c
PW		 446 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
447 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
448 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
449 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
450 NULL);
d9a16f9a
PW		 451 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
452 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
4de34f35
VH		 453 omap3xxx_check_revision();
454 omap3xxx_check_features();
63a293e0 455 omap3xxx_prm_init();
c4ceedcb 456 omap3xxx_cm_init();
7b250aff
TL		 457 omap3xxx_voltagedomains_init();
458 omap3xxx_powerdomains_init();
459 omap3xxx_clockdomains_init();
460 omap3xxx_hwmod_init();
461 omap_hwmod_init_postsetup();
cfa9667d 462 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41
TL		 463}
464
465void __init omap3430_init_early(void)
466{
7b250aff 467 omap3_init_early();
3e049157
TK		 468 if (of_have_populated_dt())
469 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 470}
471
472void __init omap35xx_init_early(void)
473{
7b250aff 474 omap3_init_early();
3e049157
TK		 475 if (of_have_populated_dt())
476 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 477}
478
479void __init omap3630_init_early(void)
480{
7b250aff 481 omap3_init_early();
3e049157
TK		 482 if (of_have_populated_dt())
483 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 484}
485
486void __init am35xx_init_early(void)
487{
7b250aff 488 omap3_init_early();
3e049157
TK		 489 if (of_have_populated_dt())
490 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 491}
492
a920360f 493void __init ti81xx_init_early(void)
8f5b5a41 494{
b6a4226c
PW		 495 omap2_set_globals_tap(OMAP343X_CLASS,
496 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
497 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
498 NULL);
d9a16f9a
PW		 499 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
500 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
4de34f35
VH		 501 omap3xxx_check_revision();
502 ti81xx_check_features();
4c3cf901
TL		 503 omap3xxx_voltagedomains_init();
504 omap3xxx_powerdomains_init();
505 omap3xxx_clockdomains_init();
506 omap3xxx_hwmod_init();
507 omap_hwmod_init_postsetup();
3e049157
TK		 508 if (of_have_populated_dt())
509 omap_clk_soc_init = ti81xx_dt_clk_init;
510 else
511 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41 512}
bbd707ac
SG		 513
514void __init omap3_init_late(void)
515{
4ed12be0 516 omap_common_late_init();
bbd707ac 517 omap3_pm_init();
23fb8ba3 518 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 519}
520
521void __init omap3430_init_late(void)
522{
4ed12be0 523 omap_common_late_init();
bbd707ac 524 omap3_pm_init();
23fb8ba3 525 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 526}
527
528void __init omap35xx_init_late(void)
529{
4ed12be0 530 omap_common_late_init();
bbd707ac 531 omap3_pm_init();
23fb8ba3 532 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 533}
534
535void __init omap3630_init_late(void)
536{
4ed12be0 537 omap_common_late_init();
bbd707ac 538 omap3_pm_init();
23fb8ba3 539 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 540}
541
542void __init am35xx_init_late(void)
543{
4ed12be0 544 omap_common_late_init();
bbd707ac 545 omap3_pm_init();
23fb8ba3 546 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 547}
548
549void __init ti81xx_init_late(void)
550{
4ed12be0 551 omap_common_late_init();
bbd707ac 552 omap3_pm_init();
23fb8ba3 553 omap2_clk_enable_autoidle_all();
bbd707ac 554}
c4e2d245 555#endif
8f5b5a41 556
08f30989
AM		 557#ifdef CONFIG_SOC_AM33XX
558void __init am33xx_init_early(void)
559{
b6a4226c
PW		 560 omap2_set_globals_tap(AM335X_CLASS,
561 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
562 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
563 NULL);
d9a16f9a
PW		 564 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
565 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
08f30989 566 omap3xxx_check_revision();
7bcad170 567 am33xx_check_features();
3f0ea764 568 am33xx_powerdomains_init();
9c80f3aa 569 am33xx_clockdomains_init();
a2cfc509
VH		 570 am33xx_hwmod_init();
571 omap_hwmod_init_postsetup();
149c09d3 572 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 573}
765e7a06
NM		 574
575void __init am33xx_init_late(void)
576{
577 omap_common_late_init();
578}
08f30989
AM		 579#endif
580
c5107027
AM		 581#ifdef CONFIG_SOC_AM43XX
582void __init am43xx_init_early(void)
583{
584 omap2_set_globals_tap(AM335X_CLASS,
585 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
586 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
587 NULL);
588 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
589 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
8835cf6e
A		 590 omap_prm_base_init();
591 omap_cm_base_init();
c5107027 592 omap3xxx_check_revision();
7a2e0513 593 am33xx_check_features();
8835cf6e
A		 594 am43xx_powerdomains_init();
595 am43xx_clockdomains_init();
596 am43xx_hwmod_init();
597 omap_hwmod_init_postsetup();
d941f86f 598 omap_l2_cache_init();
d22031e2 599 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 600}
765e7a06
NM		 601
602void __init am43xx_init_late(void)
603{
604 omap_common_late_init();
605}
c5107027
AM		 606#endif
607
c4e2d245 608#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 609void __init omap4430_init_early(void)
610{
b6a4226c
PW		 611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
613 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
614 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
d9a16f9a
PW		 615 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
616 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
617 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
618 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
619 omap_prm_base_init();
620 omap_cm_base_init();
4de34f35
VH		 621 omap4xxx_check_revision();
622 omap4xxx_check_features();
de70af49 623 omap4_pm_init_early();
63a293e0 624 omap44xx_prm_init();
7b250aff
TL		 625 omap44xx_voltagedomains_init();
626 omap44xx_powerdomains_init();
627 omap44xx_clockdomains_init();
628 omap44xx_hwmod_init();
629 omap_hwmod_init_postsetup();
b39b14e6 630 omap_l2_cache_init();
c8c88d85 631 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 632}
bbd707ac
SG		 633
634void __init omap4430_init_late(void)
635{
4ed12be0 636 omap_common_late_init();
bbd707ac 637 omap4_pm_init();
23fb8ba3 638 omap2_clk_enable_autoidle_all();
bbd707ac 639}
c4e2d245 640#endif
8f5b5a41 641
05e152c7
S		 642#ifdef CONFIG_SOC_OMAP5
643void __init omap5_init_early(void)
644{
b6a4226c
PW		 645 omap2_set_globals_tap(OMAP54XX_CLASS,
646 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
647 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
648 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
d9a16f9a
PW		 649 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
650 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
651 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
652 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
628ed471 653 omap4_pm_init_early();
d9a16f9a
PW		 654 omap_prm_base_init();
655 omap_cm_base_init();
e4020aa9 656 omap44xx_prm_init();
05e152c7 657 omap5xxx_check_revision();
e4020aa9
SS		 658 omap54xx_voltagedomains_init();
659 omap54xx_powerdomains_init();
660 omap54xx_clockdomains_init();
661 omap54xx_hwmod_init();
662 omap_hwmod_init_postsetup();
cfa9667d 663 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 664}
765e7a06
NM		 665
666void __init omap5_init_late(void)
667{
668 omap_common_late_init();
628ed471
SS		 669 omap4_pm_init();
670 omap2_clk_enable_autoidle_all();
765e7a06 671}
05e152c7
S		 672#endif
673
a3a9384a
S		 674#ifdef CONFIG_SOC_DRA7XX
675void __init dra7xx_init_early(void)
676{
677 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
678 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
679 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
680 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
681 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
682 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
683 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
6af16a1d 684 omap4_pm_init_early();
a3a9384a
S		 685 omap_prm_base_init();
686 omap_cm_base_init();
7de516a6 687 omap44xx_prm_init();
733d20ee 688 dra7xxx_check_revision();
7de516a6
A		 689 dra7xx_powerdomains_init();
690 dra7xx_clockdomains_init();
691 dra7xx_hwmod_init();
692 omap_hwmod_init_postsetup();
f1cf498e 693 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 694}
765e7a06
NM		 695
696void __init dra7xx_init_late(void)
697{
698 omap_common_late_init();
6af16a1d
RN		 699 omap4_pm_init();
700 omap2_clk_enable_autoidle_all();
765e7a06 701}
a3a9384a
S		 702#endif
703
704
a4ca9dbe 705void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 706 struct omap_sdrc_params *sdrc_cs1)
707{
a66cb345
TL		 708 omap_sram_init();
709
01001712 710 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 711 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
712 _omap2_init_reprogram_sdrc();
713 }
1dbae815 714}
cfa9667d
TK		 715
716int __init omap_clk_init(void)
717{
718 int ret = 0;
719
720 if (!omap_clk_soc_init)
721 return 0;
722
8111e010
TK		 723 ti_clk_init_features();
724
cfa9667d 725 ret = of_prcm_init();
c08ee14c
TK		 726 if (ret)
727 return ret;
728
729 of_clk_init(NULL);
730
731 ti_dt_clk_init_retry_clks();
732
733 ti_dt_clockdomains_setup();
734
735 ret = omap_clk_soc_init();
cfa9667d
TK		 736
737 return ret;
738}
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