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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
45c3eb7d | 28 | #include <linux/omap-dma.h> |
ee0839c2 | 29 | |
dc843280 | 30 | #include "omap_hwmod.h" |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
81a60482 | 33 | #include "voltage.h" |
72e06d08 | 34 | #include "powerdomain.h" |
1540f214 | 35 | #include "clockdomain.h" |
4e65331c | 36 | #include "common.h" |
e30384ab | 37 | #include "clock.h" |
ee0839c2 TL |
38 | #include "clock2xxx.h" |
39 | #include "clock3xxx.h" | |
1d5aef49 | 40 | #include "omap-pm.h" |
3e6ece13 | 41 | #include "sdrc.h" |
b6a4226c | 42 | #include "control.h" |
3d82cbbb | 43 | #include "serial.h" |
bf027ca1 | 44 | #include "sram.h" |
c4ceedcb PW |
45 | #include "cm2xxx.h" |
46 | #include "cm3xxx.h" | |
7632a02f | 47 | #include "cm33xx.h" |
ab6c9bbf | 48 | #include "cm44xx.h" |
d9a16f9a PW |
49 | #include "prm.h" |
50 | #include "cm.h" | |
51 | #include "prcm_mpu44xx.h" | |
52 | #include "prminst44xx.h" | |
63a293e0 PW |
53 | #include "prm2xxx.h" |
54 | #include "prm3xxx.h" | |
d9bbe84f | 55 | #include "prm33xx.h" |
63a293e0 | 56 | #include "prm44xx.h" |
69a1e7a1 | 57 | #include "opp2xxx.h" |
02bfc030 | 58 | |
ff931c82 | 59 | /* |
cfa9667d | 60 | * omap_clk_soc_init: points to a function that does the SoC-specific |
ff931c82 RN |
61 | * clock initializations |
62 | */ | |
cfa9667d | 63 | static int (*omap_clk_soc_init)(void); |
ff931c82 | 64 | |
1dbae815 TL |
65 | /* |
66 | * The machine specific code may provide the extra mapping besides the | |
67 | * default mapping provided here. | |
68 | */ | |
cc26b3b0 | 69 | |
e48f814e | 70 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 71 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
72 | { |
73 | .virtual = L3_24XX_VIRT, | |
74 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
75 | .length = L3_24XX_SIZE, | |
76 | .type = MT_DEVICE | |
77 | }, | |
09f21ed4 | 78 | { |
cc26b3b0 SMK |
79 | .virtual = L4_24XX_VIRT, |
80 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
81 | .length = L4_24XX_SIZE, | |
82 | .type = MT_DEVICE | |
09f21ed4 | 83 | }, |
cc26b3b0 SMK |
84 | }; |
85 | ||
59b479e0 | 86 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
87 | static struct map_desc omap242x_io_desc[] __initdata = { |
88 | { | |
7adb9987 PW |
89 | .virtual = DSP_MEM_2420_VIRT, |
90 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
91 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
92 | .type = MT_DEVICE |
93 | }, | |
94 | { | |
7adb9987 PW |
95 | .virtual = DSP_IPI_2420_VIRT, |
96 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
97 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 98 | .type = MT_DEVICE |
09f21ed4 | 99 | }, |
cc26b3b0 | 100 | { |
7adb9987 PW |
101 | .virtual = DSP_MMU_2420_VIRT, |
102 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
103 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
104 | .type = MT_DEVICE |
105 | }, | |
106 | }; | |
107 | ||
108 | #endif | |
109 | ||
59b479e0 | 110 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 111 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
112 | { |
113 | .virtual = L4_WK_243X_VIRT, | |
114 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
115 | .length = L4_WK_243X_SIZE, | |
116 | .type = MT_DEVICE | |
117 | }, | |
118 | { | |
119 | .virtual = OMAP243X_GPMC_VIRT, | |
120 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
121 | .length = OMAP243X_GPMC_SIZE, | |
122 | .type = MT_DEVICE | |
123 | }, | |
cc26b3b0 SMK |
124 | { |
125 | .virtual = OMAP243X_SDRC_VIRT, | |
126 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
127 | .length = OMAP243X_SDRC_SIZE, | |
128 | .type = MT_DEVICE | |
129 | }, | |
130 | { | |
131 | .virtual = OMAP243X_SMS_VIRT, | |
132 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
133 | .length = OMAP243X_SMS_SIZE, | |
134 | .type = MT_DEVICE | |
135 | }, | |
136 | }; | |
72d0f1c3 | 137 | #endif |
72d0f1c3 | 138 | #endif |
cc26b3b0 | 139 | |
a8eb7ca0 | 140 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 141 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 142 | { |
cc26b3b0 SMK |
143 | .virtual = L3_34XX_VIRT, |
144 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
145 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
146 | .type = MT_DEVICE |
147 | }, | |
148 | { | |
cc26b3b0 SMK |
149 | .virtual = L4_34XX_VIRT, |
150 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
151 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
152 | .type = MT_DEVICE |
153 | }, | |
cc26b3b0 SMK |
154 | { |
155 | .virtual = OMAP34XX_GPMC_VIRT, | |
156 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
157 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 158 | .type = MT_DEVICE |
cc26b3b0 SMK |
159 | }, |
160 | { | |
161 | .virtual = OMAP343X_SMS_VIRT, | |
162 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
163 | .length = OMAP343X_SMS_SIZE, | |
164 | .type = MT_DEVICE | |
165 | }, | |
166 | { | |
167 | .virtual = OMAP343X_SDRC_VIRT, | |
168 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
169 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 170 | .type = MT_DEVICE |
cc26b3b0 SMK |
171 | }, |
172 | { | |
173 | .virtual = L4_PER_34XX_VIRT, | |
174 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
175 | .length = L4_PER_34XX_SIZE, | |
176 | .type = MT_DEVICE | |
177 | }, | |
178 | { | |
179 | .virtual = L4_EMU_34XX_VIRT, | |
180 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
181 | .length = L4_EMU_34XX_SIZE, | |
182 | .type = MT_DEVICE | |
183 | }, | |
1dbae815 | 184 | }; |
cc26b3b0 | 185 | #endif |
01001712 | 186 | |
33959553 | 187 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 188 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
189 | { |
190 | .virtual = L4_34XX_VIRT, | |
191 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
192 | .length = L4_34XX_SIZE, | |
193 | .type = MT_DEVICE | |
194 | } | |
195 | }; | |
196 | #endif | |
197 | ||
addb154a | 198 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
1e6cb146 | 199 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
200 | { |
201 | .virtual = L4_34XX_VIRT, | |
202 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
203 | .length = L4_34XX_SIZE, | |
204 | .type = MT_DEVICE | |
205 | }, | |
1e6cb146 AM |
206 | { |
207 | .virtual = L4_WK_AM33XX_VIRT, | |
208 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
209 | .length = L4_WK_AM33XX_SIZE, | |
210 | .type = MT_DEVICE | |
211 | } | |
01001712 HP |
212 | }; |
213 | #endif | |
214 | ||
44169075 SS |
215 | #ifdef CONFIG_ARCH_OMAP4 |
216 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
217 | { | |
218 | .virtual = L3_44XX_VIRT, | |
219 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
220 | .length = L3_44XX_SIZE, | |
221 | .type = MT_DEVICE, | |
222 | }, | |
223 | { | |
224 | .virtual = L4_44XX_VIRT, | |
225 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
226 | .length = L4_44XX_SIZE, | |
227 | .type = MT_DEVICE, | |
228 | }, | |
44169075 SS |
229 | { |
230 | .virtual = L4_PER_44XX_VIRT, | |
231 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
232 | .length = L4_PER_44XX_SIZE, | |
233 | .type = MT_DEVICE, | |
234 | }, | |
44169075 SS |
235 | }; |
236 | #endif | |
1dbae815 | 237 | |
ea827ad5 | 238 | #ifdef CONFIG_SOC_OMAP5 |
05e152c7 S |
239 | static struct map_desc omap54xx_io_desc[] __initdata = { |
240 | { | |
241 | .virtual = L3_54XX_VIRT, | |
242 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
243 | .length = L3_54XX_SIZE, | |
244 | .type = MT_DEVICE, | |
245 | }, | |
246 | { | |
247 | .virtual = L4_54XX_VIRT, | |
248 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
249 | .length = L4_54XX_SIZE, | |
250 | .type = MT_DEVICE, | |
251 | }, | |
252 | { | |
253 | .virtual = L4_WK_54XX_VIRT, | |
254 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
255 | .length = L4_WK_54XX_SIZE, | |
256 | .type = MT_DEVICE, | |
257 | }, | |
258 | { | |
259 | .virtual = L4_PER_54XX_VIRT, | |
260 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
261 | .length = L4_PER_54XX_SIZE, | |
262 | .type = MT_DEVICE, | |
263 | }, | |
264 | }; | |
265 | #endif | |
266 | ||
ea827ad5 NM |
267 | #ifdef CONFIG_SOC_DRA7XX |
268 | static struct map_desc dra7xx_io_desc[] __initdata = { | |
269 | { | |
270 | .virtual = L4_CFG_MPU_DRA7XX_VIRT, | |
271 | .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), | |
272 | .length = L4_CFG_MPU_DRA7XX_SIZE, | |
273 | .type = MT_DEVICE, | |
274 | }, | |
275 | { | |
276 | .virtual = L3_MAIN_SN_DRA7XX_VIRT, | |
277 | .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), | |
278 | .length = L3_MAIN_SN_DRA7XX_SIZE, | |
279 | .type = MT_DEVICE, | |
280 | }, | |
281 | { | |
282 | .virtual = L4_PER1_DRA7XX_VIRT, | |
283 | .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), | |
284 | .length = L4_PER1_DRA7XX_SIZE, | |
285 | .type = MT_DEVICE, | |
286 | }, | |
287 | { | |
288 | .virtual = L4_PER2_DRA7XX_VIRT, | |
289 | .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), | |
290 | .length = L4_PER2_DRA7XX_SIZE, | |
291 | .type = MT_DEVICE, | |
292 | }, | |
293 | { | |
294 | .virtual = L4_PER3_DRA7XX_VIRT, | |
295 | .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), | |
296 | .length = L4_PER3_DRA7XX_SIZE, | |
297 | .type = MT_DEVICE, | |
298 | }, | |
299 | { | |
300 | .virtual = L4_CFG_DRA7XX_VIRT, | |
301 | .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), | |
302 | .length = L4_CFG_DRA7XX_SIZE, | |
303 | .type = MT_DEVICE, | |
304 | }, | |
305 | { | |
306 | .virtual = L4_WKUP_DRA7XX_VIRT, | |
307 | .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), | |
308 | .length = L4_WKUP_DRA7XX_SIZE, | |
309 | .type = MT_DEVICE, | |
310 | }, | |
311 | }; | |
312 | #endif | |
313 | ||
59b479e0 | 314 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 315 | void __init omap242x_map_io(void) |
1dbae815 | 316 | { |
cc26b3b0 SMK |
317 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
318 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 319 | } |
cc26b3b0 SMK |
320 | #endif |
321 | ||
59b479e0 | 322 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 323 | void __init omap243x_map_io(void) |
6fbd55d0 | 324 | { |
cc26b3b0 SMK |
325 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
326 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 327 | } |
cc26b3b0 SMK |
328 | #endif |
329 | ||
a8eb7ca0 | 330 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 331 | void __init omap3_map_io(void) |
6fbd55d0 | 332 | { |
cc26b3b0 | 333 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 334 | } |
cc26b3b0 | 335 | #endif |
120db2cb | 336 | |
33959553 | 337 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 338 | void __init ti81xx_map_io(void) |
01001712 | 339 | { |
a920360f | 340 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
341 | } |
342 | #endif | |
343 | ||
addb154a | 344 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
b6a4226c | 345 | void __init am33xx_map_io(void) |
01001712 | 346 | { |
1e6cb146 | 347 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
348 | } |
349 | #endif | |
350 | ||
6fbd55d0 | 351 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 352 | void __init omap4_map_io(void) |
6fbd55d0 | 353 | { |
44169075 | 354 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
f746929f | 355 | omap_barriers_init(); |
120db2cb | 356 | } |
6fbd55d0 | 357 | #endif |
120db2cb | 358 | |
ea827ad5 | 359 | #ifdef CONFIG_SOC_OMAP5 |
b6a4226c | 360 | void __init omap5_map_io(void) |
05e152c7 S |
361 | { |
362 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
f746929f | 363 | omap_barriers_init(); |
05e152c7 S |
364 | } |
365 | #endif | |
ea827ad5 NM |
366 | |
367 | #ifdef CONFIG_SOC_DRA7XX | |
368 | void __init dra7xx_map_io(void) | |
369 | { | |
370 | iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); | |
456e8d53 | 371 | omap_barriers_init(); |
ea827ad5 NM |
372 | } |
373 | #endif | |
2f135eaf PW |
374 | /* |
375 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
376 | * | |
377 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
378 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
379 | * registers to the values currently defined by the kernel. Currently | |
380 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
381 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
382 | * or passes along the return value of clk_set_rate(). | |
383 | */ | |
384 | static int __init _omap2_init_reprogram_sdrc(void) | |
385 | { | |
386 | struct clk *dpll3_m2_ck; | |
387 | int v = -EINVAL; | |
388 | long rate; | |
389 | ||
390 | if (!cpu_is_omap34xx()) | |
391 | return 0; | |
392 | ||
393 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 394 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
395 | return -EINVAL; |
396 | ||
397 | rate = clk_get_rate(dpll3_m2_ck); | |
398 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
399 | v = clk_set_rate(dpll3_m2_ck, rate); | |
400 | if (v) | |
401 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
402 | ||
403 | clk_put(dpll3_m2_ck); | |
404 | ||
405 | return v; | |
406 | } | |
407 | ||
2092e5cc PW |
408 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
409 | { | |
410 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
411 | } | |
412 | ||
7b250aff TL |
413 | static void __init omap_hwmod_init_postsetup(void) |
414 | { | |
415 | u8 postsetup_state; | |
2092e5cc PW |
416 | |
417 | /* Set the default postsetup state for all hwmods */ | |
bf7c5449 | 418 | #ifdef CONFIG_PM |
2092e5cc PW |
419 | postsetup_state = _HWMOD_STATE_IDLE; |
420 | #else | |
421 | postsetup_state = _HWMOD_STATE_ENABLED; | |
422 | #endif | |
423 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 424 | |
53da4ce2 | 425 | omap_pm_if_early_init(); |
4805734b PW |
426 | } |
427 | ||
069d0a78 | 428 | static void __init __maybe_unused omap_common_late_init(void) |
4ed12be0 RB |
429 | { |
430 | omap_mux_late_init(); | |
431 | omap2_common_pm_late_init(); | |
6770b211 | 432 | omap_soc_device_init(); |
4ed12be0 RB |
433 | } |
434 | ||
16110798 | 435 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
436 | void __init omap2420_init_early(void) |
437 | { | |
b6a4226c PW |
438 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
439 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
440 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
2208bf11 | 441 | omap2_control_base_init(); |
4de34f35 | 442 | omap2xxx_check_revision(); |
ab7b2ffc | 443 | omap2_prcm_base_init(); |
7b250aff TL |
444 | omap2xxx_voltagedomains_init(); |
445 | omap242x_powerdomains_init(); | |
446 | omap242x_clockdomains_init(); | |
447 | omap2420_hwmod_init(); | |
448 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
449 | omap_clk_soc_init = omap2420_dt_clk_init; |
450 | rate_table = omap2420_rate_table; | |
8f5b5a41 | 451 | } |
bbd707ac SG |
452 | |
453 | void __init omap2420_init_late(void) | |
454 | { | |
4ed12be0 | 455 | omap_common_late_init(); |
bbd707ac | 456 | omap2_pm_init(); |
23fb8ba3 | 457 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 458 | } |
16110798 | 459 | #endif |
8f5b5a41 | 460 | |
16110798 | 461 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
462 | void __init omap2430_init_early(void) |
463 | { | |
b6a4226c PW |
464 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
465 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
466 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
2208bf11 | 467 | omap2_control_base_init(); |
4de34f35 | 468 | omap2xxx_check_revision(); |
ab7b2ffc | 469 | omap2_prcm_base_init(); |
7b250aff TL |
470 | omap2xxx_voltagedomains_init(); |
471 | omap243x_powerdomains_init(); | |
472 | omap243x_clockdomains_init(); | |
473 | omap2430_hwmod_init(); | |
474 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
475 | omap_clk_soc_init = omap2430_dt_clk_init; |
476 | rate_table = omap2430_rate_table; | |
7b250aff | 477 | } |
bbd707ac SG |
478 | |
479 | void __init omap2430_init_late(void) | |
480 | { | |
4ed12be0 | 481 | omap_common_late_init(); |
bbd707ac | 482 | omap2_pm_init(); |
23fb8ba3 | 483 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 484 | } |
c4e2d245 | 485 | #endif |
7b250aff TL |
486 | |
487 | /* | |
488 | * Currently only board-omap3beagle.c should call this because of the | |
489 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
490 | */ | |
c4e2d245 | 491 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
492 | void __init omap3_init_early(void) |
493 | { | |
b6a4226c PW |
494 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
495 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
496 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
2208bf11 TK |
497 | /* XXX: remove these once OMAP3 is DT only */ |
498 | if (!of_have_populated_dt()) { | |
499 | omap2_set_globals_control( | |
efde2346 | 500 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); |
2208bf11 TK |
501 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
502 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), | |
503 | NULL); | |
504 | } | |
505 | omap2_control_base_init(); | |
4de34f35 VH |
506 | omap3xxx_check_revision(); |
507 | omap3xxx_check_features(); | |
ab7b2ffc | 508 | omap2_prcm_base_init(); |
425dc8b2 TK |
509 | /* XXX: remove these once OMAP3 is DT only */ |
510 | if (!of_have_populated_dt()) { | |
511 | omap3xxx_prm_init(NULL); | |
512 | omap3xxx_cm_init(NULL); | |
513 | } | |
7b250aff TL |
514 | omap3xxx_voltagedomains_init(); |
515 | omap3xxx_powerdomains_init(); | |
516 | omap3xxx_clockdomains_init(); | |
517 | omap3xxx_hwmod_init(); | |
518 | omap_hwmod_init_postsetup(); | |
eded36fe | 519 | if (!of_have_populated_dt()) { |
2208bf11 | 520 | omap3_control_legacy_iomap_init(); |
eded36fe TK |
521 | if (soc_is_am35xx()) |
522 | omap_clk_soc_init = am35xx_clk_legacy_init; | |
523 | else if (cpu_is_omap3630()) | |
524 | omap_clk_soc_init = omap36xx_clk_legacy_init; | |
525 | else if (omap_rev() == OMAP3430_REV_ES1_0) | |
526 | omap_clk_soc_init = omap3430es1_clk_legacy_init; | |
527 | else | |
528 | omap_clk_soc_init = omap3430_clk_legacy_init; | |
529 | } | |
8f5b5a41 TL |
530 | } |
531 | ||
532 | void __init omap3430_init_early(void) | |
533 | { | |
7b250aff | 534 | omap3_init_early(); |
3e049157 TK |
535 | if (of_have_populated_dt()) |
536 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
537 | } |
538 | ||
539 | void __init omap35xx_init_early(void) | |
540 | { | |
7b250aff | 541 | omap3_init_early(); |
3e049157 TK |
542 | if (of_have_populated_dt()) |
543 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
544 | } |
545 | ||
546 | void __init omap3630_init_early(void) | |
547 | { | |
7b250aff | 548 | omap3_init_early(); |
3e049157 TK |
549 | if (of_have_populated_dt()) |
550 | omap_clk_soc_init = omap3630_dt_clk_init; | |
8f5b5a41 TL |
551 | } |
552 | ||
553 | void __init am35xx_init_early(void) | |
554 | { | |
7b250aff | 555 | omap3_init_early(); |
3e049157 TK |
556 | if (of_have_populated_dt()) |
557 | omap_clk_soc_init = am35xx_dt_clk_init; | |
8f5b5a41 TL |
558 | } |
559 | ||
bbd707ac SG |
560 | void __init omap3_init_late(void) |
561 | { | |
4ed12be0 | 562 | omap_common_late_init(); |
bbd707ac | 563 | omap3_pm_init(); |
23fb8ba3 | 564 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
565 | } |
566 | ||
567 | void __init omap3430_init_late(void) | |
568 | { | |
4ed12be0 | 569 | omap_common_late_init(); |
bbd707ac | 570 | omap3_pm_init(); |
23fb8ba3 | 571 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
572 | } |
573 | ||
574 | void __init omap35xx_init_late(void) | |
575 | { | |
4ed12be0 | 576 | omap_common_late_init(); |
bbd707ac | 577 | omap3_pm_init(); |
23fb8ba3 | 578 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
579 | } |
580 | ||
581 | void __init omap3630_init_late(void) | |
582 | { | |
4ed12be0 | 583 | omap_common_late_init(); |
bbd707ac | 584 | omap3_pm_init(); |
23fb8ba3 | 585 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
586 | } |
587 | ||
588 | void __init am35xx_init_late(void) | |
589 | { | |
4ed12be0 | 590 | omap_common_late_init(); |
bbd707ac | 591 | omap3_pm_init(); |
23fb8ba3 | 592 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
593 | } |
594 | ||
595 | void __init ti81xx_init_late(void) | |
596 | { | |
4ed12be0 | 597 | omap_common_late_init(); |
23fb8ba3 | 598 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 599 | } |
c4e2d245 | 600 | #endif |
8f5b5a41 | 601 | |
a64459c4 AM |
602 | #ifdef CONFIG_SOC_TI81XX |
603 | void __init ti814x_init_early(void) | |
604 | { | |
605 | omap2_set_globals_tap(TI814X_CLASS, | |
606 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
2208bf11 | 607 | omap2_control_base_init(); |
a64459c4 AM |
608 | omap3xxx_check_revision(); |
609 | ti81xx_check_features(); | |
ab7b2ffc | 610 | omap2_prcm_base_init(); |
a64459c4 AM |
611 | omap3xxx_voltagedomains_init(); |
612 | omap3xxx_powerdomains_init(); | |
185fde6d | 613 | ti814x_clockdomains_init(); |
0f3ccb24 | 614 | dm814x_hwmod_init(); |
a64459c4 | 615 | omap_hwmod_init_postsetup(); |
d893656e | 616 | omap_clk_soc_init = dm814x_dt_clk_init; |
a64459c4 AM |
617 | } |
618 | ||
619 | void __init ti816x_init_early(void) | |
620 | { | |
621 | omap2_set_globals_tap(TI816X_CLASS, | |
622 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
2208bf11 | 623 | omap2_control_base_init(); |
a64459c4 AM |
624 | omap3xxx_check_revision(); |
625 | ti81xx_check_features(); | |
ab7b2ffc | 626 | omap2_prcm_base_init(); |
a64459c4 AM |
627 | omap3xxx_voltagedomains_init(); |
628 | omap3xxx_powerdomains_init(); | |
185fde6d | 629 | ti816x_clockdomains_init(); |
0f3ccb24 | 630 | dm816x_hwmod_init(); |
a64459c4 AM |
631 | omap_hwmod_init_postsetup(); |
632 | if (of_have_populated_dt()) | |
9cf705de | 633 | omap_clk_soc_init = dm816x_dt_clk_init; |
a64459c4 AM |
634 | } |
635 | #endif | |
636 | ||
08f30989 AM |
637 | #ifdef CONFIG_SOC_AM33XX |
638 | void __init am33xx_init_early(void) | |
639 | { | |
b6a4226c PW |
640 | omap2_set_globals_tap(AM335X_CLASS, |
641 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
2208bf11 | 642 | omap2_control_base_init(); |
08f30989 | 643 | omap3xxx_check_revision(); |
7bcad170 | 644 | am33xx_check_features(); |
ab7b2ffc | 645 | omap2_prcm_base_init(); |
3f0ea764 | 646 | am33xx_powerdomains_init(); |
9c80f3aa | 647 | am33xx_clockdomains_init(); |
a2cfc509 VH |
648 | am33xx_hwmod_init(); |
649 | omap_hwmod_init_postsetup(); | |
149c09d3 | 650 | omap_clk_soc_init = am33xx_dt_clk_init; |
08f30989 | 651 | } |
765e7a06 NM |
652 | |
653 | void __init am33xx_init_late(void) | |
654 | { | |
655 | omap_common_late_init(); | |
656 | } | |
08f30989 AM |
657 | #endif |
658 | ||
c5107027 AM |
659 | #ifdef CONFIG_SOC_AM43XX |
660 | void __init am43xx_init_early(void) | |
661 | { | |
662 | omap2_set_globals_tap(AM335X_CLASS, | |
663 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
2208bf11 | 664 | omap2_control_base_init(); |
c5107027 | 665 | omap3xxx_check_revision(); |
7a2e0513 | 666 | am33xx_check_features(); |
ab7b2ffc | 667 | omap2_prcm_base_init(); |
8835cf6e A |
668 | am43xx_powerdomains_init(); |
669 | am43xx_clockdomains_init(); | |
670 | am43xx_hwmod_init(); | |
671 | omap_hwmod_init_postsetup(); | |
d941f86f | 672 | omap_l2_cache_init(); |
d22031e2 | 673 | omap_clk_soc_init = am43xx_dt_clk_init; |
c5107027 | 674 | } |
765e7a06 NM |
675 | |
676 | void __init am43xx_init_late(void) | |
677 | { | |
678 | omap_common_late_init(); | |
08224a7d | 679 | omap2_clk_enable_autoidle_all(); |
765e7a06 | 680 | } |
c5107027 AM |
681 | #endif |
682 | ||
c4e2d245 | 683 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
684 | void __init omap4430_init_early(void) |
685 | { | |
b6a4226c PW |
686 | omap2_set_globals_tap(OMAP443X_CLASS, |
687 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
d9a16f9a | 688 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); |
ca125b5e | 689 | omap2_control_base_init(); |
4de34f35 VH |
690 | omap4xxx_check_revision(); |
691 | omap4xxx_check_features(); | |
ab7b2ffc | 692 | omap2_prcm_base_init(); |
de70af49 | 693 | omap4_pm_init_early(); |
7b250aff TL |
694 | omap44xx_voltagedomains_init(); |
695 | omap44xx_powerdomains_init(); | |
696 | omap44xx_clockdomains_init(); | |
697 | omap44xx_hwmod_init(); | |
698 | omap_hwmod_init_postsetup(); | |
b39b14e6 | 699 | omap_l2_cache_init(); |
c8c88d85 | 700 | omap_clk_soc_init = omap4xxx_dt_clk_init; |
8f5b5a41 | 701 | } |
bbd707ac SG |
702 | |
703 | void __init omap4430_init_late(void) | |
704 | { | |
4ed12be0 | 705 | omap_common_late_init(); |
bbd707ac | 706 | omap4_pm_init(); |
23fb8ba3 | 707 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 708 | } |
c4e2d245 | 709 | #endif |
8f5b5a41 | 710 | |
05e152c7 S |
711 | #ifdef CONFIG_SOC_OMAP5 |
712 | void __init omap5_init_early(void) | |
713 | { | |
b6a4226c PW |
714 | omap2_set_globals_tap(OMAP54XX_CLASS, |
715 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
d9a16f9a | 716 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
ca125b5e | 717 | omap2_control_base_init(); |
628ed471 | 718 | omap4_pm_init_early(); |
ab7b2ffc | 719 | omap2_prcm_base_init(); |
05e152c7 | 720 | omap5xxx_check_revision(); |
e4020aa9 SS |
721 | omap54xx_voltagedomains_init(); |
722 | omap54xx_powerdomains_init(); | |
723 | omap54xx_clockdomains_init(); | |
724 | omap54xx_hwmod_init(); | |
725 | omap_hwmod_init_postsetup(); | |
cfa9667d | 726 | omap_clk_soc_init = omap5xxx_dt_clk_init; |
05e152c7 | 727 | } |
765e7a06 NM |
728 | |
729 | void __init omap5_init_late(void) | |
730 | { | |
731 | omap_common_late_init(); | |
628ed471 SS |
732 | omap4_pm_init(); |
733 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 734 | } |
05e152c7 S |
735 | #endif |
736 | ||
a3a9384a S |
737 | #ifdef CONFIG_SOC_DRA7XX |
738 | void __init dra7xx_init_early(void) | |
739 | { | |
ec490f6f NM |
740 | omap2_set_globals_tap(DRA7XX_CLASS, |
741 | OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); | |
a3a9384a | 742 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); |
ca125b5e | 743 | omap2_control_base_init(); |
6af16a1d | 744 | omap4_pm_init_early(); |
ab7b2ffc | 745 | omap2_prcm_base_init(); |
733d20ee | 746 | dra7xxx_check_revision(); |
7de516a6 A |
747 | dra7xx_powerdomains_init(); |
748 | dra7xx_clockdomains_init(); | |
749 | dra7xx_hwmod_init(); | |
750 | omap_hwmod_init_postsetup(); | |
f1cf498e | 751 | omap_clk_soc_init = dra7xx_dt_clk_init; |
a3a9384a | 752 | } |
765e7a06 NM |
753 | |
754 | void __init dra7xx_init_late(void) | |
755 | { | |
756 | omap_common_late_init(); | |
6af16a1d RN |
757 | omap4_pm_init(); |
758 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 759 | } |
a3a9384a S |
760 | #endif |
761 | ||
762 | ||
a4ca9dbe | 763 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
764 | struct omap_sdrc_params *sdrc_cs1) |
765 | { | |
a66cb345 TL |
766 | omap_sram_init(); |
767 | ||
01001712 | 768 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
769 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
770 | _omap2_init_reprogram_sdrc(); | |
771 | } | |
1dbae815 | 772 | } |
cfa9667d TK |
773 | |
774 | int __init omap_clk_init(void) | |
775 | { | |
776 | int ret = 0; | |
777 | ||
778 | if (!omap_clk_soc_init) | |
779 | return 0; | |
780 | ||
8111e010 TK |
781 | ti_clk_init_features(); |
782 | ||
e9e63088 TK |
783 | omap2_clk_setup_ll_ops(); |
784 | ||
eded36fe | 785 | if (of_have_populated_dt()) { |
fe87414f TK |
786 | ret = omap_control_init(); |
787 | if (ret) | |
788 | return ret; | |
789 | ||
3a1a388e | 790 | ret = omap_prcm_init(); |
eded36fe TK |
791 | if (ret) |
792 | return ret; | |
c08ee14c | 793 | |
eded36fe | 794 | of_clk_init(NULL); |
c08ee14c | 795 | |
eded36fe | 796 | ti_dt_clk_init_retry_clks(); |
c08ee14c | 797 | |
eded36fe TK |
798 | ti_dt_clockdomains_setup(); |
799 | } | |
c08ee14c TK |
800 | |
801 | ret = omap_clk_soc_init(); | |
cfa9667d TK |
802 | |
803 | return ret; | |
804 | } |