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Commit | Line | Data |
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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
2b6c4e73 | 28 | #include <plat-omap/dma-omap.h> |
ee0839c2 | 29 | |
622297fd TL |
30 | #include "../plat-omap/sram.h" |
31 | ||
dc843280 | 32 | #include "omap_hwmod.h" |
dbc04161 | 33 | #include "soc.h" |
ee0839c2 | 34 | #include "iomap.h" |
81a60482 | 35 | #include "voltage.h" |
72e06d08 | 36 | #include "powerdomain.h" |
1540f214 | 37 | #include "clockdomain.h" |
4e65331c | 38 | #include "common.h" |
e30384ab | 39 | #include "clock.h" |
ee0839c2 TL |
40 | #include "clock2xxx.h" |
41 | #include "clock3xxx.h" | |
42 | #include "clock44xx.h" | |
1d5aef49 | 43 | #include "omap-pm.h" |
3e6ece13 | 44 | #include "sdrc.h" |
b6a4226c | 45 | #include "control.h" |
3d82cbbb | 46 | #include "serial.h" |
c4ceedcb PW |
47 | #include "cm2xxx.h" |
48 | #include "cm3xxx.h" | |
d9a16f9a PW |
49 | #include "prm.h" |
50 | #include "cm.h" | |
51 | #include "prcm_mpu44xx.h" | |
52 | #include "prminst44xx.h" | |
53 | #include "cminst44xx.h" | |
1dbae815 TL |
54 | /* |
55 | * The machine specific code may provide the extra mapping besides the | |
56 | * default mapping provided here. | |
57 | */ | |
cc26b3b0 | 58 | |
e48f814e | 59 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 60 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
61 | { |
62 | .virtual = L3_24XX_VIRT, | |
63 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
64 | .length = L3_24XX_SIZE, | |
65 | .type = MT_DEVICE | |
66 | }, | |
09f21ed4 | 67 | { |
cc26b3b0 SMK |
68 | .virtual = L4_24XX_VIRT, |
69 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
70 | .length = L4_24XX_SIZE, | |
71 | .type = MT_DEVICE | |
09f21ed4 | 72 | }, |
cc26b3b0 SMK |
73 | }; |
74 | ||
59b479e0 | 75 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
76 | static struct map_desc omap242x_io_desc[] __initdata = { |
77 | { | |
7adb9987 PW |
78 | .virtual = DSP_MEM_2420_VIRT, |
79 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
80 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
81 | .type = MT_DEVICE |
82 | }, | |
83 | { | |
7adb9987 PW |
84 | .virtual = DSP_IPI_2420_VIRT, |
85 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
86 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 87 | .type = MT_DEVICE |
09f21ed4 | 88 | }, |
cc26b3b0 | 89 | { |
7adb9987 PW |
90 | .virtual = DSP_MMU_2420_VIRT, |
91 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
92 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
93 | .type = MT_DEVICE |
94 | }, | |
95 | }; | |
96 | ||
97 | #endif | |
98 | ||
59b479e0 | 99 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 100 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
101 | { |
102 | .virtual = L4_WK_243X_VIRT, | |
103 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
104 | .length = L4_WK_243X_SIZE, | |
105 | .type = MT_DEVICE | |
106 | }, | |
107 | { | |
108 | .virtual = OMAP243X_GPMC_VIRT, | |
109 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
110 | .length = OMAP243X_GPMC_SIZE, | |
111 | .type = MT_DEVICE | |
112 | }, | |
cc26b3b0 SMK |
113 | { |
114 | .virtual = OMAP243X_SDRC_VIRT, | |
115 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
116 | .length = OMAP243X_SDRC_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | { | |
120 | .virtual = OMAP243X_SMS_VIRT, | |
121 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
122 | .length = OMAP243X_SMS_SIZE, | |
123 | .type = MT_DEVICE | |
124 | }, | |
125 | }; | |
72d0f1c3 | 126 | #endif |
72d0f1c3 | 127 | #endif |
cc26b3b0 | 128 | |
a8eb7ca0 | 129 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 130 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 131 | { |
cc26b3b0 SMK |
132 | .virtual = L3_34XX_VIRT, |
133 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
134 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
135 | .type = MT_DEVICE |
136 | }, | |
137 | { | |
cc26b3b0 SMK |
138 | .virtual = L4_34XX_VIRT, |
139 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
140 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
141 | .type = MT_DEVICE |
142 | }, | |
cc26b3b0 SMK |
143 | { |
144 | .virtual = OMAP34XX_GPMC_VIRT, | |
145 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
146 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 147 | .type = MT_DEVICE |
cc26b3b0 SMK |
148 | }, |
149 | { | |
150 | .virtual = OMAP343X_SMS_VIRT, | |
151 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
152 | .length = OMAP343X_SMS_SIZE, | |
153 | .type = MT_DEVICE | |
154 | }, | |
155 | { | |
156 | .virtual = OMAP343X_SDRC_VIRT, | |
157 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
158 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 159 | .type = MT_DEVICE |
cc26b3b0 SMK |
160 | }, |
161 | { | |
162 | .virtual = L4_PER_34XX_VIRT, | |
163 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
164 | .length = L4_PER_34XX_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
167 | { | |
168 | .virtual = L4_EMU_34XX_VIRT, | |
169 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
170 | .length = L4_EMU_34XX_SIZE, | |
171 | .type = MT_DEVICE | |
172 | }, | |
a4f57b81 TL |
173 | #if defined(CONFIG_DEBUG_LL) && \ |
174 | (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) | |
175 | { | |
176 | .virtual = ZOOM_UART_VIRT, | |
177 | .pfn = __phys_to_pfn(ZOOM_UART_BASE), | |
178 | .length = SZ_1M, | |
179 | .type = MT_DEVICE | |
180 | }, | |
181 | #endif | |
1dbae815 | 182 | }; |
cc26b3b0 | 183 | #endif |
01001712 | 184 | |
33959553 | 185 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 186 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
187 | { |
188 | .virtual = L4_34XX_VIRT, | |
189 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
190 | .length = L4_34XX_SIZE, | |
191 | .type = MT_DEVICE | |
192 | } | |
193 | }; | |
194 | #endif | |
195 | ||
bb6abcf4 | 196 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 | 197 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
198 | { |
199 | .virtual = L4_34XX_VIRT, | |
200 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
201 | .length = L4_34XX_SIZE, | |
202 | .type = MT_DEVICE | |
203 | }, | |
1e6cb146 AM |
204 | { |
205 | .virtual = L4_WK_AM33XX_VIRT, | |
206 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
207 | .length = L4_WK_AM33XX_SIZE, | |
208 | .type = MT_DEVICE | |
209 | } | |
01001712 HP |
210 | }; |
211 | #endif | |
212 | ||
44169075 SS |
213 | #ifdef CONFIG_ARCH_OMAP4 |
214 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
215 | { | |
216 | .virtual = L3_44XX_VIRT, | |
217 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
218 | .length = L3_44XX_SIZE, | |
219 | .type = MT_DEVICE, | |
220 | }, | |
221 | { | |
222 | .virtual = L4_44XX_VIRT, | |
223 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
224 | .length = L4_44XX_SIZE, | |
225 | .type = MT_DEVICE, | |
226 | }, | |
44169075 SS |
227 | { |
228 | .virtual = L4_PER_44XX_VIRT, | |
229 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
230 | .length = L4_PER_44XX_SIZE, | |
231 | .type = MT_DEVICE, | |
232 | }, | |
137d105d SS |
233 | #ifdef CONFIG_OMAP4_ERRATA_I688 |
234 | { | |
235 | .virtual = OMAP4_SRAM_VA, | |
236 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | |
237 | .length = PAGE_SIZE, | |
238 | .type = MT_MEMORY_SO, | |
239 | }, | |
240 | #endif | |
241 | ||
44169075 SS |
242 | }; |
243 | #endif | |
1dbae815 | 244 | |
05e152c7 S |
245 | #ifdef CONFIG_SOC_OMAP5 |
246 | static struct map_desc omap54xx_io_desc[] __initdata = { | |
247 | { | |
248 | .virtual = L3_54XX_VIRT, | |
249 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
250 | .length = L3_54XX_SIZE, | |
251 | .type = MT_DEVICE, | |
252 | }, | |
253 | { | |
254 | .virtual = L4_54XX_VIRT, | |
255 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
256 | .length = L4_54XX_SIZE, | |
257 | .type = MT_DEVICE, | |
258 | }, | |
259 | { | |
260 | .virtual = L4_WK_54XX_VIRT, | |
261 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
262 | .length = L4_WK_54XX_SIZE, | |
263 | .type = MT_DEVICE, | |
264 | }, | |
265 | { | |
266 | .virtual = L4_PER_54XX_VIRT, | |
267 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
268 | .length = L4_PER_54XX_SIZE, | |
269 | .type = MT_DEVICE, | |
270 | }, | |
271 | }; | |
272 | #endif | |
273 | ||
59b479e0 | 274 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 275 | void __init omap242x_map_io(void) |
1dbae815 | 276 | { |
cc26b3b0 SMK |
277 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
278 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 279 | } |
cc26b3b0 SMK |
280 | #endif |
281 | ||
59b479e0 | 282 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 283 | void __init omap243x_map_io(void) |
6fbd55d0 | 284 | { |
cc26b3b0 SMK |
285 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
286 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 287 | } |
cc26b3b0 SMK |
288 | #endif |
289 | ||
a8eb7ca0 | 290 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 291 | void __init omap3_map_io(void) |
6fbd55d0 | 292 | { |
cc26b3b0 | 293 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 294 | } |
cc26b3b0 | 295 | #endif |
120db2cb | 296 | |
33959553 | 297 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 298 | void __init ti81xx_map_io(void) |
01001712 | 299 | { |
a920360f | 300 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
301 | } |
302 | #endif | |
303 | ||
bb6abcf4 | 304 | #ifdef CONFIG_SOC_AM33XX |
b6a4226c | 305 | void __init am33xx_map_io(void) |
01001712 | 306 | { |
1e6cb146 | 307 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
308 | } |
309 | #endif | |
310 | ||
6fbd55d0 | 311 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 312 | void __init omap4_map_io(void) |
6fbd55d0 | 313 | { |
44169075 | 314 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 315 | omap_barriers_init(); |
120db2cb | 316 | } |
6fbd55d0 | 317 | #endif |
120db2cb | 318 | |
05e152c7 | 319 | #ifdef CONFIG_SOC_OMAP5 |
b6a4226c | 320 | void __init omap5_map_io(void) |
05e152c7 S |
321 | { |
322 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
323 | } | |
324 | #endif | |
2f135eaf PW |
325 | /* |
326 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
327 | * | |
328 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
329 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
330 | * registers to the values currently defined by the kernel. Currently | |
331 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
332 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
333 | * or passes along the return value of clk_set_rate(). | |
334 | */ | |
335 | static int __init _omap2_init_reprogram_sdrc(void) | |
336 | { | |
337 | struct clk *dpll3_m2_ck; | |
338 | int v = -EINVAL; | |
339 | long rate; | |
340 | ||
341 | if (!cpu_is_omap34xx()) | |
342 | return 0; | |
343 | ||
344 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 345 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
346 | return -EINVAL; |
347 | ||
348 | rate = clk_get_rate(dpll3_m2_ck); | |
349 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
350 | v = clk_set_rate(dpll3_m2_ck, rate); | |
351 | if (v) | |
352 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
353 | ||
354 | clk_put(dpll3_m2_ck); | |
355 | ||
356 | return v; | |
357 | } | |
358 | ||
2092e5cc PW |
359 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
360 | { | |
361 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
362 | } | |
363 | ||
7b250aff | 364 | static void __init omap_common_init_early(void) |
120db2cb | 365 | { |
df80442d | 366 | omap_init_consistent_dma_size(); |
7b250aff | 367 | } |
2092e5cc | 368 | |
7b250aff TL |
369 | static void __init omap_hwmod_init_postsetup(void) |
370 | { | |
371 | u8 postsetup_state; | |
2092e5cc PW |
372 | |
373 | /* Set the default postsetup state for all hwmods */ | |
374 | #ifdef CONFIG_PM_RUNTIME | |
375 | postsetup_state = _HWMOD_STATE_IDLE; | |
376 | #else | |
377 | postsetup_state = _HWMOD_STATE_ENABLED; | |
378 | #endif | |
379 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 380 | |
53da4ce2 | 381 | omap_pm_if_early_init(); |
4805734b PW |
382 | } |
383 | ||
16110798 | 384 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
385 | void __init omap2420_init_early(void) |
386 | { | |
b6a4226c PW |
387 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
388 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
389 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
390 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), | |
391 | NULL); | |
d9a16f9a PW |
392 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); |
393 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); | |
4de34f35 | 394 | omap2xxx_check_revision(); |
c4ceedcb | 395 | omap2xxx_cm_init(); |
7b250aff TL |
396 | omap_common_init_early(); |
397 | omap2xxx_voltagedomains_init(); | |
398 | omap242x_powerdomains_init(); | |
399 | omap242x_clockdomains_init(); | |
400 | omap2420_hwmod_init(); | |
401 | omap_hwmod_init_postsetup(); | |
402 | omap2420_clk_init(); | |
8f5b5a41 | 403 | } |
bbd707ac SG |
404 | |
405 | void __init omap2420_init_late(void) | |
406 | { | |
407 | omap_mux_late_init(); | |
408 | omap2_common_pm_late_init(); | |
409 | omap2_pm_init(); | |
23fb8ba3 | 410 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 411 | } |
16110798 | 412 | #endif |
8f5b5a41 | 413 | |
16110798 | 414 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
415 | void __init omap2430_init_early(void) |
416 | { | |
b6a4226c PW |
417 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
418 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
419 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
420 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | |
421 | NULL); | |
d9a16f9a PW |
422 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); |
423 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); | |
4de34f35 | 424 | omap2xxx_check_revision(); |
c4ceedcb | 425 | omap2xxx_cm_init(); |
7b250aff TL |
426 | omap_common_init_early(); |
427 | omap2xxx_voltagedomains_init(); | |
428 | omap243x_powerdomains_init(); | |
429 | omap243x_clockdomains_init(); | |
430 | omap2430_hwmod_init(); | |
431 | omap_hwmod_init_postsetup(); | |
432 | omap2430_clk_init(); | |
433 | } | |
bbd707ac SG |
434 | |
435 | void __init omap2430_init_late(void) | |
436 | { | |
437 | omap_mux_late_init(); | |
438 | omap2_common_pm_late_init(); | |
439 | omap2_pm_init(); | |
23fb8ba3 | 440 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 441 | } |
c4e2d245 | 442 | #endif |
7b250aff TL |
443 | |
444 | /* | |
445 | * Currently only board-omap3beagle.c should call this because of the | |
446 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
447 | */ | |
c4e2d245 | 448 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
449 | void __init omap3_init_early(void) |
450 | { | |
b6a4226c PW |
451 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
452 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
453 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
454 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | |
455 | NULL); | |
d9a16f9a PW |
456 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
457 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); | |
4de34f35 VH |
458 | omap3xxx_check_revision(); |
459 | omap3xxx_check_features(); | |
c4ceedcb | 460 | omap3xxx_cm_init(); |
7b250aff TL |
461 | omap_common_init_early(); |
462 | omap3xxx_voltagedomains_init(); | |
463 | omap3xxx_powerdomains_init(); | |
464 | omap3xxx_clockdomains_init(); | |
465 | omap3xxx_hwmod_init(); | |
466 | omap_hwmod_init_postsetup(); | |
467 | omap3xxx_clk_init(); | |
8f5b5a41 TL |
468 | } |
469 | ||
470 | void __init omap3430_init_early(void) | |
471 | { | |
7b250aff | 472 | omap3_init_early(); |
8f5b5a41 TL |
473 | } |
474 | ||
475 | void __init omap35xx_init_early(void) | |
476 | { | |
7b250aff | 477 | omap3_init_early(); |
8f5b5a41 TL |
478 | } |
479 | ||
480 | void __init omap3630_init_early(void) | |
481 | { | |
7b250aff | 482 | omap3_init_early(); |
8f5b5a41 TL |
483 | } |
484 | ||
485 | void __init am35xx_init_early(void) | |
486 | { | |
7b250aff | 487 | omap3_init_early(); |
8f5b5a41 TL |
488 | } |
489 | ||
a920360f | 490 | void __init ti81xx_init_early(void) |
8f5b5a41 | 491 | { |
b6a4226c PW |
492 | omap2_set_globals_tap(OMAP343X_CLASS, |
493 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
494 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), | |
495 | NULL); | |
d9a16f9a PW |
496 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); |
497 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); | |
4de34f35 VH |
498 | omap3xxx_check_revision(); |
499 | ti81xx_check_features(); | |
4c3cf901 TL |
500 | omap_common_init_early(); |
501 | omap3xxx_voltagedomains_init(); | |
502 | omap3xxx_powerdomains_init(); | |
503 | omap3xxx_clockdomains_init(); | |
504 | omap3xxx_hwmod_init(); | |
505 | omap_hwmod_init_postsetup(); | |
506 | omap3xxx_clk_init(); | |
8f5b5a41 | 507 | } |
bbd707ac SG |
508 | |
509 | void __init omap3_init_late(void) | |
510 | { | |
511 | omap_mux_late_init(); | |
512 | omap2_common_pm_late_init(); | |
513 | omap3_pm_init(); | |
23fb8ba3 | 514 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
515 | } |
516 | ||
517 | void __init omap3430_init_late(void) | |
518 | { | |
519 | omap_mux_late_init(); | |
520 | omap2_common_pm_late_init(); | |
521 | omap3_pm_init(); | |
23fb8ba3 | 522 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
523 | } |
524 | ||
525 | void __init omap35xx_init_late(void) | |
526 | { | |
527 | omap_mux_late_init(); | |
528 | omap2_common_pm_late_init(); | |
529 | omap3_pm_init(); | |
23fb8ba3 | 530 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
531 | } |
532 | ||
533 | void __init omap3630_init_late(void) | |
534 | { | |
535 | omap_mux_late_init(); | |
536 | omap2_common_pm_late_init(); | |
537 | omap3_pm_init(); | |
23fb8ba3 | 538 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
539 | } |
540 | ||
541 | void __init am35xx_init_late(void) | |
542 | { | |
543 | omap_mux_late_init(); | |
544 | omap2_common_pm_late_init(); | |
545 | omap3_pm_init(); | |
23fb8ba3 | 546 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
547 | } |
548 | ||
549 | void __init ti81xx_init_late(void) | |
550 | { | |
551 | omap_mux_late_init(); | |
552 | omap2_common_pm_late_init(); | |
553 | omap3_pm_init(); | |
23fb8ba3 | 554 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 555 | } |
c4e2d245 | 556 | #endif |
8f5b5a41 | 557 | |
08f30989 AM |
558 | #ifdef CONFIG_SOC_AM33XX |
559 | void __init am33xx_init_early(void) | |
560 | { | |
b6a4226c PW |
561 | omap2_set_globals_tap(AM335X_CLASS, |
562 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
563 | omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), | |
564 | NULL); | |
d9a16f9a PW |
565 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); |
566 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); | |
08f30989 AM |
567 | omap3xxx_check_revision(); |
568 | ti81xx_check_features(); | |
569 | omap_common_init_early(); | |
ce3fc89a | 570 | am33xx_voltagedomains_init(); |
3f0ea764 | 571 | am33xx_powerdomains_init(); |
9c80f3aa | 572 | am33xx_clockdomains_init(); |
a2cfc509 VH |
573 | am33xx_hwmod_init(); |
574 | omap_hwmod_init_postsetup(); | |
e30384ab | 575 | am33xx_clk_init(); |
08f30989 AM |
576 | } |
577 | #endif | |
578 | ||
c4e2d245 | 579 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
580 | void __init omap4430_init_early(void) |
581 | { | |
b6a4226c PW |
582 | omap2_set_globals_tap(OMAP443X_CLASS, |
583 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
584 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), | |
585 | OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); | |
d9a16f9a PW |
586 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); |
587 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | |
588 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); | |
589 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); | |
590 | omap_prm_base_init(); | |
591 | omap_cm_base_init(); | |
4de34f35 VH |
592 | omap4xxx_check_revision(); |
593 | omap4xxx_check_features(); | |
7b250aff TL |
594 | omap_common_init_early(); |
595 | omap44xx_voltagedomains_init(); | |
596 | omap44xx_powerdomains_init(); | |
597 | omap44xx_clockdomains_init(); | |
598 | omap44xx_hwmod_init(); | |
599 | omap_hwmod_init_postsetup(); | |
600 | omap4xxx_clk_init(); | |
8f5b5a41 | 601 | } |
bbd707ac SG |
602 | |
603 | void __init omap4430_init_late(void) | |
604 | { | |
605 | omap_mux_late_init(); | |
606 | omap2_common_pm_late_init(); | |
607 | omap4_pm_init(); | |
23fb8ba3 | 608 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 609 | } |
c4e2d245 | 610 | #endif |
8f5b5a41 | 611 | |
05e152c7 S |
612 | #ifdef CONFIG_SOC_OMAP5 |
613 | void __init omap5_init_early(void) | |
614 | { | |
b6a4226c PW |
615 | omap2_set_globals_tap(OMAP54XX_CLASS, |
616 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
617 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | |
618 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); | |
d9a16f9a PW |
619 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); |
620 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), | |
621 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | |
622 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | |
623 | omap_prm_base_init(); | |
624 | omap_cm_base_init(); | |
05e152c7 S |
625 | omap5xxx_check_revision(); |
626 | omap_common_init_early(); | |
627 | } | |
628 | #endif | |
629 | ||
a4ca9dbe | 630 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
631 | struct omap_sdrc_params *sdrc_cs1) |
632 | { | |
a66cb345 TL |
633 | omap_sram_init(); |
634 | ||
01001712 | 635 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
636 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
637 | _omap2_init_reprogram_sdrc(); | |
638 | } | |
1dbae815 | 639 | } |