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ARM: OMAP2+: PRCM: remove omap2_cm_wait_idlest()
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
2b6c4e73 28#include <plat-omap/dma-omap.h>
ee0839c2 29
622297fd 30#include "../plat-omap/sram.h"
b6a4226c 31#include <plat/prcm.h>
622297fd 32
dc843280 33#include "omap_hwmod.h"
dbc04161 34#include "soc.h"
ee0839c2 35#include "iomap.h"
81a60482 36#include "voltage.h"
72e06d08 37#include "powerdomain.h"
1540f214 38#include "clockdomain.h"
4e65331c 39#include "common.h"
e30384ab 40#include "clock.h"
ee0839c2
TL		 41#include "clock2xxx.h"
42#include "clock3xxx.h"
43#include "clock44xx.h"
1d5aef49 44#include "omap-pm.h"
3e6ece13 45#include "sdrc.h"
b6a4226c 46#include "control.h"
3d82cbbb 47#include "serial.h"
c4ceedcb
PW		 48#include "cm2xxx.h"
49#include "cm3xxx.h"
02bfc030 50
1dbae815
TL		 51/*
52 * The machine specific code may provide the extra mapping besides the
53 * default mapping provided here.
54 */
cc26b3b0 55
e48f814e 56#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 57static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 58 {
59 .virtual = L3_24XX_VIRT,
60 .pfn = __phys_to_pfn(L3_24XX_PHYS),
61 .length = L3_24XX_SIZE,
62 .type = MT_DEVICE
63 },
09f21ed4 64 {
cc26b3b0
SMK		 65 .virtual = L4_24XX_VIRT,
66 .pfn = __phys_to_pfn(L4_24XX_PHYS),
67 .length = L4_24XX_SIZE,
68 .type = MT_DEVICE
09f21ed4 69 },
cc26b3b0
SMK		 70};
71
59b479e0 72#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 73static struct map_desc omap242x_io_desc[] __initdata = {
74 {
7adb9987
PW		 75 .virtual = DSP_MEM_2420_VIRT,
76 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
77 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 78 .type = MT_DEVICE
79 },
80 {
7adb9987
PW		 81 .virtual = DSP_IPI_2420_VIRT,
82 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
83 .length = DSP_IPI_2420_SIZE,
cc26b3b0 84 .type = MT_DEVICE
09f21ed4 85 },
cc26b3b0 86 {
7adb9987
PW		 87 .virtual = DSP_MMU_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
89 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 90 .type = MT_DEVICE
91 },
92};
93
94#endif
95
59b479e0 96#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 97static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 98 {
99 .virtual = L4_WK_243X_VIRT,
100 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
101 .length = L4_WK_243X_SIZE,
102 .type = MT_DEVICE
103 },
104 {
105 .virtual = OMAP243X_GPMC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
107 .length = OMAP243X_GPMC_SIZE,
108 .type = MT_DEVICE
109 },
cc26b3b0
SMK		 110 {
111 .virtual = OMAP243X_SDRC_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
113 .length = OMAP243X_SDRC_SIZE,
114 .type = MT_DEVICE
115 },
116 {
117 .virtual = OMAP243X_SMS_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
119 .length = OMAP243X_SMS_SIZE,
120 .type = MT_DEVICE
121 },
122};
72d0f1c3 123#endif
72d0f1c3 124#endif
cc26b3b0 125
a8eb7ca0 126#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 127static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 128 {
cc26b3b0
SMK		 129 .virtual = L3_34XX_VIRT,
130 .pfn = __phys_to_pfn(L3_34XX_PHYS),
131 .length = L3_34XX_SIZE,
c40fae95
TL		 132 .type = MT_DEVICE
133 },
134 {
cc26b3b0
SMK		 135 .virtual = L4_34XX_VIRT,
136 .pfn = __phys_to_pfn(L4_34XX_PHYS),
137 .length = L4_34XX_SIZE,
c40fae95
TL		 138 .type = MT_DEVICE
139 },
cc26b3b0
SMK		 140 {
141 .virtual = OMAP34XX_GPMC_VIRT,
142 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
143 .length = OMAP34XX_GPMC_SIZE,
1dbae815 144 .type = MT_DEVICE
cc26b3b0
SMK		 145 },
146 {
147 .virtual = OMAP343X_SMS_VIRT,
148 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
149 .length = OMAP343X_SMS_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = OMAP343X_SDRC_VIRT,
154 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
155 .length = OMAP343X_SDRC_SIZE,
1dbae815 156 .type = MT_DEVICE
cc26b3b0
SMK		 157 },
158 {
159 .virtual = L4_PER_34XX_VIRT,
160 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
161 .length = L4_PER_34XX_SIZE,
162 .type = MT_DEVICE
163 },
164 {
165 .virtual = L4_EMU_34XX_VIRT,
166 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
167 .length = L4_EMU_34XX_SIZE,
168 .type = MT_DEVICE
169 },
a4f57b81
TL		 170#if defined(CONFIG_DEBUG_LL) && \
171 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
172 {
173 .virtual = ZOOM_UART_VIRT,
174 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
175 .length = SZ_1M,
176 .type = MT_DEVICE
177 },
178#endif
1dbae815 179};
cc26b3b0 180#endif
01001712 181
33959553 182#ifdef CONFIG_SOC_TI81XX
a920360f 183static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 184 {
185 .virtual = L4_34XX_VIRT,
186 .pfn = __phys_to_pfn(L4_34XX_PHYS),
187 .length = L4_34XX_SIZE,
188 .type = MT_DEVICE
189 }
190};
191#endif
192
bb6abcf4 193#ifdef CONFIG_SOC_AM33XX
1e6cb146 194static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 195 {
196 .virtual = L4_34XX_VIRT,
197 .pfn = __phys_to_pfn(L4_34XX_PHYS),
198 .length = L4_34XX_SIZE,
199 .type = MT_DEVICE
200 },
1e6cb146
AM		 201 {
202 .virtual = L4_WK_AM33XX_VIRT,
203 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
204 .length = L4_WK_AM33XX_SIZE,
205 .type = MT_DEVICE
206 }
01001712
HP		 207};
208#endif
209
44169075
SS		 210#ifdef CONFIG_ARCH_OMAP4
211static struct map_desc omap44xx_io_desc[] __initdata = {
212 {
213 .virtual = L3_44XX_VIRT,
214 .pfn = __phys_to_pfn(L3_44XX_PHYS),
215 .length = L3_44XX_SIZE,
216 .type = MT_DEVICE,
217 },
218 {
219 .virtual = L4_44XX_VIRT,
220 .pfn = __phys_to_pfn(L4_44XX_PHYS),
221 .length = L4_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
44169075
SS		 224 {
225 .virtual = L4_PER_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
227 .length = L4_PER_44XX_SIZE,
228 .type = MT_DEVICE,
229 },
137d105d
SS		 230#ifdef CONFIG_OMAP4_ERRATA_I688
231 {
232 .virtual = OMAP4_SRAM_VA,
233 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
234 .length = PAGE_SIZE,
235 .type = MT_MEMORY_SO,
236 },
237#endif
238
44169075
SS		 239};
240#endif
1dbae815 241
05e152c7
S		 242#ifdef CONFIG_SOC_OMAP5
243static struct map_desc omap54xx_io_desc[] __initdata = {
244 {
245 .virtual = L3_54XX_VIRT,
246 .pfn = __phys_to_pfn(L3_54XX_PHYS),
247 .length = L3_54XX_SIZE,
248 .type = MT_DEVICE,
249 },
250 {
251 .virtual = L4_54XX_VIRT,
252 .pfn = __phys_to_pfn(L4_54XX_PHYS),
253 .length = L4_54XX_SIZE,
254 .type = MT_DEVICE,
255 },
256 {
257 .virtual = L4_WK_54XX_VIRT,
258 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
259 .length = L4_WK_54XX_SIZE,
260 .type = MT_DEVICE,
261 },
262 {
263 .virtual = L4_PER_54XX_VIRT,
264 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
265 .length = L4_PER_54XX_SIZE,
266 .type = MT_DEVICE,
267 },
268};
269#endif
270
59b479e0 271#ifdef CONFIG_SOC_OMAP2420
b6a4226c 272void __init omap242x_map_io(void)
1dbae815 273{
cc26b3b0
SMK		 274 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
275 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 276}
cc26b3b0
SMK		 277#endif
278
59b479e0 279#ifdef CONFIG_SOC_OMAP2430
b6a4226c 280void __init omap243x_map_io(void)
6fbd55d0 281{
cc26b3b0
SMK		 282 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
283 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 284}
cc26b3b0
SMK		 285#endif
286
a8eb7ca0 287#ifdef CONFIG_ARCH_OMAP3
b6a4226c 288void __init omap3_map_io(void)
6fbd55d0 289{
cc26b3b0 290 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 291}
cc26b3b0 292#endif
120db2cb 293
33959553 294#ifdef CONFIG_SOC_TI81XX
b6a4226c 295void __init ti81xx_map_io(void)
01001712 296{
a920360f 297 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 298}
299#endif
300
bb6abcf4 301#ifdef CONFIG_SOC_AM33XX
b6a4226c 302void __init am33xx_map_io(void)
01001712 303{
1e6cb146 304 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 305}
306#endif
307
6fbd55d0 308#ifdef CONFIG_ARCH_OMAP4
b6a4226c 309void __init omap4_map_io(void)
6fbd55d0 310{
44169075 311 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 312 omap_barriers_init();
120db2cb 313}
6fbd55d0 314#endif
120db2cb 315
05e152c7 316#ifdef CONFIG_SOC_OMAP5
b6a4226c 317void __init omap5_map_io(void)
05e152c7
S		 318{
319 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
320}
321#endif
2f135eaf
PW		 322/*
323 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
324 *
325 * Sets the CORE DPLL3 M2 divider to the same value that it's at
326 * currently. This has the effect of setting the SDRC SDRAM AC timing
327 * registers to the values currently defined by the kernel. Currently
328 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
329 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
330 * or passes along the return value of clk_set_rate().
331 */
332static int __init _omap2_init_reprogram_sdrc(void)
333{
334 struct clk *dpll3_m2_ck;
335 int v = -EINVAL;
336 long rate;
337
338 if (!cpu_is_omap34xx())
339 return 0;
340
341 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 342 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 343 return -EINVAL;
344
345 rate = clk_get_rate(dpll3_m2_ck);
346 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
347 v = clk_set_rate(dpll3_m2_ck, rate);
348 if (v)
349 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
350
351 clk_put(dpll3_m2_ck);
352
353 return v;
354}
355
2092e5cc
PW		 356static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
357{
358 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
359}
360
7b250aff 361static void __init omap_common_init_early(void)
120db2cb 362{
df80442d 363 omap_init_consistent_dma_size();
7b250aff 364}
2092e5cc 365
7b250aff
TL		 366static void __init omap_hwmod_init_postsetup(void)
367{
368 u8 postsetup_state;
2092e5cc
PW		 369
370 /* Set the default postsetup state for all hwmods */
371#ifdef CONFIG_PM_RUNTIME
372 postsetup_state = _HWMOD_STATE_IDLE;
373#else
374 postsetup_state = _HWMOD_STATE_ENABLED;
375#endif
376 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 377
53da4ce2 378 omap_pm_if_early_init();
4805734b
PW		 379}
380
16110798 381#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 382void __init omap2420_init_early(void)
383{
b6a4226c
PW		 384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
387 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
388 NULL);
389 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
390 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
391 NULL, NULL);
4de34f35 392 omap2xxx_check_revision();
c4ceedcb 393 omap2xxx_cm_init();
7b250aff
TL		 394 omap_common_init_early();
395 omap2xxx_voltagedomains_init();
396 omap242x_powerdomains_init();
397 omap242x_clockdomains_init();
398 omap2420_hwmod_init();
399 omap_hwmod_init_postsetup();
400 omap2420_clk_init();
8f5b5a41 401}
bbd707ac
SG		 402
403void __init omap2420_init_late(void)
404{
405 omap_mux_late_init();
406 omap2_common_pm_late_init();
407 omap2_pm_init();
408}
16110798 409#endif
8f5b5a41 410
16110798 411#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 412void __init omap2430_init_early(void)
413{
b6a4226c
PW		 414 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
415 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
416 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
417 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
418 NULL);
419 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
420 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
421 NULL, NULL);
4de34f35 422 omap2xxx_check_revision();
c4ceedcb 423 omap2xxx_cm_init();
7b250aff
TL		 424 omap_common_init_early();
425 omap2xxx_voltagedomains_init();
426 omap243x_powerdomains_init();
427 omap243x_clockdomains_init();
428 omap2430_hwmod_init();
429 omap_hwmod_init_postsetup();
430 omap2430_clk_init();
431}
bbd707ac
SG		 432
433void __init omap2430_init_late(void)
434{
435 omap_mux_late_init();
436 omap2_common_pm_late_init();
437 omap2_pm_init();
438}
c4e2d245 439#endif
7b250aff
TL		 440
441/*
442 * Currently only board-omap3beagle.c should call this because of the
443 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
444 */
c4e2d245 445#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 446void __init omap3_init_early(void)
447{
b6a4226c
PW		 448 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
449 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
450 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
451 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
452 NULL);
453 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
454 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
455 NULL, NULL);
4de34f35
VH		 456 omap3xxx_check_revision();
457 omap3xxx_check_features();
c4ceedcb 458 omap3xxx_cm_init();
7b250aff
TL		 459 omap_common_init_early();
460 omap3xxx_voltagedomains_init();
461 omap3xxx_powerdomains_init();
462 omap3xxx_clockdomains_init();
463 omap3xxx_hwmod_init();
464 omap_hwmod_init_postsetup();
465 omap3xxx_clk_init();
8f5b5a41
TL		 466}
467
468void __init omap3430_init_early(void)
469{
7b250aff 470 omap3_init_early();
8f5b5a41
TL		 471}
472
473void __init omap35xx_init_early(void)
474{
7b250aff 475 omap3_init_early();
8f5b5a41
TL		 476}
477
478void __init omap3630_init_early(void)
479{
7b250aff 480 omap3_init_early();
8f5b5a41
TL		 481}
482
483void __init am35xx_init_early(void)
484{
7b250aff 485 omap3_init_early();
8f5b5a41
TL		 486}
487
a920360f 488void __init ti81xx_init_early(void)
8f5b5a41 489{
b6a4226c
PW		 490 omap2_set_globals_tap(OMAP343X_CLASS,
491 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
492 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
493 NULL);
494 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
495 OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
496 NULL, NULL);
4de34f35
VH		 497 omap3xxx_check_revision();
498 ti81xx_check_features();
4c3cf901
TL		 499 omap_common_init_early();
500 omap3xxx_voltagedomains_init();
501 omap3xxx_powerdomains_init();
502 omap3xxx_clockdomains_init();
503 omap3xxx_hwmod_init();
504 omap_hwmod_init_postsetup();
505 omap3xxx_clk_init();
8f5b5a41 506}
bbd707ac
SG		 507
508void __init omap3_init_late(void)
509{
510 omap_mux_late_init();
511 omap2_common_pm_late_init();
512 omap3_pm_init();
513}
514
515void __init omap3430_init_late(void)
516{
517 omap_mux_late_init();
518 omap2_common_pm_late_init();
519 omap3_pm_init();
520}
521
522void __init omap35xx_init_late(void)
523{
524 omap_mux_late_init();
525 omap2_common_pm_late_init();
526 omap3_pm_init();
527}
528
529void __init omap3630_init_late(void)
530{
531 omap_mux_late_init();
532 omap2_common_pm_late_init();
533 omap3_pm_init();
534}
535
536void __init am35xx_init_late(void)
537{
538 omap_mux_late_init();
539 omap2_common_pm_late_init();
540 omap3_pm_init();
541}
542
543void __init ti81xx_init_late(void)
544{
545 omap_mux_late_init();
546 omap2_common_pm_late_init();
547 omap3_pm_init();
548}
c4e2d245 549#endif
8f5b5a41 550
08f30989
AM		 551#ifdef CONFIG_SOC_AM33XX
552void __init am33xx_init_early(void)
553{
b6a4226c
PW		 554 omap2_set_globals_tap(AM335X_CLASS,
555 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
556 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
557 NULL);
558 omap2_set_globals_prcm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
559 AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
560 NULL, NULL);
08f30989
AM		 561 omap3xxx_check_revision();
562 ti81xx_check_features();
563 omap_common_init_early();
ce3fc89a 564 am33xx_voltagedomains_init();
3f0ea764 565 am33xx_powerdomains_init();
9c80f3aa 566 am33xx_clockdomains_init();
a2cfc509
VH		 567 am33xx_hwmod_init();
568 omap_hwmod_init_postsetup();
e30384ab 569 am33xx_clk_init();
08f30989
AM		 570}
571#endif
572
c4e2d245 573#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 574void __init omap4430_init_early(void)
575{
b6a4226c
PW		 576 omap2_set_globals_tap(OMAP443X_CLASS,
577 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
578 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
579 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
580 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
581 OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
582 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
583 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
4de34f35
VH		 584 omap4xxx_check_revision();
585 omap4xxx_check_features();
7b250aff
TL		 586 omap_common_init_early();
587 omap44xx_voltagedomains_init();
588 omap44xx_powerdomains_init();
589 omap44xx_clockdomains_init();
590 omap44xx_hwmod_init();
591 omap_hwmod_init_postsetup();
592 omap4xxx_clk_init();
8f5b5a41 593}
bbd707ac
SG		 594
595void __init omap4430_init_late(void)
596{
597 omap_mux_late_init();
598 omap2_common_pm_late_init();
599 omap4_pm_init();
600}
c4e2d245 601#endif
8f5b5a41 602
05e152c7
S		 603#ifdef CONFIG_SOC_OMAP5
604void __init omap5_init_early(void)
605{
b6a4226c
PW		 606 omap2_set_globals_tap(OMAP54XX_CLASS,
607 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
608 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
609 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
610 omap2_set_globals_prcm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
611 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
612 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
613 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
05e152c7
S		 614 omap5xxx_check_revision();
615 omap_common_init_early();
616}
617#endif
618
a4ca9dbe 619void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 620 struct omap_sdrc_params *sdrc_cs1)
621{
a66cb345
TL		 622 omap_sram_init();
623
01001712 624 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 625 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
626 _omap2_init_reprogram_sdrc();
627 }
1dbae815 628}
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