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[mirror_ubuntu-zesty-kernel.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
1dbae815
TL		 19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
fced80c7 22#include <linux/io.h>
2f135eaf 23#include <linux/clk.h>
1dbae815 24
120db2cb 25#include <asm/tlb.h>
120db2cb
TL		 26#include <asm/mach/map.h>
27
45c3eb7d 28#include <linux/omap-dma.h>
ee0839c2 29
dc843280 30#include "omap_hwmod.h"
dbc04161 31#include "soc.h"
ee0839c2 32#include "iomap.h"
81a60482 33#include "voltage.h"
72e06d08 34#include "powerdomain.h"
1540f214 35#include "clockdomain.h"
4e65331c 36#include "common.h"
e30384ab 37#include "clock.h"
ee0839c2
TL		 38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
1d5aef49 41#include "omap-pm.h"
3e6ece13 42#include "sdrc.h"
b6a4226c 43#include "control.h"
3d82cbbb 44#include "serial.h"
bf027ca1 45#include "sram.h"
c4ceedcb
PW		 46#include "cm2xxx.h"
47#include "cm3xxx.h"
7632a02f 48#include "cm33xx.h"
ab6c9bbf 49#include "cm44xx.h"
d9a16f9a
PW		 50#include "prm.h"
51#include "cm.h"
52#include "prcm_mpu44xx.h"
53#include "prminst44xx.h"
63a293e0
PW		 54#include "prm2xxx.h"
55#include "prm3xxx.h"
d9bbe84f 56#include "prm33xx.h"
63a293e0 57#include "prm44xx.h"
69a1e7a1 58#include "opp2xxx.h"
02bfc030 59
ff931c82 60/*
cfa9667d 61 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 62 * clock initializations
63 */
cfa9667d 64static int (*omap_clk_soc_init)(void);
ff931c82 65
1dbae815
TL		 66/*
67 * The machine specific code may provide the extra mapping besides the
68 * default mapping provided here.
69 */
cc26b3b0 70
e48f814e 71#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 72static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 73 {
74 .virtual = L3_24XX_VIRT,
75 .pfn = __phys_to_pfn(L3_24XX_PHYS),
76 .length = L3_24XX_SIZE,
77 .type = MT_DEVICE
78 },
09f21ed4 79 {
cc26b3b0
SMK		 80 .virtual = L4_24XX_VIRT,
81 .pfn = __phys_to_pfn(L4_24XX_PHYS),
82 .length = L4_24XX_SIZE,
83 .type = MT_DEVICE
09f21ed4 84 },
cc26b3b0
SMK		 85};
86
59b479e0 87#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 88static struct map_desc omap242x_io_desc[] __initdata = {
89 {
7adb9987
PW		 90 .virtual = DSP_MEM_2420_VIRT,
91 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
92 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 93 .type = MT_DEVICE
94 },
95 {
7adb9987
PW		 96 .virtual = DSP_IPI_2420_VIRT,
97 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
98 .length = DSP_IPI_2420_SIZE,
cc26b3b0 99 .type = MT_DEVICE
09f21ed4 100 },
cc26b3b0 101 {
7adb9987
PW		 102 .virtual = DSP_MMU_2420_VIRT,
103 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
104 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 105 .type = MT_DEVICE
106 },
107};
108
109#endif
110
59b479e0 111#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 112static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 113 {
114 .virtual = L4_WK_243X_VIRT,
115 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
116 .length = L4_WK_243X_SIZE,
117 .type = MT_DEVICE
118 },
119 {
120 .virtual = OMAP243X_GPMC_VIRT,
121 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
122 .length = OMAP243X_GPMC_SIZE,
123 .type = MT_DEVICE
124 },
cc26b3b0
SMK		 125 {
126 .virtual = OMAP243X_SDRC_VIRT,
127 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
128 .length = OMAP243X_SDRC_SIZE,
129 .type = MT_DEVICE
130 },
131 {
132 .virtual = OMAP243X_SMS_VIRT,
133 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
134 .length = OMAP243X_SMS_SIZE,
135 .type = MT_DEVICE
136 },
137};
72d0f1c3 138#endif
72d0f1c3 139#endif
cc26b3b0 140
a8eb7ca0 141#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 142static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 143 {
cc26b3b0
SMK		 144 .virtual = L3_34XX_VIRT,
145 .pfn = __phys_to_pfn(L3_34XX_PHYS),
146 .length = L3_34XX_SIZE,
c40fae95
TL		 147 .type = MT_DEVICE
148 },
149 {
cc26b3b0
SMK		 150 .virtual = L4_34XX_VIRT,
151 .pfn = __phys_to_pfn(L4_34XX_PHYS),
152 .length = L4_34XX_SIZE,
c40fae95
TL		 153 .type = MT_DEVICE
154 },
cc26b3b0
SMK		 155 {
156 .virtual = OMAP34XX_GPMC_VIRT,
157 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
158 .length = OMAP34XX_GPMC_SIZE,
1dbae815 159 .type = MT_DEVICE
cc26b3b0
SMK		 160 },
161 {
162 .virtual = OMAP343X_SMS_VIRT,
163 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
164 .length = OMAP343X_SMS_SIZE,
165 .type = MT_DEVICE
166 },
167 {
168 .virtual = OMAP343X_SDRC_VIRT,
169 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
170 .length = OMAP343X_SDRC_SIZE,
1dbae815 171 .type = MT_DEVICE
cc26b3b0
SMK		 172 },
173 {
174 .virtual = L4_PER_34XX_VIRT,
175 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
176 .length = L4_PER_34XX_SIZE,
177 .type = MT_DEVICE
178 },
179 {
180 .virtual = L4_EMU_34XX_VIRT,
181 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
182 .length = L4_EMU_34XX_SIZE,
183 .type = MT_DEVICE
184 },
1dbae815 185};
cc26b3b0 186#endif
01001712 187
33959553 188#ifdef CONFIG_SOC_TI81XX
a920360f 189static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 190 {
191 .virtual = L4_34XX_VIRT,
192 .pfn = __phys_to_pfn(L4_34XX_PHYS),
193 .length = L4_34XX_SIZE,
194 .type = MT_DEVICE
195 }
196};
197#endif
198
addb154a 199#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 200static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 201 {
202 .virtual = L4_34XX_VIRT,
203 .pfn = __phys_to_pfn(L4_34XX_PHYS),
204 .length = L4_34XX_SIZE,
205 .type = MT_DEVICE
206 },
1e6cb146
AM		 207 {
208 .virtual = L4_WK_AM33XX_VIRT,
209 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
210 .length = L4_WK_AM33XX_SIZE,
211 .type = MT_DEVICE
212 }
01001712
HP		 213};
214#endif
215
44169075
SS		 216#ifdef CONFIG_ARCH_OMAP4
217static struct map_desc omap44xx_io_desc[] __initdata = {
218 {
219 .virtual = L3_44XX_VIRT,
220 .pfn = __phys_to_pfn(L3_44XX_PHYS),
221 .length = L3_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
224 {
225 .virtual = L4_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_44XX_PHYS),
227 .length = L4_44XX_SIZE,
228 .type = MT_DEVICE,
229 },
44169075
SS		 230 {
231 .virtual = L4_PER_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
233 .length = L4_PER_44XX_SIZE,
234 .type = MT_DEVICE,
235 },
44169075
SS		 236};
237#endif
1dbae815 238
a3a9384a 239#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
05e152c7
S		 240static struct map_desc omap54xx_io_desc[] __initdata = {
241 {
242 .virtual = L3_54XX_VIRT,
243 .pfn = __phys_to_pfn(L3_54XX_PHYS),
244 .length = L3_54XX_SIZE,
245 .type = MT_DEVICE,
246 },
247 {
248 .virtual = L4_54XX_VIRT,
249 .pfn = __phys_to_pfn(L4_54XX_PHYS),
250 .length = L4_54XX_SIZE,
251 .type = MT_DEVICE,
252 },
253 {
254 .virtual = L4_WK_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
256 .length = L4_WK_54XX_SIZE,
257 .type = MT_DEVICE,
258 },
259 {
260 .virtual = L4_PER_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
262 .length = L4_PER_54XX_SIZE,
263 .type = MT_DEVICE,
264 },
265};
266#endif
267
59b479e0 268#ifdef CONFIG_SOC_OMAP2420
b6a4226c 269void __init omap242x_map_io(void)
1dbae815 270{
cc26b3b0
SMK		 271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
272 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 273}
cc26b3b0
SMK		 274#endif
275
59b479e0 276#ifdef CONFIG_SOC_OMAP2430
b6a4226c 277void __init omap243x_map_io(void)
6fbd55d0 278{
cc26b3b0
SMK		 279 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
280 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 281}
cc26b3b0
SMK		 282#endif
283
a8eb7ca0 284#ifdef CONFIG_ARCH_OMAP3
b6a4226c 285void __init omap3_map_io(void)
6fbd55d0 286{
cc26b3b0 287 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 288}
cc26b3b0 289#endif
120db2cb 290
33959553 291#ifdef CONFIG_SOC_TI81XX
b6a4226c 292void __init ti81xx_map_io(void)
01001712 293{
a920360f 294 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 295}
296#endif
297
addb154a 298#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 299void __init am33xx_map_io(void)
01001712 300{
1e6cb146 301 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 302}
303#endif
304
6fbd55d0 305#ifdef CONFIG_ARCH_OMAP4
b6a4226c 306void __init omap4_map_io(void)
6fbd55d0 307{
44169075 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
2ec1fc4e 309 omap_barriers_init();
120db2cb 310}
6fbd55d0 311#endif
120db2cb 312
a3a9384a 313#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
b6a4226c 314void __init omap5_map_io(void)
05e152c7
S		 315{
316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
1348bbf9 317 omap_barriers_init();
05e152c7
S		 318}
319#endif
2f135eaf
PW		 320/*
321 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
322 *
323 * Sets the CORE DPLL3 M2 divider to the same value that it's at
324 * currently. This has the effect of setting the SDRC SDRAM AC timing
325 * registers to the values currently defined by the kernel. Currently
326 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
327 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
328 * or passes along the return value of clk_set_rate().
329 */
330static int __init _omap2_init_reprogram_sdrc(void)
331{
332 struct clk *dpll3_m2_ck;
333 int v = -EINVAL;
334 long rate;
335
336 if (!cpu_is_omap34xx())
337 return 0;
338
339 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 340 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 341 return -EINVAL;
342
343 rate = clk_get_rate(dpll3_m2_ck);
344 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
345 v = clk_set_rate(dpll3_m2_ck, rate);
346 if (v)
347 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
348
349 clk_put(dpll3_m2_ck);
350
351 return v;
352}
353
2092e5cc
PW		 354static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
355{
356 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
357}
358
7b250aff
TL		 359static void __init omap_hwmod_init_postsetup(void)
360{
361 u8 postsetup_state;
2092e5cc
PW		 362
363 /* Set the default postsetup state for all hwmods */
364#ifdef CONFIG_PM_RUNTIME
365 postsetup_state = _HWMOD_STATE_IDLE;
366#else
367 postsetup_state = _HWMOD_STATE_ENABLED;
368#endif
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
55d2cb08 370
53da4ce2 371 omap_pm_if_early_init();
4805734b
PW		 372}
373
069d0a78 374static void __init __maybe_unused omap_common_late_init(void)
4ed12be0
RB		 375{
376 omap_mux_late_init();
377 omap2_common_pm_late_init();
6770b211 378 omap_soc_device_init();
4ed12be0
RB		 379}
380
16110798 381#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 382void __init omap2420_init_early(void)
383{
b6a4226c
PW		 384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
387 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
388 NULL);
d9a16f9a
PW		 389 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
390 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
4de34f35 391 omap2xxx_check_revision();
63a293e0 392 omap2xxx_prm_init();
c4ceedcb 393 omap2xxx_cm_init();
7b250aff
TL		 394 omap2xxx_voltagedomains_init();
395 omap242x_powerdomains_init();
396 omap242x_clockdomains_init();
397 omap2420_hwmod_init();
398 omap_hwmod_init_postsetup();
6a194a6e
TK		 399 omap_clk_soc_init = omap2420_dt_clk_init;
400 rate_table = omap2420_rate_table;
8f5b5a41 401}
bbd707ac
SG		 402
403void __init omap2420_init_late(void)
404{
4ed12be0 405 omap_common_late_init();
bbd707ac 406 omap2_pm_init();
23fb8ba3 407 omap2_clk_enable_autoidle_all();
bbd707ac 408}
16110798 409#endif
8f5b5a41 410
16110798 411#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 412void __init omap2430_init_early(void)
413{
b6a4226c
PW		 414 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
415 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
416 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
417 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
418 NULL);
d9a16f9a
PW		 419 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
420 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
4de34f35 421 omap2xxx_check_revision();
63a293e0 422 omap2xxx_prm_init();
c4ceedcb 423 omap2xxx_cm_init();
7b250aff
TL		 424 omap2xxx_voltagedomains_init();
425 omap243x_powerdomains_init();
426 omap243x_clockdomains_init();
427 omap2430_hwmod_init();
428 omap_hwmod_init_postsetup();
6a194a6e
TK		 429 omap_clk_soc_init = omap2430_dt_clk_init;
430 rate_table = omap2430_rate_table;
7b250aff 431}
bbd707ac
SG		 432
433void __init omap2430_init_late(void)
434{
4ed12be0 435 omap_common_late_init();
bbd707ac 436 omap2_pm_init();
23fb8ba3 437 omap2_clk_enable_autoidle_all();
bbd707ac 438}
c4e2d245 439#endif
7b250aff
TL		 440
441/*
442 * Currently only board-omap3beagle.c should call this because of the
443 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
444 */
c4e2d245 445#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 446void __init omap3_init_early(void)
447{
b6a4226c
PW		 448 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
449 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
450 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
451 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
452 NULL);
d9a16f9a
PW		 453 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
454 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
4de34f35
VH		 455 omap3xxx_check_revision();
456 omap3xxx_check_features();
63a293e0 457 omap3xxx_prm_init();
c4ceedcb 458 omap3xxx_cm_init();
7b250aff
TL		 459 omap3xxx_voltagedomains_init();
460 omap3xxx_powerdomains_init();
461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup();
cfa9667d 464 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41
TL		 465}
466
467void __init omap3430_init_early(void)
468{
7b250aff 469 omap3_init_early();
3e049157
TK		 470 if (of_have_populated_dt())
471 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 472}
473
474void __init omap35xx_init_early(void)
475{
7b250aff 476 omap3_init_early();
3e049157
TK		 477 if (of_have_populated_dt())
478 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 479}
480
481void __init omap3630_init_early(void)
482{
7b250aff 483 omap3_init_early();
3e049157
TK		 484 if (of_have_populated_dt())
485 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 486}
487
488void __init am35xx_init_early(void)
489{
7b250aff 490 omap3_init_early();
3e049157
TK		 491 if (of_have_populated_dt())
492 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 493}
494
a920360f 495void __init ti81xx_init_early(void)
8f5b5a41 496{
b6a4226c
PW		 497 omap2_set_globals_tap(OMAP343X_CLASS,
498 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
499 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
500 NULL);
d9a16f9a
PW		 501 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
502 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
4de34f35
VH		 503 omap3xxx_check_revision();
504 ti81xx_check_features();
4c3cf901
TL		 505 omap3xxx_voltagedomains_init();
506 omap3xxx_powerdomains_init();
507 omap3xxx_clockdomains_init();
508 omap3xxx_hwmod_init();
509 omap_hwmod_init_postsetup();
3e049157
TK		 510 if (of_have_populated_dt())
511 omap_clk_soc_init = ti81xx_dt_clk_init;
512 else
513 omap_clk_soc_init = omap3xxx_clk_init;
8f5b5a41 514}
bbd707ac
SG		 515
516void __init omap3_init_late(void)
517{
4ed12be0 518 omap_common_late_init();
bbd707ac 519 omap3_pm_init();
23fb8ba3 520 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 521}
522
523void __init omap3430_init_late(void)
524{
4ed12be0 525 omap_common_late_init();
bbd707ac 526 omap3_pm_init();
23fb8ba3 527 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 528}
529
530void __init omap35xx_init_late(void)
531{
4ed12be0 532 omap_common_late_init();
bbd707ac 533 omap3_pm_init();
23fb8ba3 534 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 535}
536
537void __init omap3630_init_late(void)
538{
4ed12be0 539 omap_common_late_init();
bbd707ac 540 omap3_pm_init();
23fb8ba3 541 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 542}
543
544void __init am35xx_init_late(void)
545{
4ed12be0 546 omap_common_late_init();
bbd707ac 547 omap3_pm_init();
23fb8ba3 548 omap2_clk_enable_autoidle_all();
bbd707ac
SG		 549}
550
551void __init ti81xx_init_late(void)
552{
4ed12be0 553 omap_common_late_init();
bbd707ac 554 omap3_pm_init();
23fb8ba3 555 omap2_clk_enable_autoidle_all();
bbd707ac 556}
c4e2d245 557#endif
8f5b5a41 558
08f30989
AM		 559#ifdef CONFIG_SOC_AM33XX
560void __init am33xx_init_early(void)
561{
b6a4226c
PW		 562 omap2_set_globals_tap(AM335X_CLASS,
563 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
564 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
565 NULL);
d9a16f9a
PW		 566 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
567 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
08f30989 568 omap3xxx_check_revision();
7bcad170 569 am33xx_check_features();
d9bbe84f 570 am33xx_prm_init();
7632a02f 571 am33xx_cm_init();
3f0ea764 572 am33xx_powerdomains_init();
9c80f3aa 573 am33xx_clockdomains_init();
a2cfc509
VH		 574 am33xx_hwmod_init();
575 omap_hwmod_init_postsetup();
149c09d3 576 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 577}
765e7a06
NM		 578
579void __init am33xx_init_late(void)
580{
581 omap_common_late_init();
582}
08f30989
AM		 583#endif
584
c5107027
AM		 585#ifdef CONFIG_SOC_AM43XX
586void __init am43xx_init_early(void)
587{
588 omap2_set_globals_tap(AM335X_CLASS,
589 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
590 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
591 NULL);
592 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
593 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
8835cf6e
A		 594 omap_prm_base_init();
595 omap_cm_base_init();
c5107027 596 omap3xxx_check_revision();
7a2e0513 597 am33xx_check_features();
8843b119 598 omap44xx_prm_init();
7632a02f 599 omap4_cm_init();
8835cf6e
A		 600 am43xx_powerdomains_init();
601 am43xx_clockdomains_init();
602 am43xx_hwmod_init();
603 omap_hwmod_init_postsetup();
d941f86f 604 omap_l2_cache_init();
d22031e2 605 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 606}
765e7a06
NM		 607
608void __init am43xx_init_late(void)
609{
610 omap_common_late_init();
611}
c5107027
AM		 612#endif
613
c4e2d245 614#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 615void __init omap4430_init_early(void)
616{
b6a4226c
PW		 617 omap2_set_globals_tap(OMAP443X_CLASS,
618 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
619 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
620 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
d9a16f9a
PW		 621 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
622 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
623 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
624 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
625 omap_prm_base_init();
626 omap_cm_base_init();
4de34f35
VH		 627 omap4xxx_check_revision();
628 omap4xxx_check_features();
7632a02f 629 omap4_cm_init();
de70af49 630 omap4_pm_init_early();
63a293e0 631 omap44xx_prm_init();
7b250aff
TL		 632 omap44xx_voltagedomains_init();
633 omap44xx_powerdomains_init();
634 omap44xx_clockdomains_init();
635 omap44xx_hwmod_init();
636 omap_hwmod_init_postsetup();
b39b14e6 637 omap_l2_cache_init();
c8c88d85 638 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 639}
bbd707ac
SG		 640
641void __init omap4430_init_late(void)
642{
4ed12be0 643 omap_common_late_init();
bbd707ac 644 omap4_pm_init();
23fb8ba3 645 omap2_clk_enable_autoidle_all();
bbd707ac 646}
c4e2d245 647#endif
8f5b5a41 648
05e152c7
S		 649#ifdef CONFIG_SOC_OMAP5
650void __init omap5_init_early(void)
651{
b6a4226c
PW		 652 omap2_set_globals_tap(OMAP54XX_CLASS,
653 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
654 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
655 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
d9a16f9a
PW		 656 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
657 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
658 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
628ed471 660 omap4_pm_init_early();
d9a16f9a
PW		 661 omap_prm_base_init();
662 omap_cm_base_init();
e4020aa9 663 omap44xx_prm_init();
05e152c7 664 omap5xxx_check_revision();
7632a02f 665 omap4_cm_init();
e4020aa9
SS		 666 omap54xx_voltagedomains_init();
667 omap54xx_powerdomains_init();
668 omap54xx_clockdomains_init();
669 omap54xx_hwmod_init();
670 omap_hwmod_init_postsetup();
cfa9667d 671 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 672}
765e7a06
NM		 673
674void __init omap5_init_late(void)
675{
676 omap_common_late_init();
628ed471
SS		 677 omap4_pm_init();
678 omap2_clk_enable_autoidle_all();
765e7a06 679}
05e152c7
S		 680#endif
681
a3a9384a
S		 682#ifdef CONFIG_SOC_DRA7XX
683void __init dra7xx_init_early(void)
684{
685 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
686 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
687 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
688 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
689 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
690 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
691 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
6af16a1d 692 omap4_pm_init_early();
a3a9384a
S		 693 omap_prm_base_init();
694 omap_cm_base_init();
7de516a6 695 omap44xx_prm_init();
733d20ee 696 dra7xxx_check_revision();
7632a02f 697 omap4_cm_init();
7de516a6
A		 698 dra7xx_powerdomains_init();
699 dra7xx_clockdomains_init();
700 dra7xx_hwmod_init();
701 omap_hwmod_init_postsetup();
f1cf498e 702 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 703}
765e7a06
NM		 704
705void __init dra7xx_init_late(void)
706{
707 omap_common_late_init();
6af16a1d
RN		 708 omap4_pm_init();
709 omap2_clk_enable_autoidle_all();
765e7a06 710}
a3a9384a
S		 711#endif
712
713
a4ca9dbe 714void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 715 struct omap_sdrc_params *sdrc_cs1)
716{
a66cb345
TL		 717 omap_sram_init();
718
01001712 719 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 720 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
721 _omap2_init_reprogram_sdrc();
722 }
1dbae815 723}
cfa9667d
TK		 724
725int __init omap_clk_init(void)
726{
727 int ret = 0;
728
729 if (!omap_clk_soc_init)
730 return 0;
731
8111e010
TK		 732 ti_clk_init_features();
733
cfa9667d 734 ret = of_prcm_init();
c08ee14c
TK		 735 if (ret)
736 return ret;
737
738 of_clk_init(NULL);
739
740 ti_dt_clk_init_retry_clks();
741
742 ti_dt_clockdomains_setup();
743
744 ret = omap_clk_soc_init();
cfa9667d
TK		 745
746 return ret;
747}
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