]>
Commit | Line | Data |
---|---|---|
1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/io.c | |
3 | * | |
4 | * OMAP2 I/O mapping code | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
44169075 | 7 | * Copyright (C) 2007-2009 Texas Instruments |
646e3ed1 TL |
8 | * |
9 | * Author: | |
10 | * Juha Yrjola <juha.yrjola@nokia.com> | |
11 | * Syed Khasim <x0khasim@ti.com> | |
1dbae815 | 12 | * |
44169075 SS |
13 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> |
14 | * | |
1dbae815 TL |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
1dbae815 TL |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/init.h> | |
fced80c7 | 22 | #include <linux/io.h> |
2f135eaf | 23 | #include <linux/clk.h> |
1dbae815 | 24 | |
120db2cb | 25 | #include <asm/tlb.h> |
120db2cb TL |
26 | #include <asm/mach/map.h> |
27 | ||
45c3eb7d | 28 | #include <linux/omap-dma.h> |
ee0839c2 | 29 | |
dc843280 | 30 | #include "omap_hwmod.h" |
dbc04161 | 31 | #include "soc.h" |
ee0839c2 | 32 | #include "iomap.h" |
81a60482 | 33 | #include "voltage.h" |
72e06d08 | 34 | #include "powerdomain.h" |
1540f214 | 35 | #include "clockdomain.h" |
4e65331c | 36 | #include "common.h" |
e30384ab | 37 | #include "clock.h" |
ee0839c2 TL |
38 | #include "clock2xxx.h" |
39 | #include "clock3xxx.h" | |
40 | #include "clock44xx.h" | |
1d5aef49 | 41 | #include "omap-pm.h" |
3e6ece13 | 42 | #include "sdrc.h" |
b6a4226c | 43 | #include "control.h" |
3d82cbbb | 44 | #include "serial.h" |
bf027ca1 | 45 | #include "sram.h" |
c4ceedcb PW |
46 | #include "cm2xxx.h" |
47 | #include "cm3xxx.h" | |
7632a02f | 48 | #include "cm33xx.h" |
ab6c9bbf | 49 | #include "cm44xx.h" |
d9a16f9a PW |
50 | #include "prm.h" |
51 | #include "cm.h" | |
52 | #include "prcm_mpu44xx.h" | |
53 | #include "prminst44xx.h" | |
63a293e0 PW |
54 | #include "prm2xxx.h" |
55 | #include "prm3xxx.h" | |
d9bbe84f | 56 | #include "prm33xx.h" |
63a293e0 | 57 | #include "prm44xx.h" |
69a1e7a1 | 58 | #include "opp2xxx.h" |
02bfc030 | 59 | |
ff931c82 | 60 | /* |
cfa9667d | 61 | * omap_clk_soc_init: points to a function that does the SoC-specific |
ff931c82 RN |
62 | * clock initializations |
63 | */ | |
cfa9667d | 64 | static int (*omap_clk_soc_init)(void); |
ff931c82 | 65 | |
1dbae815 TL |
66 | /* |
67 | * The machine specific code may provide the extra mapping besides the | |
68 | * default mapping provided here. | |
69 | */ | |
cc26b3b0 | 70 | |
e48f814e | 71 | #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) |
cc26b3b0 | 72 | static struct map_desc omap24xx_io_desc[] __initdata = { |
1dbae815 TL |
73 | { |
74 | .virtual = L3_24XX_VIRT, | |
75 | .pfn = __phys_to_pfn(L3_24XX_PHYS), | |
76 | .length = L3_24XX_SIZE, | |
77 | .type = MT_DEVICE | |
78 | }, | |
09f21ed4 | 79 | { |
cc26b3b0 SMK |
80 | .virtual = L4_24XX_VIRT, |
81 | .pfn = __phys_to_pfn(L4_24XX_PHYS), | |
82 | .length = L4_24XX_SIZE, | |
83 | .type = MT_DEVICE | |
09f21ed4 | 84 | }, |
cc26b3b0 SMK |
85 | }; |
86 | ||
59b479e0 | 87 | #ifdef CONFIG_SOC_OMAP2420 |
cc26b3b0 SMK |
88 | static struct map_desc omap242x_io_desc[] __initdata = { |
89 | { | |
7adb9987 PW |
90 | .virtual = DSP_MEM_2420_VIRT, |
91 | .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), | |
92 | .length = DSP_MEM_2420_SIZE, | |
cc26b3b0 SMK |
93 | .type = MT_DEVICE |
94 | }, | |
95 | { | |
7adb9987 PW |
96 | .virtual = DSP_IPI_2420_VIRT, |
97 | .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), | |
98 | .length = DSP_IPI_2420_SIZE, | |
cc26b3b0 | 99 | .type = MT_DEVICE |
09f21ed4 | 100 | }, |
cc26b3b0 | 101 | { |
7adb9987 PW |
102 | .virtual = DSP_MMU_2420_VIRT, |
103 | .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), | |
104 | .length = DSP_MMU_2420_SIZE, | |
cc26b3b0 SMK |
105 | .type = MT_DEVICE |
106 | }, | |
107 | }; | |
108 | ||
109 | #endif | |
110 | ||
59b479e0 | 111 | #ifdef CONFIG_SOC_OMAP2430 |
cc26b3b0 | 112 | static struct map_desc omap243x_io_desc[] __initdata = { |
72d0f1c3 SMK |
113 | { |
114 | .virtual = L4_WK_243X_VIRT, | |
115 | .pfn = __phys_to_pfn(L4_WK_243X_PHYS), | |
116 | .length = L4_WK_243X_SIZE, | |
117 | .type = MT_DEVICE | |
118 | }, | |
119 | { | |
120 | .virtual = OMAP243X_GPMC_VIRT, | |
121 | .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), | |
122 | .length = OMAP243X_GPMC_SIZE, | |
123 | .type = MT_DEVICE | |
124 | }, | |
cc26b3b0 SMK |
125 | { |
126 | .virtual = OMAP243X_SDRC_VIRT, | |
127 | .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), | |
128 | .length = OMAP243X_SDRC_SIZE, | |
129 | .type = MT_DEVICE | |
130 | }, | |
131 | { | |
132 | .virtual = OMAP243X_SMS_VIRT, | |
133 | .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), | |
134 | .length = OMAP243X_SMS_SIZE, | |
135 | .type = MT_DEVICE | |
136 | }, | |
137 | }; | |
72d0f1c3 | 138 | #endif |
72d0f1c3 | 139 | #endif |
cc26b3b0 | 140 | |
a8eb7ca0 | 141 | #ifdef CONFIG_ARCH_OMAP3 |
cc26b3b0 | 142 | static struct map_desc omap34xx_io_desc[] __initdata = { |
1dbae815 | 143 | { |
cc26b3b0 SMK |
144 | .virtual = L3_34XX_VIRT, |
145 | .pfn = __phys_to_pfn(L3_34XX_PHYS), | |
146 | .length = L3_34XX_SIZE, | |
c40fae95 TL |
147 | .type = MT_DEVICE |
148 | }, | |
149 | { | |
cc26b3b0 SMK |
150 | .virtual = L4_34XX_VIRT, |
151 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
152 | .length = L4_34XX_SIZE, | |
c40fae95 TL |
153 | .type = MT_DEVICE |
154 | }, | |
cc26b3b0 SMK |
155 | { |
156 | .virtual = OMAP34XX_GPMC_VIRT, | |
157 | .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), | |
158 | .length = OMAP34XX_GPMC_SIZE, | |
1dbae815 | 159 | .type = MT_DEVICE |
cc26b3b0 SMK |
160 | }, |
161 | { | |
162 | .virtual = OMAP343X_SMS_VIRT, | |
163 | .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), | |
164 | .length = OMAP343X_SMS_SIZE, | |
165 | .type = MT_DEVICE | |
166 | }, | |
167 | { | |
168 | .virtual = OMAP343X_SDRC_VIRT, | |
169 | .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), | |
170 | .length = OMAP343X_SDRC_SIZE, | |
1dbae815 | 171 | .type = MT_DEVICE |
cc26b3b0 SMK |
172 | }, |
173 | { | |
174 | .virtual = L4_PER_34XX_VIRT, | |
175 | .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), | |
176 | .length = L4_PER_34XX_SIZE, | |
177 | .type = MT_DEVICE | |
178 | }, | |
179 | { | |
180 | .virtual = L4_EMU_34XX_VIRT, | |
181 | .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), | |
182 | .length = L4_EMU_34XX_SIZE, | |
183 | .type = MT_DEVICE | |
184 | }, | |
1dbae815 | 185 | }; |
cc26b3b0 | 186 | #endif |
01001712 | 187 | |
33959553 | 188 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 189 | static struct map_desc omapti81xx_io_desc[] __initdata = { |
1e6cb146 AM |
190 | { |
191 | .virtual = L4_34XX_VIRT, | |
192 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
193 | .length = L4_34XX_SIZE, | |
194 | .type = MT_DEVICE | |
195 | } | |
196 | }; | |
197 | #endif | |
198 | ||
addb154a | 199 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
1e6cb146 | 200 | static struct map_desc omapam33xx_io_desc[] __initdata = { |
01001712 HP |
201 | { |
202 | .virtual = L4_34XX_VIRT, | |
203 | .pfn = __phys_to_pfn(L4_34XX_PHYS), | |
204 | .length = L4_34XX_SIZE, | |
205 | .type = MT_DEVICE | |
206 | }, | |
1e6cb146 AM |
207 | { |
208 | .virtual = L4_WK_AM33XX_VIRT, | |
209 | .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), | |
210 | .length = L4_WK_AM33XX_SIZE, | |
211 | .type = MT_DEVICE | |
212 | } | |
01001712 HP |
213 | }; |
214 | #endif | |
215 | ||
44169075 SS |
216 | #ifdef CONFIG_ARCH_OMAP4 |
217 | static struct map_desc omap44xx_io_desc[] __initdata = { | |
218 | { | |
219 | .virtual = L3_44XX_VIRT, | |
220 | .pfn = __phys_to_pfn(L3_44XX_PHYS), | |
221 | .length = L3_44XX_SIZE, | |
222 | .type = MT_DEVICE, | |
223 | }, | |
224 | { | |
225 | .virtual = L4_44XX_VIRT, | |
226 | .pfn = __phys_to_pfn(L4_44XX_PHYS), | |
227 | .length = L4_44XX_SIZE, | |
228 | .type = MT_DEVICE, | |
229 | }, | |
44169075 SS |
230 | { |
231 | .virtual = L4_PER_44XX_VIRT, | |
232 | .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), | |
233 | .length = L4_PER_44XX_SIZE, | |
234 | .type = MT_DEVICE, | |
235 | }, | |
44169075 SS |
236 | }; |
237 | #endif | |
1dbae815 | 238 | |
a3a9384a | 239 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
05e152c7 S |
240 | static struct map_desc omap54xx_io_desc[] __initdata = { |
241 | { | |
242 | .virtual = L3_54XX_VIRT, | |
243 | .pfn = __phys_to_pfn(L3_54XX_PHYS), | |
244 | .length = L3_54XX_SIZE, | |
245 | .type = MT_DEVICE, | |
246 | }, | |
247 | { | |
248 | .virtual = L4_54XX_VIRT, | |
249 | .pfn = __phys_to_pfn(L4_54XX_PHYS), | |
250 | .length = L4_54XX_SIZE, | |
251 | .type = MT_DEVICE, | |
252 | }, | |
253 | { | |
254 | .virtual = L4_WK_54XX_VIRT, | |
255 | .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), | |
256 | .length = L4_WK_54XX_SIZE, | |
257 | .type = MT_DEVICE, | |
258 | }, | |
259 | { | |
260 | .virtual = L4_PER_54XX_VIRT, | |
261 | .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), | |
262 | .length = L4_PER_54XX_SIZE, | |
263 | .type = MT_DEVICE, | |
264 | }, | |
265 | }; | |
266 | #endif | |
267 | ||
59b479e0 | 268 | #ifdef CONFIG_SOC_OMAP2420 |
b6a4226c | 269 | void __init omap242x_map_io(void) |
1dbae815 | 270 | { |
cc26b3b0 SMK |
271 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
272 | iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); | |
6fbd55d0 | 273 | } |
cc26b3b0 SMK |
274 | #endif |
275 | ||
59b479e0 | 276 | #ifdef CONFIG_SOC_OMAP2430 |
b6a4226c | 277 | void __init omap243x_map_io(void) |
6fbd55d0 | 278 | { |
cc26b3b0 SMK |
279 | iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); |
280 | iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); | |
6fbd55d0 | 281 | } |
cc26b3b0 SMK |
282 | #endif |
283 | ||
a8eb7ca0 | 284 | #ifdef CONFIG_ARCH_OMAP3 |
b6a4226c | 285 | void __init omap3_map_io(void) |
6fbd55d0 | 286 | { |
cc26b3b0 | 287 | iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); |
6fbd55d0 | 288 | } |
cc26b3b0 | 289 | #endif |
120db2cb | 290 | |
33959553 | 291 | #ifdef CONFIG_SOC_TI81XX |
b6a4226c | 292 | void __init ti81xx_map_io(void) |
01001712 | 293 | { |
a920360f | 294 | iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); |
01001712 HP |
295 | } |
296 | #endif | |
297 | ||
addb154a | 298 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) |
b6a4226c | 299 | void __init am33xx_map_io(void) |
01001712 | 300 | { |
1e6cb146 | 301 | iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); |
01001712 HP |
302 | } |
303 | #endif | |
304 | ||
6fbd55d0 | 305 | #ifdef CONFIG_ARCH_OMAP4 |
b6a4226c | 306 | void __init omap4_map_io(void) |
6fbd55d0 | 307 | { |
44169075 | 308 | iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); |
2ec1fc4e | 309 | omap_barriers_init(); |
120db2cb | 310 | } |
6fbd55d0 | 311 | #endif |
120db2cb | 312 | |
a3a9384a | 313 | #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) |
b6a4226c | 314 | void __init omap5_map_io(void) |
05e152c7 S |
315 | { |
316 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | |
1348bbf9 | 317 | omap_barriers_init(); |
05e152c7 S |
318 | } |
319 | #endif | |
2f135eaf PW |
320 | /* |
321 | * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters | |
322 | * | |
323 | * Sets the CORE DPLL3 M2 divider to the same value that it's at | |
324 | * currently. This has the effect of setting the SDRC SDRAM AC timing | |
325 | * registers to the values currently defined by the kernel. Currently | |
326 | * only defined for OMAP3; will return 0 if called on OMAP2. Returns | |
327 | * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, | |
328 | * or passes along the return value of clk_set_rate(). | |
329 | */ | |
330 | static int __init _omap2_init_reprogram_sdrc(void) | |
331 | { | |
332 | struct clk *dpll3_m2_ck; | |
333 | int v = -EINVAL; | |
334 | long rate; | |
335 | ||
336 | if (!cpu_is_omap34xx()) | |
337 | return 0; | |
338 | ||
339 | dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); | |
e281f7ec | 340 | if (IS_ERR(dpll3_m2_ck)) |
2f135eaf PW |
341 | return -EINVAL; |
342 | ||
343 | rate = clk_get_rate(dpll3_m2_ck); | |
344 | pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); | |
345 | v = clk_set_rate(dpll3_m2_ck, rate); | |
346 | if (v) | |
347 | pr_err("dpll3_m2_clk rate change failed: %d\n", v); | |
348 | ||
349 | clk_put(dpll3_m2_ck); | |
350 | ||
351 | return v; | |
352 | } | |
353 | ||
2092e5cc PW |
354 | static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) |
355 | { | |
356 | return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); | |
357 | } | |
358 | ||
7b250aff TL |
359 | static void __init omap_hwmod_init_postsetup(void) |
360 | { | |
361 | u8 postsetup_state; | |
2092e5cc PW |
362 | |
363 | /* Set the default postsetup state for all hwmods */ | |
bf7c5449 | 364 | #ifdef CONFIG_PM |
2092e5cc PW |
365 | postsetup_state = _HWMOD_STATE_IDLE; |
366 | #else | |
367 | postsetup_state = _HWMOD_STATE_ENABLED; | |
368 | #endif | |
369 | omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); | |
55d2cb08 | 370 | |
53da4ce2 | 371 | omap_pm_if_early_init(); |
4805734b PW |
372 | } |
373 | ||
069d0a78 | 374 | static void __init __maybe_unused omap_common_late_init(void) |
4ed12be0 RB |
375 | { |
376 | omap_mux_late_init(); | |
377 | omap2_common_pm_late_init(); | |
6770b211 | 378 | omap_soc_device_init(); |
4ed12be0 RB |
379 | } |
380 | ||
16110798 | 381 | #ifdef CONFIG_SOC_OMAP2420 |
8f5b5a41 TL |
382 | void __init omap2420_init_early(void) |
383 | { | |
b6a4226c PW |
384 | omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); |
385 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
386 | OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); | |
387 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), | |
388 | NULL); | |
d9a16f9a PW |
389 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); |
390 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); | |
4de34f35 | 391 | omap2xxx_check_revision(); |
63a293e0 | 392 | omap2xxx_prm_init(); |
c4ceedcb | 393 | omap2xxx_cm_init(); |
7b250aff TL |
394 | omap2xxx_voltagedomains_init(); |
395 | omap242x_powerdomains_init(); | |
396 | omap242x_clockdomains_init(); | |
397 | omap2420_hwmod_init(); | |
398 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
399 | omap_clk_soc_init = omap2420_dt_clk_init; |
400 | rate_table = omap2420_rate_table; | |
8f5b5a41 | 401 | } |
bbd707ac SG |
402 | |
403 | void __init omap2420_init_late(void) | |
404 | { | |
4ed12be0 | 405 | omap_common_late_init(); |
bbd707ac | 406 | omap2_pm_init(); |
23fb8ba3 | 407 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 408 | } |
16110798 | 409 | #endif |
8f5b5a41 | 410 | |
16110798 | 411 | #ifdef CONFIG_SOC_OMAP2430 |
8f5b5a41 TL |
412 | void __init omap2430_init_early(void) |
413 | { | |
b6a4226c PW |
414 | omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); |
415 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
416 | OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); | |
417 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | |
418 | NULL); | |
d9a16f9a PW |
419 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); |
420 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); | |
4de34f35 | 421 | omap2xxx_check_revision(); |
63a293e0 | 422 | omap2xxx_prm_init(); |
c4ceedcb | 423 | omap2xxx_cm_init(); |
7b250aff TL |
424 | omap2xxx_voltagedomains_init(); |
425 | omap243x_powerdomains_init(); | |
426 | omap243x_clockdomains_init(); | |
427 | omap2430_hwmod_init(); | |
428 | omap_hwmod_init_postsetup(); | |
6a194a6e TK |
429 | omap_clk_soc_init = omap2430_dt_clk_init; |
430 | rate_table = omap2430_rate_table; | |
7b250aff | 431 | } |
bbd707ac SG |
432 | |
433 | void __init omap2430_init_late(void) | |
434 | { | |
4ed12be0 | 435 | omap_common_late_init(); |
bbd707ac | 436 | omap2_pm_init(); |
23fb8ba3 | 437 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 438 | } |
c4e2d245 | 439 | #endif |
7b250aff TL |
440 | |
441 | /* | |
442 | * Currently only board-omap3beagle.c should call this because of the | |
443 | * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. | |
444 | */ | |
c4e2d245 | 445 | #ifdef CONFIG_ARCH_OMAP3 |
7b250aff TL |
446 | void __init omap3_init_early(void) |
447 | { | |
b6a4226c PW |
448 | omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); |
449 | omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
450 | OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); | |
451 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | |
452 | NULL); | |
d9a16f9a PW |
453 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); |
454 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); | |
4de34f35 VH |
455 | omap3xxx_check_revision(); |
456 | omap3xxx_check_features(); | |
63a293e0 | 457 | omap3xxx_prm_init(); |
c4ceedcb | 458 | omap3xxx_cm_init(); |
7b250aff TL |
459 | omap3xxx_voltagedomains_init(); |
460 | omap3xxx_powerdomains_init(); | |
461 | omap3xxx_clockdomains_init(); | |
462 | omap3xxx_hwmod_init(); | |
463 | omap_hwmod_init_postsetup(); | |
cfa9667d | 464 | omap_clk_soc_init = omap3xxx_clk_init; |
8f5b5a41 TL |
465 | } |
466 | ||
467 | void __init omap3430_init_early(void) | |
468 | { | |
7b250aff | 469 | omap3_init_early(); |
3e049157 TK |
470 | if (of_have_populated_dt()) |
471 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
472 | } |
473 | ||
474 | void __init omap35xx_init_early(void) | |
475 | { | |
7b250aff | 476 | omap3_init_early(); |
3e049157 TK |
477 | if (of_have_populated_dt()) |
478 | omap_clk_soc_init = omap3430_dt_clk_init; | |
8f5b5a41 TL |
479 | } |
480 | ||
481 | void __init omap3630_init_early(void) | |
482 | { | |
7b250aff | 483 | omap3_init_early(); |
3e049157 TK |
484 | if (of_have_populated_dt()) |
485 | omap_clk_soc_init = omap3630_dt_clk_init; | |
8f5b5a41 TL |
486 | } |
487 | ||
488 | void __init am35xx_init_early(void) | |
489 | { | |
7b250aff | 490 | omap3_init_early(); |
3e049157 TK |
491 | if (of_have_populated_dt()) |
492 | omap_clk_soc_init = am35xx_dt_clk_init; | |
8f5b5a41 TL |
493 | } |
494 | ||
c27964b5 | 495 | void __init ti814x_init_early(void) |
8f5b5a41 | 496 | { |
c27964b5 TL |
497 | omap2_set_globals_tap(TI814X_CLASS, |
498 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); | |
499 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), | |
500 | NULL); | |
501 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); | |
502 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); | |
503 | omap3xxx_check_revision(); | |
504 | ti81xx_check_features(); | |
505 | omap3xxx_voltagedomains_init(); | |
506 | omap3xxx_powerdomains_init(); | |
507 | omap3xxx_clockdomains_init(); | |
508 | omap3xxx_hwmod_init(); | |
509 | omap_hwmod_init_postsetup(); | |
510 | if (of_have_populated_dt()) | |
511 | omap_clk_soc_init = ti81xx_dt_clk_init; | |
512 | } | |
513 | ||
514 | void __init ti816x_init_early(void) | |
515 | { | |
516 | omap2_set_globals_tap(TI816X_CLASS, | |
b6a4226c PW |
517 | OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); |
518 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), | |
519 | NULL); | |
d9a16f9a PW |
520 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); |
521 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); | |
4de34f35 VH |
522 | omap3xxx_check_revision(); |
523 | ti81xx_check_features(); | |
4c3cf901 TL |
524 | omap3xxx_voltagedomains_init(); |
525 | omap3xxx_powerdomains_init(); | |
526 | omap3xxx_clockdomains_init(); | |
527 | omap3xxx_hwmod_init(); | |
528 | omap_hwmod_init_postsetup(); | |
3e049157 TK |
529 | if (of_have_populated_dt()) |
530 | omap_clk_soc_init = ti81xx_dt_clk_init; | |
8f5b5a41 | 531 | } |
bbd707ac SG |
532 | |
533 | void __init omap3_init_late(void) | |
534 | { | |
4ed12be0 | 535 | omap_common_late_init(); |
bbd707ac | 536 | omap3_pm_init(); |
23fb8ba3 | 537 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
538 | } |
539 | ||
540 | void __init omap3430_init_late(void) | |
541 | { | |
4ed12be0 | 542 | omap_common_late_init(); |
bbd707ac | 543 | omap3_pm_init(); |
23fb8ba3 | 544 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
545 | } |
546 | ||
547 | void __init omap35xx_init_late(void) | |
548 | { | |
4ed12be0 | 549 | omap_common_late_init(); |
bbd707ac | 550 | omap3_pm_init(); |
23fb8ba3 | 551 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
552 | } |
553 | ||
554 | void __init omap3630_init_late(void) | |
555 | { | |
4ed12be0 | 556 | omap_common_late_init(); |
bbd707ac | 557 | omap3_pm_init(); |
23fb8ba3 | 558 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
559 | } |
560 | ||
561 | void __init am35xx_init_late(void) | |
562 | { | |
4ed12be0 | 563 | omap_common_late_init(); |
bbd707ac | 564 | omap3_pm_init(); |
23fb8ba3 | 565 | omap2_clk_enable_autoidle_all(); |
bbd707ac SG |
566 | } |
567 | ||
568 | void __init ti81xx_init_late(void) | |
569 | { | |
4ed12be0 | 570 | omap_common_late_init(); |
23fb8ba3 | 571 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 572 | } |
c4e2d245 | 573 | #endif |
8f5b5a41 | 574 | |
08f30989 AM |
575 | #ifdef CONFIG_SOC_AM33XX |
576 | void __init am33xx_init_early(void) | |
577 | { | |
b6a4226c PW |
578 | omap2_set_globals_tap(AM335X_CLASS, |
579 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
580 | omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), | |
581 | NULL); | |
d9a16f9a PW |
582 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); |
583 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); | |
08f30989 | 584 | omap3xxx_check_revision(); |
7bcad170 | 585 | am33xx_check_features(); |
d9bbe84f | 586 | am33xx_prm_init(); |
7632a02f | 587 | am33xx_cm_init(); |
3f0ea764 | 588 | am33xx_powerdomains_init(); |
9c80f3aa | 589 | am33xx_clockdomains_init(); |
a2cfc509 VH |
590 | am33xx_hwmod_init(); |
591 | omap_hwmod_init_postsetup(); | |
149c09d3 | 592 | omap_clk_soc_init = am33xx_dt_clk_init; |
08f30989 | 593 | } |
765e7a06 NM |
594 | |
595 | void __init am33xx_init_late(void) | |
596 | { | |
597 | omap_common_late_init(); | |
598 | } | |
08f30989 AM |
599 | #endif |
600 | ||
c5107027 AM |
601 | #ifdef CONFIG_SOC_AM43XX |
602 | void __init am43xx_init_early(void) | |
603 | { | |
604 | omap2_set_globals_tap(AM335X_CLASS, | |
605 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); | |
606 | omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), | |
607 | NULL); | |
608 | omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); | |
609 | omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); | |
8835cf6e A |
610 | omap_prm_base_init(); |
611 | omap_cm_base_init(); | |
c5107027 | 612 | omap3xxx_check_revision(); |
7a2e0513 | 613 | am33xx_check_features(); |
8843b119 | 614 | omap44xx_prm_init(); |
7632a02f | 615 | omap4_cm_init(); |
8835cf6e A |
616 | am43xx_powerdomains_init(); |
617 | am43xx_clockdomains_init(); | |
618 | am43xx_hwmod_init(); | |
619 | omap_hwmod_init_postsetup(); | |
d941f86f | 620 | omap_l2_cache_init(); |
d22031e2 | 621 | omap_clk_soc_init = am43xx_dt_clk_init; |
c5107027 | 622 | } |
765e7a06 NM |
623 | |
624 | void __init am43xx_init_late(void) | |
625 | { | |
626 | omap_common_late_init(); | |
627 | } | |
c5107027 AM |
628 | #endif |
629 | ||
c4e2d245 | 630 | #ifdef CONFIG_ARCH_OMAP4 |
8f5b5a41 TL |
631 | void __init omap4430_init_early(void) |
632 | { | |
b6a4226c PW |
633 | omap2_set_globals_tap(OMAP443X_CLASS, |
634 | OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); | |
635 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), | |
636 | OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); | |
d9a16f9a PW |
637 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); |
638 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | |
639 | OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); | |
640 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); | |
641 | omap_prm_base_init(); | |
642 | omap_cm_base_init(); | |
4de34f35 VH |
643 | omap4xxx_check_revision(); |
644 | omap4xxx_check_features(); | |
7632a02f | 645 | omap4_cm_init(); |
de70af49 | 646 | omap4_pm_init_early(); |
63a293e0 | 647 | omap44xx_prm_init(); |
7b250aff TL |
648 | omap44xx_voltagedomains_init(); |
649 | omap44xx_powerdomains_init(); | |
650 | omap44xx_clockdomains_init(); | |
651 | omap44xx_hwmod_init(); | |
652 | omap_hwmod_init_postsetup(); | |
b39b14e6 | 653 | omap_l2_cache_init(); |
c8c88d85 | 654 | omap_clk_soc_init = omap4xxx_dt_clk_init; |
8f5b5a41 | 655 | } |
bbd707ac SG |
656 | |
657 | void __init omap4430_init_late(void) | |
658 | { | |
4ed12be0 | 659 | omap_common_late_init(); |
bbd707ac | 660 | omap4_pm_init(); |
23fb8ba3 | 661 | omap2_clk_enable_autoidle_all(); |
bbd707ac | 662 | } |
c4e2d245 | 663 | #endif |
8f5b5a41 | 664 | |
05e152c7 S |
665 | #ifdef CONFIG_SOC_OMAP5 |
666 | void __init omap5_init_early(void) | |
667 | { | |
b6a4226c PW |
668 | omap2_set_globals_tap(OMAP54XX_CLASS, |
669 | OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); | |
670 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | |
671 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); | |
d9a16f9a PW |
672 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); |
673 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), | |
674 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | |
675 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | |
628ed471 | 676 | omap4_pm_init_early(); |
d9a16f9a PW |
677 | omap_prm_base_init(); |
678 | omap_cm_base_init(); | |
e4020aa9 | 679 | omap44xx_prm_init(); |
05e152c7 | 680 | omap5xxx_check_revision(); |
7632a02f | 681 | omap4_cm_init(); |
e4020aa9 SS |
682 | omap54xx_voltagedomains_init(); |
683 | omap54xx_powerdomains_init(); | |
684 | omap54xx_clockdomains_init(); | |
685 | omap54xx_hwmod_init(); | |
686 | omap_hwmod_init_postsetup(); | |
cfa9667d | 687 | omap_clk_soc_init = omap5xxx_dt_clk_init; |
05e152c7 | 688 | } |
765e7a06 NM |
689 | |
690 | void __init omap5_init_late(void) | |
691 | { | |
692 | omap_common_late_init(); | |
628ed471 SS |
693 | omap4_pm_init(); |
694 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 695 | } |
05e152c7 S |
696 | #endif |
697 | ||
a3a9384a S |
698 | #ifdef CONFIG_SOC_DRA7XX |
699 | void __init dra7xx_init_early(void) | |
700 | { | |
701 | omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); | |
702 | omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), | |
703 | OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); | |
704 | omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); | |
705 | omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), | |
706 | OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); | |
707 | omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); | |
6af16a1d | 708 | omap4_pm_init_early(); |
a3a9384a S |
709 | omap_prm_base_init(); |
710 | omap_cm_base_init(); | |
7de516a6 | 711 | omap44xx_prm_init(); |
733d20ee | 712 | dra7xxx_check_revision(); |
7632a02f | 713 | omap4_cm_init(); |
7de516a6 A |
714 | dra7xx_powerdomains_init(); |
715 | dra7xx_clockdomains_init(); | |
716 | dra7xx_hwmod_init(); | |
717 | omap_hwmod_init_postsetup(); | |
f1cf498e | 718 | omap_clk_soc_init = dra7xx_dt_clk_init; |
a3a9384a | 719 | } |
765e7a06 NM |
720 | |
721 | void __init dra7xx_init_late(void) | |
722 | { | |
723 | omap_common_late_init(); | |
6af16a1d RN |
724 | omap4_pm_init(); |
725 | omap2_clk_enable_autoidle_all(); | |
765e7a06 | 726 | } |
a3a9384a S |
727 | #endif |
728 | ||
729 | ||
a4ca9dbe | 730 | void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
4805734b PW |
731 | struct omap_sdrc_params *sdrc_cs1) |
732 | { | |
a66cb345 TL |
733 | omap_sram_init(); |
734 | ||
01001712 | 735 | if (cpu_is_omap24xx() || omap3_has_sdrc()) { |
aa4b1f6e KH |
736 | omap2_sdrc_init(sdrc_cs0, sdrc_cs1); |
737 | _omap2_init_reprogram_sdrc(); | |
738 | } | |
1dbae815 | 739 | } |
cfa9667d TK |
740 | |
741 | int __init omap_clk_init(void) | |
742 | { | |
743 | int ret = 0; | |
744 | ||
745 | if (!omap_clk_soc_init) | |
746 | return 0; | |
747 | ||
8111e010 TK |
748 | ti_clk_init_features(); |
749 | ||
cfa9667d | 750 | ret = of_prcm_init(); |
c08ee14c TK |
751 | if (ret) |
752 | return ret; | |
753 | ||
754 | of_clk_init(NULL); | |
755 | ||
756 | ti_dt_clk_init_retry_clks(); | |
757 | ||
758 | ti_dt_clockdomains_setup(); | |
759 | ||
760 | ret = omap_clk_soc_init(); | |
cfa9667d TK |
761 | |
762 | return ret; | |
763 | } |