]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - arch/arm/mach-omap2/io.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / io.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1dbae815
TL		 2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
44169075 8 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
1dbae815 13 *
44169075 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 15 */
1dbae815
TL		 16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
fced80c7 19#include <linux/io.h>
2f135eaf 20#include <linux/clk.h>
1dbae815 21
120db2cb 22#include <asm/tlb.h>
120db2cb
TL		 23#include <asm/mach/map.h>
24
45c3eb7d 25#include <linux/omap-dma.h>
ee0839c2 26
dc843280 27#include "omap_hwmod.h"
dbc04161 28#include "soc.h"
ee0839c2 29#include "iomap.h"
81a60482 30#include "voltage.h"
72e06d08 31#include "powerdomain.h"
1540f214 32#include "clockdomain.h"
4e65331c 33#include "common.h"
e30384ab 34#include "clock.h"
ee0839c2
TL		 35#include "clock2xxx.h"
36#include "clock3xxx.h"
3e6ece13 37#include "sdrc.h"
b6a4226c 38#include "control.h"
3d82cbbb 39#include "serial.h"
bf027ca1 40#include "sram.h"
c4ceedcb
PW		 41#include "cm2xxx.h"
42#include "cm3xxx.h"
7632a02f 43#include "cm33xx.h"
ab6c9bbf 44#include "cm44xx.h"
d9a16f9a
PW		 45#include "prm.h"
46#include "cm.h"
47#include "prcm_mpu44xx.h"
48#include "prminst44xx.h"
63a293e0
PW		 49#include "prm2xxx.h"
50#include "prm3xxx.h"
d9bbe84f 51#include "prm33xx.h"
63a293e0 52#include "prm44xx.h"
69a1e7a1 53#include "opp2xxx.h"
02bfc030 54
ff931c82 55/*
cfa9667d 56 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 57 * clock initializations
58 */
cfa9667d 59static int (*omap_clk_soc_init)(void);
ff931c82 60
1dbae815
TL		 61/*
62 * The machine specific code may provide the extra mapping besides the
63 * default mapping provided here.
64 */
cc26b3b0 65
e48f814e 66#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 67static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 68 {
69 .virtual = L3_24XX_VIRT,
70 .pfn = __phys_to_pfn(L3_24XX_PHYS),
71 .length = L3_24XX_SIZE,
72 .type = MT_DEVICE
73 },
09f21ed4 74 {
cc26b3b0
SMK		 75 .virtual = L4_24XX_VIRT,
76 .pfn = __phys_to_pfn(L4_24XX_PHYS),
77 .length = L4_24XX_SIZE,
78 .type = MT_DEVICE
09f21ed4 79 },
cc26b3b0
SMK		 80};
81
59b479e0 82#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 83static struct map_desc omap242x_io_desc[] __initdata = {
84 {
7adb9987
PW		 85 .virtual = DSP_MEM_2420_VIRT,
86 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
87 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 88 .type = MT_DEVICE
89 },
90 {
7adb9987
PW		 91 .virtual = DSP_IPI_2420_VIRT,
92 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
93 .length = DSP_IPI_2420_SIZE,
cc26b3b0 94 .type = MT_DEVICE
09f21ed4 95 },
cc26b3b0 96 {
7adb9987
PW		 97 .virtual = DSP_MMU_2420_VIRT,
98 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
99 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 100 .type = MT_DEVICE
101 },
102};
103
104#endif
105
59b479e0 106#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 107static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 108 {
109 .virtual = L4_WK_243X_VIRT,
110 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
111 .length = L4_WK_243X_SIZE,
112 .type = MT_DEVICE
113 },
114 {
115 .virtual = OMAP243X_GPMC_VIRT,
116 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
117 .length = OMAP243X_GPMC_SIZE,
118 .type = MT_DEVICE
119 },
cc26b3b0
SMK		 120 {
121 .virtual = OMAP243X_SDRC_VIRT,
122 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
123 .length = OMAP243X_SDRC_SIZE,
124 .type = MT_DEVICE
125 },
126 {
127 .virtual = OMAP243X_SMS_VIRT,
128 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
129 .length = OMAP243X_SMS_SIZE,
130 .type = MT_DEVICE
131 },
132};
72d0f1c3 133#endif
72d0f1c3 134#endif
cc26b3b0 135
a8eb7ca0 136#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 137static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 138 {
cc26b3b0
SMK		 139 .virtual = L3_34XX_VIRT,
140 .pfn = __phys_to_pfn(L3_34XX_PHYS),
141 .length = L3_34XX_SIZE,
c40fae95
TL		 142 .type = MT_DEVICE
143 },
144 {
cc26b3b0
SMK		 145 .virtual = L4_34XX_VIRT,
146 .pfn = __phys_to_pfn(L4_34XX_PHYS),
147 .length = L4_34XX_SIZE,
c40fae95
TL		 148 .type = MT_DEVICE
149 },
cc26b3b0
SMK		 150 {
151 .virtual = OMAP34XX_GPMC_VIRT,
152 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
153 .length = OMAP34XX_GPMC_SIZE,
1dbae815 154 .type = MT_DEVICE
cc26b3b0
SMK		 155 },
156 {
157 .virtual = OMAP343X_SMS_VIRT,
158 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
159 .length = OMAP343X_SMS_SIZE,
160 .type = MT_DEVICE
161 },
162 {
163 .virtual = OMAP343X_SDRC_VIRT,
164 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
165 .length = OMAP343X_SDRC_SIZE,
1dbae815 166 .type = MT_DEVICE
cc26b3b0
SMK		 167 },
168 {
169 .virtual = L4_PER_34XX_VIRT,
170 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
171 .length = L4_PER_34XX_SIZE,
172 .type = MT_DEVICE
173 },
174 {
175 .virtual = L4_EMU_34XX_VIRT,
176 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
177 .length = L4_EMU_34XX_SIZE,
178 .type = MT_DEVICE
179 },
1dbae815 180};
cc26b3b0 181#endif
01001712 182
33959553 183#ifdef CONFIG_SOC_TI81XX
a920360f 184static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 185 {
186 .virtual = L4_34XX_VIRT,
187 .pfn = __phys_to_pfn(L4_34XX_PHYS),
188 .length = L4_34XX_SIZE,
189 .type = MT_DEVICE
190 }
191};
192#endif
193
addb154a 194#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 195static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 196 {
197 .virtual = L4_34XX_VIRT,
198 .pfn = __phys_to_pfn(L4_34XX_PHYS),
199 .length = L4_34XX_SIZE,
200 .type = MT_DEVICE
201 },
1e6cb146
AM		 202 {
203 .virtual = L4_WK_AM33XX_VIRT,
204 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
205 .length = L4_WK_AM33XX_SIZE,
206 .type = MT_DEVICE
207 }
01001712
HP		 208};
209#endif
210
44169075
SS		 211#ifdef CONFIG_ARCH_OMAP4
212static struct map_desc omap44xx_io_desc[] __initdata = {
213 {
214 .virtual = L3_44XX_VIRT,
215 .pfn = __phys_to_pfn(L3_44XX_PHYS),
216 .length = L3_44XX_SIZE,
217 .type = MT_DEVICE,
218 },
219 {
220 .virtual = L4_44XX_VIRT,
221 .pfn = __phys_to_pfn(L4_44XX_PHYS),
222 .length = L4_44XX_SIZE,
223 .type = MT_DEVICE,
224 },
44169075
SS		 225 {
226 .virtual = L4_PER_44XX_VIRT,
227 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
228 .length = L4_PER_44XX_SIZE,
229 .type = MT_DEVICE,
230 },
44169075
SS		 231};
232#endif
1dbae815 233
ea827ad5 234#ifdef CONFIG_SOC_OMAP5
05e152c7
S		 235static struct map_desc omap54xx_io_desc[] __initdata = {
236 {
237 .virtual = L3_54XX_VIRT,
238 .pfn = __phys_to_pfn(L3_54XX_PHYS),
239 .length = L3_54XX_SIZE,
240 .type = MT_DEVICE,
241 },
242 {
243 .virtual = L4_54XX_VIRT,
244 .pfn = __phys_to_pfn(L4_54XX_PHYS),
245 .length = L4_54XX_SIZE,
246 .type = MT_DEVICE,
247 },
248 {
249 .virtual = L4_WK_54XX_VIRT,
250 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
251 .length = L4_WK_54XX_SIZE,
252 .type = MT_DEVICE,
253 },
254 {
255 .virtual = L4_PER_54XX_VIRT,
256 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
257 .length = L4_PER_54XX_SIZE,
258 .type = MT_DEVICE,
259 },
260};
261#endif
262
ea827ad5
NM		 263#ifdef CONFIG_SOC_DRA7XX
264static struct map_desc dra7xx_io_desc[] __initdata = {
265 {
266 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
267 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
268 .length = L4_CFG_MPU_DRA7XX_SIZE,
269 .type = MT_DEVICE,
270 },
271 {
272 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
273 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
274 .length = L3_MAIN_SN_DRA7XX_SIZE,
275 .type = MT_DEVICE,
276 },
277 {
278 .virtual = L4_PER1_DRA7XX_VIRT,
279 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
280 .length = L4_PER1_DRA7XX_SIZE,
281 .type = MT_DEVICE,
282 },
283 {
284 .virtual = L4_PER2_DRA7XX_VIRT,
285 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
286 .length = L4_PER2_DRA7XX_SIZE,
287 .type = MT_DEVICE,
288 },
289 {
290 .virtual = L4_PER3_DRA7XX_VIRT,
291 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
292 .length = L4_PER3_DRA7XX_SIZE,
293 .type = MT_DEVICE,
294 },
295 {
296 .virtual = L4_CFG_DRA7XX_VIRT,
297 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
298 .length = L4_CFG_DRA7XX_SIZE,
299 .type = MT_DEVICE,
300 },
301 {
302 .virtual = L4_WKUP_DRA7XX_VIRT,
303 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
304 .length = L4_WKUP_DRA7XX_SIZE,
305 .type = MT_DEVICE,
306 },
307};
308#endif
309
59b479e0 310#ifdef CONFIG_SOC_OMAP2420
b6a4226c 311void __init omap242x_map_io(void)
1dbae815 312{
cc26b3b0
SMK		 313 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
314 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 315}
cc26b3b0
SMK		 316#endif
317
59b479e0 318#ifdef CONFIG_SOC_OMAP2430
b6a4226c 319void __init omap243x_map_io(void)
6fbd55d0 320{
cc26b3b0
SMK		 321 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
322 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 323}
cc26b3b0
SMK		 324#endif
325
a8eb7ca0 326#ifdef CONFIG_ARCH_OMAP3
b6a4226c 327void __init omap3_map_io(void)
6fbd55d0 328{
cc26b3b0 329 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 330}
cc26b3b0 331#endif
120db2cb 332
33959553 333#ifdef CONFIG_SOC_TI81XX
b6a4226c 334void __init ti81xx_map_io(void)
01001712 335{
a920360f 336 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 337}
338#endif
339
addb154a 340#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 341void __init am33xx_map_io(void)
01001712 342{
1e6cb146 343 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 344}
345#endif
346
6fbd55d0 347#ifdef CONFIG_ARCH_OMAP4
b6a4226c 348void __init omap4_map_io(void)
6fbd55d0 349{
44169075 350 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
f746929f 351 omap_barriers_init();
120db2cb 352}
6fbd55d0 353#endif
120db2cb 354
ea827ad5 355#ifdef CONFIG_SOC_OMAP5
b6a4226c 356void __init omap5_map_io(void)
05e152c7
S		 357{
358 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
f746929f 359 omap_barriers_init();
05e152c7
S		 360}
361#endif
ea827ad5
NM		 362
363#ifdef CONFIG_SOC_DRA7XX
364void __init dra7xx_map_io(void)
365{
366 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
456e8d53 367 omap_barriers_init();
ea827ad5
NM		 368}
369#endif
2f135eaf
PW		 370/*
371 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
372 *
373 * Sets the CORE DPLL3 M2 divider to the same value that it's at
374 * currently. This has the effect of setting the SDRC SDRAM AC timing
375 * registers to the values currently defined by the kernel. Currently
376 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
377 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
378 * or passes along the return value of clk_set_rate().
379 */
380static int __init _omap2_init_reprogram_sdrc(void)
381{
382 struct clk *dpll3_m2_ck;
383 int v = -EINVAL;
384 long rate;
385
386 if (!cpu_is_omap34xx())
387 return 0;
388
389 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 390 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 391 return -EINVAL;
392
393 rate = clk_get_rate(dpll3_m2_ck);
394 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
395 v = clk_set_rate(dpll3_m2_ck, rate);
396 if (v)
397 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
398
399 clk_put(dpll3_m2_ck);
400
401 return v;
402}
403
2092e5cc
PW		 404static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
405{
406 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
407}
408
293ea3d0 409static void __init __maybe_unused omap_hwmod_init_postsetup(void)
7b250aff 410{
6d63b12d 411 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
2092e5cc
PW		 412
413 /* Set the default postsetup state for all hwmods */
2092e5cc 414 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
4805734b
PW		 415}
416
16110798 417#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 418void __init omap2420_init_early(void)
419{
b6a4226c
PW		 420 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
421 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
422 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
2208bf11 423 omap2_control_base_init();
4de34f35 424 omap2xxx_check_revision();
ab7b2ffc 425 omap2_prcm_base_init();
7b250aff
TL		 426 omap2xxx_voltagedomains_init();
427 omap242x_powerdomains_init();
428 omap242x_clockdomains_init();
429 omap2420_hwmod_init();
430 omap_hwmod_init_postsetup();
6a194a6e
TK		 431 omap_clk_soc_init = omap2420_dt_clk_init;
432 rate_table = omap2420_rate_table;
8f5b5a41 433}
bbd707ac
SG		 434
435void __init omap2420_init_late(void)
436{
02b83dcb 437 omap_pm_soc_init = omap2_pm_init;
bbd707ac 438}
16110798 439#endif
8f5b5a41 440
16110798 441#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 442void __init omap2430_init_early(void)
443{
b6a4226c
PW		 444 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
445 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
446 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
2208bf11 447 omap2_control_base_init();
4de34f35 448 omap2xxx_check_revision();
ab7b2ffc 449 omap2_prcm_base_init();
7b250aff
TL		 450 omap2xxx_voltagedomains_init();
451 omap243x_powerdomains_init();
452 omap243x_clockdomains_init();
453 omap2430_hwmod_init();
454 omap_hwmod_init_postsetup();
6a194a6e
TK		 455 omap_clk_soc_init = omap2430_dt_clk_init;
456 rate_table = omap2430_rate_table;
7b250aff 457}
bbd707ac
SG		 458
459void __init omap2430_init_late(void)
460{
02b83dcb 461 omap_pm_soc_init = omap2_pm_init;
bbd707ac 462}
c4e2d245 463#endif
7b250aff
TL		 464
465/*
466 * Currently only board-omap3beagle.c should call this because of the
467 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
468 */
c4e2d245 469#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 470void __init omap3_init_early(void)
471{
b6a4226c
PW		 472 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
473 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
474 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
2208bf11 475 omap2_control_base_init();
4de34f35
VH		 476 omap3xxx_check_revision();
477 omap3xxx_check_features();
ab7b2ffc 478 omap2_prcm_base_init();
7b250aff
TL		 479 omap3xxx_voltagedomains_init();
480 omap3xxx_powerdomains_init();
481 omap3xxx_clockdomains_init();
482 omap3xxx_hwmod_init();
483 omap_hwmod_init_postsetup();
8f5b5a41
TL		 484}
485
486void __init omap3430_init_early(void)
487{
7b250aff 488 omap3_init_early();
58a641c8 489 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 490}
491
492void __init omap35xx_init_early(void)
493{
7b250aff 494 omap3_init_early();
58a641c8 495 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 496}
497
498void __init omap3630_init_early(void)
499{
7b250aff 500 omap3_init_early();
58a641c8 501 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 502}
503
504void __init am35xx_init_early(void)
505{
7b250aff 506 omap3_init_early();
58a641c8 507 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 508}
509
bbd707ac
SG		 510void __init omap3_init_late(void)
511{
02b83dcb 512 omap_pm_soc_init = omap3_pm_init;
bbd707ac
SG		 513}
514
515void __init ti81xx_init_late(void)
516{
02b83dcb 517 omap_pm_soc_init = omap_pm_nop_init;
bbd707ac 518}
c4e2d245 519#endif
8f5b5a41 520
a64459c4
AM		 521#ifdef CONFIG_SOC_TI81XX
522void __init ti814x_init_early(void)
523{
524 omap2_set_globals_tap(TI814X_CLASS,
525 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 526 omap2_control_base_init();
a64459c4
AM		 527 omap3xxx_check_revision();
528 ti81xx_check_features();
ab7b2ffc 529 omap2_prcm_base_init();
a64459c4
AM		 530 omap3xxx_voltagedomains_init();
531 omap3xxx_powerdomains_init();
185fde6d 532 ti814x_clockdomains_init();
0f3ccb24 533 dm814x_hwmod_init();
a64459c4 534 omap_hwmod_init_postsetup();
d893656e 535 omap_clk_soc_init = dm814x_dt_clk_init;
a64459c4
AM		 536}
537
538void __init ti816x_init_early(void)
539{
540 omap2_set_globals_tap(TI816X_CLASS,
541 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 542 omap2_control_base_init();
a64459c4
AM		 543 omap3xxx_check_revision();
544 ti81xx_check_features();
ab7b2ffc 545 omap2_prcm_base_init();
a64459c4
AM		 546 omap3xxx_voltagedomains_init();
547 omap3xxx_powerdomains_init();
185fde6d 548 ti816x_clockdomains_init();
0f3ccb24 549 dm816x_hwmod_init();
a64459c4 550 omap_hwmod_init_postsetup();
58a641c8 551 omap_clk_soc_init = dm816x_dt_clk_init;
a64459c4
AM		 552}
553#endif
554
08f30989
AM		 555#ifdef CONFIG_SOC_AM33XX
556void __init am33xx_init_early(void)
557{
b6a4226c
PW		 558 omap2_set_globals_tap(AM335X_CLASS,
559 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 560 omap2_control_base_init();
08f30989 561 omap3xxx_check_revision();
7bcad170 562 am33xx_check_features();
ab7b2ffc 563 omap2_prcm_base_init();
3f0ea764 564 am33xx_powerdomains_init();
9c80f3aa 565 am33xx_clockdomains_init();
a2cfc509
VH		 566 am33xx_hwmod_init();
567 omap_hwmod_init_postsetup();
149c09d3 568 omap_clk_soc_init = am33xx_dt_clk_init;
08f30989 569}
765e7a06
NM		 570
571void __init am33xx_init_late(void)
572{
02b83dcb 573 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 574}
08f30989
AM		 575#endif
576
c5107027
AM		 577#ifdef CONFIG_SOC_AM43XX
578void __init am43xx_init_early(void)
579{
580 omap2_set_globals_tap(AM335X_CLASS,
581 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 582 omap2_control_base_init();
c5107027 583 omap3xxx_check_revision();
7a2e0513 584 am33xx_check_features();
ab7b2ffc 585 omap2_prcm_base_init();
8835cf6e
A		 586 am43xx_powerdomains_init();
587 am43xx_clockdomains_init();
588 am43xx_hwmod_init();
589 omap_hwmod_init_postsetup();
d941f86f 590 omap_l2_cache_init();
d22031e2 591 omap_clk_soc_init = am43xx_dt_clk_init;
c5107027 592}
765e7a06
NM		 593
594void __init am43xx_init_late(void)
595{
02b83dcb 596 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 597}
c5107027
AM		 598#endif
599
c4e2d245 600#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 601void __init omap4430_init_early(void)
602{
b6a4226c
PW		 603 omap2_set_globals_tap(OMAP443X_CLASS,
604 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
d9a16f9a 605 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
ca125b5e 606 omap2_control_base_init();
4de34f35
VH		 607 omap4xxx_check_revision();
608 omap4xxx_check_features();
ab7b2ffc 609 omap2_prcm_base_init();
f4b9f40a 610 omap4_sar_ram_init();
0573b957 611 omap4_mpuss_early_init();
de70af49 612 omap4_pm_init_early();
7b250aff
TL		 613 omap44xx_voltagedomains_init();
614 omap44xx_powerdomains_init();
615 omap44xx_clockdomains_init();
616 omap44xx_hwmod_init();
617 omap_hwmod_init_postsetup();
b39b14e6 618 omap_l2_cache_init();
c8c88d85 619 omap_clk_soc_init = omap4xxx_dt_clk_init;
8f5b5a41 620}
bbd707ac
SG		 621
622void __init omap4430_init_late(void)
623{
02b83dcb 624 omap_pm_soc_init = omap4_pm_init;
bbd707ac 625}
c4e2d245 626#endif
8f5b5a41 627
05e152c7
S		 628#ifdef CONFIG_SOC_OMAP5
629void __init omap5_init_early(void)
630{
b6a4226c
PW		 631 omap2_set_globals_tap(OMAP54XX_CLASS,
632 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
d9a16f9a 633 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 634 omap2_control_base_init();
ab7b2ffc 635 omap2_prcm_base_init();
05e152c7 636 omap5xxx_check_revision();
f4b9f40a 637 omap4_sar_ram_init();
8a8be46a
TL		 638 omap4_mpuss_early_init();
639 omap4_pm_init_early();
e4020aa9
SS		 640 omap54xx_voltagedomains_init();
641 omap54xx_powerdomains_init();
642 omap54xx_clockdomains_init();
643 omap54xx_hwmod_init();
644 omap_hwmod_init_postsetup();
cfa9667d 645 omap_clk_soc_init = omap5xxx_dt_clk_init;
05e152c7 646}
765e7a06
NM		 647
648void __init omap5_init_late(void)
649{
02b83dcb 650 omap_pm_soc_init = omap4_pm_init;
765e7a06 651}
05e152c7
S		 652#endif
653
a3a9384a
S		 654#ifdef CONFIG_SOC_DRA7XX
655void __init dra7xx_init_early(void)
656{
ec490f6f
NM		 657 omap2_set_globals_tap(DRA7XX_CLASS,
658 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
a3a9384a 659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 660 omap2_control_base_init();
6af16a1d 661 omap4_pm_init_early();
ab7b2ffc 662 omap2_prcm_base_init();
733d20ee 663 dra7xxx_check_revision();
7de516a6
A		 664 dra7xx_powerdomains_init();
665 dra7xx_clockdomains_init();
666 dra7xx_hwmod_init();
667 omap_hwmod_init_postsetup();
f1cf498e 668 omap_clk_soc_init = dra7xx_dt_clk_init;
a3a9384a 669}
765e7a06
NM		 670
671void __init dra7xx_init_late(void)
672{
02b83dcb 673 omap_pm_soc_init = omap4_pm_init;
765e7a06 674}
a3a9384a
S		 675#endif
676
677
a4ca9dbe 678void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 679 struct omap_sdrc_params *sdrc_cs1)
680{
a66cb345
TL		 681 omap_sram_init();
682
01001712 683 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 684 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
685 _omap2_init_reprogram_sdrc();
686 }
1dbae815 687}
cfa9667d
TK		 688
689int __init omap_clk_init(void)
690{
691 int ret = 0;
692
693 if (!omap_clk_soc_init)
694 return 0;
695
8111e010
TK		 696 ti_clk_init_features();
697
e9e63088
TK		 698 omap2_clk_setup_ll_ops();
699
58a641c8
TL		 700 ret = omap_control_init();
701 if (ret)
702 return ret;
fe87414f 703
58a641c8
TL		 704 ret = omap_prcm_init();
705 if (ret)
706 return ret;
c08ee14c 707
58a641c8 708 of_clk_init(NULL);
c08ee14c 709
58a641c8 710 ti_dt_clk_init_retry_clks();
c08ee14c 711
58a641c8 712 ti_dt_clockdomains_setup();
c08ee14c
TK		 713
714 ret = omap_clk_soc_init();
cfa9667d
TK		 715
716 return ret;
717}
Ubuntu Hirsute Linux kernel mirror