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UBUNTU: Ubuntu-5.15.0-39.42
[mirror_ubuntu-jammy-kernel.git] / arch / arm / mach-omap2 / io.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
1dbae815
TL		 2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
44169075 8 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
1dbae815 13 *
44169075 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1dbae815 15 */
1dbae815
TL		 16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
fced80c7 19#include <linux/io.h>
2f135eaf 20#include <linux/clk.h>
1dbae815 21
120db2cb 22#include <asm/tlb.h>
120db2cb
TL		 23#include <asm/mach/map.h>
24
45c3eb7d 25#include <linux/omap-dma.h>
ee0839c2 26
dc843280 27#include "omap_hwmod.h"
dbc04161 28#include "soc.h"
ee0839c2 29#include "iomap.h"
81a60482 30#include "voltage.h"
72e06d08 31#include "powerdomain.h"
1540f214 32#include "clockdomain.h"
4e65331c 33#include "common.h"
e30384ab 34#include "clock.h"
ee0839c2
TL		 35#include "clock2xxx.h"
36#include "clock3xxx.h"
3e6ece13 37#include "sdrc.h"
b6a4226c 38#include "control.h"
3d82cbbb 39#include "serial.h"
bf027ca1 40#include "sram.h"
c4ceedcb
PW		 41#include "cm2xxx.h"
42#include "cm3xxx.h"
7632a02f 43#include "cm33xx.h"
ab6c9bbf 44#include "cm44xx.h"
d9a16f9a
PW		 45#include "prm.h"
46#include "cm.h"
47#include "prcm_mpu44xx.h"
48#include "prminst44xx.h"
63a293e0
PW		 49#include "prm2xxx.h"
50#include "prm3xxx.h"
d9bbe84f 51#include "prm33xx.h"
63a293e0 52#include "prm44xx.h"
69a1e7a1 53#include "opp2xxx.h"
db711893 54#include "omap-secure.h"
02bfc030 55
ff931c82 56/*
cfa9667d 57 * omap_clk_soc_init: points to a function that does the SoC-specific
ff931c82
RN		 58 * clock initializations
59 */
cfa9667d 60static int (*omap_clk_soc_init)(void);
ff931c82 61
1dbae815
TL		 62/*
63 * The machine specific code may provide the extra mapping besides the
64 * default mapping provided here.
65 */
cc26b3b0 66
e48f814e 67#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
cc26b3b0 68static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 69 {
70 .virtual = L3_24XX_VIRT,
71 .pfn = __phys_to_pfn(L3_24XX_PHYS),
72 .length = L3_24XX_SIZE,
73 .type = MT_DEVICE
74 },
09f21ed4 75 {
cc26b3b0
SMK		 76 .virtual = L4_24XX_VIRT,
77 .pfn = __phys_to_pfn(L4_24XX_PHYS),
78 .length = L4_24XX_SIZE,
79 .type = MT_DEVICE
09f21ed4 80 },
cc26b3b0
SMK		 81};
82
59b479e0 83#ifdef CONFIG_SOC_OMAP2420
cc26b3b0
SMK		 84static struct map_desc omap242x_io_desc[] __initdata = {
85 {
7adb9987
PW		 86 .virtual = DSP_MEM_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
88 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 89 .type = MT_DEVICE
90 },
91 {
7adb9987
PW		 92 .virtual = DSP_IPI_2420_VIRT,
93 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
94 .length = DSP_IPI_2420_SIZE,
cc26b3b0 95 .type = MT_DEVICE
09f21ed4 96 },
cc26b3b0 97 {
7adb9987
PW		 98 .virtual = DSP_MMU_2420_VIRT,
99 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
100 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 101 .type = MT_DEVICE
102 },
103};
104
105#endif
106
59b479e0 107#ifdef CONFIG_SOC_OMAP2430
cc26b3b0 108static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 109 {
110 .virtual = L4_WK_243X_VIRT,
111 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
112 .length = L4_WK_243X_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_GPMC_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
118 .length = OMAP243X_GPMC_SIZE,
119 .type = MT_DEVICE
120 },
cc26b3b0
SMK		 121 {
122 .virtual = OMAP243X_SDRC_VIRT,
123 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
124 .length = OMAP243X_SDRC_SIZE,
125 .type = MT_DEVICE
126 },
127 {
128 .virtual = OMAP243X_SMS_VIRT,
129 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
130 .length = OMAP243X_SMS_SIZE,
131 .type = MT_DEVICE
132 },
133};
72d0f1c3 134#endif
72d0f1c3 135#endif
cc26b3b0 136
a8eb7ca0 137#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 138static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 139 {
cc26b3b0
SMK		 140 .virtual = L3_34XX_VIRT,
141 .pfn = __phys_to_pfn(L3_34XX_PHYS),
142 .length = L3_34XX_SIZE,
c40fae95
TL		 143 .type = MT_DEVICE
144 },
145 {
cc26b3b0
SMK		 146 .virtual = L4_34XX_VIRT,
147 .pfn = __phys_to_pfn(L4_34XX_PHYS),
148 .length = L4_34XX_SIZE,
c40fae95
TL		 149 .type = MT_DEVICE
150 },
cc26b3b0
SMK		 151 {
152 .virtual = OMAP34XX_GPMC_VIRT,
153 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
154 .length = OMAP34XX_GPMC_SIZE,
1dbae815 155 .type = MT_DEVICE
cc26b3b0
SMK		 156 },
157 {
158 .virtual = OMAP343X_SMS_VIRT,
159 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
160 .length = OMAP343X_SMS_SIZE,
161 .type = MT_DEVICE
162 },
163 {
164 .virtual = OMAP343X_SDRC_VIRT,
165 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
166 .length = OMAP343X_SDRC_SIZE,
1dbae815 167 .type = MT_DEVICE
cc26b3b0
SMK		 168 },
169 {
170 .virtual = L4_PER_34XX_VIRT,
171 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
172 .length = L4_PER_34XX_SIZE,
173 .type = MT_DEVICE
174 },
175 {
176 .virtual = L4_EMU_34XX_VIRT,
177 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
178 .length = L4_EMU_34XX_SIZE,
179 .type = MT_DEVICE
180 },
1dbae815 181};
cc26b3b0 182#endif
01001712 183
33959553 184#ifdef CONFIG_SOC_TI81XX
a920360f 185static struct map_desc omapti81xx_io_desc[] __initdata = {
1e6cb146
AM		 186 {
187 .virtual = L4_34XX_VIRT,
188 .pfn = __phys_to_pfn(L4_34XX_PHYS),
189 .length = L4_34XX_SIZE,
190 .type = MT_DEVICE
191 }
192};
193#endif
194
addb154a 195#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
1e6cb146 196static struct map_desc omapam33xx_io_desc[] __initdata = {
01001712
HP		 197 {
198 .virtual = L4_34XX_VIRT,
199 .pfn = __phys_to_pfn(L4_34XX_PHYS),
200 .length = L4_34XX_SIZE,
201 .type = MT_DEVICE
202 },
1e6cb146
AM		 203 {
204 .virtual = L4_WK_AM33XX_VIRT,
205 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
206 .length = L4_WK_AM33XX_SIZE,
207 .type = MT_DEVICE
208 }
01001712
HP		 209};
210#endif
211
44169075
SS		 212#ifdef CONFIG_ARCH_OMAP4
213static struct map_desc omap44xx_io_desc[] __initdata = {
214 {
215 .virtual = L3_44XX_VIRT,
216 .pfn = __phys_to_pfn(L3_44XX_PHYS),
217 .length = L3_44XX_SIZE,
218 .type = MT_DEVICE,
219 },
220 {
221 .virtual = L4_44XX_VIRT,
222 .pfn = __phys_to_pfn(L4_44XX_PHYS),
223 .length = L4_44XX_SIZE,
224 .type = MT_DEVICE,
225 },
44169075
SS		 226 {
227 .virtual = L4_PER_44XX_VIRT,
228 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
229 .length = L4_PER_44XX_SIZE,
230 .type = MT_DEVICE,
231 },
44169075
SS		 232};
233#endif
1dbae815 234
ea827ad5 235#ifdef CONFIG_SOC_OMAP5
05e152c7
S		 236static struct map_desc omap54xx_io_desc[] __initdata = {
237 {
238 .virtual = L3_54XX_VIRT,
239 .pfn = __phys_to_pfn(L3_54XX_PHYS),
240 .length = L3_54XX_SIZE,
241 .type = MT_DEVICE,
242 },
243 {
244 .virtual = L4_54XX_VIRT,
245 .pfn = __phys_to_pfn(L4_54XX_PHYS),
246 .length = L4_54XX_SIZE,
247 .type = MT_DEVICE,
248 },
249 {
250 .virtual = L4_WK_54XX_VIRT,
251 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
252 .length = L4_WK_54XX_SIZE,
253 .type = MT_DEVICE,
254 },
255 {
256 .virtual = L4_PER_54XX_VIRT,
257 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
258 .length = L4_PER_54XX_SIZE,
259 .type = MT_DEVICE,
260 },
261};
262#endif
263
ea827ad5
NM		 264#ifdef CONFIG_SOC_DRA7XX
265static struct map_desc dra7xx_io_desc[] __initdata = {
266 {
267 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
268 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
269 .length = L4_CFG_MPU_DRA7XX_SIZE,
270 .type = MT_DEVICE,
271 },
272 {
273 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
274 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
275 .length = L3_MAIN_SN_DRA7XX_SIZE,
276 .type = MT_DEVICE,
277 },
278 {
279 .virtual = L4_PER1_DRA7XX_VIRT,
280 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
281 .length = L4_PER1_DRA7XX_SIZE,
282 .type = MT_DEVICE,
283 },
284 {
285 .virtual = L4_PER2_DRA7XX_VIRT,
286 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
287 .length = L4_PER2_DRA7XX_SIZE,
288 .type = MT_DEVICE,
289 },
290 {
291 .virtual = L4_PER3_DRA7XX_VIRT,
292 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
293 .length = L4_PER3_DRA7XX_SIZE,
294 .type = MT_DEVICE,
295 },
296 {
297 .virtual = L4_CFG_DRA7XX_VIRT,
298 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
299 .length = L4_CFG_DRA7XX_SIZE,
300 .type = MT_DEVICE,
301 },
302 {
303 .virtual = L4_WKUP_DRA7XX_VIRT,
304 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
305 .length = L4_WKUP_DRA7XX_SIZE,
306 .type = MT_DEVICE,
307 },
308};
309#endif
310
59b479e0 311#ifdef CONFIG_SOC_OMAP2420
b6a4226c 312void __init omap242x_map_io(void)
1dbae815 313{
cc26b3b0
SMK		 314 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
315 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0 316}
cc26b3b0
SMK		 317#endif
318
59b479e0 319#ifdef CONFIG_SOC_OMAP2430
b6a4226c 320void __init omap243x_map_io(void)
6fbd55d0 321{
cc26b3b0
SMK		 322 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
323 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0 324}
cc26b3b0
SMK		 325#endif
326
a8eb7ca0 327#ifdef CONFIG_ARCH_OMAP3
b6a4226c 328void __init omap3_map_io(void)
6fbd55d0 329{
cc26b3b0 330 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0 331}
cc26b3b0 332#endif
120db2cb 333
33959553 334#ifdef CONFIG_SOC_TI81XX
b6a4226c 335void __init ti81xx_map_io(void)
01001712 336{
a920360f 337 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
01001712
HP		 338}
339#endif
340
addb154a 341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
b6a4226c 342void __init am33xx_map_io(void)
01001712 343{
1e6cb146 344 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
01001712
HP		 345}
346#endif
347
6fbd55d0 348#ifdef CONFIG_ARCH_OMAP4
b6a4226c 349void __init omap4_map_io(void)
6fbd55d0 350{
44169075 351 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
f746929f 352 omap_barriers_init();
120db2cb 353}
6fbd55d0 354#endif
120db2cb 355
ea827ad5 356#ifdef CONFIG_SOC_OMAP5
b6a4226c 357void __init omap5_map_io(void)
05e152c7
S		 358{
359 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
f746929f 360 omap_barriers_init();
05e152c7
S		 361}
362#endif
ea827ad5
NM		 363
364#ifdef CONFIG_SOC_DRA7XX
365void __init dra7xx_map_io(void)
366{
367 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
456e8d53 368 omap_barriers_init();
ea827ad5
NM		 369}
370#endif
2f135eaf
PW		 371/*
372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
373 *
374 * Sets the CORE DPLL3 M2 divider to the same value that it's at
375 * currently. This has the effect of setting the SDRC SDRAM AC timing
376 * registers to the values currently defined by the kernel. Currently
377 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
378 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
379 * or passes along the return value of clk_set_rate().
380 */
381static int __init _omap2_init_reprogram_sdrc(void)
382{
383 struct clk *dpll3_m2_ck;
384 int v = -EINVAL;
385 long rate;
386
387 if (!cpu_is_omap34xx())
388 return 0;
389
390 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
e281f7ec 391 if (IS_ERR(dpll3_m2_ck))
2f135eaf
PW		 392 return -EINVAL;
393
394 rate = clk_get_rate(dpll3_m2_ck);
395 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
396 v = clk_set_rate(dpll3_m2_ck, rate);
397 if (v)
398 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
399
400 clk_put(dpll3_m2_ck);
401
402 return v;
403}
404
f21af425 405#ifdef CONFIG_OMAP_HWMOD
2092e5cc
PW		 406static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
407{
408 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
409}
410
293ea3d0 411static void __init __maybe_unused omap_hwmod_init_postsetup(void)
7b250aff 412{
6d63b12d 413 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
2092e5cc
PW		 414
415 /* Set the default postsetup state for all hwmods */
2092e5cc 416 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
4805734b 417}
f21af425
TL		 418#else
419static inline void omap_hwmod_init_postsetup(void)
420{
421}
422#endif
4805734b 423
16110798 424#ifdef CONFIG_SOC_OMAP2420
8f5b5a41
TL		 425void __init omap2420_init_early(void)
426{
b6a4226c
PW		 427 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
429 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
2208bf11 430 omap2_control_base_init();
4de34f35 431 omap2xxx_check_revision();
ab7b2ffc 432 omap2_prcm_base_init();
7b250aff
TL		 433 omap2xxx_voltagedomains_init();
434 omap242x_powerdomains_init();
435 omap242x_clockdomains_init();
436 omap2420_hwmod_init();
437 omap_hwmod_init_postsetup();
6a194a6e
TK		 438 omap_clk_soc_init = omap2420_dt_clk_init;
439 rate_table = omap2420_rate_table;
8f5b5a41 440}
bbd707ac
SG		 441
442void __init omap2420_init_late(void)
443{
02b83dcb 444 omap_pm_soc_init = omap2_pm_init;
bbd707ac 445}
16110798 446#endif
8f5b5a41 447
16110798 448#ifdef CONFIG_SOC_OMAP2430
8f5b5a41
TL		 449void __init omap2430_init_early(void)
450{
b6a4226c
PW		 451 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
452 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
453 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
2208bf11 454 omap2_control_base_init();
4de34f35 455 omap2xxx_check_revision();
ab7b2ffc 456 omap2_prcm_base_init();
7b250aff
TL		 457 omap2xxx_voltagedomains_init();
458 omap243x_powerdomains_init();
459 omap243x_clockdomains_init();
460 omap2430_hwmod_init();
461 omap_hwmod_init_postsetup();
6a194a6e
TK		 462 omap_clk_soc_init = omap2430_dt_clk_init;
463 rate_table = omap2430_rate_table;
7b250aff 464}
bbd707ac
SG		 465
466void __init omap2430_init_late(void)
467{
02b83dcb 468 omap_pm_soc_init = omap2_pm_init;
bbd707ac 469}
c4e2d245 470#endif
7b250aff
TL		 471
472/*
473 * Currently only board-omap3beagle.c should call this because of the
474 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
475 */
c4e2d245 476#ifdef CONFIG_ARCH_OMAP3
7b250aff
TL		 477void __init omap3_init_early(void)
478{
b6a4226c
PW		 479 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
480 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
481 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
2208bf11 482 omap2_control_base_init();
4de34f35
VH		 483 omap3xxx_check_revision();
484 omap3xxx_check_features();
ab7b2ffc 485 omap2_prcm_base_init();
7b250aff
TL		 486 omap3xxx_voltagedomains_init();
487 omap3xxx_powerdomains_init();
488 omap3xxx_clockdomains_init();
489 omap3xxx_hwmod_init();
490 omap_hwmod_init_postsetup();
db711893 491 omap_secure_init();
8f5b5a41
TL		 492}
493
494void __init omap3430_init_early(void)
495{
7b250aff 496 omap3_init_early();
58a641c8 497 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 498}
499
500void __init omap35xx_init_early(void)
501{
7b250aff 502 omap3_init_early();
58a641c8 503 omap_clk_soc_init = omap3430_dt_clk_init;
8f5b5a41
TL		 504}
505
506void __init omap3630_init_early(void)
507{
7b250aff 508 omap3_init_early();
58a641c8 509 omap_clk_soc_init = omap3630_dt_clk_init;
8f5b5a41
TL		 510}
511
512void __init am35xx_init_early(void)
513{
7b250aff 514 omap3_init_early();
58a641c8 515 omap_clk_soc_init = am35xx_dt_clk_init;
8f5b5a41
TL		 516}
517
bbd707ac
SG		 518void __init omap3_init_late(void)
519{
02b83dcb 520 omap_pm_soc_init = omap3_pm_init;
bbd707ac
SG		 521}
522
523void __init ti81xx_init_late(void)
524{
02b83dcb 525 omap_pm_soc_init = omap_pm_nop_init;
bbd707ac 526}
c4e2d245 527#endif
8f5b5a41 528
a64459c4
AM		 529#ifdef CONFIG_SOC_TI81XX
530void __init ti814x_init_early(void)
531{
532 omap2_set_globals_tap(TI814X_CLASS,
533 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 534 omap2_control_base_init();
a64459c4
AM		 535 omap3xxx_check_revision();
536 ti81xx_check_features();
ab7b2ffc 537 omap2_prcm_base_init();
a64459c4
AM		 538 omap3xxx_voltagedomains_init();
539 omap3xxx_powerdomains_init();
185fde6d 540 ti814x_clockdomains_init();
0f3ccb24 541 dm814x_hwmod_init();
a64459c4 542 omap_hwmod_init_postsetup();
d893656e 543 omap_clk_soc_init = dm814x_dt_clk_init;
db711893 544 omap_secure_init();
a64459c4
AM		 545}
546
547void __init ti816x_init_early(void)
548{
549 omap2_set_globals_tap(TI816X_CLASS,
550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
2208bf11 551 omap2_control_base_init();
a64459c4
AM		 552 omap3xxx_check_revision();
553 ti81xx_check_features();
ab7b2ffc 554 omap2_prcm_base_init();
a64459c4
AM		 555 omap3xxx_voltagedomains_init();
556 omap3xxx_powerdomains_init();
185fde6d 557 ti816x_clockdomains_init();
0f3ccb24 558 dm816x_hwmod_init();
a64459c4 559 omap_hwmod_init_postsetup();
58a641c8 560 omap_clk_soc_init = dm816x_dt_clk_init;
db711893 561 omap_secure_init();
a64459c4
AM		 562}
563#endif
564
08f30989
AM		 565#ifdef CONFIG_SOC_AM33XX
566void __init am33xx_init_early(void)
567{
b6a4226c
PW		 568 omap2_set_globals_tap(AM335X_CLASS,
569 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 570 omap2_control_base_init();
08f30989 571 omap3xxx_check_revision();
7bcad170 572 am33xx_check_features();
ab7b2ffc 573 omap2_prcm_base_init();
3f0ea764 574 am33xx_powerdomains_init();
9c80f3aa 575 am33xx_clockdomains_init();
149c09d3 576 omap_clk_soc_init = am33xx_dt_clk_init;
db711893 577 omap_secure_init();
08f30989 578}
765e7a06
NM		 579
580void __init am33xx_init_late(void)
581{
02b83dcb 582 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 583}
08f30989
AM		 584#endif
585
c5107027
AM		 586#ifdef CONFIG_SOC_AM43XX
587void __init am43xx_init_early(void)
588{
589 omap2_set_globals_tap(AM335X_CLASS,
590 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
2208bf11 591 omap2_control_base_init();
c5107027 592 omap3xxx_check_revision();
7a2e0513 593 am33xx_check_features();
ab7b2ffc 594 omap2_prcm_base_init();
8835cf6e
A		 595 am43xx_powerdomains_init();
596 am43xx_clockdomains_init();
d941f86f 597 omap_l2_cache_init();
d22031e2 598 omap_clk_soc_init = am43xx_dt_clk_init;
db711893 599 omap_secure_init();
c5107027 600}
765e7a06
NM		 601
602void __init am43xx_init_late(void)
603{
02b83dcb 604 omap_pm_soc_init = amx3_common_pm_init;
765e7a06 605}
c5107027
AM		 606#endif
607
c4e2d245 608#ifdef CONFIG_ARCH_OMAP4
8f5b5a41
TL		 609void __init omap4430_init_early(void)
610{
b6a4226c
PW		 611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
d9a16f9a 613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
ca125b5e 614 omap2_control_base_init();
4de34f35
VH		 615 omap4xxx_check_revision();
616 omap4xxx_check_features();
ab7b2ffc 617 omap2_prcm_base_init();
f4b9f40a 618 omap4_sar_ram_init();
0573b957 619 omap4_mpuss_early_init();
de70af49 620 omap4_pm_init_early();
7b250aff
TL		 621 omap44xx_voltagedomains_init();
622 omap44xx_powerdomains_init();
623 omap44xx_clockdomains_init();
b39b14e6 624 omap_l2_cache_init();
c8c88d85 625 omap_clk_soc_init = omap4xxx_dt_clk_init;
db711893 626 omap_secure_init();
8f5b5a41 627}
bbd707ac
SG		 628
629void __init omap4430_init_late(void)
630{
02b83dcb 631 omap_pm_soc_init = omap4_pm_init;
bbd707ac 632}
c4e2d245 633#endif
8f5b5a41 634
05e152c7
S		 635#ifdef CONFIG_SOC_OMAP5
636void __init omap5_init_early(void)
637{
b6a4226c
PW		 638 omap2_set_globals_tap(OMAP54XX_CLASS,
639 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
d9a16f9a 640 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 641 omap2_control_base_init();
ab7b2ffc 642 omap2_prcm_base_init();
05e152c7 643 omap5xxx_check_revision();
f4b9f40a 644 omap4_sar_ram_init();
8a8be46a
TL		 645 omap4_mpuss_early_init();
646 omap4_pm_init_early();
e4020aa9
SS		 647 omap54xx_voltagedomains_init();
648 omap54xx_powerdomains_init();
649 omap54xx_clockdomains_init();
cfa9667d 650 omap_clk_soc_init = omap5xxx_dt_clk_init;
db711893 651 omap_secure_init();
05e152c7 652}
765e7a06
NM		 653
654void __init omap5_init_late(void)
655{
02b83dcb 656 omap_pm_soc_init = omap4_pm_init;
765e7a06 657}
05e152c7
S		 658#endif
659
a3a9384a
S		 660#ifdef CONFIG_SOC_DRA7XX
661void __init dra7xx_init_early(void)
662{
ec490f6f
NM		 663 omap2_set_globals_tap(DRA7XX_CLASS,
664 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
a3a9384a 665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
ca125b5e 666 omap2_control_base_init();
6af16a1d 667 omap4_pm_init_early();
ab7b2ffc 668 omap2_prcm_base_init();
733d20ee 669 dra7xxx_check_revision();
7de516a6
A		 670 dra7xx_powerdomains_init();
671 dra7xx_clockdomains_init();
f1cf498e 672 omap_clk_soc_init = dra7xx_dt_clk_init;
db711893 673 omap_secure_init();
a3a9384a 674}
765e7a06
NM		 675
676void __init dra7xx_init_late(void)
677{
02b83dcb 678 omap_pm_soc_init = omap4_pm_init;
765e7a06 679}
a3a9384a
S		 680#endif
681
682
a4ca9dbe 683void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
4805734b
PW		 684 struct omap_sdrc_params *sdrc_cs1)
685{
a66cb345
TL		 686 omap_sram_init();
687
01001712 688 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
aa4b1f6e
KH		 689 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
690 _omap2_init_reprogram_sdrc();
691 }
1dbae815 692}
cfa9667d
TK		 693
694int __init omap_clk_init(void)
695{
696 int ret = 0;
697
698 if (!omap_clk_soc_init)
699 return 0;
700
8111e010
TK		 701 ti_clk_init_features();
702
e9e63088
TK		 703 omap2_clk_setup_ll_ops();
704
58a641c8
TL		 705 ret = omap_control_init();
706 if (ret)
707 return ret;
fe87414f 708
58a641c8
TL		 709 ret = omap_prcm_init();
710 if (ret)
711 return ret;
c08ee14c 712
58a641c8 713 of_clk_init(NULL);
c08ee14c 714
58a641c8 715 ti_dt_clk_init_retry_clks();
c08ee14c 716
58a641c8 717 ti_dt_clockdomains_setup();
c08ee14c
TK		 718
719 ret = omap_clk_soc_init();
cfa9667d
TK		 720
721 return ret;
722}
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