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340a614a HD |
1 | /* |
2 | * Mailbox reservation modules for OMAP2 | |
3 | * | |
4 | * Copyright (C) 2006 Nokia Corporation | |
5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | |
6 | * and Paul Mundt <paul.mundt@nokia.com> | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/platform_device.h> | |
fced80c7 | 17 | #include <linux/io.h> |
a09e64fb RK |
18 | #include <mach/mailbox.h> |
19 | #include <mach/irqs.h> | |
340a614a HD |
20 | |
21 | #define MAILBOX_REVISION 0x00 | |
22 | #define MAILBOX_SYSCONFIG 0x10 | |
23 | #define MAILBOX_SYSSTATUS 0x14 | |
24 | #define MAILBOX_MESSAGE_0 0x40 | |
25 | #define MAILBOX_MESSAGE_1 0x44 | |
26 | #define MAILBOX_MESSAGE_2 0x48 | |
27 | #define MAILBOX_MESSAGE_3 0x4c | |
28 | #define MAILBOX_MESSAGE_4 0x50 | |
29 | #define MAILBOX_MESSAGE_5 0x54 | |
30 | #define MAILBOX_FIFOSTATUS_0 0x80 | |
31 | #define MAILBOX_FIFOSTATUS_1 0x84 | |
32 | #define MAILBOX_FIFOSTATUS_2 0x88 | |
33 | #define MAILBOX_FIFOSTATUS_3 0x8c | |
34 | #define MAILBOX_FIFOSTATUS_4 0x90 | |
35 | #define MAILBOX_FIFOSTATUS_5 0x94 | |
36 | #define MAILBOX_MSGSTATUS_0 0xc0 | |
37 | #define MAILBOX_MSGSTATUS_1 0xc4 | |
38 | #define MAILBOX_MSGSTATUS_2 0xc8 | |
39 | #define MAILBOX_MSGSTATUS_3 0xcc | |
40 | #define MAILBOX_MSGSTATUS_4 0xd0 | |
41 | #define MAILBOX_MSGSTATUS_5 0xd4 | |
42 | #define MAILBOX_IRQSTATUS_0 0x100 | |
43 | #define MAILBOX_IRQENABLE_0 0x104 | |
44 | #define MAILBOX_IRQSTATUS_1 0x108 | |
45 | #define MAILBOX_IRQENABLE_1 0x10c | |
46 | #define MAILBOX_IRQSTATUS_2 0x110 | |
47 | #define MAILBOX_IRQENABLE_2 0x114 | |
48 | #define MAILBOX_IRQSTATUS_3 0x118 | |
49 | #define MAILBOX_IRQENABLE_3 0x11c | |
50 | ||
51 | static unsigned long mbox_base; | |
52 | ||
53 | #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1)) | |
54 | #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n))) | |
55 | ||
56 | struct omap_mbox2_fifo { | |
57 | unsigned long msg; | |
58 | unsigned long fifo_stat; | |
59 | unsigned long msg_stat; | |
60 | }; | |
61 | ||
62 | struct omap_mbox2_priv { | |
63 | struct omap_mbox2_fifo tx_fifo; | |
64 | struct omap_mbox2_fifo rx_fifo; | |
65 | unsigned long irqenable; | |
66 | unsigned long irqstatus; | |
67 | u32 newmsg_bit; | |
68 | u32 notfull_bit; | |
69 | }; | |
70 | ||
71 | static struct clk *mbox_ick_handle; | |
72 | ||
bfbdcf8a HD |
73 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, |
74 | omap_mbox_type_t irq); | |
75 | ||
340a614a HD |
76 | static inline unsigned int mbox_read_reg(unsigned int reg) |
77 | { | |
78 | return __raw_readl(mbox_base + reg); | |
79 | } | |
80 | ||
81 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | |
82 | { | |
83 | __raw_writel(val, mbox_base + reg); | |
84 | } | |
85 | ||
86 | /* Mailbox H/W preparations */ | |
bfbdcf8a | 87 | static int omap2_mbox_startup(struct omap_mbox *mbox) |
340a614a HD |
88 | { |
89 | unsigned int l; | |
90 | ||
91 | mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); | |
92 | if (IS_ERR(mbox_ick_handle)) { | |
93 | printk("Could not get mailboxes_ick\n"); | |
94 | return -ENODEV; | |
95 | } | |
96 | clk_enable(mbox_ick_handle); | |
97 | ||
98 | /* set smart-idle & autoidle */ | |
99 | l = mbox_read_reg(MAILBOX_SYSCONFIG); | |
100 | l |= 0x00000011; | |
101 | mbox_write_reg(l, MAILBOX_SYSCONFIG); | |
102 | ||
bfbdcf8a HD |
103 | omap2_mbox_enable_irq(mbox, IRQ_RX); |
104 | ||
340a614a HD |
105 | return 0; |
106 | } | |
107 | ||
bfbdcf8a | 108 | static void omap2_mbox_shutdown(struct omap_mbox *mbox) |
340a614a HD |
109 | { |
110 | clk_disable(mbox_ick_handle); | |
111 | clk_put(mbox_ick_handle); | |
112 | } | |
113 | ||
114 | /* Mailbox FIFO handle functions */ | |
bfbdcf8a | 115 | static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) |
340a614a HD |
116 | { |
117 | struct omap_mbox2_fifo *fifo = | |
118 | &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; | |
119 | return (mbox_msg_t) mbox_read_reg(fifo->msg); | |
120 | } | |
121 | ||
bfbdcf8a | 122 | static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) |
340a614a HD |
123 | { |
124 | struct omap_mbox2_fifo *fifo = | |
125 | &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; | |
126 | mbox_write_reg(msg, fifo->msg); | |
127 | } | |
128 | ||
bfbdcf8a | 129 | static int omap2_mbox_fifo_empty(struct omap_mbox *mbox) |
340a614a HD |
130 | { |
131 | struct omap_mbox2_fifo *fifo = | |
132 | &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; | |
133 | return (mbox_read_reg(fifo->msg_stat) == 0); | |
134 | } | |
135 | ||
bfbdcf8a | 136 | static int omap2_mbox_fifo_full(struct omap_mbox *mbox) |
340a614a HD |
137 | { |
138 | struct omap_mbox2_fifo *fifo = | |
139 | &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; | |
140 | return (mbox_read_reg(fifo->fifo_stat)); | |
141 | } | |
142 | ||
143 | /* Mailbox IRQ handle functions */ | |
bfbdcf8a | 144 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, |
340a614a HD |
145 | omap_mbox_type_t irq) |
146 | { | |
147 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
148 | u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
149 | ||
150 | l = mbox_read_reg(p->irqenable); | |
151 | l |= bit; | |
152 | mbox_write_reg(l, p->irqenable); | |
153 | } | |
154 | ||
bfbdcf8a | 155 | static void omap2_mbox_disable_irq(struct omap_mbox *mbox, |
340a614a HD |
156 | omap_mbox_type_t irq) |
157 | { | |
158 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
159 | u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
160 | ||
161 | l = mbox_read_reg(p->irqenable); | |
162 | l &= ~bit; | |
163 | mbox_write_reg(l, p->irqenable); | |
164 | } | |
165 | ||
bfbdcf8a | 166 | static void omap2_mbox_ack_irq(struct omap_mbox *mbox, |
340a614a HD |
167 | omap_mbox_type_t irq) |
168 | { | |
169 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
170 | u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
171 | ||
172 | mbox_write_reg(bit, p->irqstatus); | |
173 | } | |
174 | ||
bfbdcf8a | 175 | static int omap2_mbox_is_irq(struct omap_mbox *mbox, |
340a614a HD |
176 | omap_mbox_type_t irq) |
177 | { | |
178 | struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; | |
179 | u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; | |
180 | u32 enable = mbox_read_reg(p->irqenable); | |
181 | u32 status = mbox_read_reg(p->irqstatus); | |
182 | ||
183 | return (enable & status & bit); | |
184 | } | |
185 | ||
186 | static struct omap_mbox_ops omap2_mbox_ops = { | |
187 | .type = OMAP_MBOX_TYPE2, | |
188 | .startup = omap2_mbox_startup, | |
189 | .shutdown = omap2_mbox_shutdown, | |
190 | .fifo_read = omap2_mbox_fifo_read, | |
191 | .fifo_write = omap2_mbox_fifo_write, | |
192 | .fifo_empty = omap2_mbox_fifo_empty, | |
193 | .fifo_full = omap2_mbox_fifo_full, | |
194 | .enable_irq = omap2_mbox_enable_irq, | |
195 | .disable_irq = omap2_mbox_disable_irq, | |
196 | .ack_irq = omap2_mbox_ack_irq, | |
197 | .is_irq = omap2_mbox_is_irq, | |
198 | }; | |
199 | ||
200 | /* | |
201 | * MAILBOX 0: ARM -> DSP, | |
202 | * MAILBOX 1: ARM <- DSP. | |
203 | * MAILBOX 2: ARM -> IVA, | |
204 | * MAILBOX 3: ARM <- IVA. | |
205 | */ | |
206 | ||
207 | /* FIXME: the following structs should be filled automatically by the user id */ | |
208 | ||
209 | /* DSP */ | |
210 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | |
211 | .tx_fifo = { | |
212 | .msg = MAILBOX_MESSAGE_0, | |
213 | .fifo_stat = MAILBOX_FIFOSTATUS_0, | |
214 | }, | |
215 | .rx_fifo = { | |
216 | .msg = MAILBOX_MESSAGE_1, | |
217 | .msg_stat = MAILBOX_MSGSTATUS_1, | |
218 | }, | |
219 | .irqenable = MAILBOX_IRQENABLE_0, | |
220 | .irqstatus = MAILBOX_IRQSTATUS_0, | |
221 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), | |
222 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), | |
223 | }; | |
224 | ||
225 | struct omap_mbox mbox_dsp_info = { | |
226 | .name = "dsp", | |
227 | .ops = &omap2_mbox_ops, | |
228 | .priv = &omap2_mbox_dsp_priv, | |
229 | }; | |
230 | EXPORT_SYMBOL(mbox_dsp_info); | |
231 | ||
232 | /* IVA */ | |
233 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | |
234 | .tx_fifo = { | |
235 | .msg = MAILBOX_MESSAGE_2, | |
236 | .fifo_stat = MAILBOX_FIFOSTATUS_2, | |
237 | }, | |
238 | .rx_fifo = { | |
239 | .msg = MAILBOX_MESSAGE_3, | |
240 | .msg_stat = MAILBOX_MSGSTATUS_3, | |
241 | }, | |
242 | .irqenable = MAILBOX_IRQENABLE_3, | |
243 | .irqstatus = MAILBOX_IRQSTATUS_3, | |
244 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | |
245 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | |
246 | }; | |
247 | ||
248 | static struct omap_mbox mbox_iva_info = { | |
249 | .name = "iva", | |
250 | .ops = &omap2_mbox_ops, | |
251 | .priv = &omap2_mbox_iva_priv, | |
252 | }; | |
253 | ||
254 | static int __init omap2_mbox_probe(struct platform_device *pdev) | |
255 | { | |
256 | struct resource *res; | |
257 | int ret = 0; | |
258 | ||
259 | if (pdev->num_resources != 3) { | |
260 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | |
261 | pdev->num_resources); | |
262 | return -ENODEV; | |
263 | } | |
264 | ||
265 | /* MBOX base */ | |
266 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
267 | if (unlikely(!res)) { | |
268 | dev_err(&pdev->dev, "invalid mem resource\n"); | |
269 | return -ENODEV; | |
270 | } | |
271 | mbox_base = res->start; | |
272 | ||
273 | /* DSP IRQ */ | |
274 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
275 | if (unlikely(!res)) { | |
276 | dev_err(&pdev->dev, "invalid irq resource\n"); | |
277 | return -ENODEV; | |
278 | } | |
279 | mbox_dsp_info.irq = res->start; | |
280 | ||
281 | ret = omap_mbox_register(&mbox_dsp_info); | |
282 | ||
283 | /* IVA IRQ */ | |
284 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
285 | if (unlikely(!res)) { | |
286 | dev_err(&pdev->dev, "invalid irq resource\n"); | |
287 | return -ENODEV; | |
288 | } | |
289 | mbox_iva_info.irq = res->start; | |
290 | ||
291 | ret = omap_mbox_register(&mbox_iva_info); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
296 | static int omap2_mbox_remove(struct platform_device *pdev) | |
297 | { | |
298 | omap_mbox_unregister(&mbox_dsp_info); | |
299 | return 0; | |
300 | } | |
301 | ||
302 | static struct platform_driver omap2_mbox_driver = { | |
303 | .probe = omap2_mbox_probe, | |
304 | .remove = omap2_mbox_remove, | |
305 | .driver = { | |
306 | .name = "mailbox", | |
307 | }, | |
308 | }; | |
309 | ||
310 | static int __init omap2_mbox_init(void) | |
311 | { | |
312 | return platform_driver_register(&omap2_mbox_driver); | |
313 | } | |
314 | ||
315 | static void __exit omap2_mbox_exit(void) | |
316 | { | |
317 | platform_driver_unregister(&omap2_mbox_driver); | |
318 | } | |
319 | ||
320 | module_init(omap2_mbox_init); | |
321 | module_exit(omap2_mbox_exit); | |
322 | ||
323 | MODULE_LICENSE("GPL"); |