[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / mailbox.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>

#include <plat/mailbox.h>

#include "soc.h"

#define MAILBOX_REVISION		0x000
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))

#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

#define MBOX_REG_SIZE			0x120

#define OMAP4_MBOX_REG_SIZE		0x130

#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[OMAP4_MBOX_NR_REGS];
	unsigned long irqdisable;
};

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;

	pm_runtime_enable(mbox->dev->parent);
	pm_runtime_get_sync(mbox->dev->parent);

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	pm_runtime_put_sync(mbox->dev->parent);
	pm_runtime_disable(mbox->dev->parent);
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return mbox_read_reg(fifo->fifo_stat);
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	if (!cpu_is_omap44xx())
		bit = mbox_read_reg(p->irqdisable) & ~bit;

	mbox_write_reg(bit, p->irqdisable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);

	/* Flush posted write for irq status to avoid spurious interrupts */
	mbox_read_reg(p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (int)(enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;
	if (cpu_is_omap44xx())
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

/*
 * MAILBOX 0: ARM -> DSP,
 * MAILBOX 1: ARM <- DSP.
 * MAILBOX 2: ARM -> IVA,
 * MAILBOX 3: ARM <- IVA.
 */

/* FIXME: the following structs should be filled automatically by the user id */

#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
/* DSP */
static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= MAILBOX_IRQENABLE(0),
	.irqstatus	= MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= MAILBOX_IRQENABLE(0),
};

struct omap_mbox mbox_dsp_info = {
	.name	= "dsp",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_dsp_priv,
};
#endif

#if defined(CONFIG_ARCH_OMAP3)
struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
#endif

#if defined(CONFIG_SOC_OMAP2420)
/* IVA */
static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.msg_stat	= MAILBOX_MSGSTATUS(3),
	},
	.irqenable	= MAILBOX_IRQENABLE(3),
	.irqstatus	= MAILBOX_IRQSTATUS(3),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
	.irqdisable	= MAILBOX_IRQENABLE(3),
};

static struct omap_mbox mbox_iva_info = {
	.name	= "iva",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_iva_priv,
};
#endif

#ifdef CONFIG_ARCH_OMAP2
struct omap_mbox *omap2_mboxes[] = {
	&mbox_dsp_info,
#ifdef CONFIG_SOC_OMAP2420
	&mbox_iva_info,
#endif
	NULL
};
#endif

#if defined(CONFIG_ARCH_OMAP4)
/* OMAP4 */
static struct omap_mbox2_priv omap2_mbox_1_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(0),
		.fifo_stat	= MAILBOX_FIFOSTATUS(0),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(1),
		.msg_stat	= MAILBOX_MSGSTATUS(1),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(0),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(1),
	.irqdisable	= OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_1_info = {
	.name	= "mailbox-1",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_1_priv,
};

static struct omap_mbox2_priv omap2_mbox_2_priv = {
	.tx_fifo = {
		.msg		= MAILBOX_MESSAGE(3),
		.fifo_stat	= MAILBOX_FIFOSTATUS(3),
	},
	.rx_fifo = {
		.msg		= MAILBOX_MESSAGE(2),
		.msg_stat	= MAILBOX_MSGSTATUS(2),
	},
	.irqenable	= OMAP4_MAILBOX_IRQENABLE(0),
	.irqstatus	= OMAP4_MAILBOX_IRQSTATUS(0),
	.notfull_bit	= MAILBOX_IRQ_NOTFULL(3),
	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(2),
	.irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
};

struct omap_mbox mbox_2_info = {
	.name	= "mailbox-2",
	.ops	= &omap2_mbox_ops,
	.priv	= &omap2_mbox_2_priv,
};

struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
#endif

static int omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *mem;
	int ret;
	struct omap_mbox **list;

	if (false)
		;
#if defined(CONFIG_ARCH_OMAP3)
	else if (cpu_is_omap34xx()) {
		list = omap3_mboxes;

		list[0]->irq = platform_get_irq(pdev, 0);
	}
#endif
#if defined(CONFIG_ARCH_OMAP2)
	else if (cpu_is_omap2430()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq(pdev, 0);
	} else if (cpu_is_omap2420()) {
		list = omap2_mboxes;

		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
		list[1]->irq = platform_get_irq_byname(pdev, "iva");
	}
#endif
#if defined(CONFIG_ARCH_OMAP4)
	else if (cpu_is_omap44xx()) {
		list = omap4_mboxes;

		list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
	}
#endif
	else {
		pr_err("%s: platform not supported\n", __func__);
		return -ENODEV;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem)
		return -ENOENT;

	mbox_base = ioremap(mem->start, resource_size(mem));
	if (!mbox_base)
		return -ENOMEM;

	ret = omap_mbox_register(&pdev->dev, list);
	if (ret) {
		iounmap(mbox_base);
		return ret;
	}

	return 0;
}

static int omap2_mbox_remove(struct platform_device *pdev)
{
	omap_mbox_unregister();
	iounmap(mbox_base);
	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe = omap2_mbox_probe,
	.remove = omap2_mbox_remove,
	.driver = {
		.name = "omap-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_AUTHOR("Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
a1bcc1dc	13	#include <linux/module.h>
340a614a HD	14	#include <linux/clk.h>
	15	#include <linux/err.h>
	16	#include <linux/platform_device.h>
fced80c7	17	#include <linux/io.h>
82d2a5db	18	#include <linux/pm_runtime.h>
7d7e1eba	19
ce491cf8	20	#include <plat/mailbox.h>
340a614a	21
dbc04161 TL	22	#include "soc.h"
dbc04161 TL	23
733ecc5c	24	#define MAILBOX_REVISION 0x000
733ecc5c HD	25	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	26	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	27	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	28	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	29	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	30
256a4bd7 TL	31	#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
	32	#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
	33	#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
5f00ec64 S	34
	35	#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
	36	#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
340a614a	37
c75ee752	38	#define MBOX_REG_SIZE 0x120
5f00ec64 S	39
	40	#define OMAP4_MBOX_REG_SIZE 0x130
	41
c75ee752	42	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
5f00ec64	43	#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
c75ee752	44
6c20a683	45	static void __iomem *mbox_base;
340a614a HD	46
	47	struct omap_mbox2_fifo {
	48	unsigned long msg;
	49	unsigned long fifo_stat;
	50	unsigned long msg_stat;
	51	};
	52
	53	struct omap_mbox2_priv {
	54	struct omap_mbox2_fifo tx_fifo;
	55	struct omap_mbox2_fifo rx_fifo;
	56	unsigned long irqenable;
	57	unsigned long irqstatus;
	58	u32 newmsg_bit;
	59	u32 notfull_bit;
5f00ec64 S	60	u32 ctx[OMAP4_MBOX_NR_REGS];
5f00ec64 S	61	unsigned long irqdisable;
340a614a HD	62	};
340a614a HD	63
6c20a683	64	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	65	{
6c20a683	66	return __raw_readl(mbox_base + ofs);
340a614a HD	67	}
340a614a HD	68
6c20a683	69	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	70	{
6c20a683	71	__raw_writel(val, mbox_base + ofs);
340a614a HD	72	}
	73
	74	/* Mailbox H/W preparations */
bfbdcf8a	75	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	76	{
1ffe627d	77	u32 l;
340a614a	78
82d2a5db ORL	79	pm_runtime_enable(mbox->dev->parent);
82d2a5db ORL	80	pm_runtime_get_sync(mbox->dev->parent);
1ffe627d	81
94fc58c6	82	l = mbox_read_reg(MAILBOX_REVISION);
909f9dc7	83	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
94fc58c6	84
340a614a HD	85	return 0;
	86	}
	87
bfbdcf8a	88	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a	89	{
82d2a5db ORL	90	pm_runtime_put_sync(mbox->dev->parent);
82d2a5db ORL	91	pm_runtime_disable(mbox->dev->parent);
340a614a HD	92	}
	93
	94	/* Mailbox FIFO handle functions */
bfbdcf8a	95	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	96	{
	97	struct omap_mbox2_fifo *fifo =
	98	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	99	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	100	}
	101
bfbdcf8a	102	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	103	{
	104	struct omap_mbox2_fifo *fifo =
	105	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	106	mbox_write_reg(msg, fifo->msg);
	107	}
	108
bfbdcf8a	109	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	110	{
	111	struct omap_mbox2_fifo *fifo =
	112	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	113	return (mbox_read_reg(fifo->msg_stat) == 0);
	114	}
	115
bfbdcf8a	116	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	117	{
	118	struct omap_mbox2_fifo *fifo =
	119	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
5f00ec64	120	return mbox_read_reg(fifo->fifo_stat);
340a614a HD	121	}
	122
	123	/* Mailbox IRQ handle functions */
f91ca05f	124	static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	125	{
b45b501c	126	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	127	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	128
	129	l = mbox_read_reg(p->irqenable);
	130	l \|= bit;
	131	mbox_write_reg(l, p->irqenable);
	132	}
	133
f91ca05f	134	static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	135	{
b45b501c	136	struct omap_mbox2_priv *p = mbox->priv;
525a1138 HK	137	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	138
	139	if (!cpu_is_omap44xx())
	140	bit = mbox_read_reg(p->irqdisable) & ~bit;
	141
	142	mbox_write_reg(bit, p->irqdisable);
340a614a HD	143	}
340a614a HD	144
f91ca05f	145	static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	146	{
b45b501c	147	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	148	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	149
	150	mbox_write_reg(bit, p->irqstatus);
8828880d HD	151
	152	/* Flush posted write for irq status to avoid spurious interrupts */
	153	mbox_read_reg(p->irqstatus);
340a614a HD	154	}
340a614a HD	155
f91ca05f	156	static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	157	{
b45b501c	158	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	159	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	160	u32 enable = mbox_read_reg(p->irqenable);
	161	u32 status = mbox_read_reg(p->irqstatus);
	162
5f00ec64	163	return (int)(enable & status & bit);
340a614a HD	164	}
340a614a HD	165
c75ee752 HD	166	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	167	{
	168	int i;
	169	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	170	int nr_regs;
	171	if (cpu_is_omap44xx())
	172	nr_regs = OMAP4_MBOX_NR_REGS;
	173	else
	174	nr_regs = MBOX_NR_REGS;
	175	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	176	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	177
	178	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	179	i, p->ctx[i]);
	180	}
	181	}
	182
	183	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	184	{
	185	int i;
	186	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64 S	187	int nr_regs;
	188	if (cpu_is_omap44xx())
	189	nr_regs = OMAP4_MBOX_NR_REGS;
	190	else
	191	nr_regs = MBOX_NR_REGS;
	192	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	193	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	194
	195	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	196	i, p->ctx[i]);
	197	}
	198	}
	199
340a614a HD	200	static struct omap_mbox_ops omap2_mbox_ops = {
	201	.type = OMAP_MBOX_TYPE2,
	202	.startup = omap2_mbox_startup,
	203	.shutdown = omap2_mbox_shutdown,
	204	.fifo_read = omap2_mbox_fifo_read,
	205	.fifo_write = omap2_mbox_fifo_write,
	206	.fifo_empty = omap2_mbox_fifo_empty,
	207	.fifo_full = omap2_mbox_fifo_full,
	208	.enable_irq = omap2_mbox_enable_irq,
	209	.disable_irq = omap2_mbox_disable_irq,
	210	.ack_irq = omap2_mbox_ack_irq,
	211	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	212	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	213	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	214	};
	215
	216	/*
	217	* MAILBOX 0: ARM -> DSP,
	218	* MAILBOX 1: ARM <- DSP.
	219	* MAILBOX 2: ARM -> IVA,
	220	* MAILBOX 3: ARM <- IVA.
	221	*/
	222
	223	/* FIXME: the following structs should be filled automatically by the user id */
07d65d8b	224
ff0fba0b	225	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP2)
340a614a HD	226	/* DSP */
	227	static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
	228	.tx_fifo = {
733ecc5c HD	229	.msg = MAILBOX_MESSAGE(0),
733ecc5c HD	230	.fifo_stat = MAILBOX_FIFOSTATUS(0),
340a614a HD	231	},
340a614a HD	232	.rx_fifo = {
733ecc5c HD	233	.msg = MAILBOX_MESSAGE(1),
733ecc5c HD	234	.msg_stat = MAILBOX_MSGSTATUS(1),
340a614a	235	},
733ecc5c HD	236	.irqenable = MAILBOX_IRQENABLE(0),
733ecc5c HD	237	.irqstatus = MAILBOX_IRQSTATUS(0),
340a614a HD	238	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
340a614a HD	239	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
5f00ec64 S	240	.irqdisable = MAILBOX_IRQENABLE(0),
	241	};
	242
07d65d8b FC	243	struct omap_mbox mbox_dsp_info = {
	244	.name = "dsp",
	245	.ops = &omap2_mbox_ops,
	246	.priv = &omap2_mbox_dsp_priv,
	247	};
14476bd9	248	#endif
07d65d8b	249
ff0fba0b	250	#if defined(CONFIG_ARCH_OMAP3)
898ee756	251	struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
14476bd9	252	#endif
898ee756	253
59b479e0	254	#if defined(CONFIG_SOC_OMAP2420)
07d65d8b FC	255	/* IVA */
	256	static struct omap_mbox2_priv omap2_mbox_iva_priv = {
	257	.tx_fifo = {
	258	.msg = MAILBOX_MESSAGE(2),
	259	.fifo_stat = MAILBOX_FIFOSTATUS(2),
	260	},
	261	.rx_fifo = {
	262	.msg = MAILBOX_MESSAGE(3),
	263	.msg_stat = MAILBOX_MSGSTATUS(3),
	264	},
	265	.irqenable = MAILBOX_IRQENABLE(3),
	266	.irqstatus = MAILBOX_IRQSTATUS(3),
	267	.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
	268	.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
	269	.irqdisable = MAILBOX_IRQENABLE(3),
	270	};
	271
	272	static struct omap_mbox mbox_iva_info = {
	273	.name = "iva",
	274	.ops = &omap2_mbox_ops,
	275	.priv = &omap2_mbox_iva_priv,
	276	};
655850ed	277	#endif
898ee756	278
655850ed OBC	279	#ifdef CONFIG_ARCH_OMAP2
	280	struct omap_mbox *omap2_mboxes[] = {
	281	&mbox_dsp_info,
	282	#ifdef CONFIG_SOC_OMAP2420
	283	&mbox_iva_info,
	284	#endif
	285	NULL
	286	};
07d65d8b FC	287	#endif
07d65d8b FC	288
14476bd9	289	#if defined(CONFIG_ARCH_OMAP4)
07d65d8b	290	/* OMAP4 */
5f00ec64 S	291	static struct omap_mbox2_priv omap2_mbox_1_priv = {
	292	.tx_fifo = {
	293	.msg = MAILBOX_MESSAGE(0),
	294	.fifo_stat = MAILBOX_FIFOSTATUS(0),
	295	},
	296	.rx_fifo = {
	297	.msg = MAILBOX_MESSAGE(1),
	298	.msg_stat = MAILBOX_MSGSTATUS(1),
	299	},
	300	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	301	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	302	.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
	303	.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
	304	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
340a614a HD	305	};
340a614a HD	306
5f00ec64 S	307	struct omap_mbox mbox_1_info = {
	308	.name = "mailbox-1",
	309	.ops = &omap2_mbox_ops,
	310	.priv = &omap2_mbox_1_priv,
	311	};
5f00ec64	312
5f00ec64 S	313	static struct omap_mbox2_priv omap2_mbox_2_priv = {
	314	.tx_fifo = {
	315	.msg = MAILBOX_MESSAGE(3),
	316	.fifo_stat = MAILBOX_FIFOSTATUS(3),
	317	},
	318	.rx_fifo = {
	319	.msg = MAILBOX_MESSAGE(2),
	320	.msg_stat = MAILBOX_MSGSTATUS(2),
	321	},
	322	.irqenable = OMAP4_MAILBOX_IRQENABLE(0),
	323	.irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
	324	.notfull_bit = MAILBOX_IRQ_NOTFULL(3),
	325	.newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
	326	.irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
	327	};
	328
	329	struct omap_mbox mbox_2_info = {
	330	.name = "mailbox-2",
	331	.ops = &omap2_mbox_ops,
	332	.priv = &omap2_mbox_2_priv,
	333	};
5f00ec64	334
898ee756	335	struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
14476bd9	336	#endif
898ee756	337
351a102d	338	static int omap2_mbox_probe(struct platform_device *pdev)
340a614a	339	{
898ee756	340	struct resource *mem;
6c20a683	341	int ret;
9c80c8cd	342	struct omap_mbox **list;
340a614a	343
14476bd9 FC	344	if (false)
14476bd9 FC	345	;
ff0fba0b ORL	346	#if defined(CONFIG_ARCH_OMAP3)
ff0fba0b ORL	347	else if (cpu_is_omap34xx()) {
898ee756 FC	348	list = omap3_mboxes;
898ee756 FC	349
69dbf857	350	list[0]->irq = platform_get_irq(pdev, 0);
340a614a	351	}
14476bd9	352	#endif
ff0fba0b ORL	353	#if defined(CONFIG_ARCH_OMAP2)
	354	else if (cpu_is_omap2430()) {
	355	list = omap2_mboxes;
	356
69dbf857	357	list[0]->irq = platform_get_irq(pdev, 0);
ff0fba0b	358	} else if (cpu_is_omap2420()) {
898ee756	359	list = omap2_mboxes;
340a614a	360
898ee756 FC	361	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
	362	list[1]->irq = platform_get_irq_byname(pdev, "iva");
	363	}
	364	#endif
14476bd9	365	#if defined(CONFIG_ARCH_OMAP4)
898ee756 FC	366	else if (cpu_is_omap44xx()) {
898ee756 FC	367	list = omap4_mboxes;
5f00ec64	368
69dbf857	369	list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
340a614a	370	}
14476bd9	371	#endif
898ee756 FC	372	else {
	373	pr_err("%s: platform not supported\n", __func__);
	374	return -ENODEV;
5f00ec64	375	}
6c20a683	376
898ee756	377	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a41677c6 SA	378	if (!mem)
	379	return -ENOENT;
	380
898ee756 FC	381	mbox_base = ioremap(mem->start, resource_size(mem));
	382	if (!mbox_base)
	383	return -ENOMEM;
	384
9c80c8cd FC	385	ret = omap_mbox_register(&pdev->dev, list);
	386	if (ret) {
	387	iounmap(mbox_base);
	388	return ret;
340a614a	389	}
340a614a	390
5d783731	391	return 0;
340a614a HD	392	}
340a614a HD	393
351a102d	394	static int omap2_mbox_remove(struct platform_device *pdev)
340a614a	395	{
9c80c8cd	396	omap_mbox_unregister();
6c20a683	397	iounmap(mbox_base);
340a614a HD	398	return 0;
	399	}
	400
	401	static struct platform_driver omap2_mbox_driver = {
	402	.probe = omap2_mbox_probe,
351a102d	403	.remove = omap2_mbox_remove,
340a614a	404	.driver = {
d742709e	405	.name = "omap-mailbox",
340a614a HD	406	},
	407	};
	408
	409	static int __init omap2_mbox_init(void)
	410	{
	411	return platform_driver_register(&omap2_mbox_driver);
	412	}
	413
	414	static void __exit omap2_mbox_exit(void)
	415	{
	416	platform_driver_unregister(&omap2_mbox_driver);
	417	}
	418
134d12fa	419	module_init(omap2_mbox_init);
340a614a HD	420	module_exit(omap2_mbox_exit);
340a614a HD	421
733ecc5c	422	MODULE_LICENSE("GPL v2");
5f00ec64	423	MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
f375325a OBC	424	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
f375325a OBC	425	MODULE_AUTHOR("Paul Mundt");
d742709e	426	MODULE_ALIAS("platform:omap2-mailbox");