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Commit | Line | Data |
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fcf6efa3 SS |
1 | /* |
2 | * OMAP WakeupGen Source file | |
3 | * | |
4 | * OMAP WakeupGen is the interrupt controller extension used along | |
5 | * with ARM GIC to wake the CPU out from low power states on | |
6 | * external interrupts. It is responsible for generating wakeup | |
7 | * event from the incoming interrupts and enable bits. It is | |
8 | * implemented in MPU always ON power domain. During normal operation, | |
9 | * WakeupGen delivers external interrupts directly to the GIC. | |
10 | * | |
11 | * Copyright (C) 2011 Texas Instruments, Inc. | |
12 | * Santosh Shilimkar <santosh.shilimkar@ti.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/irq.h> | |
0cc09e85 | 23 | #include <linux/irqchip.h> |
7136d457 MZ |
24 | #include <linux/irqdomain.h> |
25 | #include <linux/of_address.h> | |
fcf6efa3 SS |
26 | #include <linux/platform_device.h> |
27 | #include <linux/cpu.h> | |
0f3cf2ec SS |
28 | #include <linux/notifier.h> |
29 | #include <linux/cpu_pm.h> | |
fcf6efa3 | 30 | |
732231a7 | 31 | #include "omap-wakeupgen.h" |
c1db9d73 | 32 | #include "omap-secure.h" |
0f3cf2ec | 33 | |
dbc04161 | 34 | #include "soc.h" |
0f3cf2ec SS |
35 | #include "omap4-sar-layout.h" |
36 | #include "common.h" | |
6099dd37 | 37 | #include "pm.h" |
fcf6efa3 | 38 | |
6246cd06 AM |
39 | #define AM43XX_NR_REG_BANKS 7 |
40 | #define AM43XX_IRQS 224 | |
41 | #define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS | |
42 | #define MAX_IRQS AM43XX_IRQS | |
43 | #define DEFAULT_NR_REG_BANKS 5 | |
44 | #define DEFAULT_IRQS 160 | |
fcf6efa3 SS |
45 | #define WKG_MASK_ALL 0x00000000 |
46 | #define WKG_UNMASK_ALL 0xffffffff | |
47 | #define CPU_ENA_OFFSET 0x400 | |
48 | #define CPU0_ID 0x0 | |
49 | #define CPU1_ID 0x1 | |
247c445c SS |
50 | #define OMAP4_NR_BANKS 4 |
51 | #define OMAP4_NR_IRQS 128 | |
fcf6efa3 SS |
52 | |
53 | static void __iomem *wakeupgen_base; | |
0f3cf2ec | 54 | static void __iomem *sar_base; |
aecb9e14 | 55 | static DEFINE_RAW_SPINLOCK(wakeupgen_lock); |
e534e871 | 56 | static unsigned int irq_target_cpu[MAX_IRQS]; |
6246cd06 AM |
57 | static unsigned int irq_banks = DEFAULT_NR_REG_BANKS; |
58 | static unsigned int max_irqs = DEFAULT_IRQS; | |
247c445c | 59 | static unsigned int omap_secure_apis; |
fcf6efa3 SS |
60 | |
61 | /* | |
62 | * Static helper functions. | |
63 | */ | |
64 | static inline u32 wakeupgen_readl(u8 idx, u32 cpu) | |
65 | { | |
edfaf05c | 66 | return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 + |
fcf6efa3 SS |
67 | (cpu * CPU_ENA_OFFSET) + (idx * 4)); |
68 | } | |
69 | ||
70 | static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu) | |
71 | { | |
edfaf05c | 72 | writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 + |
fcf6efa3 SS |
73 | (cpu * CPU_ENA_OFFSET) + (idx * 4)); |
74 | } | |
75 | ||
0f3cf2ec SS |
76 | static inline void sar_writel(u32 val, u32 offset, u8 idx) |
77 | { | |
edfaf05c | 78 | writel_relaxed(val, sar_base + offset + (idx * 4)); |
0f3cf2ec SS |
79 | } |
80 | ||
fcf6efa3 SS |
81 | static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index) |
82 | { | |
fcf6efa3 SS |
83 | /* |
84 | * Each WakeupGen register controls 32 interrupt. | |
85 | * i.e. 1 bit per SPI IRQ | |
86 | */ | |
7136d457 MZ |
87 | *reg_index = irq >> 5; |
88 | *bit_posn = irq %= 32; | |
fcf6efa3 SS |
89 | |
90 | return 0; | |
91 | } | |
92 | ||
93 | static void _wakeupgen_clear(unsigned int irq, unsigned int cpu) | |
94 | { | |
95 | u32 val, bit_number; | |
96 | u8 i; | |
97 | ||
98 | if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) | |
99 | return; | |
100 | ||
101 | val = wakeupgen_readl(i, cpu); | |
102 | val &= ~BIT(bit_number); | |
103 | wakeupgen_writel(val, i, cpu); | |
104 | } | |
105 | ||
106 | static void _wakeupgen_set(unsigned int irq, unsigned int cpu) | |
107 | { | |
108 | u32 val, bit_number; | |
109 | u8 i; | |
110 | ||
111 | if (_wakeupgen_get_irq_info(irq, &bit_number, &i)) | |
112 | return; | |
113 | ||
114 | val = wakeupgen_readl(i, cpu); | |
115 | val |= BIT(bit_number); | |
116 | wakeupgen_writel(val, i, cpu); | |
117 | } | |
118 | ||
fcf6efa3 SS |
119 | /* |
120 | * Architecture specific Mask extension | |
121 | */ | |
122 | static void wakeupgen_mask(struct irq_data *d) | |
123 | { | |
124 | unsigned long flags; | |
125 | ||
aecb9e14 | 126 | raw_spin_lock_irqsave(&wakeupgen_lock, flags); |
1cc4b1a9 | 127 | _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]); |
aecb9e14 | 128 | raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); |
7136d457 | 129 | irq_chip_mask_parent(d); |
fcf6efa3 SS |
130 | } |
131 | ||
132 | /* | |
133 | * Architecture specific Unmask extension | |
134 | */ | |
135 | static void wakeupgen_unmask(struct irq_data *d) | |
136 | { | |
137 | unsigned long flags; | |
138 | ||
aecb9e14 | 139 | raw_spin_lock_irqsave(&wakeupgen_lock, flags); |
1cc4b1a9 | 140 | _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]); |
aecb9e14 | 141 | raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); |
7136d457 | 142 | irq_chip_unmask_parent(d); |
fcf6efa3 SS |
143 | } |
144 | ||
bb1dbe7c | 145 | #ifdef CONFIG_HOTPLUG_CPU |
247c445c | 146 | static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks); |
bb1dbe7c KH |
147 | |
148 | static void _wakeupgen_save_masks(unsigned int cpu) | |
149 | { | |
150 | u8 i; | |
151 | ||
247c445c | 152 | for (i = 0; i < irq_banks; i++) |
bb1dbe7c KH |
153 | per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu); |
154 | } | |
155 | ||
156 | static void _wakeupgen_restore_masks(unsigned int cpu) | |
157 | { | |
158 | u8 i; | |
159 | ||
247c445c | 160 | for (i = 0; i < irq_banks; i++) |
bb1dbe7c KH |
161 | wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu); |
162 | } | |
163 | ||
164 | static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg) | |
165 | { | |
166 | u8 i; | |
167 | ||
247c445c | 168 | for (i = 0; i < irq_banks; i++) |
bb1dbe7c KH |
169 | wakeupgen_writel(reg, i, cpu); |
170 | } | |
171 | ||
fcf6efa3 SS |
172 | /* |
173 | * Mask or unmask all interrupts on given CPU. | |
174 | * 0 = Mask all interrupts on the 'cpu' | |
175 | * 1 = Unmask all interrupts on the 'cpu' | |
176 | * Ensure that the initial mask is maintained. This is faster than | |
177 | * iterating through GIC registers to arrive at the correct masks. | |
178 | */ | |
179 | static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set) | |
180 | { | |
181 | unsigned long flags; | |
182 | ||
aecb9e14 | 183 | raw_spin_lock_irqsave(&wakeupgen_lock, flags); |
fcf6efa3 SS |
184 | if (set) { |
185 | _wakeupgen_save_masks(cpu); | |
186 | _wakeupgen_set_all(cpu, WKG_MASK_ALL); | |
187 | } else { | |
188 | _wakeupgen_set_all(cpu, WKG_UNMASK_ALL); | |
189 | _wakeupgen_restore_masks(cpu); | |
190 | } | |
aecb9e14 | 191 | raw_spin_unlock_irqrestore(&wakeupgen_lock, flags); |
fcf6efa3 | 192 | } |
bb1dbe7c | 193 | #endif |
fcf6efa3 | 194 | |
0f3cf2ec | 195 | #ifdef CONFIG_CPU_PM |
247c445c | 196 | static inline void omap4_irq_save_context(void) |
0f3cf2ec SS |
197 | { |
198 | u32 i, val; | |
199 | ||
200 | if (omap_rev() == OMAP4430_REV_ES1_0) | |
201 | return; | |
202 | ||
247c445c | 203 | for (i = 0; i < irq_banks; i++) { |
0f3cf2ec SS |
204 | /* Save the CPUx interrupt mask for IRQ 0 to 127 */ |
205 | val = wakeupgen_readl(i, 0); | |
206 | sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i); | |
207 | val = wakeupgen_readl(i, 1); | |
208 | sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i); | |
209 | ||
210 | /* | |
211 | * Disable the secure interrupts for CPUx. The restore | |
212 | * code blindly restores secure and non-secure interrupt | |
213 | * masks from SAR RAM. Secure interrupts are not suppose | |
214 | * to be enabled from HLOS. So overwrite the SAR location | |
215 | * so that the secure interrupt remains disabled. | |
216 | */ | |
217 | sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i); | |
218 | sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i); | |
219 | } | |
220 | ||
221 | /* Save AuxBoot* registers */ | |
edfaf05c VK |
222 | val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
223 | writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); | |
224 | val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); | |
225 | writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); | |
0f3cf2ec | 226 | |
0f3cf2ec | 227 | /* Save SyncReq generation logic */ |
edfaf05c VK |
228 | val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); |
229 | writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); | |
230 | val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); | |
231 | writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); | |
0f3cf2ec SS |
232 | |
233 | /* Set the Backup Bit Mask status */ | |
edfaf05c | 234 | val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); |
0f3cf2ec | 235 | val |= SAR_BACKUP_STATUS_WAKEUPGEN; |
edfaf05c | 236 | writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); |
247c445c SS |
237 | |
238 | } | |
239 | ||
240 | static inline void omap5_irq_save_context(void) | |
241 | { | |
242 | u32 i, val; | |
243 | ||
244 | for (i = 0; i < irq_banks; i++) { | |
245 | /* Save the CPUx interrupt mask for IRQ 0 to 159 */ | |
246 | val = wakeupgen_readl(i, 0); | |
247 | sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i); | |
248 | val = wakeupgen_readl(i, 1); | |
249 | sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i); | |
250 | sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i); | |
251 | sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i); | |
252 | } | |
253 | ||
254 | /* Save AuxBoot* registers */ | |
edfaf05c VK |
255 | val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); |
256 | writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); | |
257 | val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); | |
258 | writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); | |
247c445c SS |
259 | |
260 | /* Set the Backup Bit Mask status */ | |
edfaf05c | 261 | val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); |
247c445c | 262 | val |= SAR_BACKUP_STATUS_WAKEUPGEN; |
edfaf05c | 263 | writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); |
247c445c SS |
264 | |
265 | } | |
266 | ||
267 | /* | |
268 | * Save WakeupGen interrupt context in SAR BANK3. Restore is done by | |
269 | * ROM code. WakeupGen IP is integrated along with GIC to manage the | |
270 | * interrupt wakeups from CPU low power states. It manages | |
271 | * masking/unmasking of Shared peripheral interrupts(SPI). So the | |
272 | * interrupt enable/disable control should be in sync and consistent | |
273 | * at WakeupGen and GIC so that interrupts are not lost. | |
274 | */ | |
275 | static void irq_save_context(void) | |
276 | { | |
c783e6fd NM |
277 | /* DRA7 has no SAR to save */ |
278 | if (soc_is_dra7xx()) | |
279 | return; | |
280 | ||
247c445c SS |
281 | if (!sar_base) |
282 | sar_base = omap4_get_sar_ram_base(); | |
283 | ||
284 | if (soc_is_omap54xx()) | |
285 | omap5_irq_save_context(); | |
286 | else | |
287 | omap4_irq_save_context(); | |
0f3cf2ec SS |
288 | } |
289 | ||
290 | /* | |
291 | * Clear WakeupGen SAR backup status. | |
292 | */ | |
8c3d4534 | 293 | static void irq_sar_clear(void) |
0f3cf2ec SS |
294 | { |
295 | u32 val; | |
247c445c | 296 | u32 offset = SAR_BACKUP_STATUS_OFFSET; |
c783e6fd NM |
297 | /* DRA7 has no SAR to save */ |
298 | if (soc_is_dra7xx()) | |
299 | return; | |
247c445c SS |
300 | |
301 | if (soc_is_omap54xx()) | |
302 | offset = OMAP5_SAR_BACKUP_STATUS_OFFSET; | |
303 | ||
edfaf05c | 304 | val = readl_relaxed(sar_base + offset); |
0f3cf2ec | 305 | val &= ~SAR_BACKUP_STATUS_WAKEUPGEN; |
edfaf05c | 306 | writel_relaxed(val, sar_base + offset); |
0f3cf2ec SS |
307 | } |
308 | ||
309 | /* | |
310 | * Save GIC and Wakeupgen interrupt context using secure API | |
311 | * for HS/EMU devices. | |
312 | */ | |
313 | static void irq_save_secure_context(void) | |
314 | { | |
315 | u32 ret; | |
316 | ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX, | |
317 | FLAG_START_CRITICAL, | |
318 | 0, 0, 0, 0, 0); | |
319 | if (ret != API_HAL_RET_VALUE_OK) | |
320 | pr_err("GIC and Wakeupgen context save failed\n"); | |
321 | } | |
322 | #endif | |
323 | ||
b5b4f288 | 324 | #ifdef CONFIG_HOTPLUG_CPU |
8bd26e3a PG |
325 | static int irq_cpu_hotplug_notify(struct notifier_block *self, |
326 | unsigned long action, void *hcpu) | |
b5b4f288 SS |
327 | { |
328 | unsigned int cpu = (unsigned int)hcpu; | |
329 | ||
330 | switch (action) { | |
331 | case CPU_ONLINE: | |
332 | wakeupgen_irqmask_all(cpu, 0); | |
333 | break; | |
334 | case CPU_DEAD: | |
335 | wakeupgen_irqmask_all(cpu, 1); | |
336 | break; | |
337 | } | |
338 | return NOTIFY_OK; | |
339 | } | |
340 | ||
b96fc2f3 | 341 | static struct notifier_block irq_hotplug_notifier = { |
b5b4f288 SS |
342 | .notifier_call = irq_cpu_hotplug_notify, |
343 | }; | |
344 | ||
345 | static void __init irq_hotplug_init(void) | |
346 | { | |
347 | register_hotcpu_notifier(&irq_hotplug_notifier); | |
348 | } | |
349 | #else | |
350 | static void __init irq_hotplug_init(void) | |
351 | {} | |
352 | #endif | |
353 | ||
0f3cf2ec SS |
354 | #ifdef CONFIG_CPU_PM |
355 | static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
356 | { | |
357 | switch (cmd) { | |
358 | case CPU_CLUSTER_PM_ENTER: | |
359 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) | |
360 | irq_save_context(); | |
361 | else | |
362 | irq_save_secure_context(); | |
363 | break; | |
364 | case CPU_CLUSTER_PM_EXIT: | |
365 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) | |
366 | irq_sar_clear(); | |
367 | break; | |
368 | } | |
369 | return NOTIFY_OK; | |
370 | } | |
371 | ||
372 | static struct notifier_block irq_notifier_block = { | |
373 | .notifier_call = irq_notifier, | |
374 | }; | |
375 | ||
376 | static void __init irq_pm_init(void) | |
377 | { | |
247c445c | 378 | /* FIXME: Remove this when MPU OSWR support is added */ |
6099dd37 | 379 | if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) |
247c445c | 380 | cpu_pm_register_notifier(&irq_notifier_block); |
0f3cf2ec SS |
381 | } |
382 | #else | |
383 | static void __init irq_pm_init(void) | |
384 | {} | |
385 | #endif | |
386 | ||
247c445c SS |
387 | void __iomem *omap_get_wakeupgen_base(void) |
388 | { | |
389 | return wakeupgen_base; | |
390 | } | |
391 | ||
392 | int omap_secure_apis_support(void) | |
393 | { | |
394 | return omap_secure_apis; | |
395 | } | |
396 | ||
7136d457 MZ |
397 | static struct irq_chip wakeupgen_chip = { |
398 | .name = "WUGEN", | |
399 | .irq_eoi = irq_chip_eoi_parent, | |
400 | .irq_mask = wakeupgen_mask, | |
401 | .irq_unmask = wakeupgen_unmask, | |
402 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
63059a27 | 403 | .irq_set_type = irq_chip_set_type_parent, |
7136d457 MZ |
404 | .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND, |
405 | #ifdef CONFIG_SMP | |
406 | .irq_set_affinity = irq_chip_set_affinity_parent, | |
407 | #endif | |
408 | }; | |
409 | ||
f833f57f MZ |
410 | static int wakeupgen_domain_translate(struct irq_domain *d, |
411 | struct irq_fwspec *fwspec, | |
412 | unsigned long *hwirq, | |
413 | unsigned int *type) | |
7136d457 | 414 | { |
f833f57f MZ |
415 | if (is_of_node(fwspec->fwnode)) { |
416 | if (fwspec->param_count != 3) | |
417 | return -EINVAL; | |
7136d457 | 418 | |
f833f57f MZ |
419 | /* No PPI should point to this domain */ |
420 | if (fwspec->param[0] != 0) | |
421 | return -EINVAL; | |
422 | ||
423 | *hwirq = fwspec->param[1]; | |
424 | *type = fwspec->param[2]; | |
425 | return 0; | |
426 | } | |
427 | ||
428 | return -EINVAL; | |
7136d457 MZ |
429 | } |
430 | ||
431 | static int wakeupgen_domain_alloc(struct irq_domain *domain, | |
432 | unsigned int virq, | |
433 | unsigned int nr_irqs, void *data) | |
434 | { | |
f833f57f MZ |
435 | struct irq_fwspec *fwspec = data; |
436 | struct irq_fwspec parent_fwspec; | |
7136d457 MZ |
437 | irq_hw_number_t hwirq; |
438 | int i; | |
439 | ||
f833f57f | 440 | if (fwspec->param_count != 3) |
7136d457 | 441 | return -EINVAL; /* Not GIC compliant */ |
f833f57f | 442 | if (fwspec->param[0] != 0) |
7136d457 MZ |
443 | return -EINVAL; /* No PPI should point to this domain */ |
444 | ||
f833f57f | 445 | hwirq = fwspec->param[1]; |
7136d457 MZ |
446 | if (hwirq >= MAX_IRQS) |
447 | return -EINVAL; /* Can't deal with this */ | |
448 | ||
449 | for (i = 0; i < nr_irqs; i++) | |
450 | irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, | |
451 | &wakeupgen_chip, NULL); | |
452 | ||
f833f57f MZ |
453 | parent_fwspec = *fwspec; |
454 | parent_fwspec.fwnode = domain->parent->fwnode; | |
455 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, | |
456 | &parent_fwspec); | |
7136d457 MZ |
457 | } |
458 | ||
8297955f | 459 | static const struct irq_domain_ops wakeupgen_domain_ops = { |
f833f57f MZ |
460 | .translate = wakeupgen_domain_translate, |
461 | .alloc = wakeupgen_domain_alloc, | |
462 | .free = irq_domain_free_irqs_common, | |
7136d457 MZ |
463 | }; |
464 | ||
fcf6efa3 SS |
465 | /* |
466 | * Initialise the wakeupgen module. | |
467 | */ | |
7136d457 MZ |
468 | static int __init wakeupgen_init(struct device_node *node, |
469 | struct device_node *parent) | |
fcf6efa3 | 470 | { |
7136d457 | 471 | struct irq_domain *parent_domain, *domain; |
fcf6efa3 SS |
472 | int i; |
473 | unsigned int boot_cpu = smp_processor_id(); | |
4664d4d8 | 474 | u32 val; |
fcf6efa3 | 475 | |
7136d457 MZ |
476 | if (!parent) { |
477 | pr_err("%s: no parent, giving up\n", node->full_name); | |
478 | return -ENODEV; | |
479 | } | |
480 | ||
481 | parent_domain = irq_find_host(parent); | |
482 | if (!parent_domain) { | |
483 | pr_err("%s: unable to obtain parent domain\n", node->full_name); | |
484 | return -ENXIO; | |
485 | } | |
fcf6efa3 SS |
486 | /* Not supported on OMAP4 ES1.0 silicon */ |
487 | if (omap_rev() == OMAP4430_REV_ES1_0) { | |
488 | WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n"); | |
489 | return -EPERM; | |
490 | } | |
491 | ||
492 | /* Static mapping, never released */ | |
7136d457 | 493 | wakeupgen_base = of_iomap(node, 0); |
fcf6efa3 SS |
494 | if (WARN_ON(!wakeupgen_base)) |
495 | return -ENOMEM; | |
496 | ||
247c445c SS |
497 | if (cpu_is_omap44xx()) { |
498 | irq_banks = OMAP4_NR_BANKS; | |
499 | max_irqs = OMAP4_NR_IRQS; | |
500 | omap_secure_apis = 1; | |
6246cd06 AM |
501 | } else if (soc_is_am43xx()) { |
502 | irq_banks = AM43XX_NR_REG_BANKS; | |
503 | max_irqs = AM43XX_IRQS; | |
247c445c SS |
504 | } |
505 | ||
7136d457 MZ |
506 | domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs, |
507 | node, &wakeupgen_domain_ops, | |
508 | NULL); | |
509 | if (!domain) { | |
510 | iounmap(wakeupgen_base); | |
511 | return -ENOMEM; | |
512 | } | |
513 | ||
fcf6efa3 | 514 | /* Clear all IRQ bitmasks at wakeupGen level */ |
247c445c | 515 | for (i = 0; i < irq_banks; i++) { |
fcf6efa3 | 516 | wakeupgen_writel(0, i, CPU0_ID); |
6246cd06 AM |
517 | if (!soc_is_am43xx()) |
518 | wakeupgen_writel(0, i, CPU1_ID); | |
fcf6efa3 SS |
519 | } |
520 | ||
fcf6efa3 SS |
521 | /* |
522 | * FIXME: Add support to set_smp_affinity() once the core | |
523 | * GIC code has necessary hooks in place. | |
524 | */ | |
525 | ||
526 | /* Associate all the IRQs to boot CPU like GIC init does. */ | |
247c445c | 527 | for (i = 0; i < max_irqs; i++) |
fcf6efa3 SS |
528 | irq_target_cpu[i] = boot_cpu; |
529 | ||
4664d4d8 SS |
530 | /* |
531 | * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE | |
532 | * 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together. | |
533 | * 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode | |
534 | * independently. | |
535 | * This needs to be set one time thanks to always ON domain. | |
536 | * | |
537 | * We do not support ES1 behavior anymore. OMAP5 is assumed to be | |
538 | * ES2.0, and the same is applicable for DRA7. | |
539 | */ | |
540 | if (soc_is_omap54xx() || soc_is_dra7xx()) { | |
541 | val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE); | |
542 | val |= BIT(5); | |
543 | omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val); | |
544 | } | |
545 | ||
b5b4f288 | 546 | irq_hotplug_init(); |
0f3cf2ec | 547 | irq_pm_init(); |
b5b4f288 | 548 | |
fcf6efa3 SS |
549 | return 0; |
550 | } | |
0cc09e85 | 551 | IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init); |