[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / omap-wakeupgen.c

/*
 * OMAP WakeupGen Source file
 *
 * OMAP WakeupGen is the interrupt controller extension used along
 * with ARM GIC to wake the CPU out from low power states on
 * external interrupts. It is responsible for generating wakeup
 * event from the incoming interrupts and enable bits. It is
 * implemented in MPU always ON power domain. During normal operation,
 * WakeupGen delivers external interrupts directly to the GIC.
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
#include <linux/notifier.h>
#include <linux/cpu_pm.h>

#include "omap-wakeupgen.h"
#include "omap-secure.h"

#include "soc.h"
#include "omap4-sar-layout.h"
#include "common.h"
#include "pm.h"

#define AM43XX_NR_REG_BANKS	7
#define AM43XX_IRQS		224
#define MAX_NR_REG_BANKS	AM43XX_NR_REG_BANKS
#define MAX_IRQS		AM43XX_IRQS
#define DEFAULT_NR_REG_BANKS	5
#define DEFAULT_IRQS		160
#define WKG_MASK_ALL		0x00000000
#define WKG_UNMASK_ALL		0xffffffff
#define CPU_ENA_OFFSET		0x400
#define CPU0_ID			0x0
#define CPU1_ID			0x1
#define OMAP4_NR_BANKS		4
#define OMAP4_NR_IRQS		128

static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
static unsigned int max_irqs = DEFAULT_IRQS;
static unsigned int omap_secure_apis;

/*
 * Static helper functions.
 */
static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
{
	return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
				(cpu * CPU_ENA_OFFSET) + (idx * 4));
}

static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
{
	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
				(cpu * CPU_ENA_OFFSET) + (idx * 4));
}

static inline void sar_writel(u32 val, u32 offset, u8 idx)
{
	writel_relaxed(val, sar_base + offset + (idx * 4));
}

static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
{
	/*
	 * Each WakeupGen register controls 32 interrupt.
	 * i.e. 1 bit per SPI IRQ
	 */
	*reg_index = irq >> 5;
	*bit_posn = irq %= 32;

	return 0;
}

static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
{
	u32 val, bit_number;
	u8 i;

	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
		return;

	val = wakeupgen_readl(i, cpu);
	val &= ~BIT(bit_number);
	wakeupgen_writel(val, i, cpu);
}

static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
{
	u32 val, bit_number;
	u8 i;

	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
		return;

	val = wakeupgen_readl(i, cpu);
	val |= BIT(bit_number);
	wakeupgen_writel(val, i, cpu);
}

/*
 * Architecture specific Mask extension
 */
static void wakeupgen_mask(struct irq_data *d)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
	irq_chip_mask_parent(d);
}

/*
 * Architecture specific Unmask extension
 */
static void wakeupgen_unmask(struct irq_data *d)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
	irq_chip_unmask_parent(d);
}

#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);

static void _wakeupgen_save_masks(unsigned int cpu)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}

static void _wakeupgen_restore_masks(unsigned int cpu)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}

static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		wakeupgen_writel(reg, i, cpu);
}

/*
 * Mask or unmask all interrupts on given CPU.
 *	0 = Mask all interrupts on the 'cpu'
 *	1 = Unmask all interrupts on the 'cpu'
 * Ensure that the initial mask is maintained. This is faster than
 * iterating through GIC registers to arrive at the correct masks.
 */
static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	if (set) {
		_wakeupgen_save_masks(cpu);
		_wakeupgen_set_all(cpu, WKG_MASK_ALL);
	} else {
		_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
		_wakeupgen_restore_masks(cpu);
	}
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#endif

#ifdef CONFIG_CPU_PM
static inline void omap4_irq_save_context(void)
{
	u32 i, val;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return;

	for (i = 0; i < irq_banks; i++) {
		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);

		/*
		 * Disable the secure interrupts for CPUx. The restore
		 * code blindly restores secure and non-secure interrupt
		 * masks from SAR RAM. Secure interrupts are not suppose
		 * to be enabled from HLOS. So overwrite the SAR location
		 * so that the secure interrupt remains disabled.
		 */
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/* Save AuxBoot* registers */
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);

	/* Save SyncReq generation logic */
	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);

	/* Set the Backup Bit Mask status */
	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);

}

static inline void omap5_irq_save_context(void)
{
	u32 i, val;

	for (i = 0; i < irq_banks; i++) {
		/* Save the CPUx interrupt mask for IRQ 0 to 159 */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/* Save AuxBoot* registers */
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);

	/* Set the Backup Bit Mask status */
	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);

}

/*
 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
 * ROM code. WakeupGen IP is integrated along with GIC to manage the
 * interrupt wakeups from CPU low power states. It manages
 * masking/unmasking of Shared peripheral interrupts(SPI). So the
 * interrupt enable/disable control should be in sync and consistent
 * at WakeupGen and GIC so that interrupts are not lost.
 */
static void irq_save_context(void)
{
	if (!sar_base)
		sar_base = omap4_get_sar_ram_base();

	if (soc_is_omap54xx())
		omap5_irq_save_context();
	else
		omap4_irq_save_context();
}

/*
 * Clear WakeupGen SAR backup status.
 */
static void irq_sar_clear(void)
{
	u32 val;
	u32 offset = SAR_BACKUP_STATUS_OFFSET;

	if (soc_is_omap54xx())
		offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;

	val = readl_relaxed(sar_base + offset);
	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + offset);
}

/*
 * Save GIC and Wakeupgen interrupt context using secure API
 * for HS/EMU devices.
 */
static void irq_save_secure_context(void)
{
	u32 ret;
	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
				FLAG_START_CRITICAL,
				0, 0, 0, 0, 0);
	if (ret != API_HAL_RET_VALUE_OK)
		pr_err("GIC and Wakeupgen context save failed\n");
}
#endif

#ifdef CONFIG_HOTPLUG_CPU
static int irq_cpu_hotplug_notify(struct notifier_block *self,
				  unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned int)hcpu;

	switch (action) {
	case CPU_ONLINE:
		wakeupgen_irqmask_all(cpu, 0);
		break;
	case CPU_DEAD:
		wakeupgen_irqmask_all(cpu, 1);
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block irq_hotplug_notifier = {
	.notifier_call = irq_cpu_hotplug_notify,
};

static void __init irq_hotplug_init(void)
{
	register_hotcpu_notifier(&irq_hotplug_notifier);
}
#else
static void __init irq_hotplug_init(void)
{}
#endif

#ifdef CONFIG_CPU_PM
static int irq_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
{
	switch (cmd) {
	case CPU_CLUSTER_PM_ENTER:
		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
			irq_save_context();
		else
			irq_save_secure_context();
		break;
	case CPU_CLUSTER_PM_EXIT:
		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
			irq_sar_clear();
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block irq_notifier_block = {
	.notifier_call = irq_notifier,
};

static void __init irq_pm_init(void)
{
	/* FIXME: Remove this when MPU OSWR support is added */
	if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
		cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
{}
#endif

void __iomem *omap_get_wakeupgen_base(void)
{
	return wakeupgen_base;
}

int omap_secure_apis_support(void)
{
	return omap_secure_apis;
}

static struct irq_chip wakeupgen_chip = {
	.name			= "WUGEN",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= wakeupgen_mask,
	.irq_unmask		= wakeupgen_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_type		= irq_chip_set_type_parent,
	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int wakeupgen_domain_translate(struct irq_domain *d,
				      struct irq_fwspec *fwspec,
				      unsigned long *hwirq,
				      unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2];
		return 0;
	}

	return -EINVAL;
}

static int wakeupgen_domain_alloc(struct irq_domain *domain,
				  unsigned int virq,
				  unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	int i;

	if (fwspec->param_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (fwspec->param[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = fwspec->param[1];
	if (hwirq >= MAX_IRQS)
		return -EINVAL;	/* Can't deal with this */

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &wakeupgen_chip, NULL);

	parent_fwspec = *fwspec;
	parent_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops wakeupgen_domain_ops = {
	.translate	= wakeupgen_domain_translate,
	.alloc		= wakeupgen_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

/*
 * Initialise the wakeupgen module.
 */
static int __init wakeupgen_init(struct device_node *node,
				 struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	int i;
	unsigned int boot_cpu = smp_processor_id();
	u32 val;

	if (!parent) {
		pr_err("%s: no parent, giving up\n", node->full_name);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%s: unable to obtain parent domain\n", node->full_name);
		return -ENXIO;
	}
	/* Not supported on OMAP4 ES1.0 silicon */
	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
		return -EPERM;
	}

	/* Static mapping, never released */
	wakeupgen_base = of_iomap(node, 0);
	if (WARN_ON(!wakeupgen_base))
		return -ENOMEM;

	if (cpu_is_omap44xx()) {
		irq_banks = OMAP4_NR_BANKS;
		max_irqs = OMAP4_NR_IRQS;
		omap_secure_apis = 1;
	} else if (soc_is_am43xx()) {
		irq_banks = AM43XX_NR_REG_BANKS;
		max_irqs = AM43XX_IRQS;
	}

	domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
					  node, &wakeupgen_domain_ops,
					  NULL);
	if (!domain) {
		iounmap(wakeupgen_base);
		return -ENOMEM;
	}

	/* Clear all IRQ bitmasks at wakeupGen level */
	for (i = 0; i < irq_banks; i++) {
		wakeupgen_writel(0, i, CPU0_ID);
		if (!soc_is_am43xx())
			wakeupgen_writel(0, i, CPU1_ID);
	}

	/*
	 * FIXME: Add support to set_smp_affinity() once the core
	 * GIC code has necessary hooks in place.
	 */

	/* Associate all the IRQs to boot CPU like GIC init does. */
	for (i = 0; i < max_irqs; i++)
		irq_target_cpu[i] = boot_cpu;

	/*
	 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
	 * 0x0:	ES1 behavior, CPU cores would enter and exit OFF mode together.
	 * 0x1:	ES2 behavior, CPU cores are allowed to enter/exit OFF mode
	 * independently.
	 * This needs to be set one time thanks to always ON domain.
	 *
	 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
	 * ES2.0, and the same is applicable for DRA7.
	 */
	if (soc_is_omap54xx() || soc_is_dra7xx()) {
		val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
		val |= BIT(5);
		omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
	}

	irq_hotplug_init();
	irq_pm_init();

	return 0;
}
IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
Commit	Line	Data
fcf6efa3 SS	1	/*
	2	* OMAP WakeupGen Source file
	3	*
	4	* OMAP WakeupGen is the interrupt controller extension used along
	5	* with ARM GIC to wake the CPU out from low power states on
	6	* external interrupts. It is responsible for generating wakeup
	7	* event from the incoming interrupts and enable bits. It is
	8	* implemented in MPU always ON power domain. During normal operation,
	9	* WakeupGen delivers external interrupts directly to the GIC.
	10	*
	11	* Copyright (C) 2011 Texas Instruments, Inc.
	12	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License version 2 as
	16	* published by the Free Software Foundation.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/io.h>
	22	#include <linux/irq.h>
0cc09e85	23	#include <linux/irqchip.h>
7136d457 MZ	24	#include <linux/irqdomain.h>
7136d457 MZ	25	#include <linux/of_address.h>
fcf6efa3 SS	26	#include <linux/platform_device.h>
fcf6efa3 SS	27	#include <linux/cpu.h>
0f3cf2ec SS	28	#include <linux/notifier.h>
0f3cf2ec SS	29	#include <linux/cpu_pm.h>
fcf6efa3	30
732231a7	31	#include "omap-wakeupgen.h"
c1db9d73	32	#include "omap-secure.h"
0f3cf2ec	33
dbc04161	34	#include "soc.h"
0f3cf2ec SS	35	#include "omap4-sar-layout.h"
0f3cf2ec SS	36	#include "common.h"
6099dd37	37	#include "pm.h"
fcf6efa3	38
6246cd06 AM	39	#define AM43XX_NR_REG_BANKS 7
	40	#define AM43XX_IRQS 224
	41	#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
	42	#define MAX_IRQS AM43XX_IRQS
	43	#define DEFAULT_NR_REG_BANKS 5
	44	#define DEFAULT_IRQS 160
fcf6efa3 SS	45	#define WKG_MASK_ALL 0x00000000
	46	#define WKG_UNMASK_ALL 0xffffffff
	47	#define CPU_ENA_OFFSET 0x400
	48	#define CPU0_ID 0x0
	49	#define CPU1_ID 0x1
247c445c SS	50	#define OMAP4_NR_BANKS 4
247c445c SS	51	#define OMAP4_NR_IRQS 128
fcf6efa3 SS	52
fcf6efa3 SS	53	static void __iomem *wakeupgen_base;
0f3cf2ec	54	static void __iomem *sar_base;
aecb9e14	55	static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
e534e871	56	static unsigned int irq_target_cpu[MAX_IRQS];
6246cd06 AM	57	static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
6246cd06 AM	58	static unsigned int max_irqs = DEFAULT_IRQS;
247c445c	59	static unsigned int omap_secure_apis;
fcf6efa3 SS	60
	61	/*
	62	* Static helper functions.
	63	*/
	64	static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
	65	{
edfaf05c	66	return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
fcf6efa3 SS	67	(cpu * CPU_ENA_OFFSET) + (idx * 4));
	68	}
	69
	70	static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
	71	{
edfaf05c	72	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
fcf6efa3 SS	73	(cpu * CPU_ENA_OFFSET) + (idx * 4));
	74	}
	75
0f3cf2ec SS	76	static inline void sar_writel(u32 val, u32 offset, u8 idx)
0f3cf2ec SS	77	{
edfaf05c	78	writel_relaxed(val, sar_base + offset + (idx * 4));
0f3cf2ec SS	79	}
0f3cf2ec SS	80
fcf6efa3 SS	81	static inline int _wakeupgen_get_irq_info(u32 irq, u32 bit_posn, u8 reg_index)
fcf6efa3 SS	82	{
fcf6efa3 SS	83	/*
	84	* Each WakeupGen register controls 32 interrupt.
	85	* i.e. 1 bit per SPI IRQ
	86	*/
7136d457 MZ	87	*reg_index = irq >> 5;
7136d457 MZ	88	*bit_posn = irq %= 32;
fcf6efa3 SS	89
	90	return 0;
	91	}
	92
	93	static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
	94	{
	95	u32 val, bit_number;
	96	u8 i;
	97
	98	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
	99	return;
	100
	101	val = wakeupgen_readl(i, cpu);
	102	val &= ~BIT(bit_number);
	103	wakeupgen_writel(val, i, cpu);
	104	}
	105
	106	static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
	107	{
	108	u32 val, bit_number;
	109	u8 i;
	110
	111	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
	112	return;
	113
	114	val = wakeupgen_readl(i, cpu);
	115	val \|= BIT(bit_number);
	116	wakeupgen_writel(val, i, cpu);
	117	}
	118
fcf6efa3 SS	119	/*
	120	* Architecture specific Mask extension
	121	*/
	122	static void wakeupgen_mask(struct irq_data *d)
	123	{
	124	unsigned long flags;
	125
aecb9e14	126	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
1cc4b1a9	127	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
aecb9e14	128	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
7136d457	129	irq_chip_mask_parent(d);
fcf6efa3 SS	130	}
	131
	132	/*
	133	* Architecture specific Unmask extension
	134	*/
	135	static void wakeupgen_unmask(struct irq_data *d)
	136	{
	137	unsigned long flags;
	138
aecb9e14	139	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
1cc4b1a9	140	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
aecb9e14	141	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
7136d457	142	irq_chip_unmask_parent(d);
fcf6efa3 SS	143	}
fcf6efa3 SS	144
bb1dbe7c	145	#ifdef CONFIG_HOTPLUG_CPU
247c445c	146	static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
bb1dbe7c KH	147
	148	static void _wakeupgen_save_masks(unsigned int cpu)
	149	{
	150	u8 i;
	151
247c445c	152	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	153	per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
	154	}
	155
	156	static void _wakeupgen_restore_masks(unsigned int cpu)
	157	{
	158	u8 i;
	159
247c445c	160	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	161	wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
	162	}
	163
	164	static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
	165	{
	166	u8 i;
	167
247c445c	168	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	169	wakeupgen_writel(reg, i, cpu);
	170	}
	171
fcf6efa3 SS	172	/*
	173	* Mask or unmask all interrupts on given CPU.
	174	* 0 = Mask all interrupts on the 'cpu'
	175	* 1 = Unmask all interrupts on the 'cpu'
	176	* Ensure that the initial mask is maintained. This is faster than
	177	* iterating through GIC registers to arrive at the correct masks.
	178	*/
	179	static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
	180	{
	181	unsigned long flags;
	182
aecb9e14	183	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
fcf6efa3 SS	184	if (set) {
	185	_wakeupgen_save_masks(cpu);
	186	_wakeupgen_set_all(cpu, WKG_MASK_ALL);
	187	} else {
	188	_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
	189	_wakeupgen_restore_masks(cpu);
	190	}
aecb9e14	191	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
fcf6efa3	192	}
bb1dbe7c	193	#endif
fcf6efa3	194
0f3cf2ec	195	#ifdef CONFIG_CPU_PM
247c445c	196	static inline void omap4_irq_save_context(void)
0f3cf2ec SS	197	{
	198	u32 i, val;
	199
	200	if (omap_rev() == OMAP4430_REV_ES1_0)
	201	return;
	202
247c445c	203	for (i = 0; i < irq_banks; i++) {
0f3cf2ec SS	204	/* Save the CPUx interrupt mask for IRQ 0 to 127 */
	205	val = wakeupgen_readl(i, 0);
	206	sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
	207	val = wakeupgen_readl(i, 1);
	208	sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
	209
	210	/*
	211	* Disable the secure interrupts for CPUx. The restore
	212	* code blindly restores secure and non-secure interrupt
	213	* masks from SAR RAM. Secure interrupts are not suppose
	214	* to be enabled from HLOS. So overwrite the SAR location
	215	* so that the secure interrupt remains disabled.
	216	*/
	217	sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
	218	sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	219	}
	220
	221	/* Save AuxBoot* registers */
edfaf05c VK	222	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	223	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
	224	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
	225	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
0f3cf2ec	226
0f3cf2ec	227	/* Save SyncReq generation logic */
edfaf05c VK	228	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	229	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	230	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	231	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
0f3cf2ec SS	232
0f3cf2ec SS	233	/* Set the Backup Bit Mask status */
edfaf05c	234	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
0f3cf2ec	235	val \|= SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	236	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
247c445c SS	237
	238	}
	239
	240	static inline void omap5_irq_save_context(void)
	241	{
	242	u32 i, val;
	243
	244	for (i = 0; i < irq_banks; i++) {
	245	/* Save the CPUx interrupt mask for IRQ 0 to 159 */
	246	val = wakeupgen_readl(i, 0);
	247	sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
	248	val = wakeupgen_readl(i, 1);
	249	sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
	250	sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
	251	sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	252	}
	253
	254	/* Save AuxBoot* registers */
edfaf05c VK	255	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	256	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
	257	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	258	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
247c445c SS	259
247c445c SS	260	/* Set the Backup Bit Mask status */
edfaf05c	261	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
247c445c	262	val \|= SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	263	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
247c445c SS	264
	265	}
	266
	267	/*
	268	* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
	269	* ROM code. WakeupGen IP is integrated along with GIC to manage the
	270	* interrupt wakeups from CPU low power states. It manages
	271	* masking/unmasking of Shared peripheral interrupts(SPI). So the
	272	* interrupt enable/disable control should be in sync and consistent
	273	* at WakeupGen and GIC so that interrupts are not lost.
	274	*/
	275	static void irq_save_context(void)
	276	{
	277	if (!sar_base)
	278	sar_base = omap4_get_sar_ram_base();
	279
	280	if (soc_is_omap54xx())
	281	omap5_irq_save_context();
	282	else
	283	omap4_irq_save_context();
0f3cf2ec SS	284	}
	285
	286	/*
	287	* Clear WakeupGen SAR backup status.
	288	*/
8c3d4534	289	static void irq_sar_clear(void)
0f3cf2ec SS	290	{
0f3cf2ec SS	291	u32 val;
247c445c SS	292	u32 offset = SAR_BACKUP_STATUS_OFFSET;
	293
	294	if (soc_is_omap54xx())
	295	offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
	296
edfaf05c	297	val = readl_relaxed(sar_base + offset);
0f3cf2ec	298	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	299	writel_relaxed(val, sar_base + offset);
0f3cf2ec SS	300	}
	301
	302	/*
	303	* Save GIC and Wakeupgen interrupt context using secure API
	304	* for HS/EMU devices.
	305	*/
	306	static void irq_save_secure_context(void)
	307	{
	308	u32 ret;
	309	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
	310	FLAG_START_CRITICAL,
	311	0, 0, 0, 0, 0);
	312	if (ret != API_HAL_RET_VALUE_OK)
	313	pr_err("GIC and Wakeupgen context save failed\n");
	314	}
	315	#endif
	316
b5b4f288	317	#ifdef CONFIG_HOTPLUG_CPU
8bd26e3a PG	318	static int irq_cpu_hotplug_notify(struct notifier_block *self,
8bd26e3a PG	319	unsigned long action, void *hcpu)
b5b4f288 SS	320	{
	321	unsigned int cpu = (unsigned int)hcpu;
	322
	323	switch (action) {
	324	case CPU_ONLINE:
	325	wakeupgen_irqmask_all(cpu, 0);
	326	break;
	327	case CPU_DEAD:
	328	wakeupgen_irqmask_all(cpu, 1);
	329	break;
	330	}
	331	return NOTIFY_OK;
	332	}
	333
b96fc2f3	334	static struct notifier_block irq_hotplug_notifier = {
b5b4f288 SS	335	.notifier_call = irq_cpu_hotplug_notify,
	336	};
	337
	338	static void __init irq_hotplug_init(void)
	339	{
	340	register_hotcpu_notifier(&irq_hotplug_notifier);
	341	}
	342	#else
	343	static void __init irq_hotplug_init(void)
	344	{}
	345	#endif
	346
0f3cf2ec SS	347	#ifdef CONFIG_CPU_PM
	348	static int irq_notifier(struct notifier_block self, unsigned long cmd, void v)
	349	{
	350	switch (cmd) {
	351	case CPU_CLUSTER_PM_ENTER:
	352	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
	353	irq_save_context();
	354	else
	355	irq_save_secure_context();
	356	break;
	357	case CPU_CLUSTER_PM_EXIT:
	358	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
	359	irq_sar_clear();
	360	break;
	361	}
	362	return NOTIFY_OK;
	363	}
	364
	365	static struct notifier_block irq_notifier_block = {
	366	.notifier_call = irq_notifier,
	367	};
	368
	369	static void __init irq_pm_init(void)
	370	{
247c445c	371	/* FIXME: Remove this when MPU OSWR support is added */
6099dd37	372	if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
247c445c	373	cpu_pm_register_notifier(&irq_notifier_block);
0f3cf2ec SS	374	}
	375	#else
	376	static void __init irq_pm_init(void)
	377	{}
	378	#endif
	379
247c445c SS	380	void __iomem *omap_get_wakeupgen_base(void)
	381	{
	382	return wakeupgen_base;
	383	}
	384
	385	int omap_secure_apis_support(void)
	386	{
	387	return omap_secure_apis;
	388	}
	389
7136d457 MZ	390	static struct irq_chip wakeupgen_chip = {
	391	.name = "WUGEN",
	392	.irq_eoi = irq_chip_eoi_parent,
	393	.irq_mask = wakeupgen_mask,
	394	.irq_unmask = wakeupgen_unmask,
	395	.irq_retrigger = irq_chip_retrigger_hierarchy,
63059a27	396	.irq_set_type = irq_chip_set_type_parent,
7136d457 MZ	397	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
	398	#ifdef CONFIG_SMP
	399	.irq_set_affinity = irq_chip_set_affinity_parent,
	400	#endif
	401	};
	402
f833f57f MZ	403	static int wakeupgen_domain_translate(struct irq_domain *d,
	404	struct irq_fwspec *fwspec,
	405	unsigned long *hwirq,
	406	unsigned int *type)
7136d457	407	{
f833f57f MZ	408	if (is_of_node(fwspec->fwnode)) {
	409	if (fwspec->param_count != 3)
	410	return -EINVAL;
7136d457	411
f833f57f MZ	412	/* No PPI should point to this domain */
	413	if (fwspec->param[0] != 0)
	414	return -EINVAL;
	415
	416	*hwirq = fwspec->param[1];
	417	*type = fwspec->param[2];
	418	return 0;
	419	}
	420
	421	return -EINVAL;
7136d457 MZ	422	}
	423
	424	static int wakeupgen_domain_alloc(struct irq_domain *domain,
	425	unsigned int virq,
	426	unsigned int nr_irqs, void *data)
	427	{
f833f57f MZ	428	struct irq_fwspec *fwspec = data;
f833f57f MZ	429	struct irq_fwspec parent_fwspec;
7136d457 MZ	430	irq_hw_number_t hwirq;
	431	int i;
	432
f833f57f	433	if (fwspec->param_count != 3)
7136d457	434	return -EINVAL; /* Not GIC compliant */
f833f57f	435	if (fwspec->param[0] != 0)
7136d457 MZ	436	return -EINVAL; /* No PPI should point to this domain */
7136d457 MZ	437
f833f57f	438	hwirq = fwspec->param[1];
7136d457 MZ	439	if (hwirq >= MAX_IRQS)
	440	return -EINVAL; /* Can't deal with this */
	441
	442	for (i = 0; i < nr_irqs; i++)
	443	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	444	&wakeupgen_chip, NULL);
	445
f833f57f MZ	446	parent_fwspec = *fwspec;
	447	parent_fwspec.fwnode = domain->parent->fwnode;
	448	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
	449	&parent_fwspec);
7136d457 MZ	450	}
7136d457 MZ	451
8297955f	452	static const struct irq_domain_ops wakeupgen_domain_ops = {
f833f57f MZ	453	.translate = wakeupgen_domain_translate,
	454	.alloc = wakeupgen_domain_alloc,
	455	.free = irq_domain_free_irqs_common,
7136d457 MZ	456	};
7136d457 MZ	457
fcf6efa3 SS	458	/*
	459	* Initialise the wakeupgen module.
	460	*/
7136d457 MZ	461	static int __init wakeupgen_init(struct device_node *node,
7136d457 MZ	462	struct device_node *parent)
fcf6efa3	463	{
7136d457	464	struct irq_domain parent_domain, domain;
fcf6efa3 SS	465	int i;
fcf6efa3 SS	466	unsigned int boot_cpu = smp_processor_id();
4664d4d8	467	u32 val;
fcf6efa3	468
7136d457 MZ	469	if (!parent) {
	470	pr_err("%s: no parent, giving up\n", node->full_name);
	471	return -ENODEV;
	472	}
	473
	474	parent_domain = irq_find_host(parent);
	475	if (!parent_domain) {
	476	pr_err("%s: unable to obtain parent domain\n", node->full_name);
	477	return -ENXIO;
	478	}
fcf6efa3 SS	479	/* Not supported on OMAP4 ES1.0 silicon */
	480	if (omap_rev() == OMAP4430_REV_ES1_0) {
	481	WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
	482	return -EPERM;
	483	}
	484
	485	/* Static mapping, never released */
7136d457	486	wakeupgen_base = of_iomap(node, 0);
fcf6efa3 SS	487	if (WARN_ON(!wakeupgen_base))
	488	return -ENOMEM;
	489
247c445c SS	490	if (cpu_is_omap44xx()) {
	491	irq_banks = OMAP4_NR_BANKS;
	492	max_irqs = OMAP4_NR_IRQS;
	493	omap_secure_apis = 1;
6246cd06 AM	494	} else if (soc_is_am43xx()) {
	495	irq_banks = AM43XX_NR_REG_BANKS;
	496	max_irqs = AM43XX_IRQS;
247c445c SS	497	}
247c445c SS	498
7136d457 MZ	499	domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
	500	node, &wakeupgen_domain_ops,
	501	NULL);
	502	if (!domain) {
	503	iounmap(wakeupgen_base);
	504	return -ENOMEM;
	505	}
	506
fcf6efa3	507	/* Clear all IRQ bitmasks at wakeupGen level */
247c445c	508	for (i = 0; i < irq_banks; i++) {
fcf6efa3	509	wakeupgen_writel(0, i, CPU0_ID);
6246cd06 AM	510	if (!soc_is_am43xx())
6246cd06 AM	511	wakeupgen_writel(0, i, CPU1_ID);
fcf6efa3 SS	512	}
fcf6efa3 SS	513
fcf6efa3 SS	514	/*
	515	* FIXME: Add support to set_smp_affinity() once the core
	516	* GIC code has necessary hooks in place.
	517	*/
	518
	519	/* Associate all the IRQs to boot CPU like GIC init does. */
247c445c	520	for (i = 0; i < max_irqs; i++)
fcf6efa3 SS	521	irq_target_cpu[i] = boot_cpu;
fcf6efa3 SS	522
4664d4d8 SS	523	/*
	524	* Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
	525	* 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
	526	* 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
	527	* independently.
	528	* This needs to be set one time thanks to always ON domain.
	529	*
	530	* We do not support ES1 behavior anymore. OMAP5 is assumed to be
	531	* ES2.0, and the same is applicable for DRA7.
	532	*/
	533	if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
	534	val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
	535	val \|= BIT(5);
	536	omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
	537	}
	538
b5b4f288	539	irq_hotplug_init();
0f3cf2ec	540	irq_pm_init();
b5b4f288	541
fcf6efa3 SS	542	return 0;
fcf6efa3 SS	543	}
0cc09e85	544	IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);