[mirror_ubuntu-hirsute-kernel.git] / arch / arm / mach-omap2 / omap-wakeupgen.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * OMAP WakeupGen Source file
 *
 * OMAP WakeupGen is the interrupt controller extension used along
 * with ARM GIC to wake the CPU out from low power states on
 * external interrupts. It is responsible for generating wakeup
 * event from the incoming interrupts and enable bits. It is
 * implemented in MPU always ON power domain. During normal operation,
 * WakeupGen delivers external interrupts directly to the GIC.
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
#include <linux/notifier.h>
#include <linux/cpu_pm.h>

#include "omap-wakeupgen.h"
#include "omap-secure.h"

#include "soc.h"
#include "omap4-sar-layout.h"
#include "common.h"
#include "pm.h"

#define AM43XX_NR_REG_BANKS	7
#define AM43XX_IRQS		224
#define MAX_NR_REG_BANKS	AM43XX_NR_REG_BANKS
#define MAX_IRQS		AM43XX_IRQS
#define DEFAULT_NR_REG_BANKS	5
#define DEFAULT_IRQS		160
#define WKG_MASK_ALL		0x00000000
#define WKG_UNMASK_ALL		0xffffffff
#define CPU_ENA_OFFSET		0x400
#define CPU0_ID			0x0
#define CPU1_ID			0x1
#define OMAP4_NR_BANKS		4
#define OMAP4_NR_IRQS		128

#define SYS_NIRQ1_EXT_SYS_IRQ_1	7
#define SYS_NIRQ2_EXT_SYS_IRQ_2	119

static void __iomem *wakeupgen_base;
static void __iomem *sar_base;
static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
static unsigned int irq_target_cpu[MAX_IRQS];
static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
static unsigned int max_irqs = DEFAULT_IRQS;
static unsigned int omap_secure_apis;

#ifdef CONFIG_CPU_PM
static unsigned int wakeupgen_context[MAX_NR_REG_BANKS];
#endif

struct omap_wakeupgen_ops {
	void (*save_context)(void);
	void (*restore_context)(void);
};

static struct omap_wakeupgen_ops *wakeupgen_ops;

/*
 * Static helper functions.
 */
static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
{
	return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
				(cpu * CPU_ENA_OFFSET) + (idx * 4));
}

static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
{
	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
				(cpu * CPU_ENA_OFFSET) + (idx * 4));
}

static inline void sar_writel(u32 val, u32 offset, u8 idx)
{
	writel_relaxed(val, sar_base + offset + (idx * 4));
}

static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
{
	/*
	 * Each WakeupGen register controls 32 interrupt.
	 * i.e. 1 bit per SPI IRQ
	 */
	*reg_index = irq >> 5;
	*bit_posn = irq %= 32;

	return 0;
}

static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
{
	u32 val, bit_number;
	u8 i;

	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
		return;

	val = wakeupgen_readl(i, cpu);
	val &= ~BIT(bit_number);
	wakeupgen_writel(val, i, cpu);
}

static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
{
	u32 val, bit_number;
	u8 i;

	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
		return;

	val = wakeupgen_readl(i, cpu);
	val |= BIT(bit_number);
	wakeupgen_writel(val, i, cpu);
}

/*
 * Architecture specific Mask extension
 */
static void wakeupgen_mask(struct irq_data *d)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
	irq_chip_mask_parent(d);
}

/*
 * Architecture specific Unmask extension
 */
static void wakeupgen_unmask(struct irq_data *d)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
	irq_chip_unmask_parent(d);
}

/*
 * The sys_nirq pins bypass peripheral modules and are wired directly
 * to MPUSS wakeupgen. They get automatically inverted for GIC.
 */
static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
{
	bool inverted = false;

	switch (type) {
	case IRQ_TYPE_LEVEL_LOW:
		type &= ~IRQ_TYPE_LEVEL_MASK;
		type |= IRQ_TYPE_LEVEL_HIGH;
		inverted = true;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		type &= ~IRQ_TYPE_EDGE_BOTH;
		type |= IRQ_TYPE_EDGE_RISING;
		inverted = true;
		break;
	default:
		break;
	}

	if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
	    d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
		pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
			d->hwirq);

	return irq_chip_set_type_parent(d, type);
}

#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);

static void _wakeupgen_save_masks(unsigned int cpu)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
}

static void _wakeupgen_restore_masks(unsigned int cpu)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
}

static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
{
	u8 i;

	for (i = 0; i < irq_banks; i++)
		wakeupgen_writel(reg, i, cpu);
}

/*
 * Mask or unmask all interrupts on given CPU.
 *	0 = Mask all interrupts on the 'cpu'
 *	1 = Unmask all interrupts on the 'cpu'
 * Ensure that the initial mask is maintained. This is faster than
 * iterating through GIC registers to arrive at the correct masks.
 */
static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
	if (set) {
		_wakeupgen_save_masks(cpu);
		_wakeupgen_set_all(cpu, WKG_MASK_ALL);
	} else {
		_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
		_wakeupgen_restore_masks(cpu);
	}
	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
}
#endif

#ifdef CONFIG_CPU_PM
static inline void omap4_irq_save_context(void)
{
	u32 i, val;

	if (omap_rev() == OMAP4430_REV_ES1_0)
		return;

	for (i = 0; i < irq_banks; i++) {
		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);

		/*
		 * Disable the secure interrupts for CPUx. The restore
		 * code blindly restores secure and non-secure interrupt
		 * masks from SAR RAM. Secure interrupts are not suppose
		 * to be enabled from HLOS. So overwrite the SAR location
		 * so that the secure interrupt remains disabled.
		 */
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/* Save AuxBoot* registers */
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);

	/* Save SyncReq generation logic */
	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);

	/* Set the Backup Bit Mask status */
	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);

}

static inline void omap5_irq_save_context(void)
{
	u32 i, val;

	for (i = 0; i < irq_banks; i++) {
		/* Save the CPUx interrupt mask for IRQ 0 to 159 */
		val = wakeupgen_readl(i, 0);
		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
		val = wakeupgen_readl(i, 1);
		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	}

	/* Save AuxBoot* registers */
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);

	/* Set the Backup Bit Mask status */
	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);

}

static inline void am43xx_irq_save_context(void)
{
	u32 i;

	for (i = 0; i < irq_banks; i++) {
		wakeupgen_context[i] = wakeupgen_readl(i, 0);
		wakeupgen_writel(0, i, CPU0_ID);
	}
}

/*
 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
 * ROM code. WakeupGen IP is integrated along with GIC to manage the
 * interrupt wakeups from CPU low power states. It manages
 * masking/unmasking of Shared peripheral interrupts(SPI). So the
 * interrupt enable/disable control should be in sync and consistent
 * at WakeupGen and GIC so that interrupts are not lost.
 */
static void irq_save_context(void)
{
	/* DRA7 has no SAR to save */
	if (soc_is_dra7xx())
		return;

	if (wakeupgen_ops && wakeupgen_ops->save_context)
		wakeupgen_ops->save_context();
}

/*
 * Clear WakeupGen SAR backup status.
 */
static void irq_sar_clear(void)
{
	u32 val;
	u32 offset = SAR_BACKUP_STATUS_OFFSET;
	/* DRA7 has no SAR to save */
	if (soc_is_dra7xx())
		return;

	if (soc_is_omap54xx())
		offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;

	val = readl_relaxed(sar_base + offset);
	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
	writel_relaxed(val, sar_base + offset);
}

static void am43xx_irq_restore_context(void)
{
	u32 i;

	for (i = 0; i < irq_banks; i++)
		wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID);
}

static void irq_restore_context(void)
{
	if (wakeupgen_ops && wakeupgen_ops->restore_context)
		wakeupgen_ops->restore_context();
}

/*
 * Save GIC and Wakeupgen interrupt context using secure API
 * for HS/EMU devices.
 */
static void irq_save_secure_context(void)
{
	u32 ret;
	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
				FLAG_START_CRITICAL,
				0, 0, 0, 0, 0);
	if (ret != API_HAL_RET_VALUE_OK)
		pr_err("GIC and Wakeupgen context save failed\n");
}

/* Define ops for context save and restore for each SoC */
static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {
	.save_context = omap4_irq_save_context,
	.restore_context = irq_sar_clear,
};

static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {
	.save_context = omap5_irq_save_context,
	.restore_context = irq_sar_clear,
};

static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {
	.save_context = am43xx_irq_save_context,
	.restore_context = am43xx_irq_restore_context,
};
#else
static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {};
static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {};
static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {};
#endif

#ifdef CONFIG_HOTPLUG_CPU
static int omap_wakeupgen_cpu_online(unsigned int cpu)
{
	wakeupgen_irqmask_all(cpu, 0);
	return 0;
}

static int omap_wakeupgen_cpu_dead(unsigned int cpu)
{
	wakeupgen_irqmask_all(cpu, 1);
	return 0;
}

static void __init irq_hotplug_init(void)
{
	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "arm/omap-wake:online",
				  omap_wakeupgen_cpu_online, NULL);
	cpuhp_setup_state_nocalls(CPUHP_ARM_OMAP_WAKE_DEAD,
				  "arm/omap-wake:dead", NULL,
				  omap_wakeupgen_cpu_dead);
}
#else
static void __init irq_hotplug_init(void)
{}
#endif

#ifdef CONFIG_CPU_PM
static int irq_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
{
	switch (cmd) {
	case CPU_CLUSTER_PM_ENTER:
		if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
			irq_save_context();
		else
			irq_save_secure_context();
		break;
	case CPU_CLUSTER_PM_EXIT:
		if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
			irq_restore_context();
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block irq_notifier_block = {
	.notifier_call = irq_notifier,
};

static void __init irq_pm_init(void)
{
	/* FIXME: Remove this when MPU OSWR support is added */
	if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
		cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
{}
#endif

void __iomem *omap_get_wakeupgen_base(void)
{
	return wakeupgen_base;
}

int omap_secure_apis_support(void)
{
	return omap_secure_apis;
}

static struct irq_chip wakeupgen_chip = {
	.name			= "WUGEN",
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_mask		= wakeupgen_mask,
	.irq_unmask		= wakeupgen_unmask,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
	.irq_set_type		= wakeupgen_irq_set_type,
	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
};

static int wakeupgen_domain_translate(struct irq_domain *d,
				      struct irq_fwspec *fwspec,
				      unsigned long *hwirq,
				      unsigned int *type)
{
	if (is_of_node(fwspec->fwnode)) {
		if (fwspec->param_count != 3)
			return -EINVAL;

		/* No PPI should point to this domain */
		if (fwspec->param[0] != 0)
			return -EINVAL;

		*hwirq = fwspec->param[1];
		*type = fwspec->param[2];
		return 0;
	}

	return -EINVAL;
}

static int wakeupgen_domain_alloc(struct irq_domain *domain,
				  unsigned int virq,
				  unsigned int nr_irqs, void *data)
{
	struct irq_fwspec *fwspec = data;
	struct irq_fwspec parent_fwspec;
	irq_hw_number_t hwirq;
	int i;

	if (fwspec->param_count != 3)
		return -EINVAL;	/* Not GIC compliant */
	if (fwspec->param[0] != 0)
		return -EINVAL;	/* No PPI should point to this domain */

	hwirq = fwspec->param[1];
	if (hwirq >= MAX_IRQS)
		return -EINVAL;	/* Can't deal with this */

	for (i = 0; i < nr_irqs; i++)
		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
					      &wakeupgen_chip, NULL);

	parent_fwspec = *fwspec;
	parent_fwspec.fwnode = domain->parent->fwnode;
	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
					    &parent_fwspec);
}

static const struct irq_domain_ops wakeupgen_domain_ops = {
	.translate	= wakeupgen_domain_translate,
	.alloc		= wakeupgen_domain_alloc,
	.free		= irq_domain_free_irqs_common,
};

/*
 * Initialise the wakeupgen module.
 */
static int __init wakeupgen_init(struct device_node *node,
				 struct device_node *parent)
{
	struct irq_domain *parent_domain, *domain;
	int i;
	unsigned int boot_cpu = smp_processor_id();
	u32 val;

	if (!parent) {
		pr_err("%pOF: no parent, giving up\n", node);
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("%pOF: unable to obtain parent domain\n", node);
		return -ENXIO;
	}
	/* Not supported on OMAP4 ES1.0 silicon */
	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
		return -EPERM;
	}

	/* Static mapping, never released */
	wakeupgen_base = of_iomap(node, 0);
	if (WARN_ON(!wakeupgen_base))
		return -ENOMEM;

	if (cpu_is_omap44xx()) {
		irq_banks = OMAP4_NR_BANKS;
		max_irqs = OMAP4_NR_IRQS;
		omap_secure_apis = 1;
		wakeupgen_ops = &omap4_wakeupgen_ops;
	} else if (soc_is_omap54xx()) {
		wakeupgen_ops = &omap5_wakeupgen_ops;
	} else if (soc_is_am43xx()) {
		irq_banks = AM43XX_NR_REG_BANKS;
		max_irqs = AM43XX_IRQS;
		wakeupgen_ops = &am43xx_wakeupgen_ops;
	}

	domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
					  node, &wakeupgen_domain_ops,
					  NULL);
	if (!domain) {
		iounmap(wakeupgen_base);
		return -ENOMEM;
	}

	/* Clear all IRQ bitmasks at wakeupGen level */
	for (i = 0; i < irq_banks; i++) {
		wakeupgen_writel(0, i, CPU0_ID);
		if (!soc_is_am43xx())
			wakeupgen_writel(0, i, CPU1_ID);
	}

	/*
	 * FIXME: Add support to set_smp_affinity() once the core
	 * GIC code has necessary hooks in place.
	 */

	/* Associate all the IRQs to boot CPU like GIC init does. */
	for (i = 0; i < max_irqs; i++)
		irq_target_cpu[i] = boot_cpu;

	/*
	 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
	 * 0x0:	ES1 behavior, CPU cores would enter and exit OFF mode together.
	 * 0x1:	ES2 behavior, CPU cores are allowed to enter/exit OFF mode
	 * independently.
	 * This needs to be set one time thanks to always ON domain.
	 *
	 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
	 * ES2.0, and the same is applicable for DRA7.
	 */
	if (soc_is_omap54xx() || soc_is_dra7xx()) {
		val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
		val |= BIT(5);
		omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
	}

	irq_hotplug_init();
	irq_pm_init();

	sar_base = omap4_get_sar_ram_base();

	return 0;
}
IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
fcf6efa3 SS	2	/*
	3	* OMAP WakeupGen Source file
	4	*
	5	* OMAP WakeupGen is the interrupt controller extension used along
	6	* with ARM GIC to wake the CPU out from low power states on
	7	* external interrupts. It is responsible for generating wakeup
	8	* event from the incoming interrupts and enable bits. It is
	9	* implemented in MPU always ON power domain. During normal operation,
	10	* WakeupGen delivers external interrupts directly to the GIC.
	11	*
	12	* Copyright (C) 2011 Texas Instruments, Inc.
	13	* Santosh Shilimkar <santosh.shilimkar@ti.com>
fcf6efa3 SS	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/init.h>
	18	#include <linux/io.h>
	19	#include <linux/irq.h>
0cc09e85	20	#include <linux/irqchip.h>
7136d457 MZ	21	#include <linux/irqdomain.h>
7136d457 MZ	22	#include <linux/of_address.h>
fcf6efa3 SS	23	#include <linux/platform_device.h>
fcf6efa3 SS	24	#include <linux/cpu.h>
0f3cf2ec SS	25	#include <linux/notifier.h>
0f3cf2ec SS	26	#include <linux/cpu_pm.h>
fcf6efa3	27
732231a7	28	#include "omap-wakeupgen.h"
c1db9d73	29	#include "omap-secure.h"
0f3cf2ec	30
dbc04161	31	#include "soc.h"
0f3cf2ec SS	32	#include "omap4-sar-layout.h"
0f3cf2ec SS	33	#include "common.h"
6099dd37	34	#include "pm.h"
fcf6efa3	35
6246cd06 AM	36	#define AM43XX_NR_REG_BANKS 7
	37	#define AM43XX_IRQS 224
	38	#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
	39	#define MAX_IRQS AM43XX_IRQS
	40	#define DEFAULT_NR_REG_BANKS 5
	41	#define DEFAULT_IRQS 160
fcf6efa3 SS	42	#define WKG_MASK_ALL 0x00000000
	43	#define WKG_UNMASK_ALL 0xffffffff
	44	#define CPU_ENA_OFFSET 0x400
	45	#define CPU0_ID 0x0
	46	#define CPU1_ID 0x1
247c445c SS	47	#define OMAP4_NR_BANKS 4
247c445c SS	48	#define OMAP4_NR_IRQS 128
fcf6efa3	49
d0243693 TL	50	#define SYS_NIRQ1_EXT_SYS_IRQ_1 7
	51	#define SYS_NIRQ2_EXT_SYS_IRQ_2 119
	52
fcf6efa3	53	static void __iomem *wakeupgen_base;
0f3cf2ec	54	static void __iomem *sar_base;
aecb9e14	55	static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
e534e871	56	static unsigned int irq_target_cpu[MAX_IRQS];
6246cd06 AM	57	static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
6246cd06 AM	58	static unsigned int max_irqs = DEFAULT_IRQS;
247c445c	59	static unsigned int omap_secure_apis;
fcf6efa3	60
e1a9e61e DG	61	#ifdef CONFIG_CPU_PM
	62	static unsigned int wakeupgen_context[MAX_NR_REG_BANKS];
	63	#endif
	64
	65	struct omap_wakeupgen_ops {
	66	void (*save_context)(void);
	67	void (*restore_context)(void);
	68	};
	69
	70	static struct omap_wakeupgen_ops *wakeupgen_ops;
	71
fcf6efa3 SS	72	/*
	73	* Static helper functions.
	74	*/
	75	static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
	76	{
edfaf05c	77	return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
fcf6efa3 SS	78	(cpu * CPU_ENA_OFFSET) + (idx * 4));
	79	}
	80
	81	static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
	82	{
edfaf05c	83	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
fcf6efa3 SS	84	(cpu * CPU_ENA_OFFSET) + (idx * 4));
	85	}
	86
0f3cf2ec SS	87	static inline void sar_writel(u32 val, u32 offset, u8 idx)
0f3cf2ec SS	88	{
edfaf05c	89	writel_relaxed(val, sar_base + offset + (idx * 4));
0f3cf2ec SS	90	}
0f3cf2ec SS	91
fcf6efa3 SS	92	static inline int _wakeupgen_get_irq_info(u32 irq, u32 bit_posn, u8 reg_index)
fcf6efa3 SS	93	{
fcf6efa3 SS	94	/*
	95	* Each WakeupGen register controls 32 interrupt.
	96	* i.e. 1 bit per SPI IRQ
	97	*/
7136d457 MZ	98	*reg_index = irq >> 5;
7136d457 MZ	99	*bit_posn = irq %= 32;
fcf6efa3 SS	100
	101	return 0;
	102	}
	103
	104	static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
	105	{
	106	u32 val, bit_number;
	107	u8 i;
	108
	109	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
	110	return;
	111
	112	val = wakeupgen_readl(i, cpu);
	113	val &= ~BIT(bit_number);
	114	wakeupgen_writel(val, i, cpu);
	115	}
	116
	117	static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
	118	{
	119	u32 val, bit_number;
	120	u8 i;
	121
	122	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
	123	return;
	124
	125	val = wakeupgen_readl(i, cpu);
	126	val \|= BIT(bit_number);
	127	wakeupgen_writel(val, i, cpu);
	128	}
	129
fcf6efa3 SS	130	/*
	131	* Architecture specific Mask extension
	132	*/
	133	static void wakeupgen_mask(struct irq_data *d)
	134	{
	135	unsigned long flags;
	136
aecb9e14	137	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
1cc4b1a9	138	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
aecb9e14	139	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
7136d457	140	irq_chip_mask_parent(d);
fcf6efa3 SS	141	}
	142
	143	/*
	144	* Architecture specific Unmask extension
	145	*/
	146	static void wakeupgen_unmask(struct irq_data *d)
	147	{
	148	unsigned long flags;
	149
aecb9e14	150	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
1cc4b1a9	151	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
aecb9e14	152	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
7136d457	153	irq_chip_unmask_parent(d);
fcf6efa3 SS	154	}
fcf6efa3 SS	155
d0243693 TL	156	/*
	157	* The sys_nirq pins bypass peripheral modules and are wired directly
	158	* to MPUSS wakeupgen. They get automatically inverted for GIC.
	159	*/
	160	static int wakeupgen_irq_set_type(struct irq_data *d, unsigned int type)
	161	{
	162	bool inverted = false;
	163
	164	switch (type) {
	165	case IRQ_TYPE_LEVEL_LOW:
	166	type &= ~IRQ_TYPE_LEVEL_MASK;
	167	type \|= IRQ_TYPE_LEVEL_HIGH;
	168	inverted = true;
	169	break;
	170	case IRQ_TYPE_EDGE_FALLING:
	171	type &= ~IRQ_TYPE_EDGE_BOTH;
	172	type \|= IRQ_TYPE_EDGE_RISING;
	173	inverted = true;
	174	break;
	175	default:
	176	break;
	177	}
	178
	179	if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
	180	d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
	181	pr_warn("wakeupgen: irq%li polarity inverted in dts\n",
	182	d->hwirq);
	183
	184	return irq_chip_set_type_parent(d, type);
	185	}
	186
bb1dbe7c	187	#ifdef CONFIG_HOTPLUG_CPU
247c445c	188	static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
bb1dbe7c KH	189
	190	static void _wakeupgen_save_masks(unsigned int cpu)
	191	{
	192	u8 i;
	193
247c445c	194	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	195	per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
	196	}
	197
	198	static void _wakeupgen_restore_masks(unsigned int cpu)
	199	{
	200	u8 i;
	201
247c445c	202	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	203	wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
	204	}
	205
	206	static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
	207	{
	208	u8 i;
	209
247c445c	210	for (i = 0; i < irq_banks; i++)
bb1dbe7c KH	211	wakeupgen_writel(reg, i, cpu);
	212	}
	213
fcf6efa3 SS	214	/*
	215	* Mask or unmask all interrupts on given CPU.
	216	* 0 = Mask all interrupts on the 'cpu'
	217	* 1 = Unmask all interrupts on the 'cpu'
	218	* Ensure that the initial mask is maintained. This is faster than
	219	* iterating through GIC registers to arrive at the correct masks.
	220	*/
	221	static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
	222	{
	223	unsigned long flags;
	224
aecb9e14	225	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
fcf6efa3 SS	226	if (set) {
	227	_wakeupgen_save_masks(cpu);
	228	_wakeupgen_set_all(cpu, WKG_MASK_ALL);
	229	} else {
	230	_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
	231	_wakeupgen_restore_masks(cpu);
	232	}
aecb9e14	233	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
fcf6efa3	234	}
bb1dbe7c	235	#endif
fcf6efa3	236
0f3cf2ec	237	#ifdef CONFIG_CPU_PM
247c445c	238	static inline void omap4_irq_save_context(void)
0f3cf2ec SS	239	{
	240	u32 i, val;
	241
	242	if (omap_rev() == OMAP4430_REV_ES1_0)
	243	return;
	244
247c445c	245	for (i = 0; i < irq_banks; i++) {
0f3cf2ec SS	246	/* Save the CPUx interrupt mask for IRQ 0 to 127 */
	247	val = wakeupgen_readl(i, 0);
	248	sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
	249	val = wakeupgen_readl(i, 1);
	250	sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
	251
	252	/*
	253	* Disable the secure interrupts for CPUx. The restore
	254	* code blindly restores secure and non-secure interrupt
	255	* masks from SAR RAM. Secure interrupts are not suppose
	256	* to be enabled from HLOS. So overwrite the SAR location
	257	* so that the secure interrupt remains disabled.
	258	*/
	259	sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
	260	sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	261	}
	262
	263	/* Save AuxBoot* registers */
edfaf05c VK	264	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	265	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
	266	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
	267	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
0f3cf2ec	268
0f3cf2ec	269	/* Save SyncReq generation logic */
edfaf05c VK	270	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
	271	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
	272	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
	273	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
0f3cf2ec SS	274
0f3cf2ec SS	275	/* Set the Backup Bit Mask status */
edfaf05c	276	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
0f3cf2ec	277	val \|= SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	278	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
247c445c SS	279
	280	}
	281
	282	static inline void omap5_irq_save_context(void)
	283	{
	284	u32 i, val;
	285
	286	for (i = 0; i < irq_banks; i++) {
	287	/* Save the CPUx interrupt mask for IRQ 0 to 159 */
	288	val = wakeupgen_readl(i, 0);
	289	sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
	290	val = wakeupgen_readl(i, 1);
	291	sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
	292	sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
	293	sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
	294	}
	295
	296	/* Save AuxBoot* registers */
edfaf05c VK	297	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	298	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
	299	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
	300	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
247c445c SS	301
247c445c SS	302	/* Set the Backup Bit Mask status */
edfaf05c	303	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
247c445c	304	val \|= SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	305	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
247c445c SS	306
	307	}
	308
e1a9e61e DG	309	static inline void am43xx_irq_save_context(void)
	310	{
	311	u32 i;
	312
	313	for (i = 0; i < irq_banks; i++) {
	314	wakeupgen_context[i] = wakeupgen_readl(i, 0);
	315	wakeupgen_writel(0, i, CPU0_ID);
	316	}
	317	}
	318
247c445c SS	319	/*
	320	* Save WakeupGen interrupt context in SAR BANK3. Restore is done by
	321	* ROM code. WakeupGen IP is integrated along with GIC to manage the
	322	* interrupt wakeups from CPU low power states. It manages
	323	* masking/unmasking of Shared peripheral interrupts(SPI). So the
	324	* interrupt enable/disable control should be in sync and consistent
	325	* at WakeupGen and GIC so that interrupts are not lost.
	326	*/
	327	static void irq_save_context(void)
	328	{
c783e6fd NM	329	/* DRA7 has no SAR to save */
	330	if (soc_is_dra7xx())
	331	return;
	332
e1a9e61e DG	333	if (wakeupgen_ops && wakeupgen_ops->save_context)
e1a9e61e DG	334	wakeupgen_ops->save_context();
0f3cf2ec SS	335	}
	336
	337	/*
	338	* Clear WakeupGen SAR backup status.
	339	*/
8c3d4534	340	static void irq_sar_clear(void)
0f3cf2ec SS	341	{
0f3cf2ec SS	342	u32 val;
247c445c	343	u32 offset = SAR_BACKUP_STATUS_OFFSET;
c783e6fd NM	344	/* DRA7 has no SAR to save */
	345	if (soc_is_dra7xx())
	346	return;
247c445c SS	347
	348	if (soc_is_omap54xx())
	349	offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
	350
edfaf05c	351	val = readl_relaxed(sar_base + offset);
0f3cf2ec	352	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
edfaf05c	353	writel_relaxed(val, sar_base + offset);
0f3cf2ec SS	354	}
0f3cf2ec SS	355
e1a9e61e DG	356	static void am43xx_irq_restore_context(void)
	357	{
	358	u32 i;
	359
	360	for (i = 0; i < irq_banks; i++)
	361	wakeupgen_writel(wakeupgen_context[i], i, CPU0_ID);
	362	}
	363
	364	static void irq_restore_context(void)
	365	{
	366	if (wakeupgen_ops && wakeupgen_ops->restore_context)
	367	wakeupgen_ops->restore_context();
	368	}
	369
0f3cf2ec SS	370	/*
	371	* Save GIC and Wakeupgen interrupt context using secure API
	372	* for HS/EMU devices.
	373	*/
	374	static void irq_save_secure_context(void)
	375	{
	376	u32 ret;
	377	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
	378	FLAG_START_CRITICAL,
	379	0, 0, 0, 0, 0);
	380	if (ret != API_HAL_RET_VALUE_OK)
	381	pr_err("GIC and Wakeupgen context save failed\n");
	382	}
e1a9e61e DG	383
	384	/* Define ops for context save and restore for each SoC */
	385	static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {
	386	.save_context = omap4_irq_save_context,
	387	.restore_context = irq_sar_clear,
	388	};
	389
	390	static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {
	391	.save_context = omap5_irq_save_context,
	392	.restore_context = irq_sar_clear,
	393	};
	394
	395	static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {
	396	.save_context = am43xx_irq_save_context,
	397	.restore_context = am43xx_irq_restore_context,
	398	};
	399	#else
	400	static struct omap_wakeupgen_ops omap4_wakeupgen_ops = {};
	401	static struct omap_wakeupgen_ops omap5_wakeupgen_ops = {};
	402	static struct omap_wakeupgen_ops am43xx_wakeupgen_ops = {};
0f3cf2ec SS	403	#endif
0f3cf2ec SS	404
b5b4f288	405	#ifdef CONFIG_HOTPLUG_CPU
a4fa9cc2	406	static int omap_wakeupgen_cpu_online(unsigned int cpu)
b5b4f288	407	{
a4fa9cc2 SAS	408	wakeupgen_irqmask_all(cpu, 0);
a4fa9cc2 SAS	409	return 0;
b5b4f288 SS	410	}
b5b4f288 SS	411
a4fa9cc2 SAS	412	static int omap_wakeupgen_cpu_dead(unsigned int cpu)
	413	{
	414	wakeupgen_irqmask_all(cpu, 1);
	415	return 0;
	416	}
b5b4f288 SS	417
	418	static void __init irq_hotplug_init(void)
	419	{
a4fa9cc2 SAS	420	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "arm/omap-wake:online",
	421	omap_wakeupgen_cpu_online, NULL);
	422	cpuhp_setup_state_nocalls(CPUHP_ARM_OMAP_WAKE_DEAD,
	423	"arm/omap-wake:dead", NULL,
	424	omap_wakeupgen_cpu_dead);
b5b4f288 SS	425	}
	426	#else
	427	static void __init irq_hotplug_init(void)
	428	{}
	429	#endif
	430
0f3cf2ec SS	431	#ifdef CONFIG_CPU_PM
	432	static int irq_notifier(struct notifier_block self, unsigned long cmd, void v)
	433	{
	434	switch (cmd) {
	435	case CPU_CLUSTER_PM_ENTER:
f8033678	436	if (omap_type() == OMAP2_DEVICE_TYPE_GP \|\| soc_is_am43xx())
0f3cf2ec SS	437	irq_save_context();
	438	else
	439	irq_save_secure_context();
	440	break;
	441	case CPU_CLUSTER_PM_EXIT:
f8033678	442	if (omap_type() == OMAP2_DEVICE_TYPE_GP \|\| soc_is_am43xx())
e1a9e61e	443	irq_restore_context();
0f3cf2ec SS	444	break;
	445	}
	446	return NOTIFY_OK;
	447	}
	448
	449	static struct notifier_block irq_notifier_block = {
	450	.notifier_call = irq_notifier,
	451	};
	452
	453	static void __init irq_pm_init(void)
	454	{
247c445c	455	/* FIXME: Remove this when MPU OSWR support is added */
6099dd37	456	if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
247c445c	457	cpu_pm_register_notifier(&irq_notifier_block);
0f3cf2ec SS	458	}
	459	#else
	460	static void __init irq_pm_init(void)
	461	{}
	462	#endif
	463
247c445c SS	464	void __iomem *omap_get_wakeupgen_base(void)
	465	{
	466	return wakeupgen_base;
	467	}
	468
	469	int omap_secure_apis_support(void)
	470	{
	471	return omap_secure_apis;
	472	}
	473
7136d457 MZ	474	static struct irq_chip wakeupgen_chip = {
	475	.name = "WUGEN",
	476	.irq_eoi = irq_chip_eoi_parent,
	477	.irq_mask = wakeupgen_mask,
	478	.irq_unmask = wakeupgen_unmask,
	479	.irq_retrigger = irq_chip_retrigger_hierarchy,
d0243693	480	.irq_set_type = wakeupgen_irq_set_type,
7136d457 MZ	481	.flags = IRQCHIP_SKIP_SET_WAKE \| IRQCHIP_MASK_ON_SUSPEND,
	482	#ifdef CONFIG_SMP
	483	.irq_set_affinity = irq_chip_set_affinity_parent,
	484	#endif
	485	};
	486
f833f57f MZ	487	static int wakeupgen_domain_translate(struct irq_domain *d,
	488	struct irq_fwspec *fwspec,
	489	unsigned long *hwirq,
	490	unsigned int *type)
7136d457	491	{
f833f57f MZ	492	if (is_of_node(fwspec->fwnode)) {
	493	if (fwspec->param_count != 3)
	494	return -EINVAL;
7136d457	495
f833f57f MZ	496	/* No PPI should point to this domain */
	497	if (fwspec->param[0] != 0)
	498	return -EINVAL;
	499
	500	*hwirq = fwspec->param[1];
	501	*type = fwspec->param[2];
	502	return 0;
	503	}
	504
	505	return -EINVAL;
7136d457 MZ	506	}
	507
	508	static int wakeupgen_domain_alloc(struct irq_domain *domain,
	509	unsigned int virq,
	510	unsigned int nr_irqs, void *data)
	511	{
f833f57f MZ	512	struct irq_fwspec *fwspec = data;
f833f57f MZ	513	struct irq_fwspec parent_fwspec;
7136d457 MZ	514	irq_hw_number_t hwirq;
	515	int i;
	516
f833f57f	517	if (fwspec->param_count != 3)
7136d457	518	return -EINVAL; /* Not GIC compliant */
f833f57f	519	if (fwspec->param[0] != 0)
7136d457 MZ	520	return -EINVAL; /* No PPI should point to this domain */
7136d457 MZ	521
f833f57f	522	hwirq = fwspec->param[1];
7136d457 MZ	523	if (hwirq >= MAX_IRQS)
	524	return -EINVAL; /* Can't deal with this */
	525
	526	for (i = 0; i < nr_irqs; i++)
	527	irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
	528	&wakeupgen_chip, NULL);
	529
f833f57f MZ	530	parent_fwspec = *fwspec;
	531	parent_fwspec.fwnode = domain->parent->fwnode;
	532	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
	533	&parent_fwspec);
7136d457 MZ	534	}
7136d457 MZ	535
8297955f	536	static const struct irq_domain_ops wakeupgen_domain_ops = {
f833f57f MZ	537	.translate = wakeupgen_domain_translate,
	538	.alloc = wakeupgen_domain_alloc,
	539	.free = irq_domain_free_irqs_common,
7136d457 MZ	540	};
7136d457 MZ	541
fcf6efa3 SS	542	/*
	543	* Initialise the wakeupgen module.
	544	*/
7136d457 MZ	545	static int __init wakeupgen_init(struct device_node *node,
7136d457 MZ	546	struct device_node *parent)
fcf6efa3	547	{
7136d457	548	struct irq_domain parent_domain, domain;
fcf6efa3 SS	549	int i;
fcf6efa3 SS	550	unsigned int boot_cpu = smp_processor_id();
4664d4d8	551	u32 val;
fcf6efa3	552
7136d457	553	if (!parent) {
a8e65e06	554	pr_err("%pOF: no parent, giving up\n", node);
7136d457 MZ	555	return -ENODEV;
	556	}
	557
	558	parent_domain = irq_find_host(parent);
	559	if (!parent_domain) {
a8e65e06	560	pr_err("%pOF: unable to obtain parent domain\n", node);
7136d457 MZ	561	return -ENXIO;
7136d457 MZ	562	}
fcf6efa3 SS	563	/* Not supported on OMAP4 ES1.0 silicon */
	564	if (omap_rev() == OMAP4430_REV_ES1_0) {
	565	WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
	566	return -EPERM;
	567	}
	568
	569	/* Static mapping, never released */
7136d457	570	wakeupgen_base = of_iomap(node, 0);
fcf6efa3 SS	571	if (WARN_ON(!wakeupgen_base))
	572	return -ENOMEM;
	573
247c445c SS	574	if (cpu_is_omap44xx()) {
	575	irq_banks = OMAP4_NR_BANKS;
	576	max_irqs = OMAP4_NR_IRQS;
	577	omap_secure_apis = 1;
e1a9e61e DG	578	wakeupgen_ops = &omap4_wakeupgen_ops;
	579	} else if (soc_is_omap54xx()) {
	580	wakeupgen_ops = &omap5_wakeupgen_ops;
6246cd06 AM	581	} else if (soc_is_am43xx()) {
	582	irq_banks = AM43XX_NR_REG_BANKS;
	583	max_irqs = AM43XX_IRQS;
e1a9e61e	584	wakeupgen_ops = &am43xx_wakeupgen_ops;
247c445c SS	585	}
247c445c SS	586
7136d457 MZ	587	domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
	588	node, &wakeupgen_domain_ops,
	589	NULL);
	590	if (!domain) {
	591	iounmap(wakeupgen_base);
	592	return -ENOMEM;
	593	}
	594
fcf6efa3	595	/* Clear all IRQ bitmasks at wakeupGen level */
247c445c	596	for (i = 0; i < irq_banks; i++) {
fcf6efa3	597	wakeupgen_writel(0, i, CPU0_ID);
6246cd06 AM	598	if (!soc_is_am43xx())
6246cd06 AM	599	wakeupgen_writel(0, i, CPU1_ID);
fcf6efa3 SS	600	}
fcf6efa3 SS	601
fcf6efa3 SS	602	/*
	603	* FIXME: Add support to set_smp_affinity() once the core
	604	* GIC code has necessary hooks in place.
	605	*/
	606
	607	/* Associate all the IRQs to boot CPU like GIC init does. */
247c445c	608	for (i = 0; i < max_irqs; i++)
fcf6efa3 SS	609	irq_target_cpu[i] = boot_cpu;
fcf6efa3 SS	610
4664d4d8 SS	611	/*
	612	* Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
	613	* 0x0: ES1 behavior, CPU cores would enter and exit OFF mode together.
	614	* 0x1: ES2 behavior, CPU cores are allowed to enter/exit OFF mode
	615	* independently.
	616	* This needs to be set one time thanks to always ON domain.
	617	*
	618	* We do not support ES1 behavior anymore. OMAP5 is assumed to be
	619	* ES2.0, and the same is applicable for DRA7.
	620	*/
	621	if (soc_is_omap54xx() \|\| soc_is_dra7xx()) {
	622	val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
	623	val \|= BIT(5);
	624	omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
	625	}
	626
b5b4f288	627	irq_hotplug_init();
0f3cf2ec	628	irq_pm_init();
b5b4f288	629
fe27f167 TL	630	sar_base = omap4_get_sar_ram_base();
fe27f167 TL	631
fcf6efa3 SS	632	return 0;
fcf6efa3 SS	633	}
0cc09e85	634	IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);