[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / omap4-common.c

/*
 * OMAP4 specific common source file.
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Author:
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/memblock.h>

#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/memblock.h>

#include <plat/irqs.h>
#include <plat/sram.h>
#include <plat/omap-secure.h>
#include <plat/mmc.h>

#include <mach/hardware.h>
#include <mach/omap-wakeupgen.h>

#include "common.h"
#include "hsmmc.h"
#include "omap4-sar-layout.h"
#include <linux/export.h>

#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;
#endif

static void __iomem *sar_ram_base;

#ifdef CONFIG_OMAP4_ERRATA_I688
/* Used to implement memory barrier on DRAM path */
#define OMAP4_DRAM_BARRIER_VA			0xfe600000

void __iomem *dram_sync, *sram_sync;

static phys_addr_t paddr;
static u32 size;

void omap_bus_sync(void)
{
	if (dram_sync && sram_sync) {
		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
		isb();
	}
}
EXPORT_SYMBOL(omap_bus_sync);

/* Steal one page physical memory for barrier implementation */
int __init omap_barrier_reserve_memblock(void)
{

	size = ALIGN(PAGE_SIZE, SZ_1M);
	paddr = arm_memblock_steal(size, SZ_1M);

	return 0;
}

void __init omap_barriers_init(void)
{
	struct map_desc dram_io_desc[1];

	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	dram_io_desc[0].length = size;
	dram_io_desc[0].type = MT_MEMORY_SO;
	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	sram_sync = (void __iomem *) OMAP4_SRAM_VA;

	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
		(long long) paddr, dram_io_desc[0].virtual);

}
#else
void __init omap_barriers_init(void)
{}
#endif

void __init gic_init_irq(void)
{
	void __iomem *omap_irq_base;
	void __iomem *gic_dist_base_addr;

	/* Static mapping, never released */
	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	BUG_ON(!gic_dist_base_addr);

	/* Static mapping, never released */
	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
	BUG_ON(!omap_irq_base);

	omap_wakeupgen_init();

	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}

#ifdef CONFIG_CACHE_L2X0

void __iomem *omap4_get_l2cache_base(void)
{
	return l2cache_base;
}

static void omap4_l2x0_disable(void)
{
	/* Disable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x0);
}

static void omap4_l2x0_set_debug(unsigned long val)
{
	/* Program PL310 L2 Cache controller debug register */
	omap_smc1(0x100, val);
}

static int __init omap_l2_cache_init(void)
{
	u32 aux_ctrl = 0;

	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENODEV;

	/* Static mapping, never released */
	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
	if (WARN_ON(!l2cache_base))
		return -ENOMEM;

	/*
	 * 16-way associativity, parity disabled
	 * Way size - 32KB (es1.0)
	 * Way size - 64KB (es2.0 +)
	 */
	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
			(0x1 << 25) |
			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
	} else {
		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
	}
	if (omap_rev() != OMAP4430_REV_ES1_0)
		omap_smc1(0x109, aux_ctrl);

	/* Enable PL310 L2 Cache controller */
	omap_smc1(0x102, 0x1);

	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);

	/*
	 * Override default outer_cache.disable with a OMAP4
	 * specific one
	*/
	outer_cache.disable = omap4_l2x0_disable;
	outer_cache.set_debug = omap4_l2x0_set_debug;

	return 0;
}
early_initcall(omap_l2_cache_init);
#endif

void __iomem *omap4_get_sar_ram_base(void)
{
	return sar_ram_base;
}

/*
 * SAR RAM used to save and restore the HW
 * context in low power modes
 */
static int __init omap4_sar_ram_init(void)
{
	/*
	 * To avoid code running on other OMAPs in
	 * multi-omap builds
	 */
	if (!cpu_is_omap44xx())
		return -ENOMEM;

	/* Static mapping, never released */
	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	if (WARN_ON(!sar_ram_base))
		return -ENOMEM;

	return 0;
}
early_initcall(omap4_sar_ram_init);

#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
{
	int irq = 0;
	struct platform_device *pdev = container_of(dev,
				struct platform_device, dev);
	struct omap_mmc_platform_data *pdata = dev->platform_data;

	/* Setting MMC1 Card detect Irq */
	if (pdev->id == 0) {
		irq = twl6030_mmc_card_detect_config();
		if (irq < 0) {
			dev_err(dev, "%s: Error card detect config(%d)\n",
				__func__, irq);
			return irq;
		}
		pdata->slots[0].card_detect_irq = irq;
		pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	}
	return 0;
}

static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
{
	struct omap_mmc_platform_data *pdata;

	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	if (!dev) {
		pr_err("Failed %s\n", __func__);
		return;
	}
	pdata = dev->platform_data;
	pdata->init =	omap4_twl6030_hsmmc_late_init;
}

int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	struct omap2_hsmmc_info *c;

	omap_hsmmc_init(controllers);
	for (c = controllers; c->mmc; c++) {
		/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
		if (!c->pdev)
			continue;
		omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	}

	return 0;
}
#else
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
	return 0;
}
#endif
Commit	Line	Data
fbc9be10 SS	1	/*
	2	* OMAP4 specific common source file.
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Author:
	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	7	*
	8	*
	9	* This program is free software,you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/io.h>
	17	#include <linux/platform_device.h>
137d105d	18	#include <linux/memblock.h>
fbc9be10 SS	19
	20	#include <asm/hardware/gic.h>
	21	#include <asm/hardware/cache-l2x0.h>
137d105d	22	#include <asm/mach/map.h>
716a3dc2	23	#include <asm/memblock.h>
fbc9be10	24
741e3a89	25	#include <plat/irqs.h>
137d105d	26	#include <plat/sram.h>
2ec1fc4e	27	#include <plat/omap-secure.h>
1ee47b0a	28	#include <plat/mmc.h>
741e3a89	29
fbc9be10	30	#include <mach/hardware.h>
fcf6efa3	31	#include <mach/omap-wakeupgen.h>
4e65331c TL	32
4e65331c TL	33	#include "common.h"
1ee47b0a	34	#include "hsmmc.h"
501f0c75	35	#include "omap4-sar-layout.h"
cc4ad907	36	#include <linux/export.h>
fbc9be10 SS	37
fbc9be10 SS	38	#ifdef CONFIG_CACHE_L2X0
02afe8a7	39	static void __iomem *l2cache_base;
fbc9be10 SS	40	#endif
fbc9be10 SS	41
501f0c75 SS	42	static void __iomem *sar_ram_base;
501f0c75 SS	43
137d105d SS	44	#ifdef CONFIG_OMAP4_ERRATA_I688
	45	/* Used to implement memory barrier on DRAM path */
	46	#define OMAP4_DRAM_BARRIER_VA 0xfe600000
	47
	48	void __iomem dram_sync, sram_sync;
	49
2ec1fc4e SS	50	static phys_addr_t paddr;
	51	static u32 size;
	52
137d105d SS	53	void omap_bus_sync(void)
	54	{
	55	if (dram_sync && sram_sync) {
	56	writel_relaxed(readl_relaxed(dram_sync), dram_sync);
	57	writel_relaxed(readl_relaxed(sram_sync), sram_sync);
	58	isb();
	59	}
	60	}
cc4ad907	61	EXPORT_SYMBOL(omap_bus_sync);
137d105d	62
2ec1fc4e SS	63	/* Steal one page physical memory for barrier implementation */
2ec1fc4e SS	64	int __init omap_barrier_reserve_memblock(void)
137d105d	65	{
137d105d SS	66
137d105d SS	67	size = ALIGN(PAGE_SIZE, SZ_1M);
716a3dc2 RK	68	paddr = arm_memblock_steal(size, SZ_1M);
716a3dc2 RK	69
2ec1fc4e SS	70	return 0;
	71	}
	72
	73	void __init omap_barriers_init(void)
	74	{
	75	struct map_desc dram_io_desc[1];
	76
137d105d SS	77	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
	78	dram_io_desc[0].pfn = __phys_to_pfn(paddr);
	79	dram_io_desc[0].length = size;
	80	dram_io_desc[0].type = MT_MEMORY_SO;
	81	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
	82	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
	83	sram_sync = (void __iomem *) OMAP4_SRAM_VA;
	84
	85	pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
	86	(long long) paddr, dram_io_desc[0].virtual);
	87
137d105d	88	}
2ec1fc4e SS	89	#else
	90	void __init omap_barriers_init(void)
	91	{}
137d105d SS	92	#endif
137d105d SS	93
fbc9be10 SS	94	void __init gic_init_irq(void)
fbc9be10 SS	95	{
ab65be26 MZ	96	void __iomem *omap_irq_base;
	97	void __iomem *gic_dist_base_addr;
	98
fbc9be10 SS	99	/* Static mapping, never released */
	100	gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
	101	BUG_ON(!gic_dist_base_addr);
fbc9be10 SS	102
fbc9be10 SS	103	/* Static mapping, never released */
741e3a89 TL	104	omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
741e3a89 TL	105	BUG_ON(!omap_irq_base);
b580b899	106
fcf6efa3 SS	107	omap_wakeupgen_init();
fcf6efa3 SS	108
741e3a89	109	gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
fbc9be10 SS	110	}
	111
	112	#ifdef CONFIG_CACHE_L2X0
4e803c40	113
02afe8a7 SS	114	void __iomem *omap4_get_l2cache_base(void)
	115	{
	116	return l2cache_base;
	117	}
	118
4e803c40 SS	119	static void omap4_l2x0_disable(void)
	120	{
	121	/* Disable PL310 L2 Cache controller */
	122	omap_smc1(0x102, 0x0);
	123	}
	124
4bdb1577 SS	125	static void omap4_l2x0_set_debug(unsigned long val)
	126	{
	127	/* Program PL310 L2 Cache controller debug register */
	128	omap_smc1(0x100, val);
	129	}
	130
fbc9be10 SS	131	static int __init omap_l2_cache_init(void)
fbc9be10 SS	132	{
1773e60a SS	133	u32 aux_ctrl = 0;
1773e60a SS	134
fbc9be10 SS	135	/*
	136	* To avoid code running on other OMAPs in
	137	* multi-omap builds
	138	*/
	139	if (!cpu_is_omap44xx())
	140	return -ENODEV;
	141
	142	/* Static mapping, never released */
	143	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
0db1803e SS	144	if (WARN_ON(!l2cache_base))
0db1803e SS	145	return -ENOMEM;
fbc9be10	146
fbc9be10	147	/*
a777b727 SS	148	* 16-way associativity, parity disabled
	149	* Way size - 32KB (es1.0)
	150	* Way size - 64KB (es2.0 +)
fbc9be10	151	*/
1773e60a SS	152	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) \|
	153	(0x1 << 25) \|
	154	(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) \|
	155	(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
	156
11e02640	157	if (omap_rev() == OMAP4430_REV_ES1_0) {
1773e60a	158	aux_ctrl \|= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
11e02640 MR	159	} else {
11e02640 MR	160	aux_ctrl \|= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) \|
b0f20ff9	161	(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) \|
11e02640	162	(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) \|
b89cd71a SS	163	(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) \|
b89cd71a SS	164	(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
11e02640 MR	165	}
	166	if (omap_rev() != OMAP4430_REV_ES1_0)
	167	omap_smc1(0x109, aux_ctrl);
	168
	169	/* Enable PL310 L2 Cache controller */
	170	omap_smc1(0x102, 0x1);
1773e60a SS	171
1773e60a SS	172	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
fbc9be10	173
4e803c40 SS	174	/*
	175	* Override default outer_cache.disable with a OMAP4
	176	* specific one
	177	*/
	178	outer_cache.disable = omap4_l2x0_disable;
4bdb1577	179	outer_cache.set_debug = omap4_l2x0_set_debug;
4e803c40	180
fbc9be10 SS	181	return 0;
	182	}
	183	early_initcall(omap_l2_cache_init);
	184	#endif
501f0c75 SS	185
	186	void __iomem *omap4_get_sar_ram_base(void)
	187	{
	188	return sar_ram_base;
	189	}
	190
	191	/*
	192	* SAR RAM used to save and restore the HW
	193	* context in low power modes
	194	*/
	195	static int __init omap4_sar_ram_init(void)
	196	{
	197	/*
	198	* To avoid code running on other OMAPs in
	199	* multi-omap builds
	200	*/
	201	if (!cpu_is_omap44xx())
	202	return -ENOMEM;
	203
	204	/* Static mapping, never released */
	205	sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
	206	if (WARN_ON(!sar_ram_base))
	207	return -ENOMEM;
	208
	209	return 0;
	210	}
	211	early_initcall(omap4_sar_ram_init);
1ee47b0a B	212
	213	#if defined(CONFIG_MMC_OMAP_HS) \|\| defined(CONFIG_MMC_OMAP_HS_MODULE)
	214	static int omap4_twl6030_hsmmc_late_init(struct device *dev)
	215	{
	216	int irq = 0;
	217	struct platform_device *pdev = container_of(dev,
	218	struct platform_device, dev);
	219	struct omap_mmc_platform_data *pdata = dev->platform_data;
	220
	221	/* Setting MMC1 Card detect Irq */
	222	if (pdev->id == 0) {
	223	irq = twl6030_mmc_card_detect_config();
	224	if (irq < 0) {
	225	dev_err(dev, "%s: Error card detect config(%d)\n",
	226	__func__, irq);
	227	return irq;
	228	}
	229	pdata->slots[0].card_detect_irq = irq;
	230	pdata->slots[0].card_detect = twl6030_mmc_card_detect;
	231	}
	232	return 0;
	233	}
	234
	235	static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
	236	{
	237	struct omap_mmc_platform_data *pdata;
	238
	239	/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
	240	if (!dev) {
	241	pr_err("Failed %s\n", __func__);
	242	return;
	243	}
	244	pdata = dev->platform_data;
	245	pdata->init = omap4_twl6030_hsmmc_late_init;
	246	}
	247
	248	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	249	{
	250	struct omap2_hsmmc_info *c;
	251
	252	omap_hsmmc_init(controllers);
	253	for (c = controllers; c->mmc; c++) {
	254	/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
	255	if (!c->pdev)
	256	continue;
	257	omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
	258	}
	259
	260	return 0;
	261	}
	262	#else
	263	int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
	264	{
	265	return 0;
	266	}
	267	#endif