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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5b00f6f | 133 | #include <linux/clk.h> |
f5dd3bb5 | 134 | #include <linux/clk-provider.h> |
63c85238 PW |
135 | #include <linux/delay.h> |
136 | #include <linux/err.h> | |
137 | #include <linux/list.h> | |
138 | #include <linux/mutex.h> | |
dc6d1cda | 139 | #include <linux/spinlock.h> |
abc2d545 | 140 | #include <linux/slab.h> |
f7b861b7 | 141 | #include <linux/cpu.h> |
079abade SS |
142 | #include <linux/of.h> |
143 | #include <linux/of_address.h> | |
70f05be3 | 144 | #include <linux/bootmem.h> |
63c85238 | 145 | |
fa200222 PW |
146 | #include <asm/system_misc.h> |
147 | ||
a135eaae | 148 | #include "clock.h" |
2a296c8f | 149 | #include "omap_hwmod.h" |
63c85238 | 150 | |
dbc04161 TL |
151 | #include "soc.h" |
152 | #include "common.h" | |
153 | #include "clockdomain.h" | |
154 | #include "powerdomain.h" | |
ff4ae5d9 PW |
155 | #include "cm2xxx.h" |
156 | #include "cm3xxx.h" | |
1688bf19 | 157 | #include "cm33xx.h" |
b13159af | 158 | #include "prm.h" |
139563ad | 159 | #include "prm3xxx.h" |
d198b514 | 160 | #include "prm44xx.h" |
1688bf19 | 161 | #include "prm33xx.h" |
eaac329d | 162 | #include "prminst44xx.h" |
5165882a | 163 | #include "pm.h" |
63c85238 | 164 | |
63c85238 | 165 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 166 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 167 | |
2221b5cd PW |
168 | /* |
169 | * Number of struct omap_hwmod_link records per struct | |
170 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
171 | */ | |
172 | #define LINKS_PER_OCP_IF 2 | |
173 | ||
4ebf5b28 TK |
174 | /* |
175 | * Address offset (in bytes) between the reset control and the reset | |
176 | * status registers: 4 bytes on OMAP4 | |
177 | */ | |
178 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | |
179 | ||
9fabc1a2 TK |
180 | /* |
181 | * Maximum length for module clock handle names | |
182 | */ | |
183 | #define MOD_CLK_MAX_NAME_LEN 32 | |
184 | ||
70f05be3 TK |
185 | /** |
186 | * struct clkctrl_provider - clkctrl provider mapping data | |
187 | * @addr: base address for the provider | |
188 | * @offset: base offset for the provider | |
189 | * @clkdm: base clockdomain for provider | |
190 | * @node: device node associated with the provider | |
191 | * @link: list link | |
192 | */ | |
193 | struct clkctrl_provider { | |
194 | u32 addr; | |
195 | u16 offset; | |
196 | struct clockdomain *clkdm; | |
197 | struct device_node *node; | |
198 | struct list_head link; | |
199 | }; | |
200 | ||
201 | static LIST_HEAD(clkctrl_providers); | |
202 | ||
9ebfd285 KH |
203 | /** |
204 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
205 | * @enable_module: function to enable a module (via MODULEMODE) | |
206 | * @disable_module: function to disable a module (via MODULEMODE) | |
207 | * | |
208 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
209 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
210 | * conditionals in this code. | |
211 | */ | |
212 | struct omap_hwmod_soc_ops { | |
213 | void (*enable_module)(struct omap_hwmod *oh); | |
214 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 215 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
216 | int (*assert_hardreset)(struct omap_hwmod *oh, |
217 | struct omap_hwmod_rst_info *ohri); | |
218 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
219 | struct omap_hwmod_rst_info *ohri); | |
220 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
221 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 222 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
223 | void (*update_context_lost)(struct omap_hwmod *oh); |
224 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9fabc1a2 | 225 | int (*disable_direct_prcm)(struct omap_hwmod *oh); |
70f05be3 TK |
226 | u32 (*xlate_clkctrl)(struct omap_hwmod *oh, |
227 | struct clkctrl_provider *provider); | |
9ebfd285 KH |
228 | }; |
229 | ||
230 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
231 | static struct omap_hwmod_soc_ops soc_ops; | |
232 | ||
63c85238 PW |
233 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
234 | static LIST_HEAD(omap_hwmod_list); | |
235 | ||
63c85238 PW |
236 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
237 | static struct omap_hwmod *mpu_oh; | |
238 | ||
9ebfd285 KH |
239 | /* inited: set to true once the hwmod code is initialized */ |
240 | static bool inited; | |
241 | ||
63c85238 PW |
242 | /* Private functions */ |
243 | ||
244 | /** | |
245 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
246 | * @oh: struct omap_hwmod * | |
247 | * | |
248 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
249 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
250 | * OCP_SYSCONFIG register or 0 upon success. | |
251 | */ | |
252 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
253 | { | |
43b40992 PW |
254 | if (!oh->class->sysc) { |
255 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
256 | return -EINVAL; |
257 | } | |
258 | ||
259 | /* XXX ensure module interface clock is up */ | |
260 | ||
cc7a1d2a | 261 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 262 | |
43b40992 | 263 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 264 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
265 | |
266 | return 0; | |
267 | } | |
268 | ||
269 | /** | |
270 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
271 | * @v: OCP_SYSCONFIG value to write | |
272 | * @oh: struct omap_hwmod * | |
273 | * | |
43b40992 PW |
274 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
275 | * one. No return value. | |
63c85238 PW |
276 | */ |
277 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
278 | { | |
43b40992 PW |
279 | if (!oh->class->sysc) { |
280 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
281 | return; |
282 | } | |
283 | ||
284 | /* XXX ensure module interface clock is up */ | |
285 | ||
233cbe5b RN |
286 | /* Module might have lost context, always update cache and register */ |
287 | oh->_sysc_cache = v; | |
aaf2c0fb LV |
288 | |
289 | /* | |
290 | * Some IP blocks (such as RTC) require unlocking of IP before | |
291 | * accessing its registers. If a function pointer is present | |
292 | * to unlock, then call it before accessing sysconfig and | |
293 | * call lock after writing sysconfig. | |
294 | */ | |
295 | if (oh->class->unlock) | |
296 | oh->class->unlock(oh); | |
297 | ||
233cbe5b | 298 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
aaf2c0fb LV |
299 | |
300 | if (oh->class->lock) | |
301 | oh->class->lock(oh); | |
63c85238 PW |
302 | } |
303 | ||
304 | /** | |
305 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
306 | * @oh: struct omap_hwmod * | |
307 | * @standbymode: MIDLEMODE field bits | |
308 | * @v: pointer to register contents to modify | |
309 | * | |
310 | * Update the master standby mode bits in @v to be @standbymode for | |
311 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
312 | * upon error or 0 upon success. | |
313 | */ | |
314 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
315 | u32 *v) | |
316 | { | |
358f0e63 TG |
317 | u32 mstandby_mask; |
318 | u8 mstandby_shift; | |
319 | ||
43b40992 PW |
320 | if (!oh->class->sysc || |
321 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
322 | return -EINVAL; |
323 | ||
43b40992 PW |
324 | if (!oh->class->sysc->sysc_fields) { |
325 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
326 | return -EINVAL; |
327 | } | |
328 | ||
43b40992 | 329 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
330 | mstandby_mask = (0x3 << mstandby_shift); |
331 | ||
332 | *v &= ~mstandby_mask; | |
333 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
338 | /** | |
339 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
340 | * @oh: struct omap_hwmod * | |
341 | * @idlemode: SIDLEMODE field bits | |
342 | * @v: pointer to register contents to modify | |
343 | * | |
344 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
345 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
346 | * or 0 upon success. | |
347 | */ | |
348 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
349 | { | |
358f0e63 TG |
350 | u32 sidle_mask; |
351 | u8 sidle_shift; | |
352 | ||
43b40992 PW |
353 | if (!oh->class->sysc || |
354 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
355 | return -EINVAL; |
356 | ||
43b40992 PW |
357 | if (!oh->class->sysc->sysc_fields) { |
358 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
359 | return -EINVAL; |
360 | } | |
361 | ||
43b40992 | 362 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
363 | sidle_mask = (0x3 << sidle_shift); |
364 | ||
365 | *v &= ~sidle_mask; | |
366 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
367 | |
368 | return 0; | |
369 | } | |
370 | ||
371 | /** | |
372 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
373 | * @oh: struct omap_hwmod * | |
374 | * @clockact: CLOCKACTIVITY field bits | |
375 | * @v: pointer to register contents to modify | |
376 | * | |
377 | * Update the clockactivity mode bits in @v to be @clockact for the | |
378 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
379 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
380 | * success. | |
381 | */ | |
382 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
383 | { | |
358f0e63 TG |
384 | u32 clkact_mask; |
385 | u8 clkact_shift; | |
386 | ||
43b40992 PW |
387 | if (!oh->class->sysc || |
388 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
389 | return -EINVAL; |
390 | ||
43b40992 PW |
391 | if (!oh->class->sysc->sysc_fields) { |
392 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
393 | return -EINVAL; |
394 | } | |
395 | ||
43b40992 | 396 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
397 | clkact_mask = (0x3 << clkact_shift); |
398 | ||
399 | *v &= ~clkact_mask; | |
400 | *v |= clockact << clkact_shift; | |
63c85238 PW |
401 | |
402 | return 0; | |
403 | } | |
404 | ||
405 | /** | |
313a76ee | 406 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
407 | * @oh: struct omap_hwmod * |
408 | * @v: pointer to register contents to modify | |
409 | * | |
410 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
411 | * error or 0 upon success. | |
412 | */ | |
413 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
414 | { | |
358f0e63 TG |
415 | u32 softrst_mask; |
416 | ||
43b40992 PW |
417 | if (!oh->class->sysc || |
418 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
419 | return -EINVAL; |
420 | ||
43b40992 PW |
421 | if (!oh->class->sysc->sysc_fields) { |
422 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
423 | return -EINVAL; |
424 | } | |
425 | ||
43b40992 | 426 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
427 | |
428 | *v |= softrst_mask; | |
63c85238 PW |
429 | |
430 | return 0; | |
431 | } | |
432 | ||
313a76ee RQ |
433 | /** |
434 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
435 | * @oh: struct omap_hwmod * | |
436 | * @v: pointer to register contents to modify | |
437 | * | |
438 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
439 | * error or 0 upon success. | |
440 | */ | |
441 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
442 | { | |
443 | u32 softrst_mask; | |
444 | ||
445 | if (!oh->class->sysc || | |
446 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
447 | return -EINVAL; | |
448 | ||
449 | if (!oh->class->sysc->sysc_fields) { | |
450 | WARN(1, | |
451 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
452 | oh->name); | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
456 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
457 | ||
458 | *v &= ~softrst_mask; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
613ad0e9 TK |
463 | /** |
464 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
465 | * @oh: struct omap_hwmod * to wait on | |
466 | * | |
467 | * Wait until the IP block represented by @oh reports that its OCP | |
468 | * softreset is complete. This can be triggered by software (see | |
469 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
470 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
471 | * microseconds. Returns the number of microseconds waited. | |
472 | */ | |
473 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
474 | { | |
475 | struct omap_hwmod_class_sysconfig *sysc; | |
476 | u32 softrst_mask; | |
477 | int c = 0; | |
478 | ||
479 | sysc = oh->class->sysc; | |
480 | ||
481 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS) | |
482 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) | |
483 | & SYSS_RESETDONE_MASK), | |
484 | MAX_MODULE_SOFTRESET_WAIT, c); | |
485 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
486 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
487 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
488 | & softrst_mask), | |
489 | MAX_MODULE_SOFTRESET_WAIT, c); | |
490 | } | |
491 | ||
492 | return c; | |
493 | } | |
494 | ||
6668546f KVA |
495 | /** |
496 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
497 | * @oh: struct omap_hwmod * | |
498 | * | |
499 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
500 | * of some modules. When the DMA must perform read/write accesses, the | |
501 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
502 | * for power management, software must set the DMADISABLE bit back to 1. | |
503 | * | |
504 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
505 | * error or 0 upon success. | |
506 | */ | |
507 | static int _set_dmadisable(struct omap_hwmod *oh) | |
508 | { | |
509 | u32 v; | |
510 | u32 dmadisable_mask; | |
511 | ||
512 | if (!oh->class->sysc || | |
513 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
514 | return -EINVAL; | |
515 | ||
516 | if (!oh->class->sysc->sysc_fields) { | |
517 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
518 | return -EINVAL; | |
519 | } | |
520 | ||
521 | /* clocks must be on for this operation */ | |
522 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
523 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
528 | ||
529 | v = oh->_sysc_cache; | |
530 | dmadisable_mask = | |
531 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
532 | v |= dmadisable_mask; | |
533 | _write_sysconfig(v, oh); | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
726072e5 PW |
538 | /** |
539 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
540 | * @oh: struct omap_hwmod * | |
541 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
542 | * @v: pointer to register contents to modify | |
543 | * | |
544 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
545 | * hwmod. The autoidle bit controls whether the module can gate | |
546 | * internal clocks automatically when it isn't doing anything; the | |
547 | * exact function of this bit varies on a per-module basis. This | |
548 | * function does not write to the hardware. Returns -EINVAL upon | |
549 | * error or 0 upon success. | |
550 | */ | |
551 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
552 | u32 *v) | |
553 | { | |
358f0e63 TG |
554 | u32 autoidle_mask; |
555 | u8 autoidle_shift; | |
556 | ||
43b40992 PW |
557 | if (!oh->class->sysc || |
558 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
559 | return -EINVAL; |
560 | ||
43b40992 PW |
561 | if (!oh->class->sysc->sysc_fields) { |
562 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
563 | return -EINVAL; |
564 | } | |
565 | ||
43b40992 | 566 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 567 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
568 | |
569 | *v &= ~autoidle_mask; | |
570 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
571 | |
572 | return 0; | |
573 | } | |
574 | ||
63c85238 PW |
575 | /** |
576 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
577 | * @oh: struct omap_hwmod * | |
578 | * | |
579 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
580 | * upon error or 0 upon success. | |
581 | */ | |
5a7ddcbd | 582 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 583 | { |
43b40992 | 584 | if (!oh->class->sysc || |
86009eb3 | 585 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
586 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
587 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
588 | return -EINVAL; |
589 | ||
43b40992 PW |
590 | if (!oh->class->sysc->sysc_fields) { |
591 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
592 | return -EINVAL; |
593 | } | |
594 | ||
1fe74113 BC |
595 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
596 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 597 | |
86009eb3 BC |
598 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
599 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
600 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
601 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 602 | |
63c85238 PW |
603 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
604 | ||
63c85238 PW |
605 | return 0; |
606 | } | |
607 | ||
608 | /** | |
609 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
610 | * @oh: struct omap_hwmod * | |
611 | * | |
612 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
613 | * upon error or 0 upon success. | |
614 | */ | |
5a7ddcbd | 615 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 616 | { |
43b40992 | 617 | if (!oh->class->sysc || |
86009eb3 | 618 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
619 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
620 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
621 | return -EINVAL; |
622 | ||
43b40992 PW |
623 | if (!oh->class->sysc->sysc_fields) { |
624 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
625 | return -EINVAL; |
626 | } | |
627 | ||
1fe74113 BC |
628 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
629 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 630 | |
86009eb3 BC |
631 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
632 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 633 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 634 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 635 | |
63c85238 PW |
636 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
637 | ||
63c85238 PW |
638 | return 0; |
639 | } | |
640 | ||
f5dd3bb5 RN |
641 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
642 | { | |
c4a1ea2c RN |
643 | struct clk_hw_omap *clk; |
644 | ||
f5dd3bb5 RN |
645 | if (oh->clkdm) { |
646 | return oh->clkdm; | |
647 | } else if (oh->_clk) { | |
924f9498 TK |
648 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
649 | return NULL; | |
f5dd3bb5 RN |
650 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
651 | return clk->clkdm; | |
f5dd3bb5 RN |
652 | } |
653 | return NULL; | |
654 | } | |
655 | ||
63c85238 PW |
656 | /** |
657 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
658 | * @oh: struct omap_hwmod * | |
659 | * | |
660 | * Prevent the hardware module @oh from entering idle while the | |
661 | * hardare module initiator @init_oh is active. Useful when a module | |
662 | * will be accessed by a particular initiator (e.g., if a module will | |
663 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
664 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
665 | * mode. If the clockdomain is marked as not needing autodeps, return |
666 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
667 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
668 | */ |
669 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
670 | { | |
f5dd3bb5 RN |
671 | struct clockdomain *clkdm, *init_clkdm; |
672 | ||
673 | clkdm = _get_clkdm(oh); | |
674 | init_clkdm = _get_clkdm(init_oh); | |
675 | ||
676 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
677 | return -EINVAL; |
678 | ||
f5dd3bb5 | 679 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
680 | return 0; |
681 | ||
f5dd3bb5 | 682 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
683 | } |
684 | ||
685 | /** | |
686 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
687 | * @oh: struct omap_hwmod * | |
688 | * | |
689 | * Allow the hardware module @oh to enter idle while the hardare | |
690 | * module initiator @init_oh is active. Useful when a module will not | |
691 | * be accessed by a particular initiator (e.g., if a module will not | |
692 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
693 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
694 | * mode. If the clockdomain is marked as not needing autodeps, return |
695 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
696 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
697 | */ |
698 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
699 | { | |
f5dd3bb5 RN |
700 | struct clockdomain *clkdm, *init_clkdm; |
701 | ||
702 | clkdm = _get_clkdm(oh); | |
703 | init_clkdm = _get_clkdm(init_oh); | |
704 | ||
705 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
706 | return -EINVAL; |
707 | ||
f5dd3bb5 | 708 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
709 | return 0; |
710 | ||
f5dd3bb5 | 711 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
712 | } |
713 | ||
70f05be3 TK |
714 | static const struct of_device_id ti_clkctrl_match_table[] __initconst = { |
715 | { .compatible = "ti,clkctrl" }, | |
716 | { } | |
717 | }; | |
718 | ||
719 | static int _match_clkdm(struct clockdomain *clkdm, void *user) | |
720 | { | |
721 | struct clkctrl_provider *provider = user; | |
722 | ||
723 | if (clkdm_xlate_address(clkdm) == provider->addr) { | |
724 | pr_debug("%s: Matched clkdm %s for addr %x (%s)\n", __func__, | |
725 | clkdm->name, provider->addr, | |
726 | provider->node->parent->name); | |
727 | provider->clkdm = clkdm; | |
728 | ||
729 | return -1; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | static int _setup_clkctrl_provider(struct device_node *np) | |
736 | { | |
737 | const __be32 *addrp; | |
738 | struct clkctrl_provider *provider; | |
739 | ||
740 | provider = memblock_virt_alloc(sizeof(*provider), 0); | |
741 | if (!provider) | |
742 | return -ENOMEM; | |
743 | ||
744 | addrp = of_get_address(np, 0, NULL, NULL); | |
745 | provider->addr = (u32)of_translate_address(np, addrp); | |
746 | provider->offset = provider->addr & 0xff; | |
747 | provider->addr &= ~0xff; | |
748 | provider->node = np; | |
749 | ||
750 | clkdm_for_each(_match_clkdm, provider); | |
751 | ||
752 | if (!provider->clkdm) { | |
753 | pr_err("%s: nothing matched for node %s (%x)\n", | |
754 | __func__, np->parent->name, provider->addr); | |
755 | memblock_free_early(__pa(provider), sizeof(*provider)); | |
756 | return -EINVAL; | |
757 | } | |
758 | ||
759 | list_add(&provider->link, &clkctrl_providers); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static int _init_clkctrl_providers(void) | |
765 | { | |
766 | struct device_node *np; | |
767 | int ret = 0; | |
768 | ||
769 | for_each_matching_node(np, ti_clkctrl_match_table) { | |
770 | ret = _setup_clkctrl_provider(np); | |
771 | if (ret) | |
772 | break; | |
773 | } | |
774 | ||
775 | return ret; | |
776 | } | |
777 | ||
778 | static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh, | |
779 | struct clkctrl_provider *provider) | |
780 | { | |
781 | return oh->prcm.omap4.clkctrl_offs - | |
782 | provider->offset - provider->clkdm->clkdm_offs; | |
783 | } | |
784 | ||
785 | static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) | |
786 | { | |
787 | struct clkctrl_provider *provider; | |
788 | struct clk *clk; | |
789 | ||
790 | if (!soc_ops.xlate_clkctrl) | |
791 | return NULL; | |
792 | ||
793 | list_for_each_entry(provider, &clkctrl_providers, link) { | |
794 | if (provider->clkdm == oh->clkdm) { | |
795 | struct of_phandle_args clkspec; | |
796 | ||
797 | clkspec.np = provider->node; | |
798 | clkspec.args_count = 2; | |
799 | clkspec.args[0] = soc_ops.xlate_clkctrl(oh, provider); | |
800 | clkspec.args[1] = 0; | |
801 | ||
802 | clk = of_clk_get_from_provider(&clkspec); | |
803 | ||
804 | return clk; | |
805 | } | |
806 | } | |
807 | ||
808 | return NULL; | |
809 | } | |
810 | ||
63c85238 PW |
811 | /** |
812 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
813 | * @oh: struct omap_hwmod * | |
814 | * | |
815 | * Called from _init_clocks(). Populates the @oh _clk (main | |
9fabc1a2 TK |
816 | * functional clock pointer) if a clock matching the hwmod name is found, |
817 | * or a main_clk is present. Returns 0 on success or -EINVAL on error. | |
63c85238 PW |
818 | */ |
819 | static int _init_main_clk(struct omap_hwmod *oh) | |
820 | { | |
63c85238 | 821 | int ret = 0; |
70f05be3 | 822 | struct clk *clk = NULL; |
63c85238 | 823 | |
70f05be3 | 824 | clk = _lookup_clkctrl_clk(oh); |
9fabc1a2 | 825 | |
70f05be3 TK |
826 | if (!IS_ERR_OR_NULL(clk)) { |
827 | pr_debug("%s: mapped main_clk %s for %s\n", __func__, | |
828 | __clk_get_name(clk), oh->name); | |
829 | oh->main_clk = __clk_get_name(clk); | |
9fabc1a2 TK |
830 | oh->_clk = clk; |
831 | soc_ops.disable_direct_prcm(oh); | |
9fabc1a2 TK |
832 | } else { |
833 | if (!oh->main_clk) | |
834 | return 0; | |
835 | ||
836 | oh->_clk = clk_get(NULL, oh->main_clk); | |
837 | } | |
63c85238 | 838 | |
6ea74cb9 | 839 | if (IS_ERR(oh->_clk)) { |
3d0cb73e JP |
840 | pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
841 | oh->name, oh->main_clk); | |
63403384 | 842 | return -EINVAL; |
dc75925d | 843 | } |
4d7cb45e RN |
844 | /* |
845 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
846 | * to do something meaningful. Today its just a no-op. | |
847 | * If clk_prepare() is used at some point to do things like | |
848 | * voltage scaling etc, then this would have to be moved to | |
849 | * some point where subsystems like i2c and pmic become | |
850 | * available. | |
851 | */ | |
852 | clk_prepare(oh->_clk); | |
63c85238 | 853 | |
f5dd3bb5 | 854 | if (!_get_clkdm(oh)) |
3bb05dbf | 855 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 856 | oh->name, oh->main_clk); |
81d7c6ff | 857 | |
63c85238 PW |
858 | return ret; |
859 | } | |
860 | ||
861 | /** | |
887adeac | 862 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
863 | * @oh: struct omap_hwmod * |
864 | * | |
865 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
866 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
867 | */ | |
868 | static int _init_interface_clks(struct omap_hwmod *oh) | |
869 | { | |
5d95dde7 | 870 | struct omap_hwmod_ocp_if *os; |
63c85238 | 871 | struct clk *c; |
63c85238 PW |
872 | int ret = 0; |
873 | ||
b8e1bddc | 874 | list_for_each_entry(os, &oh->slave_ports, node) { |
50ebdac2 | 875 | if (!os->clk) |
63c85238 PW |
876 | continue; |
877 | ||
6ea74cb9 RN |
878 | c = clk_get(NULL, os->clk); |
879 | if (IS_ERR(c)) { | |
3d0cb73e JP |
880 | pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
881 | oh->name, os->clk); | |
63c85238 | 882 | ret = -EINVAL; |
0e7dc862 | 883 | continue; |
dc75925d | 884 | } |
63c85238 | 885 | os->_clk = c; |
4d7cb45e RN |
886 | /* |
887 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
888 | * to do something meaningful. Today its just a no-op. | |
889 | * If clk_prepare() is used at some point to do things like | |
890 | * voltage scaling etc, then this would have to be moved to | |
891 | * some point where subsystems like i2c and pmic become | |
892 | * available. | |
893 | */ | |
894 | clk_prepare(os->_clk); | |
63c85238 PW |
895 | } |
896 | ||
897 | return ret; | |
898 | } | |
899 | ||
900 | /** | |
901 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
902 | * @oh: struct omap_hwmod * | |
903 | * | |
904 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
905 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
906 | */ | |
907 | static int _init_opt_clks(struct omap_hwmod *oh) | |
908 | { | |
909 | struct omap_hwmod_opt_clk *oc; | |
910 | struct clk *c; | |
911 | int i; | |
912 | int ret = 0; | |
913 | ||
914 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
915 | c = clk_get(NULL, oc->clk); |
916 | if (IS_ERR(c)) { | |
3d0cb73e JP |
917 | pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
918 | oh->name, oc->clk); | |
63c85238 | 919 | ret = -EINVAL; |
0e7dc862 | 920 | continue; |
dc75925d | 921 | } |
63c85238 | 922 | oc->_clk = c; |
4d7cb45e RN |
923 | /* |
924 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
925 | * to do something meaningful. Today its just a no-op. | |
926 | * If clk_prepare() is used at some point to do things like | |
927 | * voltage scaling etc, then this would have to be moved to | |
928 | * some point where subsystems like i2c and pmic become | |
929 | * available. | |
930 | */ | |
931 | clk_prepare(oc->_clk); | |
63c85238 PW |
932 | } |
933 | ||
934 | return ret; | |
935 | } | |
936 | ||
c12ba8ce PU |
937 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
938 | { | |
939 | struct omap_hwmod_opt_clk *oc; | |
940 | int i; | |
941 | ||
942 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
943 | ||
944 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
945 | if (oc->_clk) { | |
946 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
947 | __clk_get_name(oc->_clk)); | |
948 | clk_enable(oc->_clk); | |
949 | } | |
950 | } | |
951 | ||
952 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
953 | { | |
954 | struct omap_hwmod_opt_clk *oc; | |
955 | int i; | |
956 | ||
957 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
958 | ||
959 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
960 | if (oc->_clk) { | |
961 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
962 | __clk_get_name(oc->_clk)); | |
963 | clk_disable(oc->_clk); | |
964 | } | |
965 | } | |
966 | ||
63c85238 PW |
967 | /** |
968 | * _enable_clocks - enable hwmod main clock and interface clocks | |
969 | * @oh: struct omap_hwmod * | |
970 | * | |
971 | * Enables all clocks necessary for register reads and writes to succeed | |
972 | * on the hwmod @oh. Returns 0. | |
973 | */ | |
974 | static int _enable_clocks(struct omap_hwmod *oh) | |
975 | { | |
5d95dde7 | 976 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
977 | |
978 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
979 | ||
4d3ae5a9 | 980 | if (oh->_clk) |
63c85238 PW |
981 | clk_enable(oh->_clk); |
982 | ||
b8e1bddc | 983 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 PW |
984 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
985 | clk_enable(os->_clk); | |
63c85238 PW |
986 | } |
987 | ||
c12ba8ce PU |
988 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
989 | _enable_optional_clocks(oh); | |
990 | ||
63c85238 PW |
991 | /* The opt clocks are controlled by the device driver. */ |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
8823ddf2 TL |
996 | /** |
997 | * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework | |
998 | * @oh: struct omap_hwmod * | |
999 | */ | |
1000 | static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh) | |
1001 | { | |
1002 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) | |
1003 | return true; | |
1004 | ||
1005 | return false; | |
1006 | } | |
1007 | ||
1008 | /** | |
1009 | * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock | |
1010 | * @oh: struct omap_hwmod * | |
1011 | */ | |
1012 | static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh) | |
1013 | { | |
1014 | if (oh->prcm.omap4.clkctrl_offs) | |
1015 | return true; | |
1016 | ||
1017 | if (!oh->prcm.omap4.clkctrl_offs && | |
1018 | oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) | |
1019 | return true; | |
1020 | ||
1021 | return false; | |
1022 | } | |
1023 | ||
63c85238 PW |
1024 | /** |
1025 | * _disable_clocks - disable hwmod main clock and interface clocks | |
1026 | * @oh: struct omap_hwmod * | |
1027 | * | |
1028 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
1029 | */ | |
1030 | static int _disable_clocks(struct omap_hwmod *oh) | |
1031 | { | |
5d95dde7 | 1032 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
1033 | |
1034 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
1035 | ||
4d3ae5a9 | 1036 | if (oh->_clk) |
63c85238 PW |
1037 | clk_disable(oh->_clk); |
1038 | ||
b8e1bddc | 1039 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 PW |
1040 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
1041 | clk_disable(os->_clk); | |
63c85238 PW |
1042 | } |
1043 | ||
c12ba8ce PU |
1044 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
1045 | _disable_optional_clocks(oh); | |
1046 | ||
63c85238 PW |
1047 | /* The opt clocks are controlled by the device driver. */ |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
45c38252 | 1052 | /** |
3d9f0327 | 1053 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
1054 | * @oh: struct omap_hwmod * |
1055 | * | |
1056 | * Enables the PRCM module mode related to the hwmod @oh. | |
1057 | * No return value. | |
1058 | */ | |
3d9f0327 | 1059 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 1060 | { |
8823ddf2 TL |
1061 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1062 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
45c38252 BC |
1063 | return; |
1064 | ||
3d9f0327 KH |
1065 | pr_debug("omap_hwmod: %s: %s: %d\n", |
1066 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 | 1067 | |
128603f0 TK |
1068 | omap_cm_module_enable(oh->prcm.omap4.modulemode, |
1069 | oh->clkdm->prcm_partition, | |
1070 | oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); | |
1688bf19 VH |
1071 | } |
1072 | ||
45c38252 | 1073 | /** |
bfc141e3 BC |
1074 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
1075 | * @oh: struct omap_hwmod * | |
1076 | * | |
1077 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1078 | * does not have an IDLEST bit or if the module successfully enters | |
1079 | * slave idle; otherwise, pass along the return value of the | |
1080 | * appropriate *_cm*_wait_module_idle() function. | |
1081 | */ | |
1082 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
1083 | { | |
2b026d13 | 1084 | if (!oh) |
bfc141e3 BC |
1085 | return -EINVAL; |
1086 | ||
2b026d13 | 1087 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1088 | return 0; |
1089 | ||
1090 | if (oh->flags & HWMOD_NO_IDLEST) | |
1091 | return 0; | |
1092 | ||
8823ddf2 TL |
1093 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
1094 | return 0; | |
1095 | ||
1096 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
1097 | return 0; |
1098 | ||
a8ae5afa TK |
1099 | return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, |
1100 | oh->clkdm->cm_inst, | |
1101 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
1102 | } |
1103 | ||
63c85238 | 1104 | /** |
24dbc213 | 1105 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1106 | * @oh: struct omap_hwmod * |
1107 | * | |
24dbc213 PW |
1108 | * Determines the array index of the OCP slave port that the MPU uses |
1109 | * to address the device, and saves it into the struct omap_hwmod. | |
1110 | * Intended to be called during hwmod registration only. No return | |
1111 | * value. | |
63c85238 | 1112 | */ |
24dbc213 | 1113 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1114 | { |
24dbc213 | 1115 | struct omap_hwmod_ocp_if *os = NULL; |
63c85238 | 1116 | |
5d95dde7 | 1117 | if (!oh) |
24dbc213 PW |
1118 | return; |
1119 | ||
1120 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1121 | |
b8e1bddc | 1122 | list_for_each_entry(os, &oh->slave_ports, node) { |
63c85238 | 1123 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1124 | oh->_mpu_port = os; |
24dbc213 | 1125 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1126 | break; |
1127 | } | |
1128 | } | |
1129 | ||
24dbc213 | 1130 | return; |
63c85238 PW |
1131 | } |
1132 | ||
2d6141ba PW |
1133 | /** |
1134 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1135 | * @oh: struct omap_hwmod * | |
1136 | * | |
1137 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1138 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1139 | * communicate with the IP block. This interface need not be directly | |
1140 | * connected to the MPU (and almost certainly is not), but is directly | |
1141 | * connected to the IP block represented by @oh. Returns a pointer | |
1142 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1143 | * error or if there does not appear to be a path from the MPU to this | |
1144 | * IP block. | |
1145 | */ | |
1146 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1147 | { | |
1148 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1149 | return NULL; | |
1150 | ||
11cd4b94 | 1151 | return oh->_mpu_port; |
2d6141ba PW |
1152 | }; |
1153 | ||
63c85238 | 1154 | /** |
74ff3a68 | 1155 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1156 | * @oh: struct omap_hwmod * |
1157 | * | |
006c7f18 PW |
1158 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1159 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1160 | * Usually this means placing the module into smart-idle mode and | |
1161 | * smart-standby, but if there is a bug in the automatic idle handling | |
1162 | * for the IP block, it may need to be placed into the force-idle or | |
1163 | * no-idle variants of these modes. No return value. | |
63c85238 | 1164 | */ |
74ff3a68 | 1165 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1166 | { |
43b40992 | 1167 | u8 idlemode, sf; |
63c85238 | 1168 | u32 v; |
006c7f18 | 1169 | bool clkdm_act; |
f5dd3bb5 | 1170 | struct clockdomain *clkdm; |
63c85238 | 1171 | |
43b40992 | 1172 | if (!oh->class->sysc) |
63c85238 PW |
1173 | return; |
1174 | ||
613ad0e9 TK |
1175 | /* |
1176 | * Wait until reset has completed, this is needed as the IP | |
1177 | * block is reset automatically by hardware in some cases | |
1178 | * (off-mode for example), and the drivers require the | |
1179 | * IP to be ready when they access it | |
1180 | */ | |
1181 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1182 | _enable_optional_clocks(oh); | |
1183 | _wait_softreset_complete(oh); | |
1184 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1185 | _disable_optional_clocks(oh); | |
1186 | ||
63c85238 | 1187 | v = oh->_sysc_cache; |
43b40992 | 1188 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1189 | |
f5dd3bb5 | 1190 | clkdm = _get_clkdm(oh); |
43b40992 | 1191 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1192 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1193 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1194 | idlemode = HWMOD_IDLEMODE_NO; |
1195 | } else { | |
1196 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1197 | _enable_wakeup(oh, &v); | |
1198 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1199 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1200 | else | |
1201 | idlemode = HWMOD_IDLEMODE_SMART; | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * This is special handling for some IPs like | |
1206 | * 32k sync timer. Force them to idle! | |
1207 | */ | |
f5dd3bb5 | 1208 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1209 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1210 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1211 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1212 | |
63c85238 PW |
1213 | _set_slave_idlemode(oh, idlemode, &v); |
1214 | } | |
1215 | ||
43b40992 | 1216 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1217 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1218 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1219 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1220 | idlemode = HWMOD_IDLEMODE_NO; |
1221 | } else { | |
1222 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1223 | _enable_wakeup(oh, &v); | |
1224 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1225 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1226 | else | |
1227 | idlemode = HWMOD_IDLEMODE_SMART; | |
1228 | } | |
63c85238 PW |
1229 | _set_master_standbymode(oh, idlemode, &v); |
1230 | } | |
1231 | ||
a16b1f7f PW |
1232 | /* |
1233 | * XXX The clock framework should handle this, by | |
1234 | * calling into this code. But this must wait until the | |
1235 | * clock structures are tagged with omap_hwmod entries | |
1236 | */ | |
43b40992 PW |
1237 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1238 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
ca5339b1 | 1239 | _set_clockactivity(oh, CLOCKACT_TEST_ICLK, &v); |
63c85238 | 1240 | |
3ca4a238 | 1241 | _write_sysconfig(v, oh); |
78f26e87 HH |
1242 | |
1243 | /* | |
1244 | * Set the autoidle bit only after setting the smartidle bit | |
1245 | * Setting this will not have any impact on the other modules. | |
1246 | */ | |
1247 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1248 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1249 | 0 : 1; | |
1250 | _set_module_autoidle(oh, idlemode, &v); | |
1251 | _write_sysconfig(v, oh); | |
1252 | } | |
63c85238 PW |
1253 | } |
1254 | ||
1255 | /** | |
74ff3a68 | 1256 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1257 | * @oh: struct omap_hwmod * |
1258 | * | |
1259 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1260 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1261 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1262 | * configure it for smart-standby. No return value. | |
1263 | */ | |
74ff3a68 | 1264 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1265 | { |
43b40992 | 1266 | u8 idlemode, sf; |
63c85238 PW |
1267 | u32 v; |
1268 | ||
43b40992 | 1269 | if (!oh->class->sysc) |
63c85238 PW |
1270 | return; |
1271 | ||
1272 | v = oh->_sysc_cache; | |
43b40992 | 1273 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1274 | |
43b40992 | 1275 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1276 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1277 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1278 | } else { |
1279 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1280 | _enable_wakeup(oh, &v); | |
1281 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1282 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1283 | else | |
1284 | idlemode = HWMOD_IDLEMODE_SMART; | |
1285 | } | |
63c85238 PW |
1286 | _set_slave_idlemode(oh, idlemode, &v); |
1287 | } | |
1288 | ||
43b40992 | 1289 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1290 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1291 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1292 | idlemode = HWMOD_IDLEMODE_FORCE; |
1293 | } else { | |
1294 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1295 | _enable_wakeup(oh, &v); | |
1296 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1297 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1298 | else | |
1299 | idlemode = HWMOD_IDLEMODE_SMART; | |
1300 | } | |
63c85238 PW |
1301 | _set_master_standbymode(oh, idlemode, &v); |
1302 | } | |
1303 | ||
3ca4a238 LV |
1304 | /* If the cached value is the same as the new value, skip the write */ |
1305 | if (oh->_sysc_cache != v) | |
1306 | _write_sysconfig(v, oh); | |
63c85238 PW |
1307 | } |
1308 | ||
1309 | /** | |
74ff3a68 | 1310 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1311 | * @oh: struct omap_hwmod * |
1312 | * | |
1313 | * Force the module into slave idle and master suspend. No return | |
1314 | * value. | |
1315 | */ | |
74ff3a68 | 1316 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1317 | { |
1318 | u32 v; | |
43b40992 | 1319 | u8 sf; |
63c85238 | 1320 | |
43b40992 | 1321 | if (!oh->class->sysc) |
63c85238 PW |
1322 | return; |
1323 | ||
1324 | v = oh->_sysc_cache; | |
43b40992 | 1325 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1326 | |
43b40992 | 1327 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1328 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1329 | ||
43b40992 | 1330 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1331 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1332 | ||
43b40992 | 1333 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1334 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1335 | |
1336 | _write_sysconfig(v, oh); | |
1337 | } | |
1338 | ||
1339 | /** | |
1340 | * _lookup - find an omap_hwmod by name | |
1341 | * @name: find an omap_hwmod by name | |
1342 | * | |
1343 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1344 | */ |
1345 | static struct omap_hwmod *_lookup(const char *name) | |
1346 | { | |
1347 | struct omap_hwmod *oh, *temp_oh; | |
1348 | ||
1349 | oh = NULL; | |
1350 | ||
1351 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1352 | if (!strcmp(name, temp_oh->name)) { | |
1353 | oh = temp_oh; | |
1354 | break; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | return oh; | |
1359 | } | |
868c157d | 1360 | |
6ae76997 BC |
1361 | /** |
1362 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1363 | * @oh: struct omap_hwmod * | |
1364 | * | |
1365 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1366 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1367 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1368 | */ |
1369 | static int _init_clkdm(struct omap_hwmod *oh) | |
1370 | { | |
3bb05dbf PW |
1371 | if (!oh->clkdm_name) { |
1372 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1373 | return 0; |
3bb05dbf | 1374 | } |
6ae76997 | 1375 | |
6ae76997 BC |
1376 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1377 | if (!oh->clkdm) { | |
3d0cb73e | 1378 | pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", |
6ae76997 | 1379 | oh->name, oh->clkdm_name); |
0385c582 | 1380 | return 0; |
6ae76997 BC |
1381 | } |
1382 | ||
1383 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1384 | oh->name, oh->clkdm_name); | |
1385 | ||
1386 | return 0; | |
1387 | } | |
63c85238 PW |
1388 | |
1389 | /** | |
6ae76997 BC |
1390 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1391 | * well the clockdomain. | |
63c85238 | 1392 | * @oh: struct omap_hwmod * |
70f05be3 | 1393 | * @np: device_node mapped to this hwmod |
63c85238 | 1394 | * |
a2debdbd | 1395 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1396 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1397 | * success, or a negative error code on failure. | |
63c85238 | 1398 | */ |
70f05be3 | 1399 | static int _init_clocks(struct omap_hwmod *oh, struct device_node *np) |
63c85238 PW |
1400 | { |
1401 | int ret = 0; | |
1402 | ||
48d54f3f PW |
1403 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1404 | return 0; | |
63c85238 PW |
1405 | |
1406 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1407 | ||
b797be1d VH |
1408 | if (soc_ops.init_clkdm) |
1409 | ret |= soc_ops.init_clkdm(oh); | |
1410 | ||
63c85238 PW |
1411 | ret |= _init_main_clk(oh); |
1412 | ret |= _init_interface_clks(oh); | |
1413 | ret |= _init_opt_clks(oh); | |
1414 | ||
f5c1f84b BC |
1415 | if (!ret) |
1416 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a | 1417 | else |
3d0cb73e | 1418 | pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); |
63c85238 | 1419 | |
09c35f2f | 1420 | return ret; |
63c85238 PW |
1421 | } |
1422 | ||
5365efbe | 1423 | /** |
cc1226e7 | 1424 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1425 | * @oh: struct omap_hwmod * |
1426 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1427 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1428 | * |
1429 | * Return the bit position of the reset line that match the | |
1430 | * input name. Return -ENOENT if not found. | |
1431 | */ | |
a032d33b PW |
1432 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1433 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1434 | { |
1435 | int i; | |
1436 | ||
1437 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1438 | const char *rst_line = oh->rst_lines[i].name; | |
1439 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1440 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1441 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1442 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1443 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1444 | ohri->st_shift); | |
5365efbe | 1445 | |
cc1226e7 | 1446 | return 0; |
5365efbe BC |
1447 | } |
1448 | } | |
1449 | ||
1450 | return -ENOENT; | |
1451 | } | |
1452 | ||
1453 | /** | |
1454 | * _assert_hardreset - assert the HW reset line of submodules | |
1455 | * contained in the hwmod module. | |
1456 | * @oh: struct omap_hwmod * | |
1457 | * @name: name of the reset line to lookup and assert | |
1458 | * | |
b8249cf2 KH |
1459 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1460 | * reset line to be assert / deassert in order to enable fully the IP. | |
1461 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1462 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1463 | * along the return value from _lookup_hardreset() or the SoC's | |
1464 | * assert_hardreset code. | |
5365efbe BC |
1465 | */ |
1466 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1467 | { | |
cc1226e7 | 1468 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1469 | int ret = -EINVAL; |
5365efbe BC |
1470 | |
1471 | if (!oh) | |
1472 | return -EINVAL; | |
1473 | ||
b8249cf2 KH |
1474 | if (!soc_ops.assert_hardreset) |
1475 | return -ENOSYS; | |
1476 | ||
cc1226e7 | 1477 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1478 | if (ret < 0) |
cc1226e7 | 1479 | return ret; |
5365efbe | 1480 | |
b8249cf2 KH |
1481 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1482 | ||
1483 | return ret; | |
5365efbe BC |
1484 | } |
1485 | ||
1486 | /** | |
1487 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1488 | * in the hwmod module. | |
1489 | * @oh: struct omap_hwmod * | |
1490 | * @name: name of the reset line to look up and deassert | |
1491 | * | |
b8249cf2 KH |
1492 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1493 | * reset line to be assert / deassert in order to enable fully the IP. | |
1494 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1495 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1496 | * along the return value from _lookup_hardreset() or the SoC's | |
1497 | * deassert_hardreset code. | |
5365efbe BC |
1498 | */ |
1499 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1500 | { | |
cc1226e7 | 1501 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1502 | int ret = -EINVAL; |
5365efbe BC |
1503 | |
1504 | if (!oh) | |
1505 | return -EINVAL; | |
1506 | ||
b8249cf2 KH |
1507 | if (!soc_ops.deassert_hardreset) |
1508 | return -ENOSYS; | |
1509 | ||
cc1226e7 | 1510 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1511 | if (ret < 0) |
cc1226e7 | 1512 | return ret; |
5365efbe | 1513 | |
e8e96dff ORL |
1514 | if (oh->clkdm) { |
1515 | /* | |
1516 | * A clockdomain must be in SW_SUP otherwise reset | |
1517 | * might not be completed. The clockdomain can be set | |
1518 | * in HW_AUTO only when the module become ready. | |
1519 | */ | |
1d9a5425 | 1520 | clkdm_deny_idle(oh->clkdm); |
e8e96dff ORL |
1521 | ret = clkdm_hwmod_enable(oh->clkdm, oh); |
1522 | if (ret) { | |
1523 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1524 | oh->name, oh->clkdm->name, ret); | |
1525 | return ret; | |
1526 | } | |
1527 | } | |
1528 | ||
1529 | _enable_clocks(oh); | |
1530 | if (soc_ops.enable_module) | |
1531 | soc_ops.enable_module(oh); | |
1532 | ||
b8249cf2 | 1533 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1534 | |
1535 | if (soc_ops.disable_module) | |
1536 | soc_ops.disable_module(oh); | |
1537 | _disable_clocks(oh); | |
1538 | ||
cc1226e7 | 1539 | if (ret == -EBUSY) |
3d0cb73e | 1540 | pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); |
5365efbe | 1541 | |
80d2518d | 1542 | if (oh->clkdm) { |
e8e96dff ORL |
1543 | /* |
1544 | * Set the clockdomain to HW_AUTO, assuming that the | |
1545 | * previous state was HW_AUTO. | |
1546 | */ | |
1d9a5425 | 1547 | clkdm_allow_idle(oh->clkdm); |
80d2518d TK |
1548 | |
1549 | clkdm_hwmod_disable(oh->clkdm, oh); | |
e8e96dff ORL |
1550 | } |
1551 | ||
cc1226e7 | 1552 | return ret; |
5365efbe BC |
1553 | } |
1554 | ||
1555 | /** | |
1556 | * _read_hardreset - read the HW reset line state of submodules | |
1557 | * contained in the hwmod module | |
1558 | * @oh: struct omap_hwmod * | |
1559 | * @name: name of the reset line to look up and read | |
1560 | * | |
b8249cf2 KH |
1561 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1562 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1563 | * status on the currently-booted SoC, or passes along the return | |
1564 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1565 | * code. | |
5365efbe BC |
1566 | */ |
1567 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1568 | { | |
cc1226e7 | 1569 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1570 | int ret = -EINVAL; |
5365efbe BC |
1571 | |
1572 | if (!oh) | |
1573 | return -EINVAL; | |
1574 | ||
b8249cf2 KH |
1575 | if (!soc_ops.is_hardreset_asserted) |
1576 | return -ENOSYS; | |
1577 | ||
cc1226e7 | 1578 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1579 | if (ret < 0) |
cc1226e7 | 1580 | return ret; |
5365efbe | 1581 | |
b8249cf2 | 1582 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1583 | } |
1584 | ||
747834ab | 1585 | /** |
eb05f691 | 1586 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1587 | * @oh: struct omap_hwmod * |
1588 | * | |
eb05f691 ORL |
1589 | * If all hardreset lines associated with @oh are asserted, then return true. |
1590 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1591 | * associated with @oh are asserted, then return false. | |
747834ab | 1592 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1593 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1594 | */ |
eb05f691 | 1595 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1596 | { |
eb05f691 | 1597 | int i, rst_cnt = 0; |
747834ab PW |
1598 | |
1599 | if (oh->rst_lines_cnt == 0) | |
1600 | return false; | |
1601 | ||
1602 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1603 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1604 | rst_cnt++; |
1605 | ||
1606 | if (oh->rst_lines_cnt == rst_cnt) | |
1607 | return true; | |
747834ab PW |
1608 | |
1609 | return false; | |
1610 | } | |
1611 | ||
e9332b6e PW |
1612 | /** |
1613 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1614 | * hard-reset | |
1615 | * @oh: struct omap_hwmod * | |
1616 | * | |
1617 | * If any hardreset lines associated with @oh are asserted, then | |
1618 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1619 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1620 | * This function is used to avoid executing some parts of the IP block | |
1621 | * enable/disable sequence if any hardreset line is set. | |
1622 | */ | |
1623 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1624 | { | |
1625 | int rst_cnt = 0; | |
1626 | int i; | |
1627 | ||
1628 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1629 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1630 | rst_cnt++; | |
1631 | ||
1632 | return (rst_cnt) ? true : false; | |
1633 | } | |
1634 | ||
747834ab PW |
1635 | /** |
1636 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1637 | * @oh: struct omap_hwmod * | |
1638 | * | |
1639 | * Disable the PRCM module mode related to the hwmod @oh. | |
1640 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1641 | */ | |
1642 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1643 | { | |
1644 | int v; | |
1645 | ||
8823ddf2 TL |
1646 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1647 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
747834ab PW |
1648 | return -EINVAL; |
1649 | ||
eb05f691 ORL |
1650 | /* |
1651 | * Since integration code might still be doing something, only | |
1652 | * disable if all lines are under hardreset. | |
1653 | */ | |
e9332b6e | 1654 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1655 | return 0; |
1656 | ||
747834ab PW |
1657 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1658 | ||
128603f0 TK |
1659 | omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, |
1660 | oh->prcm.omap4.clkctrl_offs); | |
747834ab | 1661 | |
747834ab PW |
1662 | v = _omap4_wait_target_disable(oh); |
1663 | if (v) | |
1664 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1665 | oh->name); | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
63c85238 | 1670 | /** |
bd36179e | 1671 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1672 | * @oh: struct omap_hwmod * |
1673 | * | |
1674 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1675 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1676 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1677 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1678 | * |
1679 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1680 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1681 | * use the SYSCONFIG softreset bit to provide the status. |
1682 | * | |
bd36179e PW |
1683 | * Note that some IP like McBSP do have reset control but don't have |
1684 | * reset status. | |
63c85238 | 1685 | */ |
bd36179e | 1686 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1687 | { |
613ad0e9 | 1688 | u32 v; |
6f8b7ff5 | 1689 | int c = 0; |
96835af9 | 1690 | int ret = 0; |
63c85238 | 1691 | |
43b40992 | 1692 | if (!oh->class->sysc || |
2cb06814 | 1693 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1694 | return -ENOENT; |
63c85238 PW |
1695 | |
1696 | /* clocks must be on for this operation */ | |
1697 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1698 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1699 | oh->name); | |
63c85238 PW |
1700 | return -EINVAL; |
1701 | } | |
1702 | ||
96835af9 BC |
1703 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1704 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1705 | _enable_optional_clocks(oh); | |
1706 | ||
bd36179e | 1707 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1708 | |
1709 | v = oh->_sysc_cache; | |
96835af9 BC |
1710 | ret = _set_softreset(oh, &v); |
1711 | if (ret) | |
1712 | goto dis_opt_clks; | |
313a76ee | 1713 | |
63c85238 PW |
1714 | _write_sysconfig(v, oh); |
1715 | ||
d99de7f5 FGL |
1716 | if (oh->class->sysc->srst_udelay) |
1717 | udelay(oh->class->sysc->srst_udelay); | |
1718 | ||
613ad0e9 | 1719 | c = _wait_softreset_complete(oh); |
01142519 | 1720 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
3d0cb73e JP |
1721 | pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1722 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1723 | ret = -ETIMEDOUT; |
1724 | goto dis_opt_clks; | |
1725 | } else { | |
5365efbe | 1726 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1727 | } |
1728 | ||
1729 | ret = _clear_softreset(oh, &v); | |
1730 | if (ret) | |
1731 | goto dis_opt_clks; | |
1732 | ||
1733 | _write_sysconfig(v, oh); | |
63c85238 PW |
1734 | |
1735 | /* | |
1736 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1737 | * _wait_target_ready() or _reset() | |
1738 | */ | |
1739 | ||
96835af9 BC |
1740 | dis_opt_clks: |
1741 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1742 | _disable_optional_clocks(oh); | |
1743 | ||
1744 | return ret; | |
63c85238 PW |
1745 | } |
1746 | ||
bd36179e PW |
1747 | /** |
1748 | * _reset - reset an omap_hwmod | |
1749 | * @oh: struct omap_hwmod * | |
1750 | * | |
30e105c0 PW |
1751 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1752 | * function pointer defined, then call it to reset the IP block, and | |
1753 | * pass along its return value to the caller. Otherwise, if the IP | |
1754 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1755 | * associated with it, call a function to reset the IP block via that | |
1756 | * method, and pass along the return value to the caller. Finally, if | |
1757 | * the IP block has some hardreset lines associated with it, assert | |
1758 | * all of those, but do _not_ deassert them. (This is because driver | |
1759 | * authors have expressed an apparent requirement to control the | |
1760 | * deassertion of the hardreset lines themselves.) | |
1761 | * | |
1762 | * The default software reset mechanism for most OMAP IP blocks is | |
1763 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1764 | * hwmods cannot be reset via this method. Some are not targets and | |
1765 | * therefore have no OCP header registers to access. Others (like the | |
1766 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1767 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1768 | * omap_hwmod_class .reset function pointer. |
1769 | * | |
1770 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1771 | * does not prevent idling of the system. This is necessary for cases | |
1772 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1773 | * kernel without disabling dma. | |
1774 | * | |
1775 | * Passes along the return value from either _ocp_softreset() or the | |
1776 | * custom reset function - these must return -EINVAL if the hwmod | |
1777 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1778 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1779 | */ |
1780 | static int _reset(struct omap_hwmod *oh) | |
1781 | { | |
30e105c0 | 1782 | int i, r; |
bd36179e PW |
1783 | |
1784 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1785 | ||
30e105c0 PW |
1786 | if (oh->class->reset) { |
1787 | r = oh->class->reset(oh); | |
1788 | } else { | |
1789 | if (oh->rst_lines_cnt > 0) { | |
1790 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1791 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1792 | return 0; | |
1793 | } else { | |
1794 | r = _ocp_softreset(oh); | |
1795 | if (r == -ENOENT) | |
1796 | r = 0; | |
1797 | } | |
1798 | } | |
1799 | ||
6668546f KVA |
1800 | _set_dmadisable(oh); |
1801 | ||
9c8b0ec7 | 1802 | /* |
30e105c0 PW |
1803 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1804 | * softreset. The _enable() function should be split to avoid | |
1805 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1806 | */ |
2800852a RN |
1807 | if (oh->class->sysc) { |
1808 | _update_sysc_cache(oh); | |
1809 | _enable_sysc(oh); | |
1810 | } | |
1811 | ||
30e105c0 | 1812 | return r; |
bd36179e PW |
1813 | } |
1814 | ||
e6d3a8b0 RN |
1815 | /** |
1816 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
1817 | * hwmod context was lost, and clear hardware context loss reg | |
1818 | * @oh: hwmod to check for context loss | |
1819 | * | |
1820 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
1821 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
1822 | * bits. No return value. | |
1823 | */ | |
1824 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
1825 | { | |
1826 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
1827 | return; | |
1828 | ||
1829 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1830 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1831 | oh->prcm.omap4.context_offs)) | |
1832 | return; | |
1833 | ||
1834 | oh->prcm.omap4.context_lost_counter++; | |
1835 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1836 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1837 | oh->prcm.omap4.context_offs); | |
1838 | } | |
1839 | ||
1840 | /** | |
1841 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
1842 | * @oh: hwmod to get context loss counter for | |
1843 | * | |
1844 | * Returns the in-memory context loss counter for a hwmod. | |
1845 | */ | |
1846 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
1847 | { | |
1848 | return oh->prcm.omap4.context_lost_counter; | |
1849 | } | |
1850 | ||
6d266f63 PW |
1851 | /** |
1852 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
1853 | * @oh: struct omap_hwmod * | |
1854 | * | |
1855 | * Some IP blocks (such as AESS) require some additional programming | |
1856 | * after enable before they can enter idle. If a function pointer to | |
1857 | * do so is present in the hwmod data, then call it and pass along the | |
1858 | * return value; otherwise, return 0. | |
1859 | */ | |
0f497039 | 1860 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
1861 | { |
1862 | if (!oh->class->enable_preprogram) | |
1863 | return 0; | |
1864 | ||
1865 | return oh->class->enable_preprogram(oh); | |
1866 | } | |
1867 | ||
63c85238 | 1868 | /** |
dc6d1cda | 1869 | * _enable - enable an omap_hwmod |
63c85238 PW |
1870 | * @oh: struct omap_hwmod * |
1871 | * | |
1872 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1873 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1874 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1875 | */ |
dc6d1cda | 1876 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1877 | { |
747834ab | 1878 | int r; |
63c85238 | 1879 | |
34617e2a BC |
1880 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1881 | ||
aacf0941 | 1882 | /* |
64813c3f | 1883 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
b4281455 | 1884 | * state at init. |
aacf0941 RN |
1885 | */ |
1886 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
aacf0941 RN |
1887 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; |
1888 | return 0; | |
1889 | } | |
1890 | ||
63c85238 PW |
1891 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1892 | oh->_state != _HWMOD_STATE_IDLE && | |
1893 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1894 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1895 | oh->name); | |
63c85238 PW |
1896 | return -EINVAL; |
1897 | } | |
1898 | ||
31f62866 | 1899 | /* |
eb05f691 | 1900 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
1901 | * asserted, we let integration code associated with that |
1902 | * block handle the enable. We've received very little | |
1903 | * information on what those driver authors need, and until | |
1904 | * detailed information is provided and the driver code is | |
1905 | * posted to the public lists, this is probably the best we | |
1906 | * can do. | |
31f62866 | 1907 | */ |
eb05f691 | 1908 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 1909 | return 0; |
63c85238 | 1910 | |
665d0013 | 1911 | _add_initiator_dep(oh, mpu_oh); |
34617e2a | 1912 | |
665d0013 RN |
1913 | if (oh->clkdm) { |
1914 | /* | |
1915 | * A clockdomain must be in SW_SUP before enabling | |
1916 | * completely the module. The clockdomain can be set | |
1917 | * in HW_AUTO only when the module become ready. | |
1918 | */ | |
1d9a5425 | 1919 | clkdm_deny_idle(oh->clkdm); |
665d0013 RN |
1920 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
1921 | if (r) { | |
1922 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1923 | oh->name, oh->clkdm->name, r); | |
1924 | return r; | |
1925 | } | |
34617e2a | 1926 | } |
665d0013 RN |
1927 | |
1928 | _enable_clocks(oh); | |
9ebfd285 KH |
1929 | if (soc_ops.enable_module) |
1930 | soc_ops.enable_module(oh); | |
fa200222 | 1931 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 1932 | cpu_idle_poll_ctrl(true); |
34617e2a | 1933 | |
e6d3a8b0 RN |
1934 | if (soc_ops.update_context_lost) |
1935 | soc_ops.update_context_lost(oh); | |
1936 | ||
8f6aa8ee KH |
1937 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
1938 | -EINVAL; | |
8ff42da4 | 1939 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) |
1d9a5425 | 1940 | clkdm_allow_idle(oh->clkdm); |
665d0013 | 1941 | |
1d9a5425 | 1942 | if (!r) { |
665d0013 RN |
1943 | oh->_state = _HWMOD_STATE_ENABLED; |
1944 | ||
1945 | /* Access the sysconfig only if the target is ready */ | |
1946 | if (oh->class->sysc) { | |
1947 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1948 | _update_sysc_cache(oh); | |
1949 | _enable_sysc(oh); | |
1950 | } | |
6d266f63 | 1951 | r = _enable_preprogram(oh); |
665d0013 | 1952 | } else { |
2577a4a6 PW |
1953 | if (soc_ops.disable_module) |
1954 | soc_ops.disable_module(oh); | |
665d0013 | 1955 | _disable_clocks(oh); |
812ce9d2 LV |
1956 | pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n", |
1957 | oh->name, r); | |
34617e2a | 1958 | |
665d0013 RN |
1959 | if (oh->clkdm) |
1960 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1961 | } |
1962 | ||
63c85238 PW |
1963 | return r; |
1964 | } | |
1965 | ||
1966 | /** | |
dc6d1cda | 1967 | * _idle - idle an omap_hwmod |
63c85238 PW |
1968 | * @oh: struct omap_hwmod * |
1969 | * | |
1970 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1971 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1972 | * state or returns 0. | |
63c85238 | 1973 | */ |
dc6d1cda | 1974 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1975 | { |
2e18f5a1 LV |
1976 | if (oh->flags & HWMOD_NO_IDLE) { |
1977 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
1978 | return 0; | |
1979 | } | |
1980 | ||
34617e2a BC |
1981 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1982 | ||
c20c8f75 SA |
1983 | if (_are_all_hardreset_lines_asserted(oh)) |
1984 | return 0; | |
1985 | ||
63c85238 | 1986 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
1987 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
1988 | oh->name); | |
63c85238 PW |
1989 | return -EINVAL; |
1990 | } | |
1991 | ||
43b40992 | 1992 | if (oh->class->sysc) |
74ff3a68 | 1993 | _idle_sysc(oh); |
63c85238 | 1994 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 1995 | |
8ff42da4 RQ |
1996 | /* |
1997 | * If HWMOD_CLKDM_NOAUTO is set then we don't | |
1998 | * deny idle the clkdm again since idle was already denied | |
1999 | * in _enable() | |
2000 | */ | |
2001 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) | |
1d9a5425 TK |
2002 | clkdm_deny_idle(oh->clkdm); |
2003 | ||
fa200222 | 2004 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2005 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2006 | if (soc_ops.disable_module) |
2007 | soc_ops.disable_module(oh); | |
bfc141e3 | 2008 | |
45c38252 BC |
2009 | /* |
2010 | * The module must be in idle mode before disabling any parents | |
2011 | * clocks. Otherwise, the parent clock might be disabled before | |
2012 | * the module transition is done, and thus will prevent the | |
2013 | * transition to complete properly. | |
2014 | */ | |
2015 | _disable_clocks(oh); | |
1d9a5425 TK |
2016 | if (oh->clkdm) { |
2017 | clkdm_allow_idle(oh->clkdm); | |
665d0013 | 2018 | clkdm_hwmod_disable(oh->clkdm, oh); |
1d9a5425 | 2019 | } |
63c85238 PW |
2020 | |
2021 | oh->_state = _HWMOD_STATE_IDLE; | |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | /** | |
2027 | * _shutdown - shutdown an omap_hwmod | |
2028 | * @oh: struct omap_hwmod * | |
2029 | * | |
2030 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2031 | * used for the hwmod is removed or unloaded or if the driver is not | |
2032 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2033 | * state or returns 0. | |
2034 | */ | |
2035 | static int _shutdown(struct omap_hwmod *oh) | |
2036 | { | |
9c8b0ec7 | 2037 | int ret, i; |
e4dc8f50 PW |
2038 | u8 prev_state; |
2039 | ||
c20c8f75 SA |
2040 | if (_are_all_hardreset_lines_asserted(oh)) |
2041 | return 0; | |
2042 | ||
63c85238 PW |
2043 | if (oh->_state != _HWMOD_STATE_IDLE && |
2044 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2045 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2046 | oh->name); | |
63c85238 PW |
2047 | return -EINVAL; |
2048 | } | |
2049 | ||
2050 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
2051 | ||
e4dc8f50 PW |
2052 | if (oh->class->pre_shutdown) { |
2053 | prev_state = oh->_state; | |
2054 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2055 | _enable(oh); |
e4dc8f50 PW |
2056 | ret = oh->class->pre_shutdown(oh); |
2057 | if (ret) { | |
2058 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2059 | _idle(oh); |
e4dc8f50 PW |
2060 | return ret; |
2061 | } | |
2062 | } | |
2063 | ||
6481c73c MV |
2064 | if (oh->class->sysc) { |
2065 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2066 | _enable(oh); | |
74ff3a68 | 2067 | _shutdown_sysc(oh); |
6481c73c | 2068 | } |
5365efbe | 2069 | |
3827f949 BC |
2070 | /* clocks and deps are already disabled in idle */ |
2071 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2072 | _del_initiator_dep(oh, mpu_oh); | |
2073 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2074 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2075 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2076 | if (soc_ops.disable_module) |
2077 | soc_ops.disable_module(oh); | |
45c38252 | 2078 | _disable_clocks(oh); |
665d0013 RN |
2079 | if (oh->clkdm) |
2080 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2081 | } |
63c85238 PW |
2082 | /* XXX Should this code also force-disable the optional clocks? */ |
2083 | ||
9c8b0ec7 PW |
2084 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2085 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2086 | |
63c85238 PW |
2087 | oh->_state = _HWMOD_STATE_DISABLED; |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
5e863c56 TL |
2092 | static int of_dev_find_hwmod(struct device_node *np, |
2093 | struct omap_hwmod *oh) | |
2094 | { | |
2095 | int count, i, res; | |
2096 | const char *p; | |
2097 | ||
2098 | count = of_property_count_strings(np, "ti,hwmods"); | |
2099 | if (count < 1) | |
2100 | return -ENODEV; | |
2101 | ||
2102 | for (i = 0; i < count; i++) { | |
2103 | res = of_property_read_string_index(np, "ti,hwmods", | |
2104 | i, &p); | |
2105 | if (res) | |
2106 | continue; | |
2107 | if (!strcmp(p, oh->name)) { | |
2108 | pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n", | |
2109 | np->name, i, oh->name); | |
2110 | return i; | |
2111 | } | |
2112 | } | |
2113 | ||
2114 | return -ENODEV; | |
2115 | } | |
2116 | ||
079abade SS |
2117 | /** |
2118 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2119 | * @np: struct device_node * | |
2120 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2121 | * @index: index of the entry found |
2122 | * @found: struct device_node * found or NULL | |
079abade SS |
2123 | * |
2124 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2125 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2126 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2127 | */ |
5e863c56 TL |
2128 | static int of_dev_hwmod_lookup(struct device_node *np, |
2129 | struct omap_hwmod *oh, | |
2130 | int *index, | |
2131 | struct device_node **found) | |
079abade | 2132 | { |
5e863c56 TL |
2133 | struct device_node *np0 = NULL; |
2134 | int res; | |
2135 | ||
2136 | res = of_dev_find_hwmod(np, oh); | |
2137 | if (res >= 0) { | |
2138 | *found = np; | |
2139 | *index = res; | |
2140 | return 0; | |
2141 | } | |
079abade SS |
2142 | |
2143 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2144 | struct device_node *fc; |
2145 | int i; | |
2146 | ||
2147 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2148 | if (res == 0) { | |
2149 | *found = fc; | |
2150 | *index = i; | |
2151 | return 0; | |
079abade SS |
2152 | } |
2153 | } | |
5e863c56 TL |
2154 | |
2155 | *found = NULL; | |
2156 | *index = 0; | |
2157 | ||
2158 | return -ENODEV; | |
079abade SS |
2159 | } |
2160 | ||
6c72b355 TL |
2161 | /** |
2162 | * omap_hwmod_parse_module_range - map module IO range from device tree | |
2163 | * @oh: struct omap_hwmod * | |
2164 | * @np: struct device_node * | |
2165 | * | |
2166 | * Parse the device tree range an interconnect target module provides | |
2167 | * for it's child device IP blocks. This way we can support the old | |
2168 | * "ti,hwmods" property with just dts data without a need for platform | |
2169 | * data for IO resources. And we don't need all the child IP device | |
2170 | * nodes available in the dts. | |
2171 | */ | |
2172 | int omap_hwmod_parse_module_range(struct omap_hwmod *oh, | |
2173 | struct device_node *np, | |
2174 | struct resource *res) | |
2175 | { | |
2176 | struct property *prop; | |
2177 | const __be32 *ranges; | |
2178 | const char *name; | |
2179 | u32 nr_addr, nr_size; | |
2180 | u64 base, size; | |
2181 | int len, error; | |
2182 | ||
2183 | if (!res) | |
2184 | return -EINVAL; | |
2185 | ||
2186 | ranges = of_get_property(np, "ranges", &len); | |
2187 | if (!ranges) | |
2188 | return -ENOENT; | |
2189 | ||
2190 | len /= sizeof(*ranges); | |
2191 | ||
2192 | if (len < 3) | |
2193 | return -EINVAL; | |
2194 | ||
2195 | of_property_for_each_string(np, "compatible", prop, name) | |
2196 | if (!strncmp("ti,sysc-", name, 8)) | |
2197 | break; | |
2198 | ||
2199 | if (!name) | |
2200 | return -ENOENT; | |
2201 | ||
2202 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
2203 | if (error) | |
2204 | return -ENOENT; | |
2205 | ||
2206 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
2207 | if (error) | |
2208 | return -ENOENT; | |
2209 | ||
2210 | if (nr_addr != 1 || nr_size != 1) { | |
2211 | pr_err("%s: invalid range for %s->%s\n", __func__, | |
2212 | oh->name, np->name); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | ||
2216 | ranges++; | |
2217 | base = of_translate_address(np, ranges++); | |
2218 | size = be32_to_cpup(ranges); | |
2219 | ||
2220 | pr_debug("omap_hwmod: %s %s at 0x%llx size 0x%llx\n", | |
2221 | oh->name, np->name, base, size); | |
2222 | ||
2223 | res->start = base; | |
2224 | res->end = base + size - 1; | |
2225 | res->flags = IORESOURCE_MEM; | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
381d033a PW |
2230 | /** |
2231 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2232 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2233 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2234 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2235 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2236 | * |
2237 | * Cache the virtual address used by the MPU to access this IP block's | |
2238 | * registers. This address is needed early so the OCP registers that | |
2239 | * are part of the device's address space can be ioremapped properly. | |
6423d6df | 2240 | * |
9a258afa RQ |
2241 | * If SYSC access is not needed, the registers will not be remapped |
2242 | * and non-availability of MPU access is not treated as an error. | |
2243 | * | |
6423d6df SA |
2244 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and |
2245 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2246 | */ |
f92d9597 | 2247 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2248 | int index, struct device_node *np) |
381d033a | 2249 | { |
079abade | 2250 | void __iomem *va_start = NULL; |
6c72b355 TL |
2251 | struct resource res; |
2252 | int error; | |
c9aafd23 PW |
2253 | |
2254 | if (!oh) | |
6423d6df | 2255 | return -EINVAL; |
c9aafd23 | 2256 | |
2221b5cd PW |
2257 | _save_mpu_port_index(oh); |
2258 | ||
9a258afa RQ |
2259 | /* if we don't need sysc access we don't need to ioremap */ |
2260 | if (!oh->class->sysc) | |
2261 | return 0; | |
2262 | ||
2263 | /* we can't continue without MPU PORT if we need sysc access */ | |
381d033a | 2264 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2265 | return -ENXIO; |
381d033a | 2266 | |
9cffb1a0 TL |
2267 | if (!np) { |
2268 | pr_err("omap_hwmod: %s: no dt node\n", oh->name); | |
2269 | return -ENXIO; | |
c9aafd23 PW |
2270 | } |
2271 | ||
9cffb1a0 TL |
2272 | /* Do we have a dts range for the interconnect target module? */ |
2273 | error = omap_hwmod_parse_module_range(oh, np, &res); | |
2274 | if (!error) | |
2275 | va_start = ioremap(res.start, resource_size(&res)); | |
2276 | ||
2277 | /* No ranges, rely on device reg entry */ | |
2278 | if (!va_start) | |
2279 | va_start = of_iomap(np, index + oh->mpu_rt_idx); | |
c9aafd23 | 2280 | if (!va_start) { |
9cffb1a0 TL |
2281 | pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n", |
2282 | oh->name, index, np); | |
6423d6df | 2283 | return -ENXIO; |
c9aafd23 PW |
2284 | } |
2285 | ||
2286 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2287 | oh->name, va_start); | |
2288 | ||
2289 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2290 | return 0; |
381d033a PW |
2291 | } |
2292 | ||
2293 | /** | |
2294 | * _init - initialize internal data for the hwmod @oh | |
2295 | * @oh: struct omap_hwmod * | |
2296 | * @n: (unused) | |
2297 | * | |
2298 | * Look up the clocks and the address space used by the MPU to access | |
2299 | * registers belonging to the hwmod @oh. @oh must already be | |
2300 | * registered at this point. This is the first of two phases for | |
2301 | * hwmod initialization. Code called here does not touch any hardware | |
2302 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2303 | * upon success or if the hwmod isn't registered or if the hwmod's |
2304 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2305 | */ |
2306 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2307 | { | |
5e863c56 | 2308 | int r, index; |
f92d9597 | 2309 | struct device_node *np = NULL; |
1aa8f0cb | 2310 | struct device_node *bus; |
381d033a PW |
2311 | |
2312 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2313 | return 0; | |
2314 | ||
1aa8f0cb TL |
2315 | bus = of_find_node_by_name(NULL, "ocp"); |
2316 | if (!bus) | |
2317 | return -ENODEV; | |
5e863c56 | 2318 | |
1aa8f0cb TL |
2319 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); |
2320 | if (r) | |
2321 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2322 | else if (np && index) | |
2323 | pr_warn("omap_hwmod: %s using broken dt data from %s\n", | |
2324 | oh->name, np->name); | |
f92d9597 | 2325 | |
9a258afa RQ |
2326 | r = _init_mpu_rt_base(oh, NULL, index, np); |
2327 | if (r < 0) { | |
2328 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2329 | oh->name); | |
2330 | return 0; | |
6423d6df | 2331 | } |
381d033a | 2332 | |
70f05be3 | 2333 | r = _init_clocks(oh, np); |
c48cd659 | 2334 | if (r < 0) { |
381d033a PW |
2335 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2336 | return -EINVAL; | |
2337 | } | |
2338 | ||
3d36ad7e | 2339 | if (np) { |
f92d9597 RN |
2340 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) |
2341 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2342 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2343 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
2e18f5a1 LV |
2344 | if (of_find_property(np, "ti,no-idle", NULL)) |
2345 | oh->flags |= HWMOD_NO_IDLE; | |
3d36ad7e | 2346 | } |
f92d9597 | 2347 | |
381d033a PW |
2348 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2349 | ||
2350 | return 0; | |
2351 | } | |
2352 | ||
63c85238 | 2353 | /** |
64813c3f | 2354 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2355 | * @oh: struct omap_hwmod * |
2356 | * | |
64813c3f PW |
2357 | * Set up the module's interface clocks. XXX This function is still mostly |
2358 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2359 | * the clock code. No return value. | |
63c85238 | 2360 | */ |
64813c3f | 2361 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2362 | { |
5d95dde7 | 2363 | struct omap_hwmod_ocp_if *os; |
b8e1bddc | 2364 | |
381d033a | 2365 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2366 | return; |
48d54f3f | 2367 | |
b8e1bddc | 2368 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 | 2369 | if (!os->_clk) |
64813c3f | 2370 | continue; |
63c85238 | 2371 | |
64813c3f PW |
2372 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2373 | /* XXX omap_iclk_deny_idle(c); */ | |
2374 | } else { | |
2375 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2376 | clk_enable(os->_clk); |
63c85238 PW |
2377 | } |
2378 | } | |
2379 | ||
64813c3f PW |
2380 | return; |
2381 | } | |
2382 | ||
2383 | /** | |
2384 | * _setup_reset - reset an IP block during the setup process | |
2385 | * @oh: struct omap_hwmod * | |
2386 | * | |
2387 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2388 | * process. The IP block is first enabled so it can be successfully | |
2389 | * reset. Returns 0 upon success or a negative error code upon | |
2390 | * failure. | |
2391 | */ | |
2392 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2393 | { | |
2394 | int r; | |
2395 | ||
2396 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2397 | return -EINVAL; | |
63c85238 | 2398 | |
5fb3d522 PW |
2399 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2400 | return -EPERM; | |
2401 | ||
747834ab PW |
2402 | if (oh->rst_lines_cnt == 0) { |
2403 | r = _enable(oh); | |
2404 | if (r) { | |
3d0cb73e JP |
2405 | pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", |
2406 | oh->name, oh->_state); | |
747834ab PW |
2407 | return -EINVAL; |
2408 | } | |
9a23dfe1 | 2409 | } |
63c85238 | 2410 | |
2800852a | 2411 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2412 | r = _reset(oh); |
2413 | ||
2414 | return r; | |
2415 | } | |
2416 | ||
2417 | /** | |
2418 | * _setup_postsetup - transition to the appropriate state after _setup | |
2419 | * @oh: struct omap_hwmod * | |
2420 | * | |
2421 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2422 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2423 | * this function is called at the end of _setup().) The postsetup | |
2424 | * state for an IP block can be changed by calling | |
2425 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2426 | * before one of the omap_hwmod_setup*() functions are called for the | |
2427 | * IP block. | |
2428 | * | |
2429 | * The IP block stays in this state until a PM runtime-based driver is | |
2430 | * loaded for that IP block. A post-setup state of IDLE is | |
2431 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2432 | * drivers, since those drivers are able to enable the IP block. A | |
2433 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2434 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2435 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2436 | * included, since the WDTIMER starts running on reset and will reset | |
2437 | * the MPU if left active. | |
2438 | * | |
2439 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2440 | * drivers have been converted to use PM runtime, and all of the IP | |
2441 | * block data and interconnect data is available to the hwmod code, it | |
2442 | * should be possible to replace this mechanism with a "lazy reset" | |
2443 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2444 | * when the driver first probes, then all remaining IP blocks without | |
2445 | * drivers are either shut down or enabled after the drivers have | |
2446 | * loaded. However, this cannot take place until the above | |
2447 | * preconditions have been met, since otherwise the late reset code | |
2448 | * has no way of knowing which IP blocks are in use by drivers, and | |
2449 | * which ones are unused. | |
2450 | * | |
2451 | * No return value. | |
2452 | */ | |
2453 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2454 | { | |
2455 | u8 postsetup_state; | |
2456 | ||
2457 | if (oh->rst_lines_cnt > 0) | |
2458 | return; | |
76e5589e | 2459 | |
2092e5cc PW |
2460 | postsetup_state = oh->_postsetup_state; |
2461 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2462 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2463 | ||
2464 | /* | |
2465 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2466 | * it should be set by the core code as a runtime flag during startup | |
2467 | */ | |
2e18f5a1 | 2468 | if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) && |
aacf0941 RN |
2469 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2470 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2471 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2472 | } |
2092e5cc PW |
2473 | |
2474 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2475 | _idle(oh); |
2092e5cc PW |
2476 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2477 | _shutdown(oh); | |
2478 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2479 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2480 | oh->name, postsetup_state); | |
63c85238 | 2481 | |
64813c3f PW |
2482 | return; |
2483 | } | |
2484 | ||
2485 | /** | |
2486 | * _setup - prepare IP block hardware for use | |
2487 | * @oh: struct omap_hwmod * | |
2488 | * @n: (unused, pass NULL) | |
2489 | * | |
2490 | * Configure the IP block represented by @oh. This may include | |
2491 | * enabling the IP block, resetting it, and placing it into a | |
2492 | * post-setup state, depending on the type of IP block and applicable | |
2493 | * flags. IP blocks are reset to prevent any previous configuration | |
2494 | * by the bootloader or previous operating system from interfering | |
2495 | * with power management or other parts of the system. The reset can | |
2496 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2497 | * two phases for hwmod initialization. Code called here generally | |
2498 | * affects the IP block hardware, or system integration hardware | |
2499 | * associated with the IP block. Returns 0. | |
2500 | */ | |
2501 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2502 | { | |
2503 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2504 | return 0; | |
2505 | ||
f22d2545 TV |
2506 | if (oh->parent_hwmod) { |
2507 | int r; | |
2508 | ||
2509 | r = _enable(oh->parent_hwmod); | |
2510 | WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n", | |
2511 | oh->name, oh->parent_hwmod->name); | |
2512 | } | |
2513 | ||
64813c3f PW |
2514 | _setup_iclk_autoidle(oh); |
2515 | ||
2516 | if (!_setup_reset(oh)) | |
2517 | _setup_postsetup(oh); | |
2518 | ||
f22d2545 TV |
2519 | if (oh->parent_hwmod) { |
2520 | u8 postsetup_state; | |
2521 | ||
2522 | postsetup_state = oh->parent_hwmod->_postsetup_state; | |
2523 | ||
2524 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
2525 | _idle(oh->parent_hwmod); | |
2526 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | |
2527 | _shutdown(oh->parent_hwmod); | |
2528 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2529 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2530 | oh->parent_hwmod->name, postsetup_state); | |
2531 | } | |
2532 | ||
63c85238 PW |
2533 | return 0; |
2534 | } | |
2535 | ||
63c85238 | 2536 | /** |
0102b627 | 2537 | * _register - register a struct omap_hwmod |
63c85238 PW |
2538 | * @oh: struct omap_hwmod * |
2539 | * | |
43b40992 PW |
2540 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2541 | * already has been registered by the same name; -EINVAL if the | |
2542 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2543 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2544 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2545 | * success. | |
63c85238 PW |
2546 | * |
2547 | * XXX The data should be copied into bootmem, so the original data | |
2548 | * should be marked __initdata and freed after init. This would allow | |
2549 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2550 | * that the copy process would be relatively complex due to the large number | |
2551 | * of substructures. | |
2552 | */ | |
01592df9 | 2553 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2554 | { |
43b40992 PW |
2555 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2556 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2557 | return -EINVAL; |
2558 | ||
63c85238 PW |
2559 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2560 | ||
ce35b244 BC |
2561 | if (_lookup(oh->name)) |
2562 | return -EEXIST; | |
63c85238 | 2563 | |
63c85238 PW |
2564 | list_add_tail(&oh->node, &omap_hwmod_list); |
2565 | ||
2221b5cd | 2566 | INIT_LIST_HEAD(&oh->slave_ports); |
dc6d1cda | 2567 | spin_lock_init(&oh->_lock); |
69317952 | 2568 | lockdep_set_class(&oh->_lock, &oh->hwmod_key); |
2092e5cc | 2569 | |
63c85238 PW |
2570 | oh->_state = _HWMOD_STATE_REGISTERED; |
2571 | ||
569edd70 PW |
2572 | /* |
2573 | * XXX Rather than doing a strcmp(), this should test a flag | |
2574 | * set in the hwmod data, inserted by the autogenerator code. | |
2575 | */ | |
2576 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2577 | mpu_oh = oh; | |
63c85238 | 2578 | |
569edd70 | 2579 | return 0; |
63c85238 PW |
2580 | } |
2581 | ||
2221b5cd PW |
2582 | /** |
2583 | * _add_link - add an interconnect between two IP blocks | |
2584 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2585 | * | |
a1e31235 | 2586 | * Add struct omap_hwmod_link records connecting the slave IP block |
2221b5cd PW |
2587 | * specified in @oi->slave to @oi. This code is assumed to run before |
2588 | * preemption or SMP has been enabled, thus avoiding the need for | |
2589 | * locking in this code. Changes to this assumption will require | |
2590 | * additional locking. Returns 0. | |
2591 | */ | |
2592 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2593 | { | |
2221b5cd PW |
2594 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, |
2595 | oi->slave->name); | |
2596 | ||
a1e31235 | 2597 | list_add(&oi->node, &oi->slave->slave_ports); |
2221b5cd PW |
2598 | oi->slave->slaves_cnt++; |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
2603 | /** | |
2604 | * _register_link - register a struct omap_hwmod_ocp_if | |
2605 | * @oi: struct omap_hwmod_ocp_if * | |
2606 | * | |
2607 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2608 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2609 | * record pointed to by @oi is missing required fields; or 0 upon | |
2610 | * success. | |
2611 | * | |
2612 | * XXX The data should be copied into bootmem, so the original data | |
2613 | * should be marked __initdata and freed after init. This would allow | |
2614 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2615 | */ | |
2616 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2617 | { | |
2618 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2619 | return -EINVAL; | |
2620 | ||
2621 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2622 | return -EEXIST; | |
2623 | ||
2624 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2625 | oi->master->name, oi->slave->name); | |
2626 | ||
2627 | /* | |
2628 | * Register the connected hwmods, if they haven't been | |
2629 | * registered already | |
2630 | */ | |
2631 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2632 | _register(oi->master); | |
2633 | ||
2634 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2635 | _register(oi->slave); | |
2636 | ||
2637 | _add_link(oi); | |
2638 | ||
2639 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2640 | ||
2641 | return 0; | |
2642 | } | |
2643 | ||
8f6aa8ee KH |
2644 | /* Static functions intended only for use in soc_ops field function pointers */ |
2645 | ||
2646 | /** | |
9002e921 | 2647 | * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2648 | * @oh: struct omap_hwmod * |
2649 | * | |
2650 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2651 | * does not have an IDLEST bit or if the module successfully leaves | |
2652 | * slave idle; otherwise, pass along the return value of the | |
2653 | * appropriate *_cm*_wait_module_ready() function. | |
2654 | */ | |
9002e921 | 2655 | static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2656 | { |
2657 | if (!oh) | |
2658 | return -EINVAL; | |
2659 | ||
2660 | if (oh->flags & HWMOD_NO_IDLEST) | |
2661 | return 0; | |
2662 | ||
2663 | if (!_find_mpu_rt_port(oh)) | |
2664 | return 0; | |
2665 | ||
2666 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2667 | ||
021b6ff0 TK |
2668 | return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs, |
2669 | oh->prcm.omap2.idlest_reg_id, | |
2670 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2671 | } |
2672 | ||
2673 | /** | |
2674 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2675 | * @oh: struct omap_hwmod * | |
2676 | * | |
2677 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2678 | * does not have an IDLEST bit or if the module successfully leaves | |
2679 | * slave idle; otherwise, pass along the return value of the | |
2680 | * appropriate *_cm*_wait_module_ready() function. | |
2681 | */ | |
2682 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2683 | { | |
2b026d13 | 2684 | if (!oh) |
8f6aa8ee KH |
2685 | return -EINVAL; |
2686 | ||
2b026d13 | 2687 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2688 | return 0; |
2689 | ||
2690 | if (!_find_mpu_rt_port(oh)) | |
2691 | return 0; | |
2692 | ||
8823ddf2 TL |
2693 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
2694 | return 0; | |
2695 | ||
2696 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
2697 | return 0; |
2698 | ||
8f6aa8ee KH |
2699 | /* XXX check module SIDLEMODE, hardreset status */ |
2700 | ||
021b6ff0 TK |
2701 | return omap_cm_wait_module_ready(oh->clkdm->prcm_partition, |
2702 | oh->clkdm->cm_inst, | |
2703 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
2704 | } |
2705 | ||
b8249cf2 KH |
2706 | /** |
2707 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2708 | * @oh: struct omap_hwmod * to assert hardreset | |
2709 | * @ohri: hardreset line data | |
2710 | * | |
2711 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2712 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2713 | * use as an soc_ops function pointer. Passes along the return value | |
2714 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2715 | * for removal when the PRM code is moved into drivers/. | |
2716 | */ | |
2717 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2718 | struct omap_hwmod_rst_info *ohri) | |
2719 | { | |
efd44dc3 TK |
2720 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
2721 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2722 | } |
2723 | ||
2724 | /** | |
2725 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2726 | * @oh: struct omap_hwmod * to deassert hardreset | |
2727 | * @ohri: hardreset line data | |
2728 | * | |
2729 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2730 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2731 | * use as an soc_ops function pointer. Passes along the return value | |
2732 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2733 | * scheduled for removal when the PRM code is moved into drivers/. | |
2734 | */ | |
2735 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2736 | struct omap_hwmod_rst_info *ohri) | |
2737 | { | |
37fb59d7 TK |
2738 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
2739 | oh->prcm.omap2.module_offs, 0, 0); | |
b8249cf2 KH |
2740 | } |
2741 | ||
2742 | /** | |
2743 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2744 | * @oh: struct omap_hwmod * to test hardreset | |
2745 | * @ohri: hardreset line data | |
2746 | * | |
2747 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2748 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2749 | * intended for use as an soc_ops function pointer. Passes along the | |
2750 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2751 | * function is scheduled for removal when the PRM code is moved into | |
2752 | * drivers/. | |
2753 | */ | |
2754 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2755 | struct omap_hwmod_rst_info *ohri) | |
2756 | { | |
1bc28b34 TK |
2757 | return omap_prm_is_hardreset_asserted(ohri->st_shift, 0, |
2758 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2759 | } |
2760 | ||
2761 | /** | |
2762 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2763 | * @oh: struct omap_hwmod * to assert hardreset | |
2764 | * @ohri: hardreset line data | |
2765 | * | |
2766 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2767 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2768 | * intended for use as an soc_ops function pointer. Passes along the | |
2769 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2770 | * function is scheduled for removal when the PRM code is moved into | |
2771 | * drivers/. | |
2772 | */ | |
2773 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2774 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2775 | { |
07b3a139 PW |
2776 | if (!oh->clkdm) |
2777 | return -EINVAL; | |
2778 | ||
efd44dc3 TK |
2779 | return omap_prm_assert_hardreset(ohri->rst_shift, |
2780 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2781 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2782 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2783 | } |
2784 | ||
2785 | /** | |
2786 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2787 | * @oh: struct omap_hwmod * to deassert hardreset | |
2788 | * @ohri: hardreset line data | |
2789 | * | |
2790 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2791 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2792 | * intended for use as an soc_ops function pointer. Passes along the | |
2793 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2794 | * function is scheduled for removal when the PRM code is moved into | |
2795 | * drivers/. | |
2796 | */ | |
2797 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2798 | struct omap_hwmod_rst_info *ohri) | |
2799 | { | |
07b3a139 PW |
2800 | if (!oh->clkdm) |
2801 | return -EINVAL; | |
2802 | ||
b8249cf2 KH |
2803 | if (ohri->st_shift) |
2804 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2805 | oh->name, ohri->name); | |
4ebf5b28 | 2806 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, |
37fb59d7 TK |
2807 | oh->clkdm->pwrdm.ptr->prcm_partition, |
2808 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
4ebf5b28 TK |
2809 | oh->prcm.omap4.rstctrl_offs, |
2810 | oh->prcm.omap4.rstctrl_offs + | |
2811 | OMAP4_RST_CTRL_ST_OFFSET); | |
b8249cf2 KH |
2812 | } |
2813 | ||
2814 | /** | |
2815 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2816 | * @oh: struct omap_hwmod * to test hardreset | |
2817 | * @ohri: hardreset line data | |
2818 | * | |
2819 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2820 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2821 | * Only intended for use as an soc_ops function pointer. Passes along | |
2822 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2823 | * This function is scheduled for removal when the PRM code is moved | |
2824 | * into drivers/. | |
2825 | */ | |
2826 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2827 | struct omap_hwmod_rst_info *ohri) | |
2828 | { | |
07b3a139 PW |
2829 | if (!oh->clkdm) |
2830 | return -EINVAL; | |
2831 | ||
1bc28b34 TK |
2832 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, |
2833 | oh->clkdm->pwrdm.ptr-> | |
2834 | prcm_partition, | |
2835 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2836 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2837 | } |
2838 | ||
9fabc1a2 TK |
2839 | /** |
2840 | * _omap4_disable_direct_prcm - disable direct PRCM control for hwmod | |
2841 | * @oh: struct omap_hwmod * to disable control for | |
2842 | * | |
2843 | * Disables direct PRCM clkctrl done by hwmod core. Instead, the hwmod | |
2844 | * will be using its main_clk to enable/disable the module. Returns | |
2845 | * 0 if successful. | |
2846 | */ | |
2847 | static int _omap4_disable_direct_prcm(struct omap_hwmod *oh) | |
2848 | { | |
2849 | if (!oh) | |
2850 | return -EINVAL; | |
2851 | ||
8823ddf2 | 2852 | oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK; |
9fabc1a2 TK |
2853 | |
2854 | return 0; | |
2855 | } | |
2856 | ||
1688bf19 VH |
2857 | /** |
2858 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2859 | * @oh: struct omap_hwmod * to deassert hardreset | |
2860 | * @ohri: hardreset line data | |
2861 | * | |
2862 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2863 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2864 | * intended for use as an soc_ops function pointer. Passes along the | |
2865 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2866 | * function is scheduled for removal when the PRM code is moved into | |
2867 | * drivers/. | |
2868 | */ | |
2869 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2870 | struct omap_hwmod_rst_info *ohri) | |
2871 | { | |
a5bf00cd TK |
2872 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, |
2873 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
37fb59d7 TK |
2874 | oh->clkdm->pwrdm.ptr->prcm_offs, |
2875 | oh->prcm.omap4.rstctrl_offs, | |
2876 | oh->prcm.omap4.rstst_offs); | |
1688bf19 VH |
2877 | } |
2878 | ||
0102b627 BC |
2879 | /* Public functions */ |
2880 | ||
2881 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2882 | { | |
2883 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2884 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 2885 | else |
edfaf05c | 2886 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2887 | } |
2888 | ||
2889 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2890 | { | |
2891 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2892 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 2893 | else |
edfaf05c | 2894 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2895 | } |
2896 | ||
6d3c55fd A |
2897 | /** |
2898 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2899 | * @oh: struct omap_hwmod * | |
2900 | * | |
2901 | * This is a public function exposed to drivers. Some drivers may need to do | |
2902 | * some settings before and after resetting the device. Those drivers after | |
2903 | * doing the necessary settings could use this function to start a reset by | |
2904 | * setting the SYSCONFIG.SOFTRESET bit. | |
2905 | */ | |
2906 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
2907 | { | |
3c55c1ba PW |
2908 | u32 v; |
2909 | int ret; | |
2910 | ||
2911 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
2912 | return -EINVAL; |
2913 | ||
3c55c1ba PW |
2914 | v = oh->_sysc_cache; |
2915 | ret = _set_softreset(oh, &v); | |
2916 | if (ret) | |
2917 | goto error; | |
2918 | _write_sysconfig(v, oh); | |
2919 | ||
313a76ee RQ |
2920 | ret = _clear_softreset(oh, &v); |
2921 | if (ret) | |
2922 | goto error; | |
2923 | _write_sysconfig(v, oh); | |
2924 | ||
3c55c1ba PW |
2925 | error: |
2926 | return ret; | |
6d3c55fd A |
2927 | } |
2928 | ||
63c85238 PW |
2929 | /** |
2930 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
2931 | * @name: name of the omap_hwmod to look up | |
2932 | * | |
2933 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
2934 | * struct omap_hwmod *, or NULL upon error. | |
2935 | */ | |
2936 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
2937 | { | |
2938 | struct omap_hwmod *oh; | |
2939 | ||
2940 | if (!name) | |
2941 | return NULL; | |
2942 | ||
63c85238 | 2943 | oh = _lookup(name); |
63c85238 PW |
2944 | |
2945 | return oh; | |
2946 | } | |
2947 | ||
2948 | /** | |
2949 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
2950 | * @fn: pointer to a callback function | |
97d60162 | 2951 | * @data: void * data to pass to callback function |
63c85238 PW |
2952 | * |
2953 | * Call @fn for each registered omap_hwmod, passing @data to each | |
2954 | * function. @fn must return 0 for success or any other value for | |
2955 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
2956 | * will stop and the non-zero return value will be passed to the | |
2957 | * caller of omap_hwmod_for_each(). @fn is called with | |
2958 | * omap_hwmod_for_each() held. | |
2959 | */ | |
97d60162 PW |
2960 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
2961 | void *data) | |
63c85238 PW |
2962 | { |
2963 | struct omap_hwmod *temp_oh; | |
30ebad9d | 2964 | int ret = 0; |
63c85238 PW |
2965 | |
2966 | if (!fn) | |
2967 | return -EINVAL; | |
2968 | ||
63c85238 | 2969 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 2970 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
2971 | if (ret) |
2972 | break; | |
2973 | } | |
63c85238 PW |
2974 | |
2975 | return ret; | |
2976 | } | |
2977 | ||
2221b5cd PW |
2978 | /** |
2979 | * omap_hwmod_register_links - register an array of hwmod links | |
2980 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
2981 | * | |
2982 | * Intended to be called early in boot before the clock framework is | |
2983 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
2984 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
2985 | * omap_hwmod_init() hasn't been called before calling this function, | |
2986 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
2987 | * success. | |
2221b5cd PW |
2988 | */ |
2989 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
2990 | { | |
2991 | int r, i; | |
2992 | ||
9ebfd285 KH |
2993 | if (!inited) |
2994 | return -EINVAL; | |
2995 | ||
2221b5cd PW |
2996 | if (!ois) |
2997 | return 0; | |
2998 | ||
f7f7a29b RN |
2999 | if (ois[0] == NULL) /* Empty list */ |
3000 | return 0; | |
3001 | ||
2221b5cd PW |
3002 | i = 0; |
3003 | do { | |
3004 | r = _register_link(ois[i]); | |
3005 | WARN(r && r != -EEXIST, | |
3006 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3007 | ois[i]->master->name, ois[i]->slave->name, r); | |
3008 | } while (ois[++i]); | |
3009 | ||
3010 | return 0; | |
3011 | } | |
3012 | ||
381d033a PW |
3013 | /** |
3014 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3015 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3016 | * | |
3017 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3018 | * hasn't been initialized and set up yet, do so now. This must be | |
3019 | * done first since sleep dependencies may be added from other hwmods | |
3020 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3021 | * return value. | |
63c85238 | 3022 | */ |
381d033a | 3023 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3024 | { |
381d033a PW |
3025 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3026 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3027 | __func__, MPU_INITIATOR_NAME); | |
3028 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3029 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3030 | } |
3031 | ||
63c85238 | 3032 | /** |
a2debdbd PW |
3033 | * omap_hwmod_setup_one - set up a single hwmod |
3034 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3035 | * | |
381d033a PW |
3036 | * Initialize and set up a single hwmod. Intended to be used for a |
3037 | * small number of early devices, such as the timer IP blocks used for | |
3038 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3039 | * Resolves the struct clk names to struct clk pointers for each | |
3040 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3041 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3042 | */ |
3043 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3044 | { |
3045 | struct omap_hwmod *oh; | |
63c85238 | 3046 | |
a2debdbd PW |
3047 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3048 | ||
a2debdbd PW |
3049 | oh = _lookup(oh_name); |
3050 | if (!oh) { | |
3051 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3052 | return -EINVAL; | |
3053 | } | |
63c85238 | 3054 | |
381d033a | 3055 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3056 | |
381d033a | 3057 | _init(oh, NULL); |
a2debdbd PW |
3058 | _setup(oh, NULL); |
3059 | ||
63c85238 PW |
3060 | return 0; |
3061 | } | |
3062 | ||
8dd6666f LV |
3063 | /** |
3064 | * omap_hwmod_setup_earlycon_flags - set up flags for early console | |
3065 | * | |
3066 | * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as | |
3067 | * early concole so that hwmod core doesn't reset and keep it in idle | |
3068 | * that specific uart. | |
3069 | */ | |
3070 | #ifdef CONFIG_SERIAL_EARLYCON | |
3071 | static void __init omap_hwmod_setup_earlycon_flags(void) | |
3072 | { | |
3073 | struct device_node *np; | |
3074 | struct omap_hwmod *oh; | |
3075 | const char *uart; | |
3076 | ||
3077 | np = of_find_node_by_path("/chosen"); | |
3078 | if (np) { | |
3079 | uart = of_get_property(np, "stdout-path", NULL); | |
3080 | if (uart) { | |
3081 | np = of_find_node_by_path(uart); | |
3082 | if (np) { | |
3083 | uart = of_get_property(np, "ti,hwmods", NULL); | |
3084 | oh = omap_hwmod_lookup(uart); | |
3085 | if (oh) | |
3086 | oh->flags |= DEBUG_OMAPUART_FLAGS; | |
3087 | } | |
3088 | } | |
3089 | } | |
3090 | } | |
3091 | #endif | |
3092 | ||
63c85238 | 3093 | /** |
381d033a | 3094 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3095 | * |
381d033a PW |
3096 | * Initialize and set up all IP blocks registered with the hwmod code. |
3097 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3098 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3099 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3100 | */ |
550c8092 | 3101 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3102 | { |
381d033a | 3103 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3104 | |
381d033a | 3105 | omap_hwmod_for_each(_init, NULL); |
8dd6666f LV |
3106 | #ifdef CONFIG_SERIAL_EARLYCON |
3107 | omap_hwmod_setup_earlycon_flags(); | |
3108 | #endif | |
2092e5cc | 3109 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3110 | |
3111 | return 0; | |
3112 | } | |
8dd5ea72 | 3113 | omap_postcore_initcall(omap_hwmod_setup_all); |
63c85238 | 3114 | |
63c85238 PW |
3115 | /** |
3116 | * omap_hwmod_enable - enable an omap_hwmod | |
3117 | * @oh: struct omap_hwmod * | |
3118 | * | |
74ff3a68 | 3119 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3120 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3121 | */ | |
3122 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3123 | { | |
3124 | int r; | |
dc6d1cda | 3125 | unsigned long flags; |
63c85238 PW |
3126 | |
3127 | if (!oh) | |
3128 | return -EINVAL; | |
3129 | ||
dc6d1cda PW |
3130 | spin_lock_irqsave(&oh->_lock, flags); |
3131 | r = _enable(oh); | |
3132 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3133 | |
3134 | return r; | |
3135 | } | |
3136 | ||
3137 | /** | |
3138 | * omap_hwmod_idle - idle an omap_hwmod | |
3139 | * @oh: struct omap_hwmod * | |
3140 | * | |
74ff3a68 | 3141 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3142 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3143 | */ | |
3144 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3145 | { | |
6da23358 | 3146 | int r; |
dc6d1cda PW |
3147 | unsigned long flags; |
3148 | ||
63c85238 PW |
3149 | if (!oh) |
3150 | return -EINVAL; | |
3151 | ||
dc6d1cda | 3152 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3153 | r = _idle(oh); |
dc6d1cda | 3154 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3155 | |
6da23358 | 3156 | return r; |
63c85238 PW |
3157 | } |
3158 | ||
3159 | /** | |
3160 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3161 | * @oh: struct omap_hwmod * | |
3162 | * | |
74ff3a68 | 3163 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3164 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3165 | * the return value from _shutdown(). | |
3166 | */ | |
3167 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3168 | { | |
6da23358 | 3169 | int r; |
dc6d1cda PW |
3170 | unsigned long flags; |
3171 | ||
63c85238 PW |
3172 | if (!oh) |
3173 | return -EINVAL; | |
3174 | ||
dc6d1cda | 3175 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3176 | r = _shutdown(oh); |
dc6d1cda | 3177 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3178 | |
6da23358 | 3179 | return r; |
63c85238 PW |
3180 | } |
3181 | ||
5e8370f1 PW |
3182 | /* |
3183 | * IP block data retrieval functions | |
3184 | */ | |
3185 | ||
63c85238 PW |
3186 | /** |
3187 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3188 | * @oh: struct omap_hwmod * | |
3189 | * | |
3190 | * Return the powerdomain pointer associated with the OMAP module | |
3191 | * @oh's main clock. If @oh does not have a main clk, return the | |
3192 | * powerdomain associated with the interface clock associated with the | |
3193 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3194 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3195 | * success. | |
3196 | */ | |
3197 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3198 | { | |
3199 | struct clk *c; | |
2d6141ba | 3200 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3201 | struct clockdomain *clkdm; |
f5dd3bb5 | 3202 | struct clk_hw_omap *clk; |
63c85238 PW |
3203 | |
3204 | if (!oh) | |
3205 | return NULL; | |
3206 | ||
f5dd3bb5 RN |
3207 | if (oh->clkdm) |
3208 | return oh->clkdm->pwrdm.ptr; | |
3209 | ||
63c85238 PW |
3210 | if (oh->_clk) { |
3211 | c = oh->_clk; | |
3212 | } else { | |
2d6141ba PW |
3213 | oi = _find_mpu_rt_port(oh); |
3214 | if (!oi) | |
63c85238 | 3215 | return NULL; |
2d6141ba | 3216 | c = oi->_clk; |
63c85238 PW |
3217 | } |
3218 | ||
f5dd3bb5 RN |
3219 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3220 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3221 | if (!clkdm) |
d5647c18 TG |
3222 | return NULL; |
3223 | ||
f5dd3bb5 | 3224 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3225 | } |
3226 | ||
db2a60bf PW |
3227 | /** |
3228 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3229 | * @oh: struct omap_hwmod * | |
3230 | * | |
3231 | * Returns the virtual address corresponding to the beginning of the | |
3232 | * module's register target, in the address range that is intended to | |
3233 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3234 | * upon error. | |
3235 | */ | |
3236 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3237 | { | |
3238 | if (!oh) | |
3239 | return NULL; | |
3240 | ||
3241 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3242 | return NULL; | |
3243 | ||
3244 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3245 | return NULL; | |
3246 | ||
3247 | return oh->_mpu_rt_va; | |
3248 | } | |
3249 | ||
63c85238 PW |
3250 | /* |
3251 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3252 | * for context save/restore operations? | |
3253 | */ | |
3254 | ||
63c85238 PW |
3255 | /** |
3256 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3257 | * @oh: struct omap_hwmod * | |
3258 | * | |
3259 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3260 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3261 | * this IP block if it has dynamic mux entries. Eventually this | |
3262 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3263 | * wakeup events from the module. Does not set any wakeup routing | |
3264 | * registers beyond this point - if the module is to wake up any other | |
3265 | * module or subsystem, that must be set separately. Called by | |
3266 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3267 | */ |
3268 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3269 | { | |
dc6d1cda | 3270 | unsigned long flags; |
5a7ddcbd | 3271 | u32 v; |
dc6d1cda | 3272 | |
dc6d1cda | 3273 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3274 | |
3275 | if (oh->class->sysc && | |
3276 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3277 | v = oh->_sysc_cache; | |
3278 | _enable_wakeup(oh, &v); | |
3279 | _write_sysconfig(v, oh); | |
3280 | } | |
3281 | ||
dc6d1cda | 3282 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3283 | |
3284 | return 0; | |
3285 | } | |
3286 | ||
3287 | /** | |
3288 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3289 | * @oh: struct omap_hwmod * | |
3290 | * | |
3291 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3292 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3293 | * events for this IP block if it has dynamic mux entries. Eventually | |
3294 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3295 | * wakeup events from the module. Does not set any wakeup routing | |
3296 | * registers beyond this point - if the module is to wake up any other | |
3297 | * module or subsystem, that must be set separately. Called by | |
3298 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3299 | */ |
3300 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3301 | { | |
dc6d1cda | 3302 | unsigned long flags; |
5a7ddcbd | 3303 | u32 v; |
dc6d1cda | 3304 | |
dc6d1cda | 3305 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3306 | |
3307 | if (oh->class->sysc && | |
3308 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3309 | v = oh->_sysc_cache; | |
3310 | _disable_wakeup(oh, &v); | |
3311 | _write_sysconfig(v, oh); | |
3312 | } | |
3313 | ||
dc6d1cda | 3314 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3315 | |
3316 | return 0; | |
3317 | } | |
43b40992 | 3318 | |
aee48e3c PW |
3319 | /** |
3320 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3321 | * contained in the hwmod module. | |
3322 | * @oh: struct omap_hwmod * | |
3323 | * @name: name of the reset line to lookup and assert | |
3324 | * | |
3325 | * Some IP like dsp, ipu or iva contain processor that require | |
3326 | * an HW reset line to be assert / deassert in order to enable fully | |
3327 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3328 | * yet supported on this OMAP; otherwise, passes along the return value | |
3329 | * from _assert_hardreset(). | |
3330 | */ | |
3331 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3332 | { | |
3333 | int ret; | |
dc6d1cda | 3334 | unsigned long flags; |
aee48e3c PW |
3335 | |
3336 | if (!oh) | |
3337 | return -EINVAL; | |
3338 | ||
dc6d1cda | 3339 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3340 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3341 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3342 | |
3343 | return ret; | |
3344 | } | |
3345 | ||
3346 | /** | |
3347 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3348 | * contained in the hwmod module. | |
3349 | * @oh: struct omap_hwmod * | |
3350 | * @name: name of the reset line to look up and deassert | |
3351 | * | |
3352 | * Some IP like dsp, ipu or iva contain processor that require | |
3353 | * an HW reset line to be assert / deassert in order to enable fully | |
3354 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3355 | * yet supported on this OMAP; otherwise, passes along the return value | |
3356 | * from _deassert_hardreset(). | |
3357 | */ | |
3358 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3359 | { | |
3360 | int ret; | |
dc6d1cda | 3361 | unsigned long flags; |
aee48e3c PW |
3362 | |
3363 | if (!oh) | |
3364 | return -EINVAL; | |
3365 | ||
dc6d1cda | 3366 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3367 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3368 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3369 | |
3370 | return ret; | |
3371 | } | |
3372 | ||
43b40992 PW |
3373 | /** |
3374 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3375 | * @classname: struct omap_hwmod_class name to search for | |
3376 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3377 | * @user: arbitrary context data to pass to the callback function | |
3378 | * | |
ce35b244 BC |
3379 | * For each omap_hwmod of class @classname, call @fn. |
3380 | * If the callback function returns something other than | |
43b40992 PW |
3381 | * zero, the iterator is terminated, and the callback function's return |
3382 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3383 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3384 | */ | |
3385 | int omap_hwmod_for_each_by_class(const char *classname, | |
3386 | int (*fn)(struct omap_hwmod *oh, | |
3387 | void *user), | |
3388 | void *user) | |
3389 | { | |
3390 | struct omap_hwmod *temp_oh; | |
3391 | int ret = 0; | |
3392 | ||
3393 | if (!classname || !fn) | |
3394 | return -EINVAL; | |
3395 | ||
3396 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3397 | __func__, classname); | |
3398 | ||
43b40992 PW |
3399 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3400 | if (!strcmp(temp_oh->class->name, classname)) { | |
3401 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3402 | __func__, temp_oh->name); | |
3403 | ret = (*fn)(temp_oh, user); | |
3404 | if (ret) | |
3405 | break; | |
3406 | } | |
3407 | } | |
3408 | ||
43b40992 PW |
3409 | if (ret) |
3410 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3411 | __func__, ret); | |
3412 | ||
3413 | return ret; | |
3414 | } | |
3415 | ||
2092e5cc PW |
3416 | /** |
3417 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3418 | * @oh: struct omap_hwmod * | |
3419 | * @state: state that _setup() should leave the hwmod in | |
3420 | * | |
550c8092 | 3421 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3422 | * (called by omap_hwmod_setup_*()). See also the documentation |
3423 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3424 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3425 | * in the wrong state. | |
2092e5cc PW |
3426 | */ |
3427 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3428 | { | |
3429 | int ret; | |
dc6d1cda | 3430 | unsigned long flags; |
2092e5cc PW |
3431 | |
3432 | if (!oh) | |
3433 | return -EINVAL; | |
3434 | ||
3435 | if (state != _HWMOD_STATE_DISABLED && | |
3436 | state != _HWMOD_STATE_ENABLED && | |
3437 | state != _HWMOD_STATE_IDLE) | |
3438 | return -EINVAL; | |
3439 | ||
dc6d1cda | 3440 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3441 | |
3442 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3443 | ret = -EINVAL; | |
3444 | goto ohsps_unlock; | |
3445 | } | |
3446 | ||
3447 | oh->_postsetup_state = state; | |
3448 | ret = 0; | |
3449 | ||
3450 | ohsps_unlock: | |
dc6d1cda | 3451 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3452 | |
3453 | return ret; | |
3454 | } | |
c80705aa KH |
3455 | |
3456 | /** | |
3457 | * omap_hwmod_get_context_loss_count - get lost context count | |
3458 | * @oh: struct omap_hwmod * | |
3459 | * | |
e6d3a8b0 RN |
3460 | * Returns the context loss count of associated @oh |
3461 | * upon success, or zero if no context loss data is available. | |
c80705aa | 3462 | * |
e6d3a8b0 RN |
3463 | * On OMAP4, this queries the per-hwmod context loss register, |
3464 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
3465 | * enclosing powerdomain context loss count. | |
c80705aa | 3466 | */ |
fc013873 | 3467 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3468 | { |
3469 | struct powerdomain *pwrdm; | |
3470 | int ret = 0; | |
3471 | ||
e6d3a8b0 RN |
3472 | if (soc_ops.get_context_lost) |
3473 | return soc_ops.get_context_lost(oh); | |
3474 | ||
c80705aa KH |
3475 | pwrdm = omap_hwmod_get_pwrdm(oh); |
3476 | if (pwrdm) | |
3477 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3478 | ||
3479 | return ret; | |
3480 | } | |
43b01643 | 3481 | |
9ebfd285 KH |
3482 | /** |
3483 | * omap_hwmod_init - initialize the hwmod code | |
3484 | * | |
3485 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3486 | * currently-booted SoC. Intended to be called once during kernel init | |
3487 | * before any hwmods are registered. No return value. | |
3488 | */ | |
3489 | void __init omap_hwmod_init(void) | |
3490 | { | |
ff4ae5d9 | 3491 | if (cpu_is_omap24xx()) { |
9002e921 | 3492 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
ff4ae5d9 PW |
3493 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3494 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3495 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3496 | } else if (cpu_is_omap34xx()) { | |
9002e921 | 3497 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
b8249cf2 KH |
3498 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3499 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3500 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 3501 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 3502 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
3503 | soc_ops.enable_module = _omap4_enable_module; |
3504 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 3505 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
3506 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3507 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
3508 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 3509 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
3510 | soc_ops.update_context_lost = _omap4_update_context_lost; |
3511 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
9fabc1a2 | 3512 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
70f05be3 | 3513 | soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; |
0f3ccb24 TL |
3514 | } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || |
3515 | soc_is_am43xx()) { | |
c8b428a5 AM |
3516 | soc_ops.enable_module = _omap4_enable_module; |
3517 | soc_ops.disable_module = _omap4_disable_module; | |
3518 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
409d7063 | 3519 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
1688bf19 | 3520 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; |
a5bf00cd | 3521 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; |
1688bf19 | 3522 | soc_ops.init_clkdm = _init_clkdm; |
9fabc1a2 | 3523 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
8f6aa8ee KH |
3524 | } else { |
3525 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
3526 | } |
3527 | ||
70f05be3 TK |
3528 | _init_clkctrl_providers(); |
3529 | ||
9ebfd285 KH |
3530 | inited = true; |
3531 | } | |
68c9a95e TL |
3532 | |
3533 | /** | |
3534 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
3535 | * @oh: struct omap_hwmod * | |
3536 | * | |
3537 | * Returns the main clock name assocated with @oh upon success, | |
3538 | * or NULL if @oh is NULL. | |
3539 | */ | |
3540 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
3541 | { | |
3542 | if (!oh) | |
3543 | return NULL; | |
3544 | ||
3545 | return oh->main_clk; | |
3546 | } |