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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5b00f6f | 133 | #include <linux/clk.h> |
f5dd3bb5 | 134 | #include <linux/clk-provider.h> |
63c85238 PW |
135 | #include <linux/delay.h> |
136 | #include <linux/err.h> | |
137 | #include <linux/list.h> | |
138 | #include <linux/mutex.h> | |
dc6d1cda | 139 | #include <linux/spinlock.h> |
abc2d545 | 140 | #include <linux/slab.h> |
f7b861b7 | 141 | #include <linux/cpu.h> |
079abade SS |
142 | #include <linux/of.h> |
143 | #include <linux/of_address.h> | |
57c8a661 | 144 | #include <linux/memblock.h> |
63c85238 | 145 | |
49a0a3d8 TL |
146 | #include <linux/platform_data/ti-sysc.h> |
147 | ||
8c879705 TL |
148 | #include <dt-bindings/bus/ti-sysc.h> |
149 | ||
fa200222 PW |
150 | #include <asm/system_misc.h> |
151 | ||
a135eaae | 152 | #include "clock.h" |
2a296c8f | 153 | #include "omap_hwmod.h" |
63c85238 | 154 | |
dbc04161 TL |
155 | #include "soc.h" |
156 | #include "common.h" | |
157 | #include "clockdomain.h" | |
158 | #include "powerdomain.h" | |
ff4ae5d9 PW |
159 | #include "cm2xxx.h" |
160 | #include "cm3xxx.h" | |
1688bf19 | 161 | #include "cm33xx.h" |
b13159af | 162 | #include "prm.h" |
139563ad | 163 | #include "prm3xxx.h" |
d198b514 | 164 | #include "prm44xx.h" |
1688bf19 | 165 | #include "prm33xx.h" |
eaac329d | 166 | #include "prminst44xx.h" |
5165882a | 167 | #include "pm.h" |
63c85238 | 168 | |
63c85238 | 169 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 170 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 171 | |
2221b5cd PW |
172 | /* |
173 | * Number of struct omap_hwmod_link records per struct | |
174 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
175 | */ | |
176 | #define LINKS_PER_OCP_IF 2 | |
177 | ||
4ebf5b28 TK |
178 | /* |
179 | * Address offset (in bytes) between the reset control and the reset | |
180 | * status registers: 4 bytes on OMAP4 | |
181 | */ | |
182 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | |
183 | ||
9fabc1a2 TK |
184 | /* |
185 | * Maximum length for module clock handle names | |
186 | */ | |
187 | #define MOD_CLK_MAX_NAME_LEN 32 | |
188 | ||
70f05be3 TK |
189 | /** |
190 | * struct clkctrl_provider - clkctrl provider mapping data | |
1b9c30fe TK |
191 | * @num_addrs: number of base address ranges for the provider |
192 | * @addr: base address(es) for the provider | |
193 | * @size: size(s) of the provider address space(s) | |
70f05be3 TK |
194 | * @node: device node associated with the provider |
195 | * @link: list link | |
196 | */ | |
197 | struct clkctrl_provider { | |
1b9c30fe TK |
198 | int num_addrs; |
199 | u32 *addr; | |
200 | u32 *size; | |
70f05be3 TK |
201 | struct device_node *node; |
202 | struct list_head link; | |
203 | }; | |
204 | ||
205 | static LIST_HEAD(clkctrl_providers); | |
206 | ||
9ebfd285 KH |
207 | /** |
208 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
209 | * @enable_module: function to enable a module (via MODULEMODE) | |
210 | * @disable_module: function to disable a module (via MODULEMODE) | |
211 | * | |
212 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
213 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
214 | * conditionals in this code. | |
215 | */ | |
216 | struct omap_hwmod_soc_ops { | |
217 | void (*enable_module)(struct omap_hwmod *oh); | |
218 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 219 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
220 | int (*assert_hardreset)(struct omap_hwmod *oh, |
221 | struct omap_hwmod_rst_info *ohri); | |
222 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
223 | struct omap_hwmod_rst_info *ohri); | |
224 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
225 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 226 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
227 | void (*update_context_lost)(struct omap_hwmod *oh); |
228 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9fabc1a2 | 229 | int (*disable_direct_prcm)(struct omap_hwmod *oh); |
6e83ecaa | 230 | u32 (*xlate_clkctrl)(struct omap_hwmod *oh); |
9ebfd285 KH |
231 | }; |
232 | ||
233 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
234 | static struct omap_hwmod_soc_ops soc_ops; | |
235 | ||
63c85238 PW |
236 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
237 | static LIST_HEAD(omap_hwmod_list); | |
238 | ||
63c85238 PW |
239 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
240 | static struct omap_hwmod *mpu_oh; | |
241 | ||
9ebfd285 KH |
242 | /* inited: set to true once the hwmod code is initialized */ |
243 | static bool inited; | |
244 | ||
63c85238 PW |
245 | /* Private functions */ |
246 | ||
247 | /** | |
248 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
249 | * @oh: struct omap_hwmod * | |
250 | * | |
251 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
252 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
253 | * OCP_SYSCONFIG register or 0 upon success. | |
254 | */ | |
255 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
256 | { | |
43b40992 PW |
257 | if (!oh->class->sysc) { |
258 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
259 | return -EINVAL; |
260 | } | |
261 | ||
262 | /* XXX ensure module interface clock is up */ | |
263 | ||
cc7a1d2a | 264 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 265 | |
43b40992 | 266 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 267 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
268 | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /** | |
273 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
274 | * @v: OCP_SYSCONFIG value to write | |
275 | * @oh: struct omap_hwmod * | |
276 | * | |
43b40992 PW |
277 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
278 | * one. No return value. | |
63c85238 PW |
279 | */ |
280 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
281 | { | |
43b40992 PW |
282 | if (!oh->class->sysc) { |
283 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
284 | return; |
285 | } | |
286 | ||
287 | /* XXX ensure module interface clock is up */ | |
288 | ||
233cbe5b RN |
289 | /* Module might have lost context, always update cache and register */ |
290 | oh->_sysc_cache = v; | |
aaf2c0fb LV |
291 | |
292 | /* | |
293 | * Some IP blocks (such as RTC) require unlocking of IP before | |
294 | * accessing its registers. If a function pointer is present | |
295 | * to unlock, then call it before accessing sysconfig and | |
296 | * call lock after writing sysconfig. | |
297 | */ | |
298 | if (oh->class->unlock) | |
299 | oh->class->unlock(oh); | |
300 | ||
233cbe5b | 301 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
aaf2c0fb LV |
302 | |
303 | if (oh->class->lock) | |
304 | oh->class->lock(oh); | |
63c85238 PW |
305 | } |
306 | ||
307 | /** | |
308 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
309 | * @oh: struct omap_hwmod * | |
310 | * @standbymode: MIDLEMODE field bits | |
311 | * @v: pointer to register contents to modify | |
312 | * | |
313 | * Update the master standby mode bits in @v to be @standbymode for | |
314 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
315 | * upon error or 0 upon success. | |
316 | */ | |
317 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
318 | u32 *v) | |
319 | { | |
358f0e63 TG |
320 | u32 mstandby_mask; |
321 | u8 mstandby_shift; | |
322 | ||
43b40992 PW |
323 | if (!oh->class->sysc || |
324 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
325 | return -EINVAL; |
326 | ||
43b40992 PW |
327 | if (!oh->class->sysc->sysc_fields) { |
328 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
329 | return -EINVAL; |
330 | } | |
331 | ||
43b40992 | 332 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
333 | mstandby_mask = (0x3 << mstandby_shift); |
334 | ||
335 | *v &= ~mstandby_mask; | |
336 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | /** | |
342 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
343 | * @oh: struct omap_hwmod * | |
344 | * @idlemode: SIDLEMODE field bits | |
345 | * @v: pointer to register contents to modify | |
346 | * | |
347 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
348 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
349 | * or 0 upon success. | |
350 | */ | |
351 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
352 | { | |
358f0e63 TG |
353 | u32 sidle_mask; |
354 | u8 sidle_shift; | |
355 | ||
43b40992 PW |
356 | if (!oh->class->sysc || |
357 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
358 | return -EINVAL; |
359 | ||
43b40992 PW |
360 | if (!oh->class->sysc->sysc_fields) { |
361 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
362 | return -EINVAL; |
363 | } | |
364 | ||
43b40992 | 365 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
366 | sidle_mask = (0x3 << sidle_shift); |
367 | ||
368 | *v &= ~sidle_mask; | |
369 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
370 | |
371 | return 0; | |
372 | } | |
373 | ||
374 | /** | |
375 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
376 | * @oh: struct omap_hwmod * | |
377 | * @clockact: CLOCKACTIVITY field bits | |
378 | * @v: pointer to register contents to modify | |
379 | * | |
380 | * Update the clockactivity mode bits in @v to be @clockact for the | |
381 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
382 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
383 | * success. | |
384 | */ | |
385 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
386 | { | |
358f0e63 TG |
387 | u32 clkact_mask; |
388 | u8 clkact_shift; | |
389 | ||
43b40992 PW |
390 | if (!oh->class->sysc || |
391 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
392 | return -EINVAL; |
393 | ||
43b40992 PW |
394 | if (!oh->class->sysc->sysc_fields) { |
395 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
396 | return -EINVAL; |
397 | } | |
398 | ||
43b40992 | 399 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
400 | clkact_mask = (0x3 << clkact_shift); |
401 | ||
402 | *v &= ~clkact_mask; | |
403 | *v |= clockact << clkact_shift; | |
63c85238 PW |
404 | |
405 | return 0; | |
406 | } | |
407 | ||
408 | /** | |
313a76ee | 409 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
410 | * @oh: struct omap_hwmod * |
411 | * @v: pointer to register contents to modify | |
412 | * | |
413 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
414 | * error or 0 upon success. | |
415 | */ | |
416 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
417 | { | |
358f0e63 TG |
418 | u32 softrst_mask; |
419 | ||
43b40992 PW |
420 | if (!oh->class->sysc || |
421 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
422 | return -EINVAL; |
423 | ||
43b40992 PW |
424 | if (!oh->class->sysc->sysc_fields) { |
425 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
426 | return -EINVAL; |
427 | } | |
428 | ||
43b40992 | 429 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
430 | |
431 | *v |= softrst_mask; | |
63c85238 PW |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
313a76ee RQ |
436 | /** |
437 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
438 | * @oh: struct omap_hwmod * | |
439 | * @v: pointer to register contents to modify | |
440 | * | |
441 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
442 | * error or 0 upon success. | |
443 | */ | |
444 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
445 | { | |
446 | u32 softrst_mask; | |
447 | ||
448 | if (!oh->class->sysc || | |
449 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
450 | return -EINVAL; | |
451 | ||
452 | if (!oh->class->sysc->sysc_fields) { | |
453 | WARN(1, | |
454 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
455 | oh->name); | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
459 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
460 | ||
461 | *v &= ~softrst_mask; | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
613ad0e9 TK |
466 | /** |
467 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
468 | * @oh: struct omap_hwmod * to wait on | |
469 | * | |
470 | * Wait until the IP block represented by @oh reports that its OCP | |
471 | * softreset is complete. This can be triggered by software (see | |
472 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
473 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
474 | * microseconds. Returns the number of microseconds waited. | |
475 | */ | |
476 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
477 | { | |
478 | struct omap_hwmod_class_sysconfig *sysc; | |
479 | u32 softrst_mask; | |
480 | int c = 0; | |
481 | ||
482 | sysc = oh->class->sysc; | |
483 | ||
103fd8e7 | 484 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS && sysc->syss_offs > 0) |
613ad0e9 TK |
485 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) |
486 | & SYSS_RESETDONE_MASK), | |
487 | MAX_MODULE_SOFTRESET_WAIT, c); | |
488 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
489 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
490 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
491 | & softrst_mask), | |
492 | MAX_MODULE_SOFTRESET_WAIT, c); | |
493 | } | |
494 | ||
495 | return c; | |
496 | } | |
497 | ||
6668546f KVA |
498 | /** |
499 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
500 | * @oh: struct omap_hwmod * | |
501 | * | |
502 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
503 | * of some modules. When the DMA must perform read/write accesses, the | |
504 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
505 | * for power management, software must set the DMADISABLE bit back to 1. | |
506 | * | |
507 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
508 | * error or 0 upon success. | |
509 | */ | |
510 | static int _set_dmadisable(struct omap_hwmod *oh) | |
511 | { | |
512 | u32 v; | |
513 | u32 dmadisable_mask; | |
514 | ||
515 | if (!oh->class->sysc || | |
516 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
517 | return -EINVAL; | |
518 | ||
519 | if (!oh->class->sysc->sysc_fields) { | |
520 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
521 | return -EINVAL; | |
522 | } | |
523 | ||
524 | /* clocks must be on for this operation */ | |
525 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
526 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
527 | return -EINVAL; | |
528 | } | |
529 | ||
530 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
531 | ||
532 | v = oh->_sysc_cache; | |
533 | dmadisable_mask = | |
534 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
535 | v |= dmadisable_mask; | |
536 | _write_sysconfig(v, oh); | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
726072e5 PW |
541 | /** |
542 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
543 | * @oh: struct omap_hwmod * | |
544 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
545 | * @v: pointer to register contents to modify | |
546 | * | |
547 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
548 | * hwmod. The autoidle bit controls whether the module can gate | |
549 | * internal clocks automatically when it isn't doing anything; the | |
550 | * exact function of this bit varies on a per-module basis. This | |
551 | * function does not write to the hardware. Returns -EINVAL upon | |
552 | * error or 0 upon success. | |
553 | */ | |
554 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
555 | u32 *v) | |
556 | { | |
358f0e63 TG |
557 | u32 autoidle_mask; |
558 | u8 autoidle_shift; | |
559 | ||
43b40992 PW |
560 | if (!oh->class->sysc || |
561 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
562 | return -EINVAL; |
563 | ||
43b40992 PW |
564 | if (!oh->class->sysc->sysc_fields) { |
565 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
566 | return -EINVAL; |
567 | } | |
568 | ||
43b40992 | 569 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 570 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
571 | |
572 | *v &= ~autoidle_mask; | |
573 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
574 | |
575 | return 0; | |
576 | } | |
577 | ||
63c85238 PW |
578 | /** |
579 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
580 | * @oh: struct omap_hwmod * | |
581 | * | |
582 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
583 | * upon error or 0 upon success. | |
584 | */ | |
5a7ddcbd | 585 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 586 | { |
43b40992 | 587 | if (!oh->class->sysc || |
86009eb3 | 588 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
589 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
590 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
591 | return -EINVAL; |
592 | ||
43b40992 PW |
593 | if (!oh->class->sysc->sysc_fields) { |
594 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
595 | return -EINVAL; |
596 | } | |
597 | ||
1fe74113 BC |
598 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
599 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 600 | |
86009eb3 BC |
601 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
602 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
603 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
604 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 605 | |
63c85238 PW |
606 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
607 | ||
63c85238 PW |
608 | return 0; |
609 | } | |
610 | ||
611 | /** | |
612 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
613 | * @oh: struct omap_hwmod * | |
614 | * | |
615 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
616 | * upon error or 0 upon success. | |
617 | */ | |
5a7ddcbd | 618 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 619 | { |
43b40992 | 620 | if (!oh->class->sysc || |
86009eb3 | 621 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
622 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
623 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
624 | return -EINVAL; |
625 | ||
43b40992 PW |
626 | if (!oh->class->sysc->sysc_fields) { |
627 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
628 | return -EINVAL; |
629 | } | |
630 | ||
1fe74113 BC |
631 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
632 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 633 | |
86009eb3 BC |
634 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
635 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 636 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 637 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 638 | |
63c85238 PW |
639 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
640 | ||
63c85238 PW |
641 | return 0; |
642 | } | |
643 | ||
f5dd3bb5 RN |
644 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
645 | { | |
c4a1ea2c RN |
646 | struct clk_hw_omap *clk; |
647 | ||
f5dd3bb5 RN |
648 | if (oh->clkdm) { |
649 | return oh->clkdm; | |
650 | } else if (oh->_clk) { | |
924f9498 TK |
651 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
652 | return NULL; | |
f5dd3bb5 RN |
653 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
654 | return clk->clkdm; | |
f5dd3bb5 RN |
655 | } |
656 | return NULL; | |
657 | } | |
658 | ||
63c85238 PW |
659 | /** |
660 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
661 | * @oh: struct omap_hwmod * | |
662 | * | |
663 | * Prevent the hardware module @oh from entering idle while the | |
664 | * hardare module initiator @init_oh is active. Useful when a module | |
665 | * will be accessed by a particular initiator (e.g., if a module will | |
666 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
667 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
668 | * mode. If the clockdomain is marked as not needing autodeps, return |
669 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
670 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
671 | */ |
672 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
673 | { | |
f5dd3bb5 RN |
674 | struct clockdomain *clkdm, *init_clkdm; |
675 | ||
676 | clkdm = _get_clkdm(oh); | |
677 | init_clkdm = _get_clkdm(init_oh); | |
678 | ||
679 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
680 | return -EINVAL; |
681 | ||
f5dd3bb5 | 682 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
683 | return 0; |
684 | ||
f5dd3bb5 | 685 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
686 | } |
687 | ||
688 | /** | |
689 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
690 | * @oh: struct omap_hwmod * | |
691 | * | |
692 | * Allow the hardware module @oh to enter idle while the hardare | |
693 | * module initiator @init_oh is active. Useful when a module will not | |
694 | * be accessed by a particular initiator (e.g., if a module will not | |
695 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
696 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
697 | * mode. If the clockdomain is marked as not needing autodeps, return |
698 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
699 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
700 | */ |
701 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
702 | { | |
f5dd3bb5 RN |
703 | struct clockdomain *clkdm, *init_clkdm; |
704 | ||
705 | clkdm = _get_clkdm(oh); | |
706 | init_clkdm = _get_clkdm(init_oh); | |
707 | ||
708 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
709 | return -EINVAL; |
710 | ||
f5dd3bb5 | 711 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
712 | return 0; |
713 | ||
f5dd3bb5 | 714 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
715 | } |
716 | ||
70f05be3 TK |
717 | static const struct of_device_id ti_clkctrl_match_table[] __initconst = { |
718 | { .compatible = "ti,clkctrl" }, | |
719 | { } | |
720 | }; | |
721 | ||
0ca14cde | 722 | static int __init _setup_clkctrl_provider(struct device_node *np) |
70f05be3 TK |
723 | { |
724 | const __be32 *addrp; | |
725 | struct clkctrl_provider *provider; | |
6e83ecaa | 726 | u64 size; |
1b9c30fe | 727 | int i; |
70f05be3 | 728 | |
7e1c4e27 | 729 | provider = memblock_alloc(sizeof(*provider), SMP_CACHE_BYTES); |
70f05be3 TK |
730 | if (!provider) |
731 | return -ENOMEM; | |
732 | ||
70f05be3 TK |
733 | provider->node = np; |
734 | ||
1b9c30fe TK |
735 | provider->num_addrs = |
736 | of_property_count_elems_of_size(np, "reg", sizeof(u32)) / 2; | |
737 | ||
738 | provider->addr = | |
7e1c4e27 MR |
739 | memblock_alloc(sizeof(void *) * provider->num_addrs, |
740 | SMP_CACHE_BYTES); | |
1b9c30fe TK |
741 | if (!provider->addr) |
742 | return -ENOMEM; | |
743 | ||
744 | provider->size = | |
7e1c4e27 MR |
745 | memblock_alloc(sizeof(u32) * provider->num_addrs, |
746 | SMP_CACHE_BYTES); | |
1b9c30fe TK |
747 | if (!provider->size) |
748 | return -ENOMEM; | |
749 | ||
750 | for (i = 0; i < provider->num_addrs; i++) { | |
751 | addrp = of_get_address(np, i, &size, NULL); | |
752 | provider->addr[i] = (u32)of_translate_address(np, addrp); | |
753 | provider->size[i] = size; | |
754 | pr_debug("%s: %pOF: %x...%x\n", __func__, np, provider->addr[i], | |
755 | provider->addr[i] + provider->size[i]); | |
756 | } | |
70f05be3 TK |
757 | |
758 | list_add(&provider->link, &clkctrl_providers); | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
0ca14cde | 763 | static int __init _init_clkctrl_providers(void) |
70f05be3 TK |
764 | { |
765 | struct device_node *np; | |
766 | int ret = 0; | |
767 | ||
768 | for_each_matching_node(np, ti_clkctrl_match_table) { | |
769 | ret = _setup_clkctrl_provider(np); | |
770 | if (ret) | |
771 | break; | |
772 | } | |
773 | ||
774 | return ret; | |
775 | } | |
776 | ||
6e83ecaa | 777 | static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh) |
70f05be3 | 778 | { |
6e83ecaa TK |
779 | if (!oh->prcm.omap4.modulemode) |
780 | return 0; | |
781 | ||
782 | return omap_cm_xlate_clkctrl(oh->clkdm->prcm_partition, | |
783 | oh->clkdm->cm_inst, | |
784 | oh->prcm.omap4.clkctrl_offs); | |
70f05be3 TK |
785 | } |
786 | ||
787 | static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) | |
788 | { | |
789 | struct clkctrl_provider *provider; | |
790 | struct clk *clk; | |
6e83ecaa | 791 | u32 addr; |
70f05be3 TK |
792 | |
793 | if (!soc_ops.xlate_clkctrl) | |
794 | return NULL; | |
795 | ||
6e83ecaa TK |
796 | addr = soc_ops.xlate_clkctrl(oh); |
797 | if (!addr) | |
798 | return NULL; | |
799 | ||
800 | pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr); | |
801 | ||
70f05be3 | 802 | list_for_each_entry(provider, &clkctrl_providers, link) { |
1b9c30fe TK |
803 | int i; |
804 | ||
805 | for (i = 0; i < provider->num_addrs; i++) { | |
806 | if (provider->addr[i] <= addr && | |
807 | provider->addr[i] + provider->size[i] > addr) { | |
808 | struct of_phandle_args clkspec; | |
70f05be3 | 809 | |
1b9c30fe TK |
810 | clkspec.np = provider->node; |
811 | clkspec.args_count = 2; | |
812 | clkspec.args[0] = addr - provider->addr[0]; | |
813 | clkspec.args[1] = 0; | |
70f05be3 | 814 | |
1b9c30fe | 815 | clk = of_clk_get_from_provider(&clkspec); |
70f05be3 | 816 | |
1b9c30fe TK |
817 | pr_debug("%s: %s got %p (offset=%x, provider=%pOF)\n", |
818 | __func__, oh->name, clk, | |
819 | clkspec.args[0], provider->node); | |
6e83ecaa | 820 | |
1b9c30fe TK |
821 | return clk; |
822 | } | |
70f05be3 TK |
823 | } |
824 | } | |
825 | ||
826 | return NULL; | |
827 | } | |
828 | ||
63c85238 PW |
829 | /** |
830 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
831 | * @oh: struct omap_hwmod * | |
832 | * | |
833 | * Called from _init_clocks(). Populates the @oh _clk (main | |
9fabc1a2 TK |
834 | * functional clock pointer) if a clock matching the hwmod name is found, |
835 | * or a main_clk is present. Returns 0 on success or -EINVAL on error. | |
63c85238 PW |
836 | */ |
837 | static int _init_main_clk(struct omap_hwmod *oh) | |
838 | { | |
63c85238 | 839 | int ret = 0; |
70f05be3 | 840 | struct clk *clk = NULL; |
63c85238 | 841 | |
70f05be3 | 842 | clk = _lookup_clkctrl_clk(oh); |
9fabc1a2 | 843 | |
70f05be3 TK |
844 | if (!IS_ERR_OR_NULL(clk)) { |
845 | pr_debug("%s: mapped main_clk %s for %s\n", __func__, | |
846 | __clk_get_name(clk), oh->name); | |
847 | oh->main_clk = __clk_get_name(clk); | |
9fabc1a2 TK |
848 | oh->_clk = clk; |
849 | soc_ops.disable_direct_prcm(oh); | |
9fabc1a2 TK |
850 | } else { |
851 | if (!oh->main_clk) | |
852 | return 0; | |
853 | ||
854 | oh->_clk = clk_get(NULL, oh->main_clk); | |
855 | } | |
63c85238 | 856 | |
6ea74cb9 | 857 | if (IS_ERR(oh->_clk)) { |
3d0cb73e JP |
858 | pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
859 | oh->name, oh->main_clk); | |
63403384 | 860 | return -EINVAL; |
dc75925d | 861 | } |
4d7cb45e RN |
862 | /* |
863 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
864 | * to do something meaningful. Today its just a no-op. | |
865 | * If clk_prepare() is used at some point to do things like | |
866 | * voltage scaling etc, then this would have to be moved to | |
867 | * some point where subsystems like i2c and pmic become | |
868 | * available. | |
869 | */ | |
870 | clk_prepare(oh->_clk); | |
63c85238 | 871 | |
f5dd3bb5 | 872 | if (!_get_clkdm(oh)) |
3bb05dbf | 873 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 874 | oh->name, oh->main_clk); |
81d7c6ff | 875 | |
63c85238 PW |
876 | return ret; |
877 | } | |
878 | ||
879 | /** | |
887adeac | 880 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
881 | * @oh: struct omap_hwmod * |
882 | * | |
883 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
884 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
885 | */ | |
886 | static int _init_interface_clks(struct omap_hwmod *oh) | |
887 | { | |
5d95dde7 | 888 | struct omap_hwmod_ocp_if *os; |
63c85238 | 889 | struct clk *c; |
63c85238 PW |
890 | int ret = 0; |
891 | ||
b8e1bddc | 892 | list_for_each_entry(os, &oh->slave_ports, node) { |
50ebdac2 | 893 | if (!os->clk) |
63c85238 PW |
894 | continue; |
895 | ||
6ea74cb9 RN |
896 | c = clk_get(NULL, os->clk); |
897 | if (IS_ERR(c)) { | |
3d0cb73e JP |
898 | pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
899 | oh->name, os->clk); | |
63c85238 | 900 | ret = -EINVAL; |
0e7dc862 | 901 | continue; |
dc75925d | 902 | } |
63c85238 | 903 | os->_clk = c; |
4d7cb45e RN |
904 | /* |
905 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
906 | * to do something meaningful. Today its just a no-op. | |
907 | * If clk_prepare() is used at some point to do things like | |
908 | * voltage scaling etc, then this would have to be moved to | |
909 | * some point where subsystems like i2c and pmic become | |
910 | * available. | |
911 | */ | |
912 | clk_prepare(os->_clk); | |
63c85238 PW |
913 | } |
914 | ||
915 | return ret; | |
916 | } | |
917 | ||
918 | /** | |
919 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
920 | * @oh: struct omap_hwmod * | |
921 | * | |
922 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
923 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
924 | */ | |
925 | static int _init_opt_clks(struct omap_hwmod *oh) | |
926 | { | |
927 | struct omap_hwmod_opt_clk *oc; | |
928 | struct clk *c; | |
929 | int i; | |
930 | int ret = 0; | |
931 | ||
932 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
933 | c = clk_get(NULL, oc->clk); |
934 | if (IS_ERR(c)) { | |
3d0cb73e JP |
935 | pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
936 | oh->name, oc->clk); | |
63c85238 | 937 | ret = -EINVAL; |
0e7dc862 | 938 | continue; |
dc75925d | 939 | } |
63c85238 | 940 | oc->_clk = c; |
4d7cb45e RN |
941 | /* |
942 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
943 | * to do something meaningful. Today its just a no-op. | |
944 | * If clk_prepare() is used at some point to do things like | |
945 | * voltage scaling etc, then this would have to be moved to | |
946 | * some point where subsystems like i2c and pmic become | |
947 | * available. | |
948 | */ | |
949 | clk_prepare(oc->_clk); | |
63c85238 PW |
950 | } |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
c12ba8ce PU |
955 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
956 | { | |
957 | struct omap_hwmod_opt_clk *oc; | |
958 | int i; | |
959 | ||
960 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
961 | ||
962 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
963 | if (oc->_clk) { | |
964 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
965 | __clk_get_name(oc->_clk)); | |
966 | clk_enable(oc->_clk); | |
967 | } | |
968 | } | |
969 | ||
970 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
971 | { | |
972 | struct omap_hwmod_opt_clk *oc; | |
973 | int i; | |
974 | ||
975 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
976 | ||
977 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
978 | if (oc->_clk) { | |
979 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
980 | __clk_get_name(oc->_clk)); | |
981 | clk_disable(oc->_clk); | |
982 | } | |
983 | } | |
984 | ||
63c85238 PW |
985 | /** |
986 | * _enable_clocks - enable hwmod main clock and interface clocks | |
987 | * @oh: struct omap_hwmod * | |
988 | * | |
989 | * Enables all clocks necessary for register reads and writes to succeed | |
990 | * on the hwmod @oh. Returns 0. | |
991 | */ | |
992 | static int _enable_clocks(struct omap_hwmod *oh) | |
993 | { | |
5d95dde7 | 994 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
995 | |
996 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
997 | ||
392ea5dd TK |
998 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
999 | _enable_optional_clocks(oh); | |
1000 | ||
4d3ae5a9 | 1001 | if (oh->_clk) |
63c85238 PW |
1002 | clk_enable(oh->_clk); |
1003 | ||
b8e1bddc | 1004 | list_for_each_entry(os, &oh->slave_ports, node) { |
12af39ca AK |
1005 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) { |
1006 | omap2_clk_deny_idle(os->_clk); | |
5d95dde7 | 1007 | clk_enable(os->_clk); |
12af39ca | 1008 | } |
63c85238 PW |
1009 | } |
1010 | ||
1011 | /* The opt clocks are controlled by the device driver. */ | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
8823ddf2 TL |
1016 | /** |
1017 | * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework | |
1018 | * @oh: struct omap_hwmod * | |
1019 | */ | |
1020 | static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh) | |
1021 | { | |
1022 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) | |
1023 | return true; | |
1024 | ||
1025 | return false; | |
1026 | } | |
1027 | ||
1028 | /** | |
1029 | * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock | |
1030 | * @oh: struct omap_hwmod * | |
1031 | */ | |
1032 | static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh) | |
1033 | { | |
1034 | if (oh->prcm.omap4.clkctrl_offs) | |
1035 | return true; | |
1036 | ||
1037 | if (!oh->prcm.omap4.clkctrl_offs && | |
1038 | oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) | |
1039 | return true; | |
1040 | ||
1041 | return false; | |
1042 | } | |
1043 | ||
63c85238 PW |
1044 | /** |
1045 | * _disable_clocks - disable hwmod main clock and interface clocks | |
1046 | * @oh: struct omap_hwmod * | |
1047 | * | |
1048 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
1049 | */ | |
1050 | static int _disable_clocks(struct omap_hwmod *oh) | |
1051 | { | |
5d95dde7 | 1052 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
1053 | |
1054 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
1055 | ||
4d3ae5a9 | 1056 | if (oh->_clk) |
63c85238 PW |
1057 | clk_disable(oh->_clk); |
1058 | ||
b8e1bddc | 1059 | list_for_each_entry(os, &oh->slave_ports, node) { |
12af39ca | 1060 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) { |
5d95dde7 | 1061 | clk_disable(os->_clk); |
12af39ca AK |
1062 | omap2_clk_allow_idle(os->_clk); |
1063 | } | |
63c85238 PW |
1064 | } |
1065 | ||
c12ba8ce PU |
1066 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
1067 | _disable_optional_clocks(oh); | |
1068 | ||
63c85238 PW |
1069 | /* The opt clocks are controlled by the device driver. */ |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
45c38252 | 1074 | /** |
3d9f0327 | 1075 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
1076 | * @oh: struct omap_hwmod * |
1077 | * | |
1078 | * Enables the PRCM module mode related to the hwmod @oh. | |
1079 | * No return value. | |
1080 | */ | |
3d9f0327 | 1081 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 1082 | { |
8823ddf2 TL |
1083 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1084 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
45c38252 BC |
1085 | return; |
1086 | ||
3d9f0327 KH |
1087 | pr_debug("omap_hwmod: %s: %s: %d\n", |
1088 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 | 1089 | |
128603f0 TK |
1090 | omap_cm_module_enable(oh->prcm.omap4.modulemode, |
1091 | oh->clkdm->prcm_partition, | |
1092 | oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); | |
1688bf19 VH |
1093 | } |
1094 | ||
45c38252 | 1095 | /** |
bfc141e3 BC |
1096 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
1097 | * @oh: struct omap_hwmod * | |
1098 | * | |
1099 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1100 | * does not have an IDLEST bit or if the module successfully enters | |
1101 | * slave idle; otherwise, pass along the return value of the | |
1102 | * appropriate *_cm*_wait_module_idle() function. | |
1103 | */ | |
1104 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
1105 | { | |
2b026d13 | 1106 | if (!oh) |
bfc141e3 BC |
1107 | return -EINVAL; |
1108 | ||
2b026d13 | 1109 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1110 | return 0; |
1111 | ||
1112 | if (oh->flags & HWMOD_NO_IDLEST) | |
1113 | return 0; | |
1114 | ||
8823ddf2 TL |
1115 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
1116 | return 0; | |
1117 | ||
1118 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
1119 | return 0; |
1120 | ||
a8ae5afa TK |
1121 | return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, |
1122 | oh->clkdm->cm_inst, | |
1123 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
1124 | } |
1125 | ||
63c85238 | 1126 | /** |
24dbc213 | 1127 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1128 | * @oh: struct omap_hwmod * |
1129 | * | |
24dbc213 PW |
1130 | * Determines the array index of the OCP slave port that the MPU uses |
1131 | * to address the device, and saves it into the struct omap_hwmod. | |
1132 | * Intended to be called during hwmod registration only. No return | |
1133 | * value. | |
63c85238 | 1134 | */ |
24dbc213 | 1135 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1136 | { |
24dbc213 | 1137 | struct omap_hwmod_ocp_if *os = NULL; |
63c85238 | 1138 | |
5d95dde7 | 1139 | if (!oh) |
24dbc213 PW |
1140 | return; |
1141 | ||
1142 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1143 | |
b8e1bddc | 1144 | list_for_each_entry(os, &oh->slave_ports, node) { |
63c85238 | 1145 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1146 | oh->_mpu_port = os; |
24dbc213 | 1147 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1148 | break; |
1149 | } | |
1150 | } | |
1151 | ||
24dbc213 | 1152 | return; |
63c85238 PW |
1153 | } |
1154 | ||
2d6141ba PW |
1155 | /** |
1156 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1157 | * @oh: struct omap_hwmod * | |
1158 | * | |
1159 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1160 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1161 | * communicate with the IP block. This interface need not be directly | |
1162 | * connected to the MPU (and almost certainly is not), but is directly | |
1163 | * connected to the IP block represented by @oh. Returns a pointer | |
1164 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1165 | * error or if there does not appear to be a path from the MPU to this | |
1166 | * IP block. | |
1167 | */ | |
1168 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1169 | { | |
1170 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1171 | return NULL; | |
1172 | ||
11cd4b94 | 1173 | return oh->_mpu_port; |
2d6141ba PW |
1174 | }; |
1175 | ||
63c85238 | 1176 | /** |
74ff3a68 | 1177 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1178 | * @oh: struct omap_hwmod * |
1179 | * | |
006c7f18 PW |
1180 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1181 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1182 | * Usually this means placing the module into smart-idle mode and | |
1183 | * smart-standby, but if there is a bug in the automatic idle handling | |
1184 | * for the IP block, it may need to be placed into the force-idle or | |
1185 | * no-idle variants of these modes. No return value. | |
63c85238 | 1186 | */ |
74ff3a68 | 1187 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1188 | { |
43b40992 | 1189 | u8 idlemode, sf; |
63c85238 | 1190 | u32 v; |
006c7f18 | 1191 | bool clkdm_act; |
f5dd3bb5 | 1192 | struct clockdomain *clkdm; |
63c85238 | 1193 | |
43b40992 | 1194 | if (!oh->class->sysc) |
63c85238 PW |
1195 | return; |
1196 | ||
613ad0e9 TK |
1197 | /* |
1198 | * Wait until reset has completed, this is needed as the IP | |
1199 | * block is reset automatically by hardware in some cases | |
1200 | * (off-mode for example), and the drivers require the | |
1201 | * IP to be ready when they access it | |
1202 | */ | |
1203 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1204 | _enable_optional_clocks(oh); | |
1205 | _wait_softreset_complete(oh); | |
1206 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1207 | _disable_optional_clocks(oh); | |
1208 | ||
63c85238 | 1209 | v = oh->_sysc_cache; |
43b40992 | 1210 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1211 | |
f5dd3bb5 | 1212 | clkdm = _get_clkdm(oh); |
43b40992 | 1213 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1214 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1215 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1216 | idlemode = HWMOD_IDLEMODE_NO; |
1217 | } else { | |
1218 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1219 | _enable_wakeup(oh, &v); | |
1220 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1221 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1222 | else | |
1223 | idlemode = HWMOD_IDLEMODE_SMART; | |
1224 | } | |
1225 | ||
1226 | /* | |
1227 | * This is special handling for some IPs like | |
1228 | * 32k sync timer. Force them to idle! | |
1229 | */ | |
f5dd3bb5 | 1230 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1231 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1232 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1233 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1234 | |
63c85238 PW |
1235 | _set_slave_idlemode(oh, idlemode, &v); |
1236 | } | |
1237 | ||
43b40992 | 1238 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1239 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1240 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1241 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1242 | idlemode = HWMOD_IDLEMODE_NO; |
1243 | } else { | |
1244 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1245 | _enable_wakeup(oh, &v); | |
1246 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1247 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1248 | else | |
1249 | idlemode = HWMOD_IDLEMODE_SMART; | |
1250 | } | |
63c85238 PW |
1251 | _set_master_standbymode(oh, idlemode, &v); |
1252 | } | |
1253 | ||
a16b1f7f PW |
1254 | /* |
1255 | * XXX The clock framework should handle this, by | |
1256 | * calling into this code. But this must wait until the | |
1257 | * clock structures are tagged with omap_hwmod entries | |
1258 | */ | |
43b40992 PW |
1259 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1260 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
ca5339b1 | 1261 | _set_clockactivity(oh, CLOCKACT_TEST_ICLK, &v); |
63c85238 | 1262 | |
3ca4a238 | 1263 | _write_sysconfig(v, oh); |
78f26e87 HH |
1264 | |
1265 | /* | |
1266 | * Set the autoidle bit only after setting the smartidle bit | |
1267 | * Setting this will not have any impact on the other modules. | |
1268 | */ | |
1269 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1270 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1271 | 0 : 1; | |
1272 | _set_module_autoidle(oh, idlemode, &v); | |
1273 | _write_sysconfig(v, oh); | |
1274 | } | |
63c85238 PW |
1275 | } |
1276 | ||
1277 | /** | |
74ff3a68 | 1278 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1279 | * @oh: struct omap_hwmod * |
1280 | * | |
1281 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1282 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1283 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1284 | * configure it for smart-standby. No return value. | |
1285 | */ | |
74ff3a68 | 1286 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1287 | { |
43b40992 | 1288 | u8 idlemode, sf; |
63c85238 PW |
1289 | u32 v; |
1290 | ||
43b40992 | 1291 | if (!oh->class->sysc) |
63c85238 PW |
1292 | return; |
1293 | ||
1294 | v = oh->_sysc_cache; | |
43b40992 | 1295 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1296 | |
43b40992 | 1297 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1298 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1299 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1300 | } else { |
1301 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1302 | _enable_wakeup(oh, &v); | |
1303 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1304 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1305 | else | |
1306 | idlemode = HWMOD_IDLEMODE_SMART; | |
1307 | } | |
63c85238 PW |
1308 | _set_slave_idlemode(oh, idlemode, &v); |
1309 | } | |
1310 | ||
43b40992 | 1311 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1312 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1313 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1314 | idlemode = HWMOD_IDLEMODE_FORCE; |
1315 | } else { | |
1316 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1317 | _enable_wakeup(oh, &v); | |
1318 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1319 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1320 | else | |
1321 | idlemode = HWMOD_IDLEMODE_SMART; | |
1322 | } | |
63c85238 PW |
1323 | _set_master_standbymode(oh, idlemode, &v); |
1324 | } | |
1325 | ||
3ca4a238 LV |
1326 | /* If the cached value is the same as the new value, skip the write */ |
1327 | if (oh->_sysc_cache != v) | |
1328 | _write_sysconfig(v, oh); | |
63c85238 PW |
1329 | } |
1330 | ||
1331 | /** | |
74ff3a68 | 1332 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1333 | * @oh: struct omap_hwmod * |
1334 | * | |
1335 | * Force the module into slave idle and master suspend. No return | |
1336 | * value. | |
1337 | */ | |
74ff3a68 | 1338 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1339 | { |
1340 | u32 v; | |
43b40992 | 1341 | u8 sf; |
63c85238 | 1342 | |
43b40992 | 1343 | if (!oh->class->sysc) |
63c85238 PW |
1344 | return; |
1345 | ||
1346 | v = oh->_sysc_cache; | |
43b40992 | 1347 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1348 | |
43b40992 | 1349 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1350 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1351 | ||
43b40992 | 1352 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1353 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1354 | ||
43b40992 | 1355 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1356 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1357 | |
1358 | _write_sysconfig(v, oh); | |
1359 | } | |
1360 | ||
1361 | /** | |
1362 | * _lookup - find an omap_hwmod by name | |
1363 | * @name: find an omap_hwmod by name | |
1364 | * | |
1365 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1366 | */ |
1367 | static struct omap_hwmod *_lookup(const char *name) | |
1368 | { | |
1369 | struct omap_hwmod *oh, *temp_oh; | |
1370 | ||
1371 | oh = NULL; | |
1372 | ||
1373 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1374 | if (!strcmp(name, temp_oh->name)) { | |
1375 | oh = temp_oh; | |
1376 | break; | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | return oh; | |
1381 | } | |
868c157d | 1382 | |
6ae76997 BC |
1383 | /** |
1384 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1385 | * @oh: struct omap_hwmod * | |
1386 | * | |
1387 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1388 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1389 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1390 | */ |
1391 | static int _init_clkdm(struct omap_hwmod *oh) | |
1392 | { | |
3bb05dbf PW |
1393 | if (!oh->clkdm_name) { |
1394 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1395 | return 0; |
3bb05dbf | 1396 | } |
6ae76997 | 1397 | |
6ae76997 BC |
1398 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1399 | if (!oh->clkdm) { | |
3d0cb73e | 1400 | pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", |
6ae76997 | 1401 | oh->name, oh->clkdm_name); |
0385c582 | 1402 | return 0; |
6ae76997 BC |
1403 | } |
1404 | ||
1405 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1406 | oh->name, oh->clkdm_name); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
63c85238 PW |
1410 | |
1411 | /** | |
6ae76997 BC |
1412 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1413 | * well the clockdomain. | |
63c85238 | 1414 | * @oh: struct omap_hwmod * |
70f05be3 | 1415 | * @np: device_node mapped to this hwmod |
63c85238 | 1416 | * |
a2debdbd | 1417 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1418 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1419 | * success, or a negative error code on failure. | |
63c85238 | 1420 | */ |
70f05be3 | 1421 | static int _init_clocks(struct omap_hwmod *oh, struct device_node *np) |
63c85238 PW |
1422 | { |
1423 | int ret = 0; | |
1424 | ||
48d54f3f PW |
1425 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1426 | return 0; | |
63c85238 PW |
1427 | |
1428 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1429 | ||
b797be1d VH |
1430 | if (soc_ops.init_clkdm) |
1431 | ret |= soc_ops.init_clkdm(oh); | |
1432 | ||
63c85238 PW |
1433 | ret |= _init_main_clk(oh); |
1434 | ret |= _init_interface_clks(oh); | |
1435 | ret |= _init_opt_clks(oh); | |
1436 | ||
f5c1f84b BC |
1437 | if (!ret) |
1438 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a | 1439 | else |
3d0cb73e | 1440 | pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); |
63c85238 | 1441 | |
09c35f2f | 1442 | return ret; |
63c85238 PW |
1443 | } |
1444 | ||
5365efbe | 1445 | /** |
cc1226e7 | 1446 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1447 | * @oh: struct omap_hwmod * |
1448 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1449 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1450 | * |
1451 | * Return the bit position of the reset line that match the | |
1452 | * input name. Return -ENOENT if not found. | |
1453 | */ | |
a032d33b PW |
1454 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1455 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1456 | { |
1457 | int i; | |
1458 | ||
1459 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1460 | const char *rst_line = oh->rst_lines[i].name; | |
1461 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1462 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1463 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1464 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1465 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1466 | ohri->st_shift); | |
5365efbe | 1467 | |
cc1226e7 | 1468 | return 0; |
5365efbe BC |
1469 | } |
1470 | } | |
1471 | ||
1472 | return -ENOENT; | |
1473 | } | |
1474 | ||
1475 | /** | |
1476 | * _assert_hardreset - assert the HW reset line of submodules | |
1477 | * contained in the hwmod module. | |
1478 | * @oh: struct omap_hwmod * | |
1479 | * @name: name of the reset line to lookup and assert | |
1480 | * | |
b8249cf2 KH |
1481 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1482 | * reset line to be assert / deassert in order to enable fully the IP. | |
1483 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1484 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1485 | * along the return value from _lookup_hardreset() or the SoC's | |
1486 | * assert_hardreset code. | |
5365efbe BC |
1487 | */ |
1488 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1489 | { | |
cc1226e7 | 1490 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1491 | int ret = -EINVAL; |
5365efbe BC |
1492 | |
1493 | if (!oh) | |
1494 | return -EINVAL; | |
1495 | ||
b8249cf2 KH |
1496 | if (!soc_ops.assert_hardreset) |
1497 | return -ENOSYS; | |
1498 | ||
cc1226e7 | 1499 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1500 | if (ret < 0) |
cc1226e7 | 1501 | return ret; |
5365efbe | 1502 | |
b8249cf2 KH |
1503 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1504 | ||
1505 | return ret; | |
5365efbe BC |
1506 | } |
1507 | ||
1508 | /** | |
1509 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1510 | * in the hwmod module. | |
1511 | * @oh: struct omap_hwmod * | |
1512 | * @name: name of the reset line to look up and deassert | |
1513 | * | |
b8249cf2 KH |
1514 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1515 | * reset line to be assert / deassert in order to enable fully the IP. | |
1516 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1517 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1518 | * along the return value from _lookup_hardreset() or the SoC's | |
1519 | * deassert_hardreset code. | |
5365efbe BC |
1520 | */ |
1521 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1522 | { | |
cc1226e7 | 1523 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1524 | int ret = -EINVAL; |
5365efbe BC |
1525 | |
1526 | if (!oh) | |
1527 | return -EINVAL; | |
1528 | ||
b8249cf2 KH |
1529 | if (!soc_ops.deassert_hardreset) |
1530 | return -ENOSYS; | |
1531 | ||
cc1226e7 | 1532 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1533 | if (ret < 0) |
cc1226e7 | 1534 | return ret; |
5365efbe | 1535 | |
e8e96dff ORL |
1536 | if (oh->clkdm) { |
1537 | /* | |
1538 | * A clockdomain must be in SW_SUP otherwise reset | |
1539 | * might not be completed. The clockdomain can be set | |
1540 | * in HW_AUTO only when the module become ready. | |
1541 | */ | |
1d9a5425 | 1542 | clkdm_deny_idle(oh->clkdm); |
e8e96dff ORL |
1543 | ret = clkdm_hwmod_enable(oh->clkdm, oh); |
1544 | if (ret) { | |
1545 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1546 | oh->name, oh->clkdm->name, ret); | |
1547 | return ret; | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | _enable_clocks(oh); | |
1552 | if (soc_ops.enable_module) | |
1553 | soc_ops.enable_module(oh); | |
1554 | ||
b8249cf2 | 1555 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1556 | |
1557 | if (soc_ops.disable_module) | |
1558 | soc_ops.disable_module(oh); | |
1559 | _disable_clocks(oh); | |
1560 | ||
cc1226e7 | 1561 | if (ret == -EBUSY) |
3d0cb73e | 1562 | pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); |
5365efbe | 1563 | |
80d2518d | 1564 | if (oh->clkdm) { |
e8e96dff ORL |
1565 | /* |
1566 | * Set the clockdomain to HW_AUTO, assuming that the | |
1567 | * previous state was HW_AUTO. | |
1568 | */ | |
1d9a5425 | 1569 | clkdm_allow_idle(oh->clkdm); |
80d2518d TK |
1570 | |
1571 | clkdm_hwmod_disable(oh->clkdm, oh); | |
e8e96dff ORL |
1572 | } |
1573 | ||
cc1226e7 | 1574 | return ret; |
5365efbe BC |
1575 | } |
1576 | ||
1577 | /** | |
1578 | * _read_hardreset - read the HW reset line state of submodules | |
1579 | * contained in the hwmod module | |
1580 | * @oh: struct omap_hwmod * | |
1581 | * @name: name of the reset line to look up and read | |
1582 | * | |
b8249cf2 KH |
1583 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1584 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1585 | * status on the currently-booted SoC, or passes along the return | |
1586 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1587 | * code. | |
5365efbe BC |
1588 | */ |
1589 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1590 | { | |
cc1226e7 | 1591 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1592 | int ret = -EINVAL; |
5365efbe BC |
1593 | |
1594 | if (!oh) | |
1595 | return -EINVAL; | |
1596 | ||
b8249cf2 KH |
1597 | if (!soc_ops.is_hardreset_asserted) |
1598 | return -ENOSYS; | |
1599 | ||
cc1226e7 | 1600 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1601 | if (ret < 0) |
cc1226e7 | 1602 | return ret; |
5365efbe | 1603 | |
b8249cf2 | 1604 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1605 | } |
1606 | ||
747834ab | 1607 | /** |
eb05f691 | 1608 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1609 | * @oh: struct omap_hwmod * |
1610 | * | |
eb05f691 ORL |
1611 | * If all hardreset lines associated with @oh are asserted, then return true. |
1612 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1613 | * associated with @oh are asserted, then return false. | |
747834ab | 1614 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1615 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1616 | */ |
eb05f691 | 1617 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1618 | { |
eb05f691 | 1619 | int i, rst_cnt = 0; |
747834ab PW |
1620 | |
1621 | if (oh->rst_lines_cnt == 0) | |
1622 | return false; | |
1623 | ||
1624 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1625 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1626 | rst_cnt++; |
1627 | ||
1628 | if (oh->rst_lines_cnt == rst_cnt) | |
1629 | return true; | |
747834ab PW |
1630 | |
1631 | return false; | |
1632 | } | |
1633 | ||
e9332b6e PW |
1634 | /** |
1635 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1636 | * hard-reset | |
1637 | * @oh: struct omap_hwmod * | |
1638 | * | |
1639 | * If any hardreset lines associated with @oh are asserted, then | |
1640 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1641 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1642 | * This function is used to avoid executing some parts of the IP block | |
1643 | * enable/disable sequence if any hardreset line is set. | |
1644 | */ | |
1645 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1646 | { | |
1647 | int rst_cnt = 0; | |
1648 | int i; | |
1649 | ||
1650 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1651 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1652 | rst_cnt++; | |
1653 | ||
1654 | return (rst_cnt) ? true : false; | |
1655 | } | |
1656 | ||
747834ab PW |
1657 | /** |
1658 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1659 | * @oh: struct omap_hwmod * | |
1660 | * | |
1661 | * Disable the PRCM module mode related to the hwmod @oh. | |
1662 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1663 | */ | |
1664 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1665 | { | |
1666 | int v; | |
1667 | ||
8823ddf2 TL |
1668 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1669 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
747834ab PW |
1670 | return -EINVAL; |
1671 | ||
eb05f691 ORL |
1672 | /* |
1673 | * Since integration code might still be doing something, only | |
1674 | * disable if all lines are under hardreset. | |
1675 | */ | |
e9332b6e | 1676 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1677 | return 0; |
1678 | ||
747834ab PW |
1679 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1680 | ||
128603f0 TK |
1681 | omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, |
1682 | oh->prcm.omap4.clkctrl_offs); | |
747834ab | 1683 | |
747834ab PW |
1684 | v = _omap4_wait_target_disable(oh); |
1685 | if (v) | |
1686 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1687 | oh->name); | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
63c85238 | 1692 | /** |
bd36179e | 1693 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1694 | * @oh: struct omap_hwmod * |
1695 | * | |
1696 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1697 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1698 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1699 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1700 | * |
1701 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1702 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1703 | * use the SYSCONFIG softreset bit to provide the status. |
1704 | * | |
bd36179e PW |
1705 | * Note that some IP like McBSP do have reset control but don't have |
1706 | * reset status. | |
63c85238 | 1707 | */ |
bd36179e | 1708 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1709 | { |
613ad0e9 | 1710 | u32 v; |
6f8b7ff5 | 1711 | int c = 0; |
96835af9 | 1712 | int ret = 0; |
63c85238 | 1713 | |
43b40992 | 1714 | if (!oh->class->sysc || |
2cb06814 | 1715 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1716 | return -ENOENT; |
63c85238 PW |
1717 | |
1718 | /* clocks must be on for this operation */ | |
1719 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1720 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1721 | oh->name); | |
63c85238 PW |
1722 | return -EINVAL; |
1723 | } | |
1724 | ||
96835af9 BC |
1725 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1726 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1727 | _enable_optional_clocks(oh); | |
1728 | ||
bd36179e | 1729 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1730 | |
1731 | v = oh->_sysc_cache; | |
96835af9 BC |
1732 | ret = _set_softreset(oh, &v); |
1733 | if (ret) | |
1734 | goto dis_opt_clks; | |
313a76ee | 1735 | |
63c85238 PW |
1736 | _write_sysconfig(v, oh); |
1737 | ||
d99de7f5 FGL |
1738 | if (oh->class->sysc->srst_udelay) |
1739 | udelay(oh->class->sysc->srst_udelay); | |
1740 | ||
613ad0e9 | 1741 | c = _wait_softreset_complete(oh); |
01142519 | 1742 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
3d0cb73e JP |
1743 | pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1744 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1745 | ret = -ETIMEDOUT; |
1746 | goto dis_opt_clks; | |
1747 | } else { | |
5365efbe | 1748 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1749 | } |
1750 | ||
1751 | ret = _clear_softreset(oh, &v); | |
1752 | if (ret) | |
1753 | goto dis_opt_clks; | |
1754 | ||
1755 | _write_sysconfig(v, oh); | |
63c85238 PW |
1756 | |
1757 | /* | |
1758 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1759 | * _wait_target_ready() or _reset() | |
1760 | */ | |
1761 | ||
96835af9 BC |
1762 | dis_opt_clks: |
1763 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1764 | _disable_optional_clocks(oh); | |
1765 | ||
1766 | return ret; | |
63c85238 PW |
1767 | } |
1768 | ||
bd36179e PW |
1769 | /** |
1770 | * _reset - reset an omap_hwmod | |
1771 | * @oh: struct omap_hwmod * | |
1772 | * | |
30e105c0 PW |
1773 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1774 | * function pointer defined, then call it to reset the IP block, and | |
1775 | * pass along its return value to the caller. Otherwise, if the IP | |
1776 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1777 | * associated with it, call a function to reset the IP block via that | |
1778 | * method, and pass along the return value to the caller. Finally, if | |
1779 | * the IP block has some hardreset lines associated with it, assert | |
1780 | * all of those, but do _not_ deassert them. (This is because driver | |
1781 | * authors have expressed an apparent requirement to control the | |
1782 | * deassertion of the hardreset lines themselves.) | |
1783 | * | |
1784 | * The default software reset mechanism for most OMAP IP blocks is | |
1785 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1786 | * hwmods cannot be reset via this method. Some are not targets and | |
1787 | * therefore have no OCP header registers to access. Others (like the | |
1788 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1789 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1790 | * omap_hwmod_class .reset function pointer. |
1791 | * | |
1792 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1793 | * does not prevent idling of the system. This is necessary for cases | |
1794 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1795 | * kernel without disabling dma. | |
1796 | * | |
1797 | * Passes along the return value from either _ocp_softreset() or the | |
1798 | * custom reset function - these must return -EINVAL if the hwmod | |
1799 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1800 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1801 | */ |
1802 | static int _reset(struct omap_hwmod *oh) | |
1803 | { | |
30e105c0 | 1804 | int i, r; |
bd36179e PW |
1805 | |
1806 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1807 | ||
30e105c0 PW |
1808 | if (oh->class->reset) { |
1809 | r = oh->class->reset(oh); | |
1810 | } else { | |
1811 | if (oh->rst_lines_cnt > 0) { | |
1812 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1813 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1814 | return 0; | |
1815 | } else { | |
1816 | r = _ocp_softreset(oh); | |
1817 | if (r == -ENOENT) | |
1818 | r = 0; | |
1819 | } | |
1820 | } | |
1821 | ||
6668546f KVA |
1822 | _set_dmadisable(oh); |
1823 | ||
9c8b0ec7 | 1824 | /* |
30e105c0 PW |
1825 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1826 | * softreset. The _enable() function should be split to avoid | |
1827 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1828 | */ |
2800852a RN |
1829 | if (oh->class->sysc) { |
1830 | _update_sysc_cache(oh); | |
1831 | _enable_sysc(oh); | |
1832 | } | |
1833 | ||
30e105c0 | 1834 | return r; |
bd36179e PW |
1835 | } |
1836 | ||
e6d3a8b0 RN |
1837 | /** |
1838 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
1839 | * hwmod context was lost, and clear hardware context loss reg | |
1840 | * @oh: hwmod to check for context loss | |
1841 | * | |
1842 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
1843 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
1844 | * bits. No return value. | |
1845 | */ | |
1846 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
1847 | { | |
1848 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
1849 | return; | |
1850 | ||
1851 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1852 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1853 | oh->prcm.omap4.context_offs)) | |
1854 | return; | |
1855 | ||
1856 | oh->prcm.omap4.context_lost_counter++; | |
1857 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1858 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1859 | oh->prcm.omap4.context_offs); | |
1860 | } | |
1861 | ||
1862 | /** | |
1863 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
1864 | * @oh: hwmod to get context loss counter for | |
1865 | * | |
1866 | * Returns the in-memory context loss counter for a hwmod. | |
1867 | */ | |
1868 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
1869 | { | |
1870 | return oh->prcm.omap4.context_lost_counter; | |
1871 | } | |
1872 | ||
6d266f63 PW |
1873 | /** |
1874 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
1875 | * @oh: struct omap_hwmod * | |
1876 | * | |
1877 | * Some IP blocks (such as AESS) require some additional programming | |
1878 | * after enable before they can enter idle. If a function pointer to | |
1879 | * do so is present in the hwmod data, then call it and pass along the | |
1880 | * return value; otherwise, return 0. | |
1881 | */ | |
0f497039 | 1882 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
1883 | { |
1884 | if (!oh->class->enable_preprogram) | |
1885 | return 0; | |
1886 | ||
1887 | return oh->class->enable_preprogram(oh); | |
1888 | } | |
1889 | ||
63c85238 | 1890 | /** |
dc6d1cda | 1891 | * _enable - enable an omap_hwmod |
63c85238 PW |
1892 | * @oh: struct omap_hwmod * |
1893 | * | |
1894 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1895 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1896 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1897 | */ |
dc6d1cda | 1898 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1899 | { |
747834ab | 1900 | int r; |
63c85238 | 1901 | |
34617e2a BC |
1902 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1903 | ||
aacf0941 | 1904 | /* |
64813c3f | 1905 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
b4281455 | 1906 | * state at init. |
aacf0941 RN |
1907 | */ |
1908 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
aacf0941 RN |
1909 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; |
1910 | return 0; | |
1911 | } | |
1912 | ||
63c85238 PW |
1913 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1914 | oh->_state != _HWMOD_STATE_IDLE && | |
1915 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1916 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1917 | oh->name); | |
63c85238 PW |
1918 | return -EINVAL; |
1919 | } | |
1920 | ||
31f62866 | 1921 | /* |
eb05f691 | 1922 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
1923 | * asserted, we let integration code associated with that |
1924 | * block handle the enable. We've received very little | |
1925 | * information on what those driver authors need, and until | |
1926 | * detailed information is provided and the driver code is | |
1927 | * posted to the public lists, this is probably the best we | |
1928 | * can do. | |
31f62866 | 1929 | */ |
eb05f691 | 1930 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 1931 | return 0; |
63c85238 | 1932 | |
665d0013 | 1933 | _add_initiator_dep(oh, mpu_oh); |
34617e2a | 1934 | |
665d0013 RN |
1935 | if (oh->clkdm) { |
1936 | /* | |
1937 | * A clockdomain must be in SW_SUP before enabling | |
1938 | * completely the module. The clockdomain can be set | |
1939 | * in HW_AUTO only when the module become ready. | |
1940 | */ | |
1d9a5425 | 1941 | clkdm_deny_idle(oh->clkdm); |
665d0013 RN |
1942 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
1943 | if (r) { | |
1944 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1945 | oh->name, oh->clkdm->name, r); | |
1946 | return r; | |
1947 | } | |
34617e2a | 1948 | } |
665d0013 RN |
1949 | |
1950 | _enable_clocks(oh); | |
9ebfd285 KH |
1951 | if (soc_ops.enable_module) |
1952 | soc_ops.enable_module(oh); | |
fa200222 | 1953 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 1954 | cpu_idle_poll_ctrl(true); |
34617e2a | 1955 | |
e6d3a8b0 RN |
1956 | if (soc_ops.update_context_lost) |
1957 | soc_ops.update_context_lost(oh); | |
1958 | ||
8f6aa8ee KH |
1959 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
1960 | -EINVAL; | |
8ff42da4 | 1961 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) |
1d9a5425 | 1962 | clkdm_allow_idle(oh->clkdm); |
665d0013 | 1963 | |
1d9a5425 | 1964 | if (!r) { |
665d0013 RN |
1965 | oh->_state = _HWMOD_STATE_ENABLED; |
1966 | ||
1967 | /* Access the sysconfig only if the target is ready */ | |
1968 | if (oh->class->sysc) { | |
1969 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1970 | _update_sysc_cache(oh); | |
1971 | _enable_sysc(oh); | |
1972 | } | |
6d266f63 | 1973 | r = _enable_preprogram(oh); |
665d0013 | 1974 | } else { |
2577a4a6 PW |
1975 | if (soc_ops.disable_module) |
1976 | soc_ops.disable_module(oh); | |
665d0013 | 1977 | _disable_clocks(oh); |
812ce9d2 LV |
1978 | pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n", |
1979 | oh->name, r); | |
34617e2a | 1980 | |
665d0013 RN |
1981 | if (oh->clkdm) |
1982 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1983 | } |
1984 | ||
63c85238 PW |
1985 | return r; |
1986 | } | |
1987 | ||
1988 | /** | |
dc6d1cda | 1989 | * _idle - idle an omap_hwmod |
63c85238 PW |
1990 | * @oh: struct omap_hwmod * |
1991 | * | |
1992 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1993 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1994 | * state or returns 0. | |
63c85238 | 1995 | */ |
dc6d1cda | 1996 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1997 | { |
2e18f5a1 LV |
1998 | if (oh->flags & HWMOD_NO_IDLE) { |
1999 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2000 | return 0; | |
2001 | } | |
2002 | ||
34617e2a BC |
2003 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2004 | ||
c20c8f75 SA |
2005 | if (_are_all_hardreset_lines_asserted(oh)) |
2006 | return 0; | |
2007 | ||
63c85238 | 2008 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2009 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2010 | oh->name); | |
63c85238 PW |
2011 | return -EINVAL; |
2012 | } | |
2013 | ||
43b40992 | 2014 | if (oh->class->sysc) |
74ff3a68 | 2015 | _idle_sysc(oh); |
63c85238 | 2016 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2017 | |
8ff42da4 RQ |
2018 | /* |
2019 | * If HWMOD_CLKDM_NOAUTO is set then we don't | |
2020 | * deny idle the clkdm again since idle was already denied | |
2021 | * in _enable() | |
2022 | */ | |
2023 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) | |
1d9a5425 TK |
2024 | clkdm_deny_idle(oh->clkdm); |
2025 | ||
fa200222 | 2026 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2027 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2028 | if (soc_ops.disable_module) |
2029 | soc_ops.disable_module(oh); | |
bfc141e3 | 2030 | |
45c38252 BC |
2031 | /* |
2032 | * The module must be in idle mode before disabling any parents | |
2033 | * clocks. Otherwise, the parent clock might be disabled before | |
2034 | * the module transition is done, and thus will prevent the | |
2035 | * transition to complete properly. | |
2036 | */ | |
2037 | _disable_clocks(oh); | |
1d9a5425 TK |
2038 | if (oh->clkdm) { |
2039 | clkdm_allow_idle(oh->clkdm); | |
665d0013 | 2040 | clkdm_hwmod_disable(oh->clkdm, oh); |
1d9a5425 | 2041 | } |
63c85238 PW |
2042 | |
2043 | oh->_state = _HWMOD_STATE_IDLE; | |
2044 | ||
2045 | return 0; | |
2046 | } | |
2047 | ||
2048 | /** | |
2049 | * _shutdown - shutdown an omap_hwmod | |
2050 | * @oh: struct omap_hwmod * | |
2051 | * | |
2052 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2053 | * used for the hwmod is removed or unloaded or if the driver is not | |
2054 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2055 | * state or returns 0. | |
2056 | */ | |
2057 | static int _shutdown(struct omap_hwmod *oh) | |
2058 | { | |
9c8b0ec7 | 2059 | int ret, i; |
e4dc8f50 PW |
2060 | u8 prev_state; |
2061 | ||
c20c8f75 SA |
2062 | if (_are_all_hardreset_lines_asserted(oh)) |
2063 | return 0; | |
2064 | ||
63c85238 PW |
2065 | if (oh->_state != _HWMOD_STATE_IDLE && |
2066 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2067 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2068 | oh->name); | |
63c85238 PW |
2069 | return -EINVAL; |
2070 | } | |
2071 | ||
2072 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
2073 | ||
e4dc8f50 PW |
2074 | if (oh->class->pre_shutdown) { |
2075 | prev_state = oh->_state; | |
2076 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2077 | _enable(oh); |
e4dc8f50 PW |
2078 | ret = oh->class->pre_shutdown(oh); |
2079 | if (ret) { | |
2080 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2081 | _idle(oh); |
e4dc8f50 PW |
2082 | return ret; |
2083 | } | |
2084 | } | |
2085 | ||
6481c73c MV |
2086 | if (oh->class->sysc) { |
2087 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2088 | _enable(oh); | |
74ff3a68 | 2089 | _shutdown_sysc(oh); |
6481c73c | 2090 | } |
5365efbe | 2091 | |
3827f949 BC |
2092 | /* clocks and deps are already disabled in idle */ |
2093 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2094 | _del_initiator_dep(oh, mpu_oh); | |
2095 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2096 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2097 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2098 | if (soc_ops.disable_module) |
2099 | soc_ops.disable_module(oh); | |
45c38252 | 2100 | _disable_clocks(oh); |
665d0013 RN |
2101 | if (oh->clkdm) |
2102 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2103 | } |
63c85238 PW |
2104 | /* XXX Should this code also force-disable the optional clocks? */ |
2105 | ||
9c8b0ec7 PW |
2106 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2107 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2108 | |
63c85238 PW |
2109 | oh->_state = _HWMOD_STATE_DISABLED; |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
5e863c56 TL |
2114 | static int of_dev_find_hwmod(struct device_node *np, |
2115 | struct omap_hwmod *oh) | |
2116 | { | |
2117 | int count, i, res; | |
2118 | const char *p; | |
2119 | ||
2120 | count = of_property_count_strings(np, "ti,hwmods"); | |
2121 | if (count < 1) | |
2122 | return -ENODEV; | |
2123 | ||
2124 | for (i = 0; i < count; i++) { | |
2125 | res = of_property_read_string_index(np, "ti,hwmods", | |
2126 | i, &p); | |
2127 | if (res) | |
2128 | continue; | |
2129 | if (!strcmp(p, oh->name)) { | |
6e771379 RH |
2130 | pr_debug("omap_hwmod: dt %pOFn[%i] uses hwmod %s\n", |
2131 | np, i, oh->name); | |
5e863c56 TL |
2132 | return i; |
2133 | } | |
2134 | } | |
2135 | ||
2136 | return -ENODEV; | |
2137 | } | |
2138 | ||
079abade SS |
2139 | /** |
2140 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2141 | * @np: struct device_node * | |
2142 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2143 | * @index: index of the entry found |
2144 | * @found: struct device_node * found or NULL | |
079abade SS |
2145 | * |
2146 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2147 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2148 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2149 | */ |
5e863c56 TL |
2150 | static int of_dev_hwmod_lookup(struct device_node *np, |
2151 | struct omap_hwmod *oh, | |
2152 | int *index, | |
2153 | struct device_node **found) | |
079abade | 2154 | { |
5e863c56 TL |
2155 | struct device_node *np0 = NULL; |
2156 | int res; | |
2157 | ||
2158 | res = of_dev_find_hwmod(np, oh); | |
2159 | if (res >= 0) { | |
2160 | *found = np; | |
2161 | *index = res; | |
2162 | return 0; | |
2163 | } | |
079abade SS |
2164 | |
2165 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2166 | struct device_node *fc; |
2167 | int i; | |
2168 | ||
2169 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2170 | if (res == 0) { | |
2171 | *found = fc; | |
2172 | *index = i; | |
2173 | return 0; | |
079abade SS |
2174 | } |
2175 | } | |
5e863c56 TL |
2176 | |
2177 | *found = NULL; | |
2178 | *index = 0; | |
2179 | ||
2180 | return -ENODEV; | |
079abade SS |
2181 | } |
2182 | ||
1dbcb97c TL |
2183 | /** |
2184 | * omap_hwmod_fix_mpu_rt_idx - fix up mpu_rt_idx register offsets | |
2185 | * | |
2186 | * @oh: struct omap_hwmod * | |
2187 | * @np: struct device_node * | |
2188 | * | |
2189 | * Fix up module register offsets for modules with mpu_rt_idx. | |
2190 | * Only needed for cpsw with interconnect target module defined | |
2191 | * in device tree while still using legacy hwmod platform data | |
2192 | * for rev, sysc and syss registers. | |
2193 | * | |
2194 | * Can be removed when all cpsw hwmod platform data has been | |
2195 | * dropped. | |
2196 | */ | |
2197 | static void omap_hwmod_fix_mpu_rt_idx(struct omap_hwmod *oh, | |
2198 | struct device_node *np, | |
2199 | struct resource *res) | |
2200 | { | |
2201 | struct device_node *child = NULL; | |
2202 | int error; | |
2203 | ||
2204 | child = of_get_next_child(np, child); | |
2205 | if (!child) | |
2206 | return; | |
2207 | ||
2208 | error = of_address_to_resource(child, oh->mpu_rt_idx, res); | |
2209 | if (error) | |
2210 | pr_err("%s: error mapping mpu_rt_idx: %i\n", | |
2211 | __func__, error); | |
2212 | } | |
2213 | ||
6c72b355 TL |
2214 | /** |
2215 | * omap_hwmod_parse_module_range - map module IO range from device tree | |
2216 | * @oh: struct omap_hwmod * | |
2217 | * @np: struct device_node * | |
2218 | * | |
2219 | * Parse the device tree range an interconnect target module provides | |
2220 | * for it's child device IP blocks. This way we can support the old | |
2221 | * "ti,hwmods" property with just dts data without a need for platform | |
2222 | * data for IO resources. And we don't need all the child IP device | |
2223 | * nodes available in the dts. | |
2224 | */ | |
2225 | int omap_hwmod_parse_module_range(struct omap_hwmod *oh, | |
2226 | struct device_node *np, | |
2227 | struct resource *res) | |
2228 | { | |
2229 | struct property *prop; | |
2230 | const __be32 *ranges; | |
2231 | const char *name; | |
2232 | u32 nr_addr, nr_size; | |
2233 | u64 base, size; | |
2234 | int len, error; | |
2235 | ||
2236 | if (!res) | |
2237 | return -EINVAL; | |
2238 | ||
2239 | ranges = of_get_property(np, "ranges", &len); | |
2240 | if (!ranges) | |
2241 | return -ENOENT; | |
2242 | ||
2243 | len /= sizeof(*ranges); | |
2244 | ||
2245 | if (len < 3) | |
2246 | return -EINVAL; | |
2247 | ||
2248 | of_property_for_each_string(np, "compatible", prop, name) | |
2249 | if (!strncmp("ti,sysc-", name, 8)) | |
2250 | break; | |
2251 | ||
2252 | if (!name) | |
2253 | return -ENOENT; | |
2254 | ||
2255 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
2256 | if (error) | |
2257 | return -ENOENT; | |
2258 | ||
2259 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
2260 | if (error) | |
2261 | return -ENOENT; | |
2262 | ||
2263 | if (nr_addr != 1 || nr_size != 1) { | |
6e771379 RH |
2264 | pr_err("%s: invalid range for %s->%pOFn\n", __func__, |
2265 | oh->name, np); | |
6c72b355 TL |
2266 | return -EINVAL; |
2267 | } | |
2268 | ||
2269 | ranges++; | |
2270 | base = of_translate_address(np, ranges++); | |
2271 | size = be32_to_cpup(ranges); | |
2272 | ||
6e771379 RH |
2273 | pr_debug("omap_hwmod: %s %pOFn at 0x%llx size 0x%llx\n", |
2274 | oh->name, np, base, size); | |
6c72b355 | 2275 | |
1dbcb97c TL |
2276 | if (oh && oh->mpu_rt_idx) { |
2277 | omap_hwmod_fix_mpu_rt_idx(oh, np, res); | |
2278 | ||
2279 | return 0; | |
2280 | } | |
2281 | ||
6c72b355 TL |
2282 | res->start = base; |
2283 | res->end = base + size - 1; | |
2284 | res->flags = IORESOURCE_MEM; | |
2285 | ||
2286 | return 0; | |
2287 | } | |
2288 | ||
381d033a PW |
2289 | /** |
2290 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2291 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2292 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2293 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2294 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2295 | * |
2296 | * Cache the virtual address used by the MPU to access this IP block's | |
2297 | * registers. This address is needed early so the OCP registers that | |
2298 | * are part of the device's address space can be ioremapped properly. | |
6423d6df | 2299 | * |
9a258afa RQ |
2300 | * If SYSC access is not needed, the registers will not be remapped |
2301 | * and non-availability of MPU access is not treated as an error. | |
2302 | * | |
6423d6df SA |
2303 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and |
2304 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2305 | */ |
f92d9597 | 2306 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2307 | int index, struct device_node *np) |
381d033a | 2308 | { |
079abade | 2309 | void __iomem *va_start = NULL; |
6c72b355 TL |
2310 | struct resource res; |
2311 | int error; | |
c9aafd23 PW |
2312 | |
2313 | if (!oh) | |
6423d6df | 2314 | return -EINVAL; |
c9aafd23 | 2315 | |
2221b5cd PW |
2316 | _save_mpu_port_index(oh); |
2317 | ||
9a258afa RQ |
2318 | /* if we don't need sysc access we don't need to ioremap */ |
2319 | if (!oh->class->sysc) | |
2320 | return 0; | |
2321 | ||
2322 | /* we can't continue without MPU PORT if we need sysc access */ | |
381d033a | 2323 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2324 | return -ENXIO; |
381d033a | 2325 | |
9cffb1a0 TL |
2326 | if (!np) { |
2327 | pr_err("omap_hwmod: %s: no dt node\n", oh->name); | |
2328 | return -ENXIO; | |
c9aafd23 PW |
2329 | } |
2330 | ||
9cffb1a0 TL |
2331 | /* Do we have a dts range for the interconnect target module? */ |
2332 | error = omap_hwmod_parse_module_range(oh, np, &res); | |
2333 | if (!error) | |
2334 | va_start = ioremap(res.start, resource_size(&res)); | |
2335 | ||
2336 | /* No ranges, rely on device reg entry */ | |
2337 | if (!va_start) | |
2338 | va_start = of_iomap(np, index + oh->mpu_rt_idx); | |
c9aafd23 | 2339 | if (!va_start) { |
9cffb1a0 TL |
2340 | pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n", |
2341 | oh->name, index, np); | |
6423d6df | 2342 | return -ENXIO; |
c9aafd23 PW |
2343 | } |
2344 | ||
2345 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2346 | oh->name, va_start); | |
2347 | ||
2348 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2349 | return 0; |
381d033a PW |
2350 | } |
2351 | ||
4f212247 TL |
2352 | static void __init parse_module_flags(struct omap_hwmod *oh, |
2353 | struct device_node *np) | |
2354 | { | |
2355 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) | |
2356 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2357 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2358 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
2359 | if (of_find_property(np, "ti,no-idle", NULL)) | |
2360 | oh->flags |= HWMOD_NO_IDLE; | |
2361 | } | |
2362 | ||
381d033a PW |
2363 | /** |
2364 | * _init - initialize internal data for the hwmod @oh | |
2365 | * @oh: struct omap_hwmod * | |
2366 | * @n: (unused) | |
2367 | * | |
2368 | * Look up the clocks and the address space used by the MPU to access | |
2369 | * registers belonging to the hwmod @oh. @oh must already be | |
2370 | * registered at this point. This is the first of two phases for | |
2371 | * hwmod initialization. Code called here does not touch any hardware | |
2372 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2373 | * upon success or if the hwmod isn't registered or if the hwmod's |
2374 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2375 | */ |
2376 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2377 | { | |
5e863c56 | 2378 | int r, index; |
f92d9597 | 2379 | struct device_node *np = NULL; |
1aa8f0cb | 2380 | struct device_node *bus; |
381d033a PW |
2381 | |
2382 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2383 | return 0; | |
2384 | ||
1aa8f0cb TL |
2385 | bus = of_find_node_by_name(NULL, "ocp"); |
2386 | if (!bus) | |
2387 | return -ENODEV; | |
5e863c56 | 2388 | |
1aa8f0cb TL |
2389 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); |
2390 | if (r) | |
2391 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2392 | else if (np && index) | |
6e771379 RH |
2393 | pr_warn("omap_hwmod: %s using broken dt data from %pOFn\n", |
2394 | oh->name, np); | |
f92d9597 | 2395 | |
9a258afa RQ |
2396 | r = _init_mpu_rt_base(oh, NULL, index, np); |
2397 | if (r < 0) { | |
2398 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2399 | oh->name); | |
2400 | return 0; | |
6423d6df | 2401 | } |
381d033a | 2402 | |
70f05be3 | 2403 | r = _init_clocks(oh, np); |
c48cd659 | 2404 | if (r < 0) { |
381d033a PW |
2405 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2406 | return -EINVAL; | |
2407 | } | |
2408 | ||
3d36ad7e | 2409 | if (np) { |
4f212247 TL |
2410 | struct device_node *child; |
2411 | ||
2412 | parse_module_flags(oh, np); | |
2413 | child = of_get_next_child(np, NULL); | |
2414 | if (child) | |
2415 | parse_module_flags(oh, child); | |
3d36ad7e | 2416 | } |
f92d9597 | 2417 | |
381d033a PW |
2418 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2419 | ||
2420 | return 0; | |
2421 | } | |
2422 | ||
63c85238 | 2423 | /** |
64813c3f | 2424 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2425 | * @oh: struct omap_hwmod * |
2426 | * | |
64813c3f PW |
2427 | * Set up the module's interface clocks. XXX This function is still mostly |
2428 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2429 | * the clock code. No return value. | |
63c85238 | 2430 | */ |
c10b26ab | 2431 | static void _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2432 | { |
5d95dde7 | 2433 | struct omap_hwmod_ocp_if *os; |
b8e1bddc | 2434 | |
381d033a | 2435 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2436 | return; |
48d54f3f | 2437 | |
b8e1bddc | 2438 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 | 2439 | if (!os->_clk) |
64813c3f | 2440 | continue; |
63c85238 | 2441 | |
64813c3f | 2442 | if (os->flags & OCPIF_SWSUP_IDLE) { |
12af39ca AK |
2443 | /* |
2444 | * we might have multiple users of one iclk with | |
2445 | * different requirements, disable autoidle when | |
2446 | * the module is enabled, e.g. dss iclk | |
2447 | */ | |
64813c3f | 2448 | } else { |
12af39ca | 2449 | /* we are enabling autoidle afterwards anyways */ |
5d95dde7 | 2450 | clk_enable(os->_clk); |
63c85238 PW |
2451 | } |
2452 | } | |
2453 | ||
64813c3f PW |
2454 | return; |
2455 | } | |
2456 | ||
2457 | /** | |
2458 | * _setup_reset - reset an IP block during the setup process | |
2459 | * @oh: struct omap_hwmod * | |
2460 | * | |
2461 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2462 | * process. The IP block is first enabled so it can be successfully | |
2463 | * reset. Returns 0 upon success or a negative error code upon | |
2464 | * failure. | |
2465 | */ | |
c10b26ab | 2466 | static int _setup_reset(struct omap_hwmod *oh) |
64813c3f PW |
2467 | { |
2468 | int r; | |
2469 | ||
2470 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2471 | return -EINVAL; | |
63c85238 | 2472 | |
5fb3d522 PW |
2473 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2474 | return -EPERM; | |
2475 | ||
747834ab PW |
2476 | if (oh->rst_lines_cnt == 0) { |
2477 | r = _enable(oh); | |
2478 | if (r) { | |
3d0cb73e JP |
2479 | pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", |
2480 | oh->name, oh->_state); | |
747834ab PW |
2481 | return -EINVAL; |
2482 | } | |
9a23dfe1 | 2483 | } |
63c85238 | 2484 | |
2800852a | 2485 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2486 | r = _reset(oh); |
2487 | ||
2488 | return r; | |
2489 | } | |
2490 | ||
2491 | /** | |
2492 | * _setup_postsetup - transition to the appropriate state after _setup | |
2493 | * @oh: struct omap_hwmod * | |
2494 | * | |
2495 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2496 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2497 | * this function is called at the end of _setup().) The postsetup | |
2498 | * state for an IP block can be changed by calling | |
2499 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2500 | * before one of the omap_hwmod_setup*() functions are called for the | |
2501 | * IP block. | |
2502 | * | |
2503 | * The IP block stays in this state until a PM runtime-based driver is | |
2504 | * loaded for that IP block. A post-setup state of IDLE is | |
2505 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2506 | * drivers, since those drivers are able to enable the IP block. A | |
2507 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2508 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2509 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2510 | * included, since the WDTIMER starts running on reset and will reset | |
2511 | * the MPU if left active. | |
2512 | * | |
2513 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2514 | * drivers have been converted to use PM runtime, and all of the IP | |
2515 | * block data and interconnect data is available to the hwmod code, it | |
2516 | * should be possible to replace this mechanism with a "lazy reset" | |
2517 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2518 | * when the driver first probes, then all remaining IP blocks without | |
2519 | * drivers are either shut down or enabled after the drivers have | |
2520 | * loaded. However, this cannot take place until the above | |
2521 | * preconditions have been met, since otherwise the late reset code | |
2522 | * has no way of knowing which IP blocks are in use by drivers, and | |
2523 | * which ones are unused. | |
2524 | * | |
2525 | * No return value. | |
2526 | */ | |
c10b26ab | 2527 | static void _setup_postsetup(struct omap_hwmod *oh) |
64813c3f PW |
2528 | { |
2529 | u8 postsetup_state; | |
2530 | ||
2531 | if (oh->rst_lines_cnt > 0) | |
2532 | return; | |
76e5589e | 2533 | |
2092e5cc PW |
2534 | postsetup_state = oh->_postsetup_state; |
2535 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2536 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2537 | ||
2538 | /* | |
2539 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2540 | * it should be set by the core code as a runtime flag during startup | |
2541 | */ | |
2e18f5a1 | 2542 | if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) && |
aacf0941 RN |
2543 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2544 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2545 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2546 | } |
2092e5cc PW |
2547 | |
2548 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2549 | _idle(oh); |
2092e5cc PW |
2550 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2551 | _shutdown(oh); | |
2552 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2553 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2554 | oh->name, postsetup_state); | |
63c85238 | 2555 | |
64813c3f PW |
2556 | return; |
2557 | } | |
2558 | ||
2559 | /** | |
2560 | * _setup - prepare IP block hardware for use | |
2561 | * @oh: struct omap_hwmod * | |
2562 | * @n: (unused, pass NULL) | |
2563 | * | |
2564 | * Configure the IP block represented by @oh. This may include | |
2565 | * enabling the IP block, resetting it, and placing it into a | |
2566 | * post-setup state, depending on the type of IP block and applicable | |
2567 | * flags. IP blocks are reset to prevent any previous configuration | |
2568 | * by the bootloader or previous operating system from interfering | |
2569 | * with power management or other parts of the system. The reset can | |
2570 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2571 | * two phases for hwmod initialization. Code called here generally | |
2572 | * affects the IP block hardware, or system integration hardware | |
2573 | * associated with the IP block. Returns 0. | |
2574 | */ | |
8c879705 | 2575 | static int _setup(struct omap_hwmod *oh, void *data) |
64813c3f PW |
2576 | { |
2577 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2578 | return 0; | |
2579 | ||
f22d2545 TV |
2580 | if (oh->parent_hwmod) { |
2581 | int r; | |
2582 | ||
2583 | r = _enable(oh->parent_hwmod); | |
2584 | WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n", | |
2585 | oh->name, oh->parent_hwmod->name); | |
2586 | } | |
2587 | ||
64813c3f PW |
2588 | _setup_iclk_autoidle(oh); |
2589 | ||
2590 | if (!_setup_reset(oh)) | |
2591 | _setup_postsetup(oh); | |
2592 | ||
f22d2545 TV |
2593 | if (oh->parent_hwmod) { |
2594 | u8 postsetup_state; | |
2595 | ||
2596 | postsetup_state = oh->parent_hwmod->_postsetup_state; | |
2597 | ||
2598 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
2599 | _idle(oh->parent_hwmod); | |
2600 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | |
2601 | _shutdown(oh->parent_hwmod); | |
2602 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2603 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2604 | oh->parent_hwmod->name, postsetup_state); | |
2605 | } | |
2606 | ||
63c85238 PW |
2607 | return 0; |
2608 | } | |
2609 | ||
63c85238 | 2610 | /** |
0102b627 | 2611 | * _register - register a struct omap_hwmod |
63c85238 PW |
2612 | * @oh: struct omap_hwmod * |
2613 | * | |
43b40992 PW |
2614 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2615 | * already has been registered by the same name; -EINVAL if the | |
2616 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2617 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2618 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2619 | * success. | |
63c85238 PW |
2620 | * |
2621 | * XXX The data should be copied into bootmem, so the original data | |
2622 | * should be marked __initdata and freed after init. This would allow | |
2623 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2624 | * that the copy process would be relatively complex due to the large number | |
2625 | * of substructures. | |
2626 | */ | |
01592df9 | 2627 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2628 | { |
43b40992 PW |
2629 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2630 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2631 | return -EINVAL; |
2632 | ||
63c85238 PW |
2633 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2634 | ||
ce35b244 BC |
2635 | if (_lookup(oh->name)) |
2636 | return -EEXIST; | |
63c85238 | 2637 | |
63c85238 PW |
2638 | list_add_tail(&oh->node, &omap_hwmod_list); |
2639 | ||
2221b5cd | 2640 | INIT_LIST_HEAD(&oh->slave_ports); |
dc6d1cda | 2641 | spin_lock_init(&oh->_lock); |
69317952 | 2642 | lockdep_set_class(&oh->_lock, &oh->hwmod_key); |
2092e5cc | 2643 | |
63c85238 PW |
2644 | oh->_state = _HWMOD_STATE_REGISTERED; |
2645 | ||
569edd70 PW |
2646 | /* |
2647 | * XXX Rather than doing a strcmp(), this should test a flag | |
2648 | * set in the hwmod data, inserted by the autogenerator code. | |
2649 | */ | |
2650 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2651 | mpu_oh = oh; | |
63c85238 | 2652 | |
569edd70 | 2653 | return 0; |
63c85238 PW |
2654 | } |
2655 | ||
2221b5cd PW |
2656 | /** |
2657 | * _add_link - add an interconnect between two IP blocks | |
2658 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2659 | * | |
a1e31235 | 2660 | * Add struct omap_hwmod_link records connecting the slave IP block |
2221b5cd PW |
2661 | * specified in @oi->slave to @oi. This code is assumed to run before |
2662 | * preemption or SMP has been enabled, thus avoiding the need for | |
2663 | * locking in this code. Changes to this assumption will require | |
2664 | * additional locking. Returns 0. | |
2665 | */ | |
2666 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2667 | { | |
2221b5cd PW |
2668 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, |
2669 | oi->slave->name); | |
2670 | ||
a1e31235 | 2671 | list_add(&oi->node, &oi->slave->slave_ports); |
2221b5cd PW |
2672 | oi->slave->slaves_cnt++; |
2673 | ||
2674 | return 0; | |
2675 | } | |
2676 | ||
2677 | /** | |
2678 | * _register_link - register a struct omap_hwmod_ocp_if | |
2679 | * @oi: struct omap_hwmod_ocp_if * | |
2680 | * | |
2681 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2682 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2683 | * record pointed to by @oi is missing required fields; or 0 upon | |
2684 | * success. | |
2685 | * | |
2686 | * XXX The data should be copied into bootmem, so the original data | |
2687 | * should be marked __initdata and freed after init. This would allow | |
2688 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2689 | */ | |
2690 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2691 | { | |
2692 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2693 | return -EINVAL; | |
2694 | ||
2695 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2696 | return -EEXIST; | |
2697 | ||
2698 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2699 | oi->master->name, oi->slave->name); | |
2700 | ||
2701 | /* | |
2702 | * Register the connected hwmods, if they haven't been | |
2703 | * registered already | |
2704 | */ | |
2705 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2706 | _register(oi->master); | |
2707 | ||
2708 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2709 | _register(oi->slave); | |
2710 | ||
2711 | _add_link(oi); | |
2712 | ||
2713 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2714 | ||
2715 | return 0; | |
2716 | } | |
2717 | ||
8f6aa8ee KH |
2718 | /* Static functions intended only for use in soc_ops field function pointers */ |
2719 | ||
2720 | /** | |
9002e921 | 2721 | * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2722 | * @oh: struct omap_hwmod * |
2723 | * | |
2724 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2725 | * does not have an IDLEST bit or if the module successfully leaves | |
2726 | * slave idle; otherwise, pass along the return value of the | |
2727 | * appropriate *_cm*_wait_module_ready() function. | |
2728 | */ | |
9002e921 | 2729 | static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2730 | { |
2731 | if (!oh) | |
2732 | return -EINVAL; | |
2733 | ||
2734 | if (oh->flags & HWMOD_NO_IDLEST) | |
2735 | return 0; | |
2736 | ||
2737 | if (!_find_mpu_rt_port(oh)) | |
2738 | return 0; | |
2739 | ||
2740 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2741 | ||
021b6ff0 TK |
2742 | return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs, |
2743 | oh->prcm.omap2.idlest_reg_id, | |
2744 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2745 | } |
2746 | ||
2747 | /** | |
2748 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2749 | * @oh: struct omap_hwmod * | |
2750 | * | |
2751 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2752 | * does not have an IDLEST bit or if the module successfully leaves | |
2753 | * slave idle; otherwise, pass along the return value of the | |
2754 | * appropriate *_cm*_wait_module_ready() function. | |
2755 | */ | |
2756 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2757 | { | |
2b026d13 | 2758 | if (!oh) |
8f6aa8ee KH |
2759 | return -EINVAL; |
2760 | ||
2b026d13 | 2761 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2762 | return 0; |
2763 | ||
2764 | if (!_find_mpu_rt_port(oh)) | |
2765 | return 0; | |
2766 | ||
8823ddf2 TL |
2767 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
2768 | return 0; | |
2769 | ||
2770 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
2771 | return 0; |
2772 | ||
8f6aa8ee KH |
2773 | /* XXX check module SIDLEMODE, hardreset status */ |
2774 | ||
021b6ff0 TK |
2775 | return omap_cm_wait_module_ready(oh->clkdm->prcm_partition, |
2776 | oh->clkdm->cm_inst, | |
2777 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
2778 | } |
2779 | ||
b8249cf2 KH |
2780 | /** |
2781 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2782 | * @oh: struct omap_hwmod * to assert hardreset | |
2783 | * @ohri: hardreset line data | |
2784 | * | |
2785 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2786 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2787 | * use as an soc_ops function pointer. Passes along the return value | |
2788 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2789 | * for removal when the PRM code is moved into drivers/. | |
2790 | */ | |
2791 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2792 | struct omap_hwmod_rst_info *ohri) | |
2793 | { | |
efd44dc3 TK |
2794 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
2795 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2796 | } |
2797 | ||
2798 | /** | |
2799 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2800 | * @oh: struct omap_hwmod * to deassert hardreset | |
2801 | * @ohri: hardreset line data | |
2802 | * | |
2803 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2804 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2805 | * use as an soc_ops function pointer. Passes along the return value | |
2806 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2807 | * scheduled for removal when the PRM code is moved into drivers/. | |
2808 | */ | |
2809 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2810 | struct omap_hwmod_rst_info *ohri) | |
2811 | { | |
37fb59d7 TK |
2812 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
2813 | oh->prcm.omap2.module_offs, 0, 0); | |
b8249cf2 KH |
2814 | } |
2815 | ||
2816 | /** | |
2817 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2818 | * @oh: struct omap_hwmod * to test hardreset | |
2819 | * @ohri: hardreset line data | |
2820 | * | |
2821 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2822 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2823 | * intended for use as an soc_ops function pointer. Passes along the | |
2824 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2825 | * function is scheduled for removal when the PRM code is moved into | |
2826 | * drivers/. | |
2827 | */ | |
2828 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2829 | struct omap_hwmod_rst_info *ohri) | |
2830 | { | |
1bc28b34 TK |
2831 | return omap_prm_is_hardreset_asserted(ohri->st_shift, 0, |
2832 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2833 | } |
2834 | ||
2835 | /** | |
2836 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2837 | * @oh: struct omap_hwmod * to assert hardreset | |
2838 | * @ohri: hardreset line data | |
2839 | * | |
2840 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2841 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2842 | * intended for use as an soc_ops function pointer. Passes along the | |
2843 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2844 | * function is scheduled for removal when the PRM code is moved into | |
2845 | * drivers/. | |
2846 | */ | |
2847 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2848 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2849 | { |
07b3a139 PW |
2850 | if (!oh->clkdm) |
2851 | return -EINVAL; | |
2852 | ||
efd44dc3 TK |
2853 | return omap_prm_assert_hardreset(ohri->rst_shift, |
2854 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2855 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2856 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2857 | } |
2858 | ||
2859 | /** | |
2860 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2861 | * @oh: struct omap_hwmod * to deassert hardreset | |
2862 | * @ohri: hardreset line data | |
2863 | * | |
2864 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2865 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2866 | * intended for use as an soc_ops function pointer. Passes along the | |
2867 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2868 | * function is scheduled for removal when the PRM code is moved into | |
2869 | * drivers/. | |
2870 | */ | |
2871 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2872 | struct omap_hwmod_rst_info *ohri) | |
2873 | { | |
07b3a139 PW |
2874 | if (!oh->clkdm) |
2875 | return -EINVAL; | |
2876 | ||
b8249cf2 KH |
2877 | if (ohri->st_shift) |
2878 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2879 | oh->name, ohri->name); | |
4ebf5b28 | 2880 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, |
37fb59d7 TK |
2881 | oh->clkdm->pwrdm.ptr->prcm_partition, |
2882 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
4ebf5b28 TK |
2883 | oh->prcm.omap4.rstctrl_offs, |
2884 | oh->prcm.omap4.rstctrl_offs + | |
2885 | OMAP4_RST_CTRL_ST_OFFSET); | |
b8249cf2 KH |
2886 | } |
2887 | ||
2888 | /** | |
2889 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2890 | * @oh: struct omap_hwmod * to test hardreset | |
2891 | * @ohri: hardreset line data | |
2892 | * | |
2893 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2894 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2895 | * Only intended for use as an soc_ops function pointer. Passes along | |
2896 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2897 | * This function is scheduled for removal when the PRM code is moved | |
2898 | * into drivers/. | |
2899 | */ | |
2900 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2901 | struct omap_hwmod_rst_info *ohri) | |
2902 | { | |
07b3a139 PW |
2903 | if (!oh->clkdm) |
2904 | return -EINVAL; | |
2905 | ||
1bc28b34 TK |
2906 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, |
2907 | oh->clkdm->pwrdm.ptr-> | |
2908 | prcm_partition, | |
2909 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2910 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2911 | } |
2912 | ||
9fabc1a2 TK |
2913 | /** |
2914 | * _omap4_disable_direct_prcm - disable direct PRCM control for hwmod | |
2915 | * @oh: struct omap_hwmod * to disable control for | |
2916 | * | |
2917 | * Disables direct PRCM clkctrl done by hwmod core. Instead, the hwmod | |
2918 | * will be using its main_clk to enable/disable the module. Returns | |
2919 | * 0 if successful. | |
2920 | */ | |
2921 | static int _omap4_disable_direct_prcm(struct omap_hwmod *oh) | |
2922 | { | |
2923 | if (!oh) | |
2924 | return -EINVAL; | |
2925 | ||
8823ddf2 | 2926 | oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK; |
9fabc1a2 TK |
2927 | |
2928 | return 0; | |
2929 | } | |
2930 | ||
1688bf19 VH |
2931 | /** |
2932 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2933 | * @oh: struct omap_hwmod * to deassert hardreset | |
2934 | * @ohri: hardreset line data | |
2935 | * | |
2936 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2937 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2938 | * intended for use as an soc_ops function pointer. Passes along the | |
2939 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2940 | * function is scheduled for removal when the PRM code is moved into | |
2941 | * drivers/. | |
2942 | */ | |
2943 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2944 | struct omap_hwmod_rst_info *ohri) | |
2945 | { | |
a5bf00cd TK |
2946 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, |
2947 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
37fb59d7 TK |
2948 | oh->clkdm->pwrdm.ptr->prcm_offs, |
2949 | oh->prcm.omap4.rstctrl_offs, | |
2950 | oh->prcm.omap4.rstst_offs); | |
1688bf19 VH |
2951 | } |
2952 | ||
0102b627 BC |
2953 | /* Public functions */ |
2954 | ||
2955 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2956 | { | |
2957 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2958 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 2959 | else |
edfaf05c | 2960 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2961 | } |
2962 | ||
2963 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2964 | { | |
2965 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2966 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 2967 | else |
edfaf05c | 2968 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2969 | } |
2970 | ||
6d3c55fd A |
2971 | /** |
2972 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2973 | * @oh: struct omap_hwmod * | |
2974 | * | |
2975 | * This is a public function exposed to drivers. Some drivers may need to do | |
2976 | * some settings before and after resetting the device. Those drivers after | |
2977 | * doing the necessary settings could use this function to start a reset by | |
2978 | * setting the SYSCONFIG.SOFTRESET bit. | |
2979 | */ | |
2980 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
2981 | { | |
3c55c1ba PW |
2982 | u32 v; |
2983 | int ret; | |
2984 | ||
2985 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
2986 | return -EINVAL; |
2987 | ||
3c55c1ba PW |
2988 | v = oh->_sysc_cache; |
2989 | ret = _set_softreset(oh, &v); | |
2990 | if (ret) | |
2991 | goto error; | |
2992 | _write_sysconfig(v, oh); | |
2993 | ||
313a76ee RQ |
2994 | ret = _clear_softreset(oh, &v); |
2995 | if (ret) | |
2996 | goto error; | |
2997 | _write_sysconfig(v, oh); | |
2998 | ||
3c55c1ba PW |
2999 | error: |
3000 | return ret; | |
6d3c55fd A |
3001 | } |
3002 | ||
63c85238 PW |
3003 | /** |
3004 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3005 | * @name: name of the omap_hwmod to look up | |
3006 | * | |
3007 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3008 | * struct omap_hwmod *, or NULL upon error. | |
3009 | */ | |
3010 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3011 | { | |
3012 | struct omap_hwmod *oh; | |
3013 | ||
3014 | if (!name) | |
3015 | return NULL; | |
3016 | ||
63c85238 | 3017 | oh = _lookup(name); |
63c85238 PW |
3018 | |
3019 | return oh; | |
3020 | } | |
3021 | ||
3022 | /** | |
3023 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3024 | * @fn: pointer to a callback function | |
97d60162 | 3025 | * @data: void * data to pass to callback function |
63c85238 PW |
3026 | * |
3027 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3028 | * function. @fn must return 0 for success or any other value for | |
3029 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3030 | * will stop and the non-zero return value will be passed to the | |
3031 | * caller of omap_hwmod_for_each(). @fn is called with | |
3032 | * omap_hwmod_for_each() held. | |
3033 | */ | |
97d60162 PW |
3034 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3035 | void *data) | |
63c85238 PW |
3036 | { |
3037 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3038 | int ret = 0; |
63c85238 PW |
3039 | |
3040 | if (!fn) | |
3041 | return -EINVAL; | |
3042 | ||
63c85238 | 3043 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3044 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3045 | if (ret) |
3046 | break; | |
3047 | } | |
63c85238 PW |
3048 | |
3049 | return ret; | |
3050 | } | |
3051 | ||
2221b5cd PW |
3052 | /** |
3053 | * omap_hwmod_register_links - register an array of hwmod links | |
3054 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3055 | * | |
3056 | * Intended to be called early in boot before the clock framework is | |
3057 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3058 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3059 | * omap_hwmod_init() hasn't been called before calling this function, | |
3060 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3061 | * success. | |
2221b5cd PW |
3062 | */ |
3063 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3064 | { | |
3065 | int r, i; | |
3066 | ||
9ebfd285 KH |
3067 | if (!inited) |
3068 | return -EINVAL; | |
3069 | ||
2221b5cd PW |
3070 | if (!ois) |
3071 | return 0; | |
3072 | ||
f7f7a29b RN |
3073 | if (ois[0] == NULL) /* Empty list */ |
3074 | return 0; | |
3075 | ||
2221b5cd PW |
3076 | i = 0; |
3077 | do { | |
3078 | r = _register_link(ois[i]); | |
3079 | WARN(r && r != -EEXIST, | |
3080 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3081 | ois[i]->master->name, ois[i]->slave->name, r); | |
3082 | } while (ois[++i]); | |
3083 | ||
3084 | return 0; | |
3085 | } | |
3086 | ||
381d033a PW |
3087 | /** |
3088 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3089 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3090 | * | |
3091 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3092 | * hasn't been initialized and set up yet, do so now. This must be | |
3093 | * done first since sleep dependencies may be added from other hwmods | |
3094 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3095 | * return value. | |
63c85238 | 3096 | */ |
381d033a | 3097 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3098 | { |
381d033a PW |
3099 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3100 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3101 | __func__, MPU_INITIATOR_NAME); | |
3102 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3103 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3104 | } |
3105 | ||
63c85238 | 3106 | /** |
a2debdbd PW |
3107 | * omap_hwmod_setup_one - set up a single hwmod |
3108 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3109 | * | |
381d033a PW |
3110 | * Initialize and set up a single hwmod. Intended to be used for a |
3111 | * small number of early devices, such as the timer IP blocks used for | |
3112 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3113 | * Resolves the struct clk names to struct clk pointers for each | |
3114 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3115 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3116 | */ |
3117 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3118 | { |
3119 | struct omap_hwmod *oh; | |
63c85238 | 3120 | |
a2debdbd PW |
3121 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3122 | ||
a2debdbd PW |
3123 | oh = _lookup(oh_name); |
3124 | if (!oh) { | |
3125 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3126 | return -EINVAL; | |
3127 | } | |
63c85238 | 3128 | |
381d033a | 3129 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3130 | |
381d033a | 3131 | _init(oh, NULL); |
a2debdbd PW |
3132 | _setup(oh, NULL); |
3133 | ||
63c85238 PW |
3134 | return 0; |
3135 | } | |
3136 | ||
a8844306 TL |
3137 | static void omap_hwmod_check_one(struct device *dev, |
3138 | const char *name, s8 v1, u8 v2) | |
3139 | { | |
3140 | if (v1 < 0) | |
3141 | return; | |
3142 | ||
3143 | if (v1 != v2) | |
3144 | dev_warn(dev, "%s %d != %d\n", name, v1, v2); | |
3145 | } | |
3146 | ||
3147 | /** | |
3148 | * omap_hwmod_check_sysc - check sysc against platform sysc | |
3149 | * @dev: struct device | |
3150 | * @data: module data | |
3151 | * @sysc_fields: new sysc configuration | |
3152 | */ | |
3153 | static int omap_hwmod_check_sysc(struct device *dev, | |
3154 | const struct ti_sysc_module_data *data, | |
3155 | struct sysc_regbits *sysc_fields) | |
3156 | { | |
3157 | const struct sysc_regbits *regbits = data->cap->regbits; | |
3158 | ||
3159 | omap_hwmod_check_one(dev, "dmadisable_shift", | |
3160 | regbits->dmadisable_shift, | |
3161 | sysc_fields->dmadisable_shift); | |
3162 | omap_hwmod_check_one(dev, "midle_shift", | |
3163 | regbits->midle_shift, | |
3164 | sysc_fields->midle_shift); | |
3165 | omap_hwmod_check_one(dev, "sidle_shift", | |
3166 | regbits->sidle_shift, | |
3167 | sysc_fields->sidle_shift); | |
3168 | omap_hwmod_check_one(dev, "clkact_shift", | |
3169 | regbits->clkact_shift, | |
3170 | sysc_fields->clkact_shift); | |
3171 | omap_hwmod_check_one(dev, "enwkup_shift", | |
3172 | regbits->enwkup_shift, | |
3173 | sysc_fields->enwkup_shift); | |
3174 | omap_hwmod_check_one(dev, "srst_shift", | |
3175 | regbits->srst_shift, | |
3176 | sysc_fields->srst_shift); | |
3177 | omap_hwmod_check_one(dev, "autoidle_shift", | |
3178 | regbits->autoidle_shift, | |
3179 | sysc_fields->autoidle_shift); | |
3180 | ||
3181 | return 0; | |
3182 | } | |
3183 | ||
8c879705 TL |
3184 | /** |
3185 | * omap_hwmod_init_regbits - init sysconfig specific register bits | |
3186 | * @dev: struct device | |
3187 | * @data: module data | |
3188 | * @sysc_fields: new sysc configuration | |
3189 | */ | |
3190 | static int omap_hwmod_init_regbits(struct device *dev, | |
3191 | const struct ti_sysc_module_data *data, | |
3192 | struct sysc_regbits **sysc_fields) | |
3193 | { | |
3194 | *sysc_fields = NULL; | |
3195 | ||
3196 | switch (data->cap->type) { | |
3197 | case TI_SYSC_OMAP2: | |
3198 | case TI_SYSC_OMAP2_TIMER: | |
3199 | *sysc_fields = &omap_hwmod_sysc_type1; | |
3200 | break; | |
3201 | case TI_SYSC_OMAP3_SHAM: | |
3202 | *sysc_fields = &omap3_sham_sysc_fields; | |
3203 | break; | |
3204 | case TI_SYSC_OMAP3_AES: | |
3205 | *sysc_fields = &omap3xxx_aes_sysc_fields; | |
3206 | break; | |
3207 | case TI_SYSC_OMAP4: | |
3208 | case TI_SYSC_OMAP4_TIMER: | |
3209 | *sysc_fields = &omap_hwmod_sysc_type2; | |
3210 | break; | |
3211 | case TI_SYSC_OMAP4_SIMPLE: | |
3212 | *sysc_fields = &omap_hwmod_sysc_type3; | |
3213 | break; | |
3214 | case TI_SYSC_OMAP34XX_SR: | |
3215 | *sysc_fields = &omap34xx_sr_sysc_fields; | |
3216 | break; | |
3217 | case TI_SYSC_OMAP36XX_SR: | |
3218 | *sysc_fields = &omap36xx_sr_sysc_fields; | |
3219 | break; | |
3220 | case TI_SYSC_OMAP4_SR: | |
3221 | *sysc_fields = &omap36xx_sr_sysc_fields; | |
3222 | break; | |
3223 | case TI_SYSC_OMAP4_MCASP: | |
3224 | *sysc_fields = &omap_hwmod_sysc_type_mcasp; | |
3225 | break; | |
3226 | case TI_SYSC_OMAP4_USB_HOST_FS: | |
3227 | *sysc_fields = &omap_hwmod_sysc_type_usb_host_fs; | |
3228 | break; | |
3229 | default: | |
3230 | return -EINVAL; | |
3231 | } | |
3232 | ||
a8844306 | 3233 | return omap_hwmod_check_sysc(dev, data, *sysc_fields); |
8c879705 TL |
3234 | } |
3235 | ||
3236 | /** | |
3237 | * omap_hwmod_init_reg_offs - initialize sysconfig register offsets | |
3238 | * @dev: struct device | |
3239 | * @data: module data | |
3240 | * @rev_offs: revision register offset | |
3241 | * @sysc_offs: sysc register offset | |
3242 | * @syss_offs: syss register offset | |
3243 | */ | |
3244 | int omap_hwmod_init_reg_offs(struct device *dev, | |
3245 | const struct ti_sysc_module_data *data, | |
103fd8e7 | 3246 | s32 *rev_offs, s32 *sysc_offs, s32 *syss_offs) |
8c879705 | 3247 | { |
103fd8e7 | 3248 | *rev_offs = -ENODEV; |
8c879705 TL |
3249 | *sysc_offs = 0; |
3250 | *syss_offs = 0; | |
3251 | ||
103fd8e7 | 3252 | if (data->offsets[SYSC_REVISION] >= 0) |
8c879705 TL |
3253 | *rev_offs = data->offsets[SYSC_REVISION]; |
3254 | ||
103fd8e7 | 3255 | if (data->offsets[SYSC_SYSCONFIG] >= 0) |
8c879705 TL |
3256 | *sysc_offs = data->offsets[SYSC_SYSCONFIG]; |
3257 | ||
103fd8e7 | 3258 | if (data->offsets[SYSC_SYSSTATUS] >= 0) |
8c879705 TL |
3259 | *syss_offs = data->offsets[SYSC_SYSSTATUS]; |
3260 | ||
3261 | return 0; | |
3262 | } | |
3263 | ||
3264 | /** | |
3265 | * omap_hwmod_init_sysc_flags - initialize sysconfig features | |
3266 | * @dev: struct device | |
3267 | * @data: module data | |
3268 | * @sysc_flags: module configuration | |
3269 | */ | |
3270 | int omap_hwmod_init_sysc_flags(struct device *dev, | |
3271 | const struct ti_sysc_module_data *data, | |
3272 | u32 *sysc_flags) | |
3273 | { | |
3274 | *sysc_flags = 0; | |
3275 | ||
3276 | switch (data->cap->type) { | |
3277 | case TI_SYSC_OMAP2: | |
3278 | case TI_SYSC_OMAP2_TIMER: | |
3279 | /* See SYSC_OMAP2_* in include/dt-bindings/bus/ti-sysc.h */ | |
3280 | if (data->cfg->sysc_val & SYSC_OMAP2_CLOCKACTIVITY) | |
3281 | *sysc_flags |= SYSC_HAS_CLOCKACTIVITY; | |
3282 | if (data->cfg->sysc_val & SYSC_OMAP2_EMUFREE) | |
3283 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3284 | if (data->cfg->sysc_val & SYSC_OMAP2_ENAWAKEUP) | |
3285 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3286 | if (data->cfg->sysc_val & SYSC_OMAP2_SOFTRESET) | |
3287 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3288 | if (data->cfg->sysc_val & SYSC_OMAP2_AUTOIDLE) | |
3289 | *sysc_flags |= SYSC_HAS_AUTOIDLE; | |
3290 | break; | |
3291 | case TI_SYSC_OMAP4: | |
3292 | case TI_SYSC_OMAP4_TIMER: | |
3293 | /* See SYSC_OMAP4_* in include/dt-bindings/bus/ti-sysc.h */ | |
3294 | if (data->cfg->sysc_val & SYSC_OMAP4_DMADISABLE) | |
3295 | *sysc_flags |= SYSC_HAS_DMADISABLE; | |
3296 | if (data->cfg->sysc_val & SYSC_OMAP4_FREEEMU) | |
3297 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3298 | if (data->cfg->sysc_val & SYSC_OMAP4_SOFTRESET) | |
3299 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3300 | break; | |
3301 | case TI_SYSC_OMAP34XX_SR: | |
3302 | case TI_SYSC_OMAP36XX_SR: | |
3303 | /* See SYSC_OMAP3_SR_* in include/dt-bindings/bus/ti-sysc.h */ | |
3304 | if (data->cfg->sysc_val & SYSC_OMAP3_SR_ENAWAKEUP) | |
3305 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3306 | break; | |
3307 | default: | |
3308 | if (data->cap->regbits->emufree_shift >= 0) | |
3309 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3310 | if (data->cap->regbits->enwkup_shift >= 0) | |
3311 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3312 | if (data->cap->regbits->srst_shift >= 0) | |
3313 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3314 | if (data->cap->regbits->autoidle_shift >= 0) | |
3315 | *sysc_flags |= SYSC_HAS_AUTOIDLE; | |
3316 | break; | |
3317 | } | |
3318 | ||
3319 | if (data->cap->regbits->midle_shift >= 0 && | |
3320 | data->cfg->midlemodes) | |
3321 | *sysc_flags |= SYSC_HAS_MIDLEMODE; | |
3322 | ||
3323 | if (data->cap->regbits->sidle_shift >= 0 && | |
3324 | data->cfg->sidlemodes) | |
3325 | *sysc_flags |= SYSC_HAS_SIDLEMODE; | |
3326 | ||
3327 | if (data->cfg->quirks & SYSC_QUIRK_UNCACHED) | |
3328 | *sysc_flags |= SYSC_NO_CACHE; | |
3329 | if (data->cfg->quirks & SYSC_QUIRK_RESET_STATUS) | |
3330 | *sysc_flags |= SYSC_HAS_RESET_STATUS; | |
3331 | ||
3332 | if (data->cfg->syss_mask & 1) | |
3333 | *sysc_flags |= SYSS_HAS_RESET_STATUS; | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
3338 | /** | |
3339 | * omap_hwmod_init_idlemodes - initialize module idle modes | |
3340 | * @dev: struct device | |
3341 | * @data: module data | |
3342 | * @idlemodes: module supported idle modes | |
3343 | */ | |
3344 | int omap_hwmod_init_idlemodes(struct device *dev, | |
3345 | const struct ti_sysc_module_data *data, | |
3346 | u32 *idlemodes) | |
3347 | { | |
3348 | *idlemodes = 0; | |
3349 | ||
3350 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE)) | |
3351 | *idlemodes |= MSTANDBY_FORCE; | |
3352 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO)) | |
3353 | *idlemodes |= MSTANDBY_NO; | |
3354 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART)) | |
3355 | *idlemodes |= MSTANDBY_SMART; | |
3356 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
3357 | *idlemodes |= MSTANDBY_SMART_WKUP; | |
3358 | ||
3359 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE)) | |
3360 | *idlemodes |= SIDLE_FORCE; | |
3361 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO)) | |
3362 | *idlemodes |= SIDLE_NO; | |
3363 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART)) | |
3364 | *idlemodes |= SIDLE_SMART; | |
3365 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
3366 | *idlemodes |= SIDLE_SMART_WKUP; | |
3367 | ||
3368 | return 0; | |
3369 | } | |
3370 | ||
a8844306 TL |
3371 | /** |
3372 | * omap_hwmod_check_module - check new module against platform data | |
3373 | * @dev: struct device | |
3374 | * @oh: module | |
3375 | * @data: new module data | |
3376 | * @sysc_fields: sysc register bits | |
3377 | * @rev_offs: revision register offset | |
3378 | * @sysc_offs: sysconfig register offset | |
3379 | * @syss_offs: sysstatus register offset | |
3380 | * @sysc_flags: sysc specific flags | |
3381 | * @idlemodes: sysc supported idlemodes | |
3382 | */ | |
3383 | static int omap_hwmod_check_module(struct device *dev, | |
3384 | struct omap_hwmod *oh, | |
3385 | const struct ti_sysc_module_data *data, | |
3386 | struct sysc_regbits *sysc_fields, | |
103fd8e7 TL |
3387 | s32 rev_offs, s32 sysc_offs, |
3388 | s32 syss_offs, u32 sysc_flags, | |
a8844306 TL |
3389 | u32 idlemodes) |
3390 | { | |
3391 | if (!oh->class->sysc) | |
3392 | return -ENODEV; | |
3393 | ||
3394 | if (sysc_fields != oh->class->sysc->sysc_fields) | |
3395 | dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields, | |
3396 | oh->class->sysc->sysc_fields); | |
3397 | ||
3398 | if (rev_offs != oh->class->sysc->rev_offs) | |
3399 | dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs, | |
3400 | oh->class->sysc->rev_offs); | |
3401 | if (sysc_offs != oh->class->sysc->sysc_offs) | |
3402 | dev_warn(dev, "sysc_offs %08x != %08x\n", sysc_offs, | |
3403 | oh->class->sysc->sysc_offs); | |
3404 | if (syss_offs != oh->class->sysc->syss_offs) | |
3405 | dev_warn(dev, "syss_offs %08x != %08x\n", syss_offs, | |
3406 | oh->class->sysc->syss_offs); | |
3407 | ||
3408 | if (sysc_flags != oh->class->sysc->sysc_flags) | |
3409 | dev_warn(dev, "sysc_flags %08x != %08x\n", sysc_flags, | |
3410 | oh->class->sysc->sysc_flags); | |
3411 | ||
3412 | if (idlemodes != oh->class->sysc->idlemodes) | |
3413 | dev_warn(dev, "idlemodes %08x != %08x\n", idlemodes, | |
3414 | oh->class->sysc->idlemodes); | |
3415 | ||
3416 | if (data->cfg->srst_udelay != oh->class->sysc->srst_udelay) | |
3417 | dev_warn(dev, "srst_udelay %i != %i\n", | |
3418 | data->cfg->srst_udelay, | |
3419 | oh->class->sysc->srst_udelay); | |
3420 | ||
3421 | return 0; | |
3422 | } | |
3423 | ||
8c879705 TL |
3424 | /** |
3425 | * omap_hwmod_allocate_module - allocate new module | |
3426 | * @dev: struct device | |
3427 | * @oh: module | |
3428 | * @sysc_fields: sysc register bits | |
3429 | * @rev_offs: revision register offset | |
3430 | * @sysc_offs: sysconfig register offset | |
3431 | * @syss_offs: sysstatus register offset | |
3432 | * @sysc_flags: sysc specific flags | |
3433 | * @idlemodes: sysc supported idlemodes | |
3434 | * | |
3435 | * Note that the allocations here cannot use devm as ti-sysc can rebind. | |
3436 | */ | |
3437 | int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, | |
3438 | const struct ti_sysc_module_data *data, | |
3439 | struct sysc_regbits *sysc_fields, | |
103fd8e7 | 3440 | s32 rev_offs, s32 sysc_offs, s32 syss_offs, |
8c879705 TL |
3441 | u32 sysc_flags, u32 idlemodes) |
3442 | { | |
3443 | struct omap_hwmod_class_sysconfig *sysc; | |
3444 | struct omap_hwmod_class *class; | |
3445 | void __iomem *regs = NULL; | |
3446 | unsigned long flags; | |
3447 | ||
3448 | sysc = kzalloc(sizeof(*sysc), GFP_KERNEL); | |
3449 | if (!sysc) | |
3450 | return -ENOMEM; | |
3451 | ||
3452 | sysc->sysc_fields = sysc_fields; | |
3453 | sysc->rev_offs = rev_offs; | |
3454 | sysc->sysc_offs = sysc_offs; | |
3455 | sysc->syss_offs = syss_offs; | |
3456 | sysc->sysc_flags = sysc_flags; | |
3457 | sysc->idlemodes = idlemodes; | |
3458 | sysc->srst_udelay = data->cfg->srst_udelay; | |
3459 | ||
3460 | if (!oh->_mpu_rt_va) { | |
3461 | regs = ioremap(data->module_pa, | |
3462 | data->module_size); | |
3463 | if (!regs) | |
3464 | return -ENOMEM; | |
3465 | } | |
3466 | ||
3467 | /* | |
3468 | * We need new oh->class as the other devices in the same class | |
3469 | * may not yet have ioremapped their registers. | |
3470 | */ | |
3471 | class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL); | |
3472 | if (!class) | |
3473 | return -ENOMEM; | |
3474 | ||
3475 | class->sysc = sysc; | |
3476 | ||
3477 | spin_lock_irqsave(&oh->_lock, flags); | |
3478 | if (regs) | |
3479 | oh->_mpu_rt_va = regs; | |
3480 | oh->class = class; | |
3481 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
3482 | _setup(oh, NULL); | |
3483 | spin_unlock_irqrestore(&oh->_lock, flags); | |
3484 | ||
3485 | return 0; | |
3486 | } | |
3487 | ||
3488 | /** | |
3489 | * omap_hwmod_init_module - initialize new module | |
3490 | * @dev: struct device | |
3491 | * @data: module data | |
3492 | * @cookie: cookie for the caller to use for later calls | |
3493 | */ | |
3494 | int omap_hwmod_init_module(struct device *dev, | |
3495 | const struct ti_sysc_module_data *data, | |
3496 | struct ti_sysc_cookie *cookie) | |
3497 | { | |
3498 | struct omap_hwmod *oh; | |
3499 | struct sysc_regbits *sysc_fields; | |
103fd8e7 TL |
3500 | s32 rev_offs, sysc_offs, syss_offs; |
3501 | u32 sysc_flags, idlemodes; | |
8c879705 TL |
3502 | int error; |
3503 | ||
3504 | if (!dev || !data) | |
3505 | return -EINVAL; | |
3506 | ||
3507 | oh = _lookup(data->name); | |
3508 | if (!oh) | |
3509 | return -ENODEV; | |
3510 | ||
3511 | cookie->data = oh; | |
3512 | ||
3513 | error = omap_hwmod_init_regbits(dev, data, &sysc_fields); | |
3514 | if (error) | |
3515 | return error; | |
3516 | ||
3517 | error = omap_hwmod_init_reg_offs(dev, data, &rev_offs, | |
3518 | &sysc_offs, &syss_offs); | |
3519 | if (error) | |
3520 | return error; | |
3521 | ||
3522 | error = omap_hwmod_init_sysc_flags(dev, data, &sysc_flags); | |
3523 | if (error) | |
3524 | return error; | |
3525 | ||
3526 | error = omap_hwmod_init_idlemodes(dev, data, &idlemodes); | |
3527 | if (error) | |
3528 | return error; | |
3529 | ||
3530 | if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) | |
3531 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
3532 | if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
3533 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3534 | ||
a8844306 TL |
3535 | error = omap_hwmod_check_module(dev, oh, data, sysc_fields, |
3536 | rev_offs, sysc_offs, syss_offs, | |
3537 | sysc_flags, idlemodes); | |
3538 | if (!error) | |
3539 | return error; | |
8c879705 TL |
3540 | |
3541 | return omap_hwmod_allocate_module(dev, oh, data, sysc_fields, | |
3542 | rev_offs, sysc_offs, syss_offs, | |
3543 | sysc_flags, idlemodes); | |
3544 | } | |
3545 | ||
8dd6666f LV |
3546 | /** |
3547 | * omap_hwmod_setup_earlycon_flags - set up flags for early console | |
3548 | * | |
3549 | * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as | |
3550 | * early concole so that hwmod core doesn't reset and keep it in idle | |
3551 | * that specific uart. | |
3552 | */ | |
3553 | #ifdef CONFIG_SERIAL_EARLYCON | |
3554 | static void __init omap_hwmod_setup_earlycon_flags(void) | |
3555 | { | |
3556 | struct device_node *np; | |
3557 | struct omap_hwmod *oh; | |
3558 | const char *uart; | |
3559 | ||
3560 | np = of_find_node_by_path("/chosen"); | |
3561 | if (np) { | |
3562 | uart = of_get_property(np, "stdout-path", NULL); | |
3563 | if (uart) { | |
3564 | np = of_find_node_by_path(uart); | |
3565 | if (np) { | |
3566 | uart = of_get_property(np, "ti,hwmods", NULL); | |
3567 | oh = omap_hwmod_lookup(uart); | |
15618256 TL |
3568 | if (!oh) { |
3569 | uart = of_get_property(np->parent, | |
3570 | "ti,hwmods", | |
3571 | NULL); | |
3572 | oh = omap_hwmod_lookup(uart); | |
3573 | } | |
8dd6666f LV |
3574 | if (oh) |
3575 | oh->flags |= DEBUG_OMAPUART_FLAGS; | |
3576 | } | |
3577 | } | |
3578 | } | |
3579 | } | |
3580 | #endif | |
3581 | ||
63c85238 | 3582 | /** |
381d033a | 3583 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3584 | * |
381d033a PW |
3585 | * Initialize and set up all IP blocks registered with the hwmod code. |
3586 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3587 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3588 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3589 | */ |
550c8092 | 3590 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3591 | { |
381d033a | 3592 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3593 | |
381d033a | 3594 | omap_hwmod_for_each(_init, NULL); |
8dd6666f LV |
3595 | #ifdef CONFIG_SERIAL_EARLYCON |
3596 | omap_hwmod_setup_earlycon_flags(); | |
3597 | #endif | |
2092e5cc | 3598 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3599 | |
3600 | return 0; | |
3601 | } | |
8dd5ea72 | 3602 | omap_postcore_initcall(omap_hwmod_setup_all); |
63c85238 | 3603 | |
63c85238 PW |
3604 | /** |
3605 | * omap_hwmod_enable - enable an omap_hwmod | |
3606 | * @oh: struct omap_hwmod * | |
3607 | * | |
74ff3a68 | 3608 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3609 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3610 | */ | |
3611 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3612 | { | |
3613 | int r; | |
dc6d1cda | 3614 | unsigned long flags; |
63c85238 PW |
3615 | |
3616 | if (!oh) | |
3617 | return -EINVAL; | |
3618 | ||
dc6d1cda PW |
3619 | spin_lock_irqsave(&oh->_lock, flags); |
3620 | r = _enable(oh); | |
3621 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3622 | |
3623 | return r; | |
3624 | } | |
3625 | ||
3626 | /** | |
3627 | * omap_hwmod_idle - idle an omap_hwmod | |
3628 | * @oh: struct omap_hwmod * | |
3629 | * | |
74ff3a68 | 3630 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3631 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3632 | */ | |
3633 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3634 | { | |
6da23358 | 3635 | int r; |
dc6d1cda PW |
3636 | unsigned long flags; |
3637 | ||
63c85238 PW |
3638 | if (!oh) |
3639 | return -EINVAL; | |
3640 | ||
dc6d1cda | 3641 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3642 | r = _idle(oh); |
dc6d1cda | 3643 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3644 | |
6da23358 | 3645 | return r; |
63c85238 PW |
3646 | } |
3647 | ||
3648 | /** | |
3649 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3650 | * @oh: struct omap_hwmod * | |
3651 | * | |
74ff3a68 | 3652 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3653 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3654 | * the return value from _shutdown(). | |
3655 | */ | |
3656 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3657 | { | |
6da23358 | 3658 | int r; |
dc6d1cda PW |
3659 | unsigned long flags; |
3660 | ||
63c85238 PW |
3661 | if (!oh) |
3662 | return -EINVAL; | |
3663 | ||
dc6d1cda | 3664 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3665 | r = _shutdown(oh); |
dc6d1cda | 3666 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3667 | |
6da23358 | 3668 | return r; |
63c85238 PW |
3669 | } |
3670 | ||
5e8370f1 PW |
3671 | /* |
3672 | * IP block data retrieval functions | |
3673 | */ | |
3674 | ||
63c85238 PW |
3675 | /** |
3676 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3677 | * @oh: struct omap_hwmod * | |
3678 | * | |
3679 | * Return the powerdomain pointer associated with the OMAP module | |
3680 | * @oh's main clock. If @oh does not have a main clk, return the | |
3681 | * powerdomain associated with the interface clock associated with the | |
3682 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3683 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3684 | * success. | |
3685 | */ | |
3686 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3687 | { | |
3688 | struct clk *c; | |
2d6141ba | 3689 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3690 | struct clockdomain *clkdm; |
f5dd3bb5 | 3691 | struct clk_hw_omap *clk; |
63c85238 PW |
3692 | |
3693 | if (!oh) | |
3694 | return NULL; | |
3695 | ||
f5dd3bb5 RN |
3696 | if (oh->clkdm) |
3697 | return oh->clkdm->pwrdm.ptr; | |
3698 | ||
63c85238 PW |
3699 | if (oh->_clk) { |
3700 | c = oh->_clk; | |
3701 | } else { | |
2d6141ba PW |
3702 | oi = _find_mpu_rt_port(oh); |
3703 | if (!oi) | |
63c85238 | 3704 | return NULL; |
2d6141ba | 3705 | c = oi->_clk; |
63c85238 PW |
3706 | } |
3707 | ||
f5dd3bb5 RN |
3708 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3709 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3710 | if (!clkdm) |
d5647c18 TG |
3711 | return NULL; |
3712 | ||
f5dd3bb5 | 3713 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3714 | } |
3715 | ||
db2a60bf PW |
3716 | /** |
3717 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3718 | * @oh: struct omap_hwmod * | |
3719 | * | |
3720 | * Returns the virtual address corresponding to the beginning of the | |
3721 | * module's register target, in the address range that is intended to | |
3722 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3723 | * upon error. | |
3724 | */ | |
3725 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3726 | { | |
3727 | if (!oh) | |
3728 | return NULL; | |
3729 | ||
3730 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3731 | return NULL; | |
3732 | ||
3733 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3734 | return NULL; | |
3735 | ||
3736 | return oh->_mpu_rt_va; | |
3737 | } | |
3738 | ||
63c85238 PW |
3739 | /* |
3740 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3741 | * for context save/restore operations? | |
3742 | */ | |
3743 | ||
63c85238 PW |
3744 | /** |
3745 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3746 | * @oh: struct omap_hwmod * | |
3747 | * | |
3748 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3749 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3750 | * this IP block if it has dynamic mux entries. Eventually this | |
3751 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3752 | * wakeup events from the module. Does not set any wakeup routing | |
3753 | * registers beyond this point - if the module is to wake up any other | |
3754 | * module or subsystem, that must be set separately. Called by | |
3755 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3756 | */ |
3757 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3758 | { | |
dc6d1cda | 3759 | unsigned long flags; |
5a7ddcbd | 3760 | u32 v; |
dc6d1cda | 3761 | |
dc6d1cda | 3762 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3763 | |
3764 | if (oh->class->sysc && | |
3765 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3766 | v = oh->_sysc_cache; | |
3767 | _enable_wakeup(oh, &v); | |
3768 | _write_sysconfig(v, oh); | |
3769 | } | |
3770 | ||
dc6d1cda | 3771 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3772 | |
3773 | return 0; | |
3774 | } | |
3775 | ||
3776 | /** | |
3777 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3778 | * @oh: struct omap_hwmod * | |
3779 | * | |
3780 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3781 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3782 | * events for this IP block if it has dynamic mux entries. Eventually | |
3783 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3784 | * wakeup events from the module. Does not set any wakeup routing | |
3785 | * registers beyond this point - if the module is to wake up any other | |
3786 | * module or subsystem, that must be set separately. Called by | |
3787 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3788 | */ |
3789 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3790 | { | |
dc6d1cda | 3791 | unsigned long flags; |
5a7ddcbd | 3792 | u32 v; |
dc6d1cda | 3793 | |
dc6d1cda | 3794 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3795 | |
3796 | if (oh->class->sysc && | |
3797 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3798 | v = oh->_sysc_cache; | |
3799 | _disable_wakeup(oh, &v); | |
3800 | _write_sysconfig(v, oh); | |
3801 | } | |
3802 | ||
dc6d1cda | 3803 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3804 | |
3805 | return 0; | |
3806 | } | |
43b40992 | 3807 | |
aee48e3c PW |
3808 | /** |
3809 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3810 | * contained in the hwmod module. | |
3811 | * @oh: struct omap_hwmod * | |
3812 | * @name: name of the reset line to lookup and assert | |
3813 | * | |
3814 | * Some IP like dsp, ipu or iva contain processor that require | |
3815 | * an HW reset line to be assert / deassert in order to enable fully | |
3816 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3817 | * yet supported on this OMAP; otherwise, passes along the return value | |
3818 | * from _assert_hardreset(). | |
3819 | */ | |
3820 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3821 | { | |
3822 | int ret; | |
dc6d1cda | 3823 | unsigned long flags; |
aee48e3c PW |
3824 | |
3825 | if (!oh) | |
3826 | return -EINVAL; | |
3827 | ||
dc6d1cda | 3828 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3829 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3830 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3831 | |
3832 | return ret; | |
3833 | } | |
3834 | ||
3835 | /** | |
3836 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3837 | * contained in the hwmod module. | |
3838 | * @oh: struct omap_hwmod * | |
3839 | * @name: name of the reset line to look up and deassert | |
3840 | * | |
3841 | * Some IP like dsp, ipu or iva contain processor that require | |
3842 | * an HW reset line to be assert / deassert in order to enable fully | |
3843 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3844 | * yet supported on this OMAP; otherwise, passes along the return value | |
3845 | * from _deassert_hardreset(). | |
3846 | */ | |
3847 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3848 | { | |
3849 | int ret; | |
dc6d1cda | 3850 | unsigned long flags; |
aee48e3c PW |
3851 | |
3852 | if (!oh) | |
3853 | return -EINVAL; | |
3854 | ||
dc6d1cda | 3855 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3856 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3857 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3858 | |
3859 | return ret; | |
3860 | } | |
3861 | ||
43b40992 PW |
3862 | /** |
3863 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3864 | * @classname: struct omap_hwmod_class name to search for | |
3865 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3866 | * @user: arbitrary context data to pass to the callback function | |
3867 | * | |
ce35b244 BC |
3868 | * For each omap_hwmod of class @classname, call @fn. |
3869 | * If the callback function returns something other than | |
43b40992 PW |
3870 | * zero, the iterator is terminated, and the callback function's return |
3871 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3872 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3873 | */ | |
3874 | int omap_hwmod_for_each_by_class(const char *classname, | |
3875 | int (*fn)(struct omap_hwmod *oh, | |
3876 | void *user), | |
3877 | void *user) | |
3878 | { | |
3879 | struct omap_hwmod *temp_oh; | |
3880 | int ret = 0; | |
3881 | ||
3882 | if (!classname || !fn) | |
3883 | return -EINVAL; | |
3884 | ||
3885 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3886 | __func__, classname); | |
3887 | ||
43b40992 PW |
3888 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3889 | if (!strcmp(temp_oh->class->name, classname)) { | |
3890 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3891 | __func__, temp_oh->name); | |
3892 | ret = (*fn)(temp_oh, user); | |
3893 | if (ret) | |
3894 | break; | |
3895 | } | |
3896 | } | |
3897 | ||
43b40992 PW |
3898 | if (ret) |
3899 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3900 | __func__, ret); | |
3901 | ||
3902 | return ret; | |
3903 | } | |
3904 | ||
2092e5cc PW |
3905 | /** |
3906 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3907 | * @oh: struct omap_hwmod * | |
3908 | * @state: state that _setup() should leave the hwmod in | |
3909 | * | |
550c8092 | 3910 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3911 | * (called by omap_hwmod_setup_*()). See also the documentation |
3912 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3913 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3914 | * in the wrong state. | |
2092e5cc PW |
3915 | */ |
3916 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3917 | { | |
3918 | int ret; | |
dc6d1cda | 3919 | unsigned long flags; |
2092e5cc PW |
3920 | |
3921 | if (!oh) | |
3922 | return -EINVAL; | |
3923 | ||
3924 | if (state != _HWMOD_STATE_DISABLED && | |
3925 | state != _HWMOD_STATE_ENABLED && | |
3926 | state != _HWMOD_STATE_IDLE) | |
3927 | return -EINVAL; | |
3928 | ||
dc6d1cda | 3929 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3930 | |
3931 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3932 | ret = -EINVAL; | |
3933 | goto ohsps_unlock; | |
3934 | } | |
3935 | ||
3936 | oh->_postsetup_state = state; | |
3937 | ret = 0; | |
3938 | ||
3939 | ohsps_unlock: | |
dc6d1cda | 3940 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3941 | |
3942 | return ret; | |
3943 | } | |
c80705aa KH |
3944 | |
3945 | /** | |
3946 | * omap_hwmod_get_context_loss_count - get lost context count | |
3947 | * @oh: struct omap_hwmod * | |
3948 | * | |
e6d3a8b0 RN |
3949 | * Returns the context loss count of associated @oh |
3950 | * upon success, or zero if no context loss data is available. | |
c80705aa | 3951 | * |
e6d3a8b0 RN |
3952 | * On OMAP4, this queries the per-hwmod context loss register, |
3953 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
3954 | * enclosing powerdomain context loss count. | |
c80705aa | 3955 | */ |
fc013873 | 3956 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3957 | { |
3958 | struct powerdomain *pwrdm; | |
3959 | int ret = 0; | |
3960 | ||
e6d3a8b0 RN |
3961 | if (soc_ops.get_context_lost) |
3962 | return soc_ops.get_context_lost(oh); | |
3963 | ||
c80705aa KH |
3964 | pwrdm = omap_hwmod_get_pwrdm(oh); |
3965 | if (pwrdm) | |
3966 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3967 | ||
3968 | return ret; | |
3969 | } | |
43b01643 | 3970 | |
9ebfd285 KH |
3971 | /** |
3972 | * omap_hwmod_init - initialize the hwmod code | |
3973 | * | |
3974 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3975 | * currently-booted SoC. Intended to be called once during kernel init | |
3976 | * before any hwmods are registered. No return value. | |
3977 | */ | |
3978 | void __init omap_hwmod_init(void) | |
3979 | { | |
ff4ae5d9 | 3980 | if (cpu_is_omap24xx()) { |
9002e921 | 3981 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
ff4ae5d9 PW |
3982 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3983 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3984 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3985 | } else if (cpu_is_omap34xx()) { | |
9002e921 | 3986 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
b8249cf2 KH |
3987 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3988 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3989 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 3990 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 3991 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
3992 | soc_ops.enable_module = _omap4_enable_module; |
3993 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 3994 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
3995 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3996 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
3997 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 3998 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
3999 | soc_ops.update_context_lost = _omap4_update_context_lost; |
4000 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
9fabc1a2 | 4001 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
70f05be3 | 4002 | soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; |
0f3ccb24 TL |
4003 | } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || |
4004 | soc_is_am43xx()) { | |
c8b428a5 AM |
4005 | soc_ops.enable_module = _omap4_enable_module; |
4006 | soc_ops.disable_module = _omap4_disable_module; | |
4007 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
409d7063 | 4008 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
1688bf19 | 4009 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; |
a5bf00cd | 4010 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; |
1688bf19 | 4011 | soc_ops.init_clkdm = _init_clkdm; |
9fabc1a2 | 4012 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
2b96be3d | 4013 | soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; |
8f6aa8ee KH |
4014 | } else { |
4015 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4016 | } |
4017 | ||
70f05be3 TK |
4018 | _init_clkctrl_providers(); |
4019 | ||
9ebfd285 KH |
4020 | inited = true; |
4021 | } | |
68c9a95e TL |
4022 | |
4023 | /** | |
4024 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4025 | * @oh: struct omap_hwmod * | |
4026 | * | |
4027 | * Returns the main clock name assocated with @oh upon success, | |
4028 | * or NULL if @oh is NULL. | |
4029 | */ | |
4030 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4031 | { | |
4032 | if (!oh) | |
4033 | return NULL; | |
4034 | ||
4035 | return oh->main_clk; | |
4036 | } |