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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
db2a60bf | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
63c85238 | 5 | * |
4788da26 PW |
6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
7 | * | |
8 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
9 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
10 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
74ff3a68 PW |
16 | * Introduction |
17 | * ------------ | |
18 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
19 | * IP blocks connected by interconnects. The IP blocks include | |
20 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
21 | * etc. Some of these devices, like the DSP, are created by TI; | |
22 | * others, like the SGX, largely originate from external vendors. In | |
23 | * TI's documentation, on-chip devices are referred to as "OMAP | |
24 | * modules." Some of these IP blocks are identical across several | |
25 | * OMAP versions. Others are revised frequently. | |
63c85238 | 26 | * |
74ff3a68 PW |
27 | * These OMAP modules are tied together by various interconnects. |
28 | * Most of the address and data flow between modules is via OCP-based | |
29 | * interconnects such as the L3 and L4 buses; but there are other | |
30 | * interconnects that distribute the hardware clock tree, handle idle | |
31 | * and reset signaling, supply power, and connect the modules to | |
32 | * various pads or balls on the OMAP package. | |
33 | * | |
34 | * OMAP hwmod provides a consistent way to describe the on-chip | |
35 | * hardware blocks and their integration into the rest of the chip. | |
36 | * This description can be automatically generated from the TI | |
37 | * hardware database. OMAP hwmod provides a standard, consistent API | |
38 | * to reset, enable, idle, and disable these hardware blocks. And | |
39 | * hwmod provides a way for other core code, such as the Linux device | |
40 | * code or the OMAP power management and address space mapping code, | |
41 | * to query the hardware database. | |
42 | * | |
43 | * Using hwmod | |
44 | * ----------- | |
45 | * Drivers won't call hwmod functions directly. That is done by the | |
46 | * omap_device code, and in rare occasions, by custom integration code | |
47 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
48 | * build a struct platform_device using omap_hwmod data, and that is | |
49 | * currently how hwmod data is communicated to drivers and to the | |
50 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
51 | * indirectly, via pm_runtime*() functions. | |
52 | * | |
53 | * From a layering perspective, here is where the OMAP hwmod code | |
54 | * fits into the kernel software stack: | |
55 | * | |
56 | * +-------------------------------+ | |
57 | * | Device driver code | | |
58 | * | (e.g., drivers/) | | |
59 | * +-------------------------------+ | |
60 | * | Linux driver model | | |
61 | * | (platform_device / | | |
62 | * | platform_driver data/code) | | |
63 | * +-------------------------------+ | |
64 | * | OMAP core-driver integration | | |
65 | * |(arch/arm/mach-omap2/devices.c)| | |
66 | * +-------------------------------+ | |
67 | * | omap_device code | | |
68 | * | (../plat-omap/omap_device.c) | | |
69 | * +-------------------------------+ | |
70 | * ----> | omap_hwmod code/data | <----- | |
71 | * | (../mach-omap2/omap_hwmod*) | | |
72 | * +-------------------------------+ | |
73 | * | OMAP clock/PRCM/register fns | | |
74 | * | (__raw_{read,write}l, clk*) | | |
75 | * +-------------------------------+ | |
76 | * | |
77 | * Device drivers should not contain any OMAP-specific code or data in | |
78 | * them. They should only contain code to operate the IP block that | |
79 | * the driver is responsible for. This is because these IP blocks can | |
80 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
81 | * other manufacturers; and drivers should be reusable across other | |
82 | * platforms. | |
83 | * | |
84 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
85 | * devices upon boot. The goal here is for the kernel to be | |
86 | * completely self-reliant and independent from bootloaders. This is | |
87 | * to ensure a repeatable configuration, both to ensure consistent | |
88 | * runtime behavior, and to make it easier for others to reproduce | |
89 | * bugs. | |
90 | * | |
91 | * OMAP module activity states | |
92 | * --------------------------- | |
93 | * The hwmod code considers modules to be in one of several activity | |
94 | * states. IP blocks start out in an UNKNOWN state, then once they | |
95 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
96 | * Once their clock names are resolved to clock pointers, the module | |
97 | * enters the CLKS_INITED state; and finally, once the module has been | |
98 | * reset and the integration registers programmed, the INITIALIZED state | |
99 | * is entered. The hwmod code will then place the module into either | |
100 | * the IDLE state to save power, or in the case of a critical system | |
101 | * module, the ENABLED state. | |
102 | * | |
103 | * OMAP core integration code can then call omap_hwmod*() functions | |
104 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
105 | * states, as needed. This is done during both the PM idle loop, and | |
106 | * in the OMAP core integration code's implementation of the PM runtime | |
107 | * functions. | |
108 | * | |
109 | * References | |
110 | * ---------- | |
111 | * This is a partial list. | |
63c85238 PW |
112 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
113 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
114 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
115 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
116 | * - Open Core Protocol Specification 2.2 | |
117 | * | |
118 | * To do: | |
119 | * - pin mux handling | |
120 | * - handle IO mapping | |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
63c85238 | 139 | |
6f8b7ff5 | 140 | #include <plat/common.h> |
ce491cf8 TL |
141 | #include <plat/cpu.h> |
142 | #include <plat/clockdomain.h> | |
143 | #include <plat/powerdomain.h> | |
144 | #include <plat/clock.h> | |
145 | #include <plat/omap_hwmod.h> | |
5365efbe | 146 | #include <plat/prcm.h> |
63c85238 PW |
147 | |
148 | #include "cm.h" | |
5365efbe | 149 | #include "prm.h" |
63c85238 | 150 | |
5365efbe BC |
151 | /* Maximum microseconds to wait for OMAP module to softreset */ |
152 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
153 | |
154 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 155 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
156 | |
157 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
158 | static LIST_HEAD(omap_hwmod_list); | |
159 | ||
160 | static DEFINE_MUTEX(omap_hwmod_mutex); | |
161 | ||
162 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ | |
163 | static struct omap_hwmod *mpu_oh; | |
164 | ||
165 | /* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ | |
166 | static u8 inited; | |
167 | ||
168 | ||
169 | /* Private functions */ | |
170 | ||
171 | /** | |
172 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
173 | * @oh: struct omap_hwmod * | |
174 | * | |
175 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
176 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
177 | * OCP_SYSCONFIG register or 0 upon success. | |
178 | */ | |
179 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
180 | { | |
43b40992 PW |
181 | if (!oh->class->sysc) { |
182 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
183 | return -EINVAL; |
184 | } | |
185 | ||
186 | /* XXX ensure module interface clock is up */ | |
187 | ||
cc7a1d2a | 188 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 189 | |
43b40992 | 190 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 191 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
196 | /** | |
197 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
198 | * @v: OCP_SYSCONFIG value to write | |
199 | * @oh: struct omap_hwmod * | |
200 | * | |
43b40992 PW |
201 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
202 | * one. No return value. | |
63c85238 PW |
203 | */ |
204 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
205 | { | |
43b40992 PW |
206 | if (!oh->class->sysc) { |
207 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
208 | return; |
209 | } | |
210 | ||
211 | /* XXX ensure module interface clock is up */ | |
212 | ||
213 | if (oh->_sysc_cache != v) { | |
214 | oh->_sysc_cache = v; | |
cc7a1d2a | 215 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
216 | } |
217 | } | |
218 | ||
219 | /** | |
220 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
221 | * @oh: struct omap_hwmod * | |
222 | * @standbymode: MIDLEMODE field bits | |
223 | * @v: pointer to register contents to modify | |
224 | * | |
225 | * Update the master standby mode bits in @v to be @standbymode for | |
226 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
227 | * upon error or 0 upon success. | |
228 | */ | |
229 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
230 | u32 *v) | |
231 | { | |
358f0e63 TG |
232 | u32 mstandby_mask; |
233 | u8 mstandby_shift; | |
234 | ||
43b40992 PW |
235 | if (!oh->class->sysc || |
236 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
237 | return -EINVAL; |
238 | ||
43b40992 PW |
239 | if (!oh->class->sysc->sysc_fields) { |
240 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
241 | return -EINVAL; |
242 | } | |
243 | ||
43b40992 | 244 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
245 | mstandby_mask = (0x3 << mstandby_shift); |
246 | ||
247 | *v &= ~mstandby_mask; | |
248 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
249 | |
250 | return 0; | |
251 | } | |
252 | ||
253 | /** | |
254 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
255 | * @oh: struct omap_hwmod * | |
256 | * @idlemode: SIDLEMODE field bits | |
257 | * @v: pointer to register contents to modify | |
258 | * | |
259 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
260 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
261 | * or 0 upon success. | |
262 | */ | |
263 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
264 | { | |
358f0e63 TG |
265 | u32 sidle_mask; |
266 | u8 sidle_shift; | |
267 | ||
43b40992 PW |
268 | if (!oh->class->sysc || |
269 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
270 | return -EINVAL; |
271 | ||
43b40992 PW |
272 | if (!oh->class->sysc->sysc_fields) { |
273 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
274 | return -EINVAL; |
275 | } | |
276 | ||
43b40992 | 277 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
278 | sidle_mask = (0x3 << sidle_shift); |
279 | ||
280 | *v &= ~sidle_mask; | |
281 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
282 | |
283 | return 0; | |
284 | } | |
285 | ||
286 | /** | |
287 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
288 | * @oh: struct omap_hwmod * | |
289 | * @clockact: CLOCKACTIVITY field bits | |
290 | * @v: pointer to register contents to modify | |
291 | * | |
292 | * Update the clockactivity mode bits in @v to be @clockact for the | |
293 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
294 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
295 | * success. | |
296 | */ | |
297 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
298 | { | |
358f0e63 TG |
299 | u32 clkact_mask; |
300 | u8 clkact_shift; | |
301 | ||
43b40992 PW |
302 | if (!oh->class->sysc || |
303 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
304 | return -EINVAL; |
305 | ||
43b40992 PW |
306 | if (!oh->class->sysc->sysc_fields) { |
307 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
308 | return -EINVAL; |
309 | } | |
310 | ||
43b40992 | 311 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
312 | clkact_mask = (0x3 << clkact_shift); |
313 | ||
314 | *v &= ~clkact_mask; | |
315 | *v |= clockact << clkact_shift; | |
63c85238 PW |
316 | |
317 | return 0; | |
318 | } | |
319 | ||
320 | /** | |
321 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
322 | * @oh: struct omap_hwmod * | |
323 | * @v: pointer to register contents to modify | |
324 | * | |
325 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
326 | * error or 0 upon success. | |
327 | */ | |
328 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
329 | { | |
358f0e63 TG |
330 | u32 softrst_mask; |
331 | ||
43b40992 PW |
332 | if (!oh->class->sysc || |
333 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
334 | return -EINVAL; |
335 | ||
43b40992 PW |
336 | if (!oh->class->sysc->sysc_fields) { |
337 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
338 | return -EINVAL; |
339 | } | |
340 | ||
43b40992 | 341 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
342 | |
343 | *v |= softrst_mask; | |
63c85238 PW |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
726072e5 PW |
348 | /** |
349 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
350 | * @oh: struct omap_hwmod * | |
351 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
352 | * @v: pointer to register contents to modify | |
353 | * | |
354 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
355 | * hwmod. The autoidle bit controls whether the module can gate | |
356 | * internal clocks automatically when it isn't doing anything; the | |
357 | * exact function of this bit varies on a per-module basis. This | |
358 | * function does not write to the hardware. Returns -EINVAL upon | |
359 | * error or 0 upon success. | |
360 | */ | |
361 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
362 | u32 *v) | |
363 | { | |
358f0e63 TG |
364 | u32 autoidle_mask; |
365 | u8 autoidle_shift; | |
366 | ||
43b40992 PW |
367 | if (!oh->class->sysc || |
368 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
369 | return -EINVAL; |
370 | ||
43b40992 PW |
371 | if (!oh->class->sysc->sysc_fields) { |
372 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
373 | return -EINVAL; |
374 | } | |
375 | ||
43b40992 | 376 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
358f0e63 TG |
377 | autoidle_mask = (0x3 << autoidle_shift); |
378 | ||
379 | *v &= ~autoidle_mask; | |
380 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
63c85238 PW |
385 | /** |
386 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
387 | * @oh: struct omap_hwmod * | |
388 | * | |
389 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
390 | * upon error or 0 upon success. | |
391 | */ | |
392 | static int _enable_wakeup(struct omap_hwmod *oh) | |
393 | { | |
358f0e63 | 394 | u32 v, wakeup_mask; |
63c85238 | 395 | |
43b40992 PW |
396 | if (!oh->class->sysc || |
397 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
398 | return -EINVAL; |
399 | ||
43b40992 PW |
400 | if (!oh->class->sysc->sysc_fields) { |
401 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
402 | return -EINVAL; |
403 | } | |
404 | ||
43b40992 | 405 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 406 | |
63c85238 | 407 | v = oh->_sysc_cache; |
358f0e63 | 408 | v |= wakeup_mask; |
63c85238 PW |
409 | _write_sysconfig(v, oh); |
410 | ||
411 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
412 | ||
413 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
414 | ||
415 | return 0; | |
416 | } | |
417 | ||
418 | /** | |
419 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
420 | * @oh: struct omap_hwmod * | |
421 | * | |
422 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
423 | * upon error or 0 upon success. | |
424 | */ | |
425 | static int _disable_wakeup(struct omap_hwmod *oh) | |
426 | { | |
358f0e63 | 427 | u32 v, wakeup_mask; |
63c85238 | 428 | |
43b40992 PW |
429 | if (!oh->class->sysc || |
430 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
431 | return -EINVAL; |
432 | ||
43b40992 PW |
433 | if (!oh->class->sysc->sysc_fields) { |
434 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
435 | return -EINVAL; |
436 | } | |
437 | ||
43b40992 | 438 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 439 | |
63c85238 | 440 | v = oh->_sysc_cache; |
358f0e63 | 441 | v &= ~wakeup_mask; |
63c85238 PW |
442 | _write_sysconfig(v, oh); |
443 | ||
444 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
445 | ||
446 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | /** | |
452 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
453 | * @oh: struct omap_hwmod * | |
454 | * | |
455 | * Prevent the hardware module @oh from entering idle while the | |
456 | * hardare module initiator @init_oh is active. Useful when a module | |
457 | * will be accessed by a particular initiator (e.g., if a module will | |
458 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
459 | * initiator and the module). Only applies to modules in smart-idle | |
460 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 461 | * clkdm_add_sleepdep() value upon success. |
63c85238 PW |
462 | */ |
463 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
464 | { | |
465 | if (!oh->_clk) | |
466 | return -EINVAL; | |
467 | ||
55ed9694 | 468 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
469 | } |
470 | ||
471 | /** | |
472 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
473 | * @oh: struct omap_hwmod * | |
474 | * | |
475 | * Allow the hardware module @oh to enter idle while the hardare | |
476 | * module initiator @init_oh is active. Useful when a module will not | |
477 | * be accessed by a particular initiator (e.g., if a module will not | |
478 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
479 | * initiator and the module). Only applies to modules in smart-idle | |
480 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 481 | * clkdm_del_sleepdep() value upon success. |
63c85238 PW |
482 | */ |
483 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
484 | { | |
485 | if (!oh->_clk) | |
486 | return -EINVAL; | |
487 | ||
55ed9694 | 488 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
489 | } |
490 | ||
491 | /** | |
492 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
493 | * @oh: struct omap_hwmod * | |
494 | * | |
495 | * Called from _init_clocks(). Populates the @oh _clk (main | |
496 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
497 | * success or -EINVAL on error. | |
498 | */ | |
499 | static int _init_main_clk(struct omap_hwmod *oh) | |
500 | { | |
63c85238 PW |
501 | int ret = 0; |
502 | ||
50ebdac2 | 503 | if (!oh->main_clk) |
63c85238 PW |
504 | return 0; |
505 | ||
63403384 | 506 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 507 | if (!oh->_clk) { |
20383d82 BC |
508 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
509 | oh->name, oh->main_clk); | |
63403384 | 510 | return -EINVAL; |
dc75925d | 511 | } |
63c85238 | 512 | |
63403384 BC |
513 | if (!oh->_clk->clkdm) |
514 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
515 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 516 | |
63c85238 PW |
517 | return ret; |
518 | } | |
519 | ||
520 | /** | |
887adeac | 521 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
522 | * @oh: struct omap_hwmod * |
523 | * | |
524 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
525 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
526 | */ | |
527 | static int _init_interface_clks(struct omap_hwmod *oh) | |
528 | { | |
63c85238 PW |
529 | struct clk *c; |
530 | int i; | |
531 | int ret = 0; | |
532 | ||
533 | if (oh->slaves_cnt == 0) | |
534 | return 0; | |
535 | ||
682fdc96 BC |
536 | for (i = 0; i < oh->slaves_cnt; i++) { |
537 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
538 | ||
50ebdac2 | 539 | if (!os->clk) |
63c85238 PW |
540 | continue; |
541 | ||
50ebdac2 | 542 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 543 | if (!c) { |
20383d82 BC |
544 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
545 | oh->name, os->clk); | |
63c85238 | 546 | ret = -EINVAL; |
dc75925d | 547 | } |
63c85238 PW |
548 | os->_clk = c; |
549 | } | |
550 | ||
551 | return ret; | |
552 | } | |
553 | ||
554 | /** | |
555 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
556 | * @oh: struct omap_hwmod * | |
557 | * | |
558 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
559 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
560 | */ | |
561 | static int _init_opt_clks(struct omap_hwmod *oh) | |
562 | { | |
563 | struct omap_hwmod_opt_clk *oc; | |
564 | struct clk *c; | |
565 | int i; | |
566 | int ret = 0; | |
567 | ||
568 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 569 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 570 | if (!c) { |
20383d82 BC |
571 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
572 | oh->name, oc->clk); | |
63c85238 | 573 | ret = -EINVAL; |
dc75925d | 574 | } |
63c85238 PW |
575 | oc->_clk = c; |
576 | } | |
577 | ||
578 | return ret; | |
579 | } | |
580 | ||
581 | /** | |
582 | * _enable_clocks - enable hwmod main clock and interface clocks | |
583 | * @oh: struct omap_hwmod * | |
584 | * | |
585 | * Enables all clocks necessary for register reads and writes to succeed | |
586 | * on the hwmod @oh. Returns 0. | |
587 | */ | |
588 | static int _enable_clocks(struct omap_hwmod *oh) | |
589 | { | |
63c85238 PW |
590 | int i; |
591 | ||
592 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
593 | ||
4d3ae5a9 | 594 | if (oh->_clk) |
63c85238 PW |
595 | clk_enable(oh->_clk); |
596 | ||
597 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
598 | for (i = 0; i < oh->slaves_cnt; i++) { |
599 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
600 | struct clk *c = os->_clk; |
601 | ||
4d3ae5a9 | 602 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
603 | clk_enable(c); |
604 | } | |
605 | } | |
606 | ||
607 | /* The opt clocks are controlled by the device driver. */ | |
608 | ||
609 | return 0; | |
610 | } | |
611 | ||
612 | /** | |
613 | * _disable_clocks - disable hwmod main clock and interface clocks | |
614 | * @oh: struct omap_hwmod * | |
615 | * | |
616 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
617 | */ | |
618 | static int _disable_clocks(struct omap_hwmod *oh) | |
619 | { | |
63c85238 PW |
620 | int i; |
621 | ||
622 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
623 | ||
4d3ae5a9 | 624 | if (oh->_clk) |
63c85238 PW |
625 | clk_disable(oh->_clk); |
626 | ||
627 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
628 | for (i = 0; i < oh->slaves_cnt; i++) { |
629 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
630 | struct clk *c = os->_clk; |
631 | ||
4d3ae5a9 | 632 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
633 | clk_disable(c); |
634 | } | |
635 | } | |
636 | ||
637 | /* The opt clocks are controlled by the device driver. */ | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
96835af9 BC |
642 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
643 | { | |
644 | struct omap_hwmod_opt_clk *oc; | |
645 | int i; | |
646 | ||
647 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
648 | ||
649 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
650 | if (oc->_clk) { | |
651 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
652 | oc->_clk->name); | |
653 | clk_enable(oc->_clk); | |
654 | } | |
655 | } | |
656 | ||
657 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
658 | { | |
659 | struct omap_hwmod_opt_clk *oc; | |
660 | int i; | |
661 | ||
662 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
663 | ||
664 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
665 | if (oc->_clk) { | |
666 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
667 | oc->_clk->name); | |
668 | clk_disable(oc->_clk); | |
669 | } | |
670 | } | |
671 | ||
63c85238 PW |
672 | /** |
673 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
674 | * @oh: struct omap_hwmod * | |
675 | * | |
676 | * Returns the array index of the OCP slave port that the MPU | |
677 | * addresses the device on, or -EINVAL upon error or not found. | |
678 | */ | |
679 | static int _find_mpu_port_index(struct omap_hwmod *oh) | |
680 | { | |
63c85238 PW |
681 | int i; |
682 | int found = 0; | |
683 | ||
684 | if (!oh || oh->slaves_cnt == 0) | |
685 | return -EINVAL; | |
686 | ||
682fdc96 BC |
687 | for (i = 0; i < oh->slaves_cnt; i++) { |
688 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
689 | ||
63c85238 PW |
690 | if (os->user & OCP_USER_MPU) { |
691 | found = 1; | |
692 | break; | |
693 | } | |
694 | } | |
695 | ||
696 | if (found) | |
697 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
698 | oh->name, i); | |
699 | else | |
700 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
701 | oh->name); | |
702 | ||
703 | return (found) ? i : -EINVAL; | |
704 | } | |
705 | ||
706 | /** | |
707 | * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU | |
708 | * @oh: struct omap_hwmod * | |
709 | * | |
710 | * Return the virtual address of the base of the register target of | |
711 | * device @oh, or NULL on error. | |
712 | */ | |
713 | static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |
714 | { | |
715 | struct omap_hwmod_ocp_if *os; | |
716 | struct omap_hwmod_addr_space *mem; | |
717 | int i; | |
718 | int found = 0; | |
986a13f5 | 719 | void __iomem *va_start; |
63c85238 PW |
720 | |
721 | if (!oh || oh->slaves_cnt == 0) | |
722 | return NULL; | |
723 | ||
682fdc96 | 724 | os = oh->slaves[index]; |
63c85238 PW |
725 | |
726 | for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { | |
727 | if (mem->flags & ADDR_TYPE_RT) { | |
728 | found = 1; | |
729 | break; | |
730 | } | |
731 | } | |
732 | ||
986a13f5 TL |
733 | if (found) { |
734 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
735 | if (!va_start) { | |
736 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
737 | return NULL; | |
738 | } | |
63c85238 | 739 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
986a13f5 TL |
740 | oh->name, va_start); |
741 | } else { | |
63c85238 PW |
742 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
743 | oh->name); | |
986a13f5 | 744 | } |
63c85238 | 745 | |
986a13f5 | 746 | return (found) ? va_start : NULL; |
63c85238 PW |
747 | } |
748 | ||
749 | /** | |
74ff3a68 | 750 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
751 | * @oh: struct omap_hwmod * |
752 | * | |
753 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
754 | * idle; otherwise, configure it for smart-idle. If module is marked | |
755 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
756 | * otherwise, configure it for smart-standby. No return value. | |
757 | */ | |
74ff3a68 | 758 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 759 | { |
43b40992 | 760 | u8 idlemode, sf; |
63c85238 PW |
761 | u32 v; |
762 | ||
43b40992 | 763 | if (!oh->class->sysc) |
63c85238 PW |
764 | return; |
765 | ||
766 | v = oh->_sysc_cache; | |
43b40992 | 767 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 768 | |
43b40992 | 769 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
770 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
771 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
772 | _set_slave_idlemode(oh, idlemode, &v); | |
773 | } | |
774 | ||
43b40992 | 775 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
776 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
777 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
778 | _set_master_standbymode(oh, idlemode, &v); | |
779 | } | |
780 | ||
a16b1f7f PW |
781 | /* |
782 | * XXX The clock framework should handle this, by | |
783 | * calling into this code. But this must wait until the | |
784 | * clock structures are tagged with omap_hwmod entries | |
785 | */ | |
43b40992 PW |
786 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
787 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
788 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 PW |
789 | |
790 | _write_sysconfig(v, oh); | |
9980ce53 RN |
791 | |
792 | /* If slave is in SMARTIDLE, also enable wakeup */ | |
793 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
794 | _enable_wakeup(oh); | |
78f26e87 HH |
795 | |
796 | /* | |
797 | * Set the autoidle bit only after setting the smartidle bit | |
798 | * Setting this will not have any impact on the other modules. | |
799 | */ | |
800 | if (sf & SYSC_HAS_AUTOIDLE) { | |
801 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
802 | 0 : 1; | |
803 | _set_module_autoidle(oh, idlemode, &v); | |
804 | _write_sysconfig(v, oh); | |
805 | } | |
63c85238 PW |
806 | } |
807 | ||
808 | /** | |
74ff3a68 | 809 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
810 | * @oh: struct omap_hwmod * |
811 | * | |
812 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
813 | * idle; otherwise, configure it for smart-idle. If module is marked | |
814 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
815 | * configure it for smart-standby. No return value. | |
816 | */ | |
74ff3a68 | 817 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 818 | { |
43b40992 | 819 | u8 idlemode, sf; |
63c85238 PW |
820 | u32 v; |
821 | ||
43b40992 | 822 | if (!oh->class->sysc) |
63c85238 PW |
823 | return; |
824 | ||
825 | v = oh->_sysc_cache; | |
43b40992 | 826 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 827 | |
43b40992 | 828 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
829 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
830 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
831 | _set_slave_idlemode(oh, idlemode, &v); | |
832 | } | |
833 | ||
43b40992 | 834 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
835 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
836 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
837 | _set_master_standbymode(oh, idlemode, &v); | |
838 | } | |
839 | ||
840 | _write_sysconfig(v, oh); | |
841 | } | |
842 | ||
843 | /** | |
74ff3a68 | 844 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
845 | * @oh: struct omap_hwmod * |
846 | * | |
847 | * Force the module into slave idle and master suspend. No return | |
848 | * value. | |
849 | */ | |
74ff3a68 | 850 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
851 | { |
852 | u32 v; | |
43b40992 | 853 | u8 sf; |
63c85238 | 854 | |
43b40992 | 855 | if (!oh->class->sysc) |
63c85238 PW |
856 | return; |
857 | ||
858 | v = oh->_sysc_cache; | |
43b40992 | 859 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 860 | |
43b40992 | 861 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
862 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
863 | ||
43b40992 | 864 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
865 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
866 | ||
43b40992 | 867 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 868 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
869 | |
870 | _write_sysconfig(v, oh); | |
871 | } | |
872 | ||
873 | /** | |
874 | * _lookup - find an omap_hwmod by name | |
875 | * @name: find an omap_hwmod by name | |
876 | * | |
877 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
878 | * Caller must hold omap_hwmod_mutex. | |
879 | */ | |
880 | static struct omap_hwmod *_lookup(const char *name) | |
881 | { | |
882 | struct omap_hwmod *oh, *temp_oh; | |
883 | ||
884 | oh = NULL; | |
885 | ||
886 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
887 | if (!strcmp(name, temp_oh->name)) { | |
888 | oh = temp_oh; | |
889 | break; | |
890 | } | |
891 | } | |
892 | ||
893 | return oh; | |
894 | } | |
895 | ||
896 | /** | |
897 | * _init_clocks - clk_get() all clocks associated with this hwmod | |
898 | * @oh: struct omap_hwmod * | |
97d60162 | 899 | * @data: not used; pass NULL |
63c85238 PW |
900 | * |
901 | * Called by omap_hwmod_late_init() (after omap2_clk_init()). | |
12b1fdb4 KH |
902 | * Resolves all clock names embedded in the hwmod. Returns -EINVAL if |
903 | * the omap_hwmod has not yet been registered or if the clocks have | |
904 | * already been initialized, 0 on success, or a non-zero error on | |
905 | * failure. | |
63c85238 | 906 | */ |
97d60162 | 907 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
908 | { |
909 | int ret = 0; | |
910 | ||
911 | if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) | |
912 | return -EINVAL; | |
913 | ||
914 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
915 | ||
916 | ret |= _init_main_clk(oh); | |
917 | ret |= _init_interface_clks(oh); | |
918 | ret |= _init_opt_clks(oh); | |
919 | ||
f5c1f84b BC |
920 | if (!ret) |
921 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
63c85238 | 922 | |
f5c1f84b | 923 | return 0; |
63c85238 PW |
924 | } |
925 | ||
926 | /** | |
927 | * _wait_target_ready - wait for a module to leave slave idle | |
928 | * @oh: struct omap_hwmod * | |
929 | * | |
930 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
931 | * does not have an IDLEST bit or if the module successfully leaves | |
932 | * slave idle; otherwise, pass along the return value of the | |
933 | * appropriate *_cm_wait_module_ready() function. | |
934 | */ | |
935 | static int _wait_target_ready(struct omap_hwmod *oh) | |
936 | { | |
937 | struct omap_hwmod_ocp_if *os; | |
938 | int ret; | |
939 | ||
940 | if (!oh) | |
941 | return -EINVAL; | |
942 | ||
943 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
944 | return 0; | |
945 | ||
682fdc96 | 946 | os = oh->slaves[oh->_mpu_port_index]; |
63c85238 | 947 | |
33f7ec81 | 948 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
949 | return 0; |
950 | ||
951 | /* XXX check module SIDLEMODE */ | |
952 | ||
953 | /* XXX check clock enable states */ | |
954 | ||
955 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
956 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
957 | oh->prcm.omap2.idlest_reg_id, | |
958 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 959 | } else if (cpu_is_omap44xx()) { |
9a23dfe1 | 960 | ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); |
63c85238 PW |
961 | } else { |
962 | BUG(); | |
963 | }; | |
964 | ||
965 | return ret; | |
966 | } | |
967 | ||
5365efbe BC |
968 | /** |
969 | * _lookup_hardreset - return the register bit shift for this hwmod/reset line | |
970 | * @oh: struct omap_hwmod * | |
971 | * @name: name of the reset line in the context of this hwmod | |
972 | * | |
973 | * Return the bit position of the reset line that match the | |
974 | * input name. Return -ENOENT if not found. | |
975 | */ | |
976 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) | |
977 | { | |
978 | int i; | |
979 | ||
980 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
981 | const char *rst_line = oh->rst_lines[i].name; | |
982 | if (!strcmp(rst_line, name)) { | |
983 | u8 shift = oh->rst_lines[i].rst_shift; | |
984 | pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", | |
985 | oh->name, rst_line, shift); | |
986 | ||
987 | return shift; | |
988 | } | |
989 | } | |
990 | ||
991 | return -ENOENT; | |
992 | } | |
993 | ||
994 | /** | |
995 | * _assert_hardreset - assert the HW reset line of submodules | |
996 | * contained in the hwmod module. | |
997 | * @oh: struct omap_hwmod * | |
998 | * @name: name of the reset line to lookup and assert | |
999 | * | |
1000 | * Some IP like dsp, ipu or iva contain processor that require | |
1001 | * an HW reset line to be assert / deassert in order to enable fully | |
1002 | * the IP. | |
1003 | */ | |
1004 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1005 | { | |
1006 | u8 shift; | |
1007 | ||
1008 | if (!oh) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | shift = _lookup_hardreset(oh, name); | |
1012 | if (IS_ERR_VALUE(shift)) | |
1013 | return shift; | |
1014 | ||
1015 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1016 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
1017 | shift); | |
1018 | else if (cpu_is_omap44xx()) | |
1019 | return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
1020 | shift); | |
1021 | else | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1027 | * in the hwmod module. | |
1028 | * @oh: struct omap_hwmod * | |
1029 | * @name: name of the reset line to look up and deassert | |
1030 | * | |
1031 | * Some IP like dsp, ipu or iva contain processor that require | |
1032 | * an HW reset line to be assert / deassert in order to enable fully | |
1033 | * the IP. | |
1034 | */ | |
1035 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1036 | { | |
1037 | u8 shift; | |
1038 | int r; | |
1039 | ||
1040 | if (!oh) | |
1041 | return -EINVAL; | |
1042 | ||
1043 | shift = _lookup_hardreset(oh, name); | |
1044 | if (IS_ERR_VALUE(shift)) | |
1045 | return shift; | |
1046 | ||
1047 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1048 | r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
1049 | shift); | |
1050 | else if (cpu_is_omap44xx()) | |
1051 | r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
1052 | shift); | |
1053 | else | |
1054 | return -EINVAL; | |
1055 | ||
1056 | if (r == -EBUSY) | |
1057 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); | |
1058 | ||
1059 | return r; | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * _read_hardreset - read the HW reset line state of submodules | |
1064 | * contained in the hwmod module | |
1065 | * @oh: struct omap_hwmod * | |
1066 | * @name: name of the reset line to look up and read | |
1067 | * | |
1068 | * Return the state of the reset line. | |
1069 | */ | |
1070 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1071 | { | |
1072 | u8 shift; | |
1073 | ||
1074 | if (!oh) | |
1075 | return -EINVAL; | |
1076 | ||
1077 | shift = _lookup_hardreset(oh, name); | |
1078 | if (IS_ERR_VALUE(shift)) | |
1079 | return shift; | |
1080 | ||
1081 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1082 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
1083 | shift); | |
1084 | } else if (cpu_is_omap44xx()) { | |
1085 | return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, | |
1086 | shift); | |
1087 | } else { | |
1088 | return -EINVAL; | |
1089 | } | |
1090 | } | |
1091 | ||
63c85238 | 1092 | /** |
bd36179e | 1093 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1094 | * @oh: struct omap_hwmod * |
1095 | * | |
1096 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
12b1fdb4 KH |
1097 | * enabled for this to work. Returns -EINVAL if the hwmod cannot be |
1098 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
1099 | * the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1100 | * |
1101 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1102 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1103 | * use the SYSCONFIG softreset bit to provide the status. |
1104 | * | |
bd36179e PW |
1105 | * Note that some IP like McBSP do have reset control but don't have |
1106 | * reset status. | |
63c85238 | 1107 | */ |
bd36179e | 1108 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1109 | { |
96835af9 | 1110 | u32 v; |
6f8b7ff5 | 1111 | int c = 0; |
96835af9 | 1112 | int ret = 0; |
63c85238 | 1113 | |
43b40992 | 1114 | if (!oh->class->sysc || |
2cb06814 | 1115 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
63c85238 PW |
1116 | return -EINVAL; |
1117 | ||
1118 | /* clocks must be on for this operation */ | |
1119 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1120 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1121 | "enabled state\n", oh->name); | |
63c85238 PW |
1122 | return -EINVAL; |
1123 | } | |
1124 | ||
96835af9 BC |
1125 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1126 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1127 | _enable_optional_clocks(oh); | |
1128 | ||
bd36179e | 1129 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1130 | |
1131 | v = oh->_sysc_cache; | |
96835af9 BC |
1132 | ret = _set_softreset(oh, &v); |
1133 | if (ret) | |
1134 | goto dis_opt_clks; | |
63c85238 PW |
1135 | _write_sysconfig(v, oh); |
1136 | ||
2cb06814 | 1137 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1138 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1139 | oh->class->sysc->syss_offs) |
1140 | & SYSS_RESETDONE_MASK), | |
1141 | MAX_MODULE_SOFTRESET_WAIT, c); | |
1142 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) | |
cc7a1d2a | 1143 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 BC |
1144 | oh->class->sysc->sysc_offs) |
1145 | & SYSC_TYPE2_SOFTRESET_MASK), | |
1146 | MAX_MODULE_SOFTRESET_WAIT, c); | |
63c85238 | 1147 | |
5365efbe | 1148 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1149 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1150 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1151 | else |
5365efbe | 1152 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1153 | |
1154 | /* | |
1155 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1156 | * _wait_target_ready() or _reset() | |
1157 | */ | |
1158 | ||
96835af9 BC |
1159 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1160 | ||
1161 | dis_opt_clks: | |
1162 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1163 | _disable_optional_clocks(oh); | |
1164 | ||
1165 | return ret; | |
63c85238 PW |
1166 | } |
1167 | ||
bd36179e PW |
1168 | /** |
1169 | * _reset - reset an omap_hwmod | |
1170 | * @oh: struct omap_hwmod * | |
1171 | * | |
1172 | * Resets an omap_hwmod @oh. The default software reset mechanism for | |
1173 | * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET | |
1174 | * bit. However, some hwmods cannot be reset via this method: some | |
1175 | * are not targets and therefore have no OCP header registers to | |
1176 | * access; others (like the IVA) have idiosyncratic reset sequences. | |
1177 | * So for these relatively rare cases, custom reset code can be | |
1178 | * supplied in the struct omap_hwmod_class .reset function pointer. | |
1179 | * Passes along the return value from either _reset() or the custom | |
1180 | * reset function - these must return -EINVAL if the hwmod cannot be | |
1181 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
1182 | * the module did not reset in time, or 0 upon success. | |
1183 | */ | |
1184 | static int _reset(struct omap_hwmod *oh) | |
1185 | { | |
1186 | int ret; | |
1187 | ||
1188 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1189 | ||
1190 | ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); | |
1191 | ||
1192 | return ret; | |
1193 | } | |
1194 | ||
63c85238 | 1195 | /** |
dc6d1cda | 1196 | * _enable - enable an omap_hwmod |
63c85238 PW |
1197 | * @oh: struct omap_hwmod * |
1198 | * | |
1199 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1200 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1201 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1202 | */ |
dc6d1cda | 1203 | static int _enable(struct omap_hwmod *oh) |
63c85238 PW |
1204 | { |
1205 | int r; | |
1206 | ||
1207 | if (oh->_state != _HWMOD_STATE_INITIALIZED && | |
1208 | oh->_state != _HWMOD_STATE_IDLE && | |
1209 | oh->_state != _HWMOD_STATE_DISABLED) { | |
1210 | WARN(1, "omap_hwmod: %s: enabled state can only be entered " | |
1211 | "from initialized, idle, or disabled state\n", oh->name); | |
1212 | return -EINVAL; | |
1213 | } | |
1214 | ||
1215 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); | |
1216 | ||
5365efbe BC |
1217 | /* |
1218 | * If an IP contains only one HW reset line, then de-assert it in order | |
1219 | * to allow to enable the clocks. Otherwise the PRCM will return | |
1220 | * Intransition status, and the init will failed. | |
1221 | */ | |
1222 | if ((oh->_state == _HWMOD_STATE_INITIALIZED || | |
1223 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) | |
1224 | _deassert_hardreset(oh, oh->rst_lines[0].name); | |
1225 | ||
63c85238 PW |
1226 | /* XXX mux balls */ |
1227 | ||
1228 | _add_initiator_dep(oh, mpu_oh); | |
1229 | _enable_clocks(oh); | |
1230 | ||
63c85238 | 1231 | r = _wait_target_ready(oh); |
9a23dfe1 | 1232 | if (!r) { |
63c85238 PW |
1233 | oh->_state = _HWMOD_STATE_ENABLED; |
1234 | ||
9a23dfe1 BC |
1235 | /* Access the sysconfig only if the target is ready */ |
1236 | if (oh->class->sysc) { | |
1237 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1238 | _update_sysc_cache(oh); | |
74ff3a68 | 1239 | _enable_sysc(oh); |
9a23dfe1 BC |
1240 | } |
1241 | } else { | |
1242 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1243 | oh->name, r); | |
1244 | } | |
1245 | ||
63c85238 PW |
1246 | return r; |
1247 | } | |
1248 | ||
1249 | /** | |
dc6d1cda | 1250 | * _idle - idle an omap_hwmod |
63c85238 PW |
1251 | * @oh: struct omap_hwmod * |
1252 | * | |
1253 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1254 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1255 | * state or returns 0. | |
63c85238 | 1256 | */ |
dc6d1cda | 1257 | static int _idle(struct omap_hwmod *oh) |
63c85238 PW |
1258 | { |
1259 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
1260 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | |
1261 | "enabled state\n", oh->name); | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | ||
1265 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | |
1266 | ||
43b40992 | 1267 | if (oh->class->sysc) |
74ff3a68 | 1268 | _idle_sysc(oh); |
63c85238 PW |
1269 | _del_initiator_dep(oh, mpu_oh); |
1270 | _disable_clocks(oh); | |
1271 | ||
1272 | oh->_state = _HWMOD_STATE_IDLE; | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | /** | |
1278 | * _shutdown - shutdown an omap_hwmod | |
1279 | * @oh: struct omap_hwmod * | |
1280 | * | |
1281 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1282 | * used for the hwmod is removed or unloaded or if the driver is not | |
1283 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1284 | * state or returns 0. | |
1285 | */ | |
1286 | static int _shutdown(struct omap_hwmod *oh) | |
1287 | { | |
e4dc8f50 PW |
1288 | int ret; |
1289 | u8 prev_state; | |
1290 | ||
63c85238 PW |
1291 | if (oh->_state != _HWMOD_STATE_IDLE && |
1292 | oh->_state != _HWMOD_STATE_ENABLED) { | |
1293 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | |
1294 | "from idle, or enabled state\n", oh->name); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
1298 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
1299 | ||
e4dc8f50 PW |
1300 | if (oh->class->pre_shutdown) { |
1301 | prev_state = oh->_state; | |
1302 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1303 | _enable(oh); |
e4dc8f50 PW |
1304 | ret = oh->class->pre_shutdown(oh); |
1305 | if (ret) { | |
1306 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1307 | _idle(oh); |
e4dc8f50 PW |
1308 | return ret; |
1309 | } | |
1310 | } | |
1311 | ||
43b40992 | 1312 | if (oh->class->sysc) |
74ff3a68 | 1313 | _shutdown_sysc(oh); |
3827f949 | 1314 | |
5365efbe BC |
1315 | /* |
1316 | * If an IP contains only one HW reset line, then assert it | |
1317 | * before disabling the clocks and shutting down the IP. | |
1318 | */ | |
1319 | if (oh->rst_lines_cnt == 1) | |
1320 | _assert_hardreset(oh, oh->rst_lines[0].name); | |
1321 | ||
3827f949 BC |
1322 | /* clocks and deps are already disabled in idle */ |
1323 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1324 | _del_initiator_dep(oh, mpu_oh); | |
1325 | /* XXX what about the other system initiators here? dma, dsp */ | |
1326 | _disable_clocks(oh); | |
1327 | } | |
63c85238 PW |
1328 | /* XXX Should this code also force-disable the optional clocks? */ |
1329 | ||
1330 | /* XXX mux any associated balls to safe mode */ | |
1331 | ||
1332 | oh->_state = _HWMOD_STATE_DISABLED; | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
63c85238 PW |
1337 | /** |
1338 | * _setup - do initial configuration of omap_hwmod | |
1339 | * @oh: struct omap_hwmod * | |
1340 | * | |
1341 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | |
2092e5cc PW |
1342 | * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the |
1343 | * wrong state or returns 0. | |
63c85238 | 1344 | */ |
97d60162 | 1345 | static int _setup(struct omap_hwmod *oh, void *data) |
63c85238 | 1346 | { |
9a23dfe1 | 1347 | int i, r; |
2092e5cc | 1348 | u8 postsetup_state; |
97d60162 | 1349 | |
63c85238 PW |
1350 | /* Set iclk autoidle mode */ |
1351 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
1352 | for (i = 0; i < oh->slaves_cnt; i++) { |
1353 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
1354 | struct clk *c = os->_clk; |
1355 | ||
4d3ae5a9 | 1356 | if (!c) |
63c85238 PW |
1357 | continue; |
1358 | ||
1359 | if (os->flags & OCPIF_SWSUP_IDLE) { | |
1360 | /* XXX omap_iclk_deny_idle(c); */ | |
1361 | } else { | |
1362 | /* XXX omap_iclk_allow_idle(c); */ | |
1363 | clk_enable(c); | |
1364 | } | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
1369 | ||
5365efbe BC |
1370 | /* |
1371 | * In the case of hwmod with hardreset that should not be | |
1372 | * de-assert at boot time, we have to keep the module | |
1373 | * initialized, because we cannot enable it properly with the | |
1374 | * reset asserted. Exit without warning because that behavior is | |
1375 | * expected. | |
1376 | */ | |
1377 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) | |
1378 | return 0; | |
1379 | ||
dc6d1cda | 1380 | r = _enable(oh); |
9a23dfe1 BC |
1381 | if (r) { |
1382 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | |
1383 | oh->name, oh->_state); | |
1384 | return 0; | |
1385 | } | |
63c85238 | 1386 | |
b835d014 | 1387 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) { |
76e5589e BC |
1388 | _reset(oh); |
1389 | ||
b835d014 | 1390 | /* |
76e5589e | 1391 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. |
dc6d1cda | 1392 | * The _enable() function should be split to |
76e5589e | 1393 | * avoid the rewrite of the OCP_SYSCONFIG register. |
b835d014 | 1394 | */ |
43b40992 | 1395 | if (oh->class->sysc) { |
b835d014 | 1396 | _update_sysc_cache(oh); |
74ff3a68 | 1397 | _enable_sysc(oh); |
b835d014 PW |
1398 | } |
1399 | } | |
63c85238 | 1400 | |
2092e5cc PW |
1401 | postsetup_state = oh->_postsetup_state; |
1402 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
1403 | postsetup_state = _HWMOD_STATE_ENABLED; | |
1404 | ||
1405 | /* | |
1406 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
1407 | * it should be set by the core code as a runtime flag during startup | |
1408 | */ | |
1409 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
1410 | (postsetup_state == _HWMOD_STATE_IDLE)) | |
1411 | postsetup_state = _HWMOD_STATE_ENABLED; | |
1412 | ||
1413 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1414 | _idle(oh); |
2092e5cc PW |
1415 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
1416 | _shutdown(oh); | |
1417 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
1418 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
1419 | oh->name, postsetup_state); | |
63c85238 PW |
1420 | |
1421 | return 0; | |
1422 | } | |
1423 | ||
1424 | ||
1425 | ||
1426 | /* Public functions */ | |
1427 | ||
cc7a1d2a | 1428 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) |
63c85238 | 1429 | { |
cc7a1d2a RN |
1430 | if (oh->flags & HWMOD_16BIT_REG) |
1431 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
1432 | else | |
1433 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
63c85238 PW |
1434 | } |
1435 | ||
cc7a1d2a | 1436 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) |
63c85238 | 1437 | { |
cc7a1d2a RN |
1438 | if (oh->flags & HWMOD_16BIT_REG) |
1439 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
1440 | else | |
1441 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
63c85238 PW |
1442 | } |
1443 | ||
887adeac PW |
1444 | /** |
1445 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
1446 | * @oh: struct omap_hwmod * | |
1447 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
1448 | * | |
1449 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
1450 | * local copy. Intended to be used by drivers that have some erratum | |
1451 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
1452 | * -EINVAL if @oh is null, or passes along the return value from | |
1453 | * _set_slave_idlemode(). | |
1454 | * | |
1455 | * XXX Does this function have any current users? If not, we should | |
1456 | * remove it; it is better to let the rest of the hwmod code handle this. | |
1457 | * Any users of this function should be scrutinized carefully. | |
1458 | */ | |
46273e6f KH |
1459 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) |
1460 | { | |
1461 | u32 v; | |
1462 | int retval = 0; | |
1463 | ||
1464 | if (!oh) | |
1465 | return -EINVAL; | |
1466 | ||
1467 | v = oh->_sysc_cache; | |
1468 | ||
1469 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
1470 | if (!retval) | |
1471 | _write_sysconfig(v, oh); | |
1472 | ||
1473 | return retval; | |
1474 | } | |
1475 | ||
63c85238 PW |
1476 | /** |
1477 | * omap_hwmod_register - register a struct omap_hwmod | |
1478 | * @oh: struct omap_hwmod * | |
1479 | * | |
43b40992 PW |
1480 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1481 | * already has been registered by the same name; -EINVAL if the | |
1482 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
1483 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
1484 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
1485 | * success. | |
63c85238 PW |
1486 | * |
1487 | * XXX The data should be copied into bootmem, so the original data | |
1488 | * should be marked __initdata and freed after init. This would allow | |
1489 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
1490 | * that the copy process would be relatively complex due to the large number | |
1491 | * of substructures. | |
1492 | */ | |
1493 | int omap_hwmod_register(struct omap_hwmod *oh) | |
1494 | { | |
1495 | int ret, ms_id; | |
1496 | ||
43b40992 PW |
1497 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1498 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
1499 | return -EINVAL; |
1500 | ||
1501 | mutex_lock(&omap_hwmod_mutex); | |
1502 | ||
1503 | pr_debug("omap_hwmod: %s: registering\n", oh->name); | |
1504 | ||
1505 | if (_lookup(oh->name)) { | |
1506 | ret = -EEXIST; | |
1507 | goto ohr_unlock; | |
1508 | } | |
1509 | ||
1510 | ms_id = _find_mpu_port_index(oh); | |
1511 | if (!IS_ERR_VALUE(ms_id)) { | |
1512 | oh->_mpu_port_index = ms_id; | |
db2a60bf | 1513 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); |
63c85238 PW |
1514 | } else { |
1515 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
1516 | } | |
1517 | ||
1518 | list_add_tail(&oh->node, &omap_hwmod_list); | |
1519 | ||
dc6d1cda | 1520 | spin_lock_init(&oh->_lock); |
2092e5cc | 1521 | |
63c85238 PW |
1522 | oh->_state = _HWMOD_STATE_REGISTERED; |
1523 | ||
1524 | ret = 0; | |
1525 | ||
1526 | ohr_unlock: | |
1527 | mutex_unlock(&omap_hwmod_mutex); | |
1528 | return ret; | |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
1533 | * @name: name of the omap_hwmod to look up | |
1534 | * | |
1535 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
1536 | * struct omap_hwmod *, or NULL upon error. | |
1537 | */ | |
1538 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
1539 | { | |
1540 | struct omap_hwmod *oh; | |
1541 | ||
1542 | if (!name) | |
1543 | return NULL; | |
1544 | ||
1545 | mutex_lock(&omap_hwmod_mutex); | |
1546 | oh = _lookup(name); | |
1547 | mutex_unlock(&omap_hwmod_mutex); | |
1548 | ||
1549 | return oh; | |
1550 | } | |
1551 | ||
1552 | /** | |
1553 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
1554 | * @fn: pointer to a callback function | |
97d60162 | 1555 | * @data: void * data to pass to callback function |
63c85238 PW |
1556 | * |
1557 | * Call @fn for each registered omap_hwmod, passing @data to each | |
1558 | * function. @fn must return 0 for success or any other value for | |
1559 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
1560 | * will stop and the non-zero return value will be passed to the | |
1561 | * caller of omap_hwmod_for_each(). @fn is called with | |
1562 | * omap_hwmod_for_each() held. | |
1563 | */ | |
97d60162 PW |
1564 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
1565 | void *data) | |
63c85238 PW |
1566 | { |
1567 | struct omap_hwmod *temp_oh; | |
1568 | int ret; | |
1569 | ||
1570 | if (!fn) | |
1571 | return -EINVAL; | |
1572 | ||
1573 | mutex_lock(&omap_hwmod_mutex); | |
1574 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
97d60162 | 1575 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
1576 | if (ret) |
1577 | break; | |
1578 | } | |
1579 | mutex_unlock(&omap_hwmod_mutex); | |
1580 | ||
1581 | return ret; | |
1582 | } | |
1583 | ||
1584 | ||
1585 | /** | |
1586 | * omap_hwmod_init - init omap_hwmod code and register hwmods | |
1587 | * @ohs: pointer to an array of omap_hwmods to register | |
1588 | * | |
1589 | * Intended to be called early in boot before the clock framework is | |
1590 | * initialized. If @ohs is not null, will register all omap_hwmods | |
1591 | * listed in @ohs that are valid for this chip. Returns -EINVAL if | |
1592 | * omap_hwmod_init() has already been called or 0 otherwise. | |
1593 | */ | |
1594 | int omap_hwmod_init(struct omap_hwmod **ohs) | |
1595 | { | |
1596 | struct omap_hwmod *oh; | |
1597 | int r; | |
1598 | ||
1599 | if (inited) | |
1600 | return -EINVAL; | |
1601 | ||
1602 | inited = 1; | |
1603 | ||
1604 | if (!ohs) | |
1605 | return 0; | |
1606 | ||
1607 | oh = *ohs; | |
1608 | while (oh) { | |
1609 | if (omap_chip_is(oh->omap_chip)) { | |
1610 | r = omap_hwmod_register(oh); | |
1611 | WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " | |
1612 | "%d\n", oh->name, r); | |
1613 | } | |
1614 | oh = *++ohs; | |
1615 | } | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
1620 | /** | |
1621 | * omap_hwmod_late_init - do some post-clock framework initialization | |
1622 | * | |
1623 | * Must be called after omap2_clk_init(). Resolves the struct clk names | |
1624 | * to struct clk pointers for each registered omap_hwmod. Also calls | |
1625 | * _setup() on each hwmod. Returns 0. | |
1626 | */ | |
2092e5cc | 1627 | int omap_hwmod_late_init(void) |
63c85238 PW |
1628 | { |
1629 | int r; | |
1630 | ||
1631 | /* XXX check return value */ | |
97d60162 | 1632 | r = omap_hwmod_for_each(_init_clocks, NULL); |
63c85238 PW |
1633 | WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); |
1634 | ||
1635 | mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); | |
1636 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", | |
1637 | MPU_INITIATOR_NAME); | |
1638 | ||
2092e5cc | 1639 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
1640 | |
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | /** | |
1645 | * omap_hwmod_unregister - unregister an omap_hwmod | |
1646 | * @oh: struct omap_hwmod * | |
1647 | * | |
1648 | * Unregisters a previously-registered omap_hwmod @oh. There's probably | |
1649 | * no use case for this, so it is likely to be removed in a later version. | |
1650 | * | |
1651 | * XXX Free all of the bootmem-allocated structures here when that is | |
1652 | * implemented. Make it clear that core code is the only code that is | |
1653 | * expected to unregister modules. | |
1654 | */ | |
1655 | int omap_hwmod_unregister(struct omap_hwmod *oh) | |
1656 | { | |
1657 | if (!oh) | |
1658 | return -EINVAL; | |
1659 | ||
1660 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | |
1661 | ||
1662 | mutex_lock(&omap_hwmod_mutex); | |
db2a60bf | 1663 | iounmap(oh->_mpu_rt_va); |
63c85238 PW |
1664 | list_del(&oh->node); |
1665 | mutex_unlock(&omap_hwmod_mutex); | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
1670 | /** | |
1671 | * omap_hwmod_enable - enable an omap_hwmod | |
1672 | * @oh: struct omap_hwmod * | |
1673 | * | |
74ff3a68 | 1674 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
1675 | * Returns -EINVAL on error or passes along the return value from _enable(). |
1676 | */ | |
1677 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
1678 | { | |
1679 | int r; | |
dc6d1cda | 1680 | unsigned long flags; |
63c85238 PW |
1681 | |
1682 | if (!oh) | |
1683 | return -EINVAL; | |
1684 | ||
dc6d1cda PW |
1685 | spin_lock_irqsave(&oh->_lock, flags); |
1686 | r = _enable(oh); | |
1687 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
1688 | |
1689 | return r; | |
1690 | } | |
1691 | ||
1692 | /** | |
1693 | * omap_hwmod_idle - idle an omap_hwmod | |
1694 | * @oh: struct omap_hwmod * | |
1695 | * | |
74ff3a68 | 1696 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
1697 | * Returns -EINVAL on error or passes along the return value from _idle(). |
1698 | */ | |
1699 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
1700 | { | |
dc6d1cda PW |
1701 | unsigned long flags; |
1702 | ||
63c85238 PW |
1703 | if (!oh) |
1704 | return -EINVAL; | |
1705 | ||
dc6d1cda PW |
1706 | spin_lock_irqsave(&oh->_lock, flags); |
1707 | _idle(oh); | |
1708 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | /** | |
1714 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
1715 | * @oh: struct omap_hwmod * | |
1716 | * | |
74ff3a68 | 1717 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
1718 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
1719 | * the return value from _shutdown(). | |
1720 | */ | |
1721 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
1722 | { | |
dc6d1cda PW |
1723 | unsigned long flags; |
1724 | ||
63c85238 PW |
1725 | if (!oh) |
1726 | return -EINVAL; | |
1727 | ||
dc6d1cda | 1728 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 1729 | _shutdown(oh); |
dc6d1cda | 1730 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1731 | |
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | /** | |
1736 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
1737 | * @oh: struct omap_hwmod *oh | |
1738 | * | |
1739 | * Intended to be called by the omap_device code. | |
1740 | */ | |
1741 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
1742 | { | |
dc6d1cda PW |
1743 | unsigned long flags; |
1744 | ||
1745 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 1746 | _enable_clocks(oh); |
dc6d1cda | 1747 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1748 | |
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | /** | |
1753 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
1754 | * @oh: struct omap_hwmod *oh | |
1755 | * | |
1756 | * Intended to be called by the omap_device code. | |
1757 | */ | |
1758 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
1759 | { | |
dc6d1cda PW |
1760 | unsigned long flags; |
1761 | ||
1762 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 1763 | _disable_clocks(oh); |
dc6d1cda | 1764 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1765 | |
1766 | return 0; | |
1767 | } | |
1768 | ||
1769 | /** | |
1770 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
1771 | * @oh: struct omap_hwmod *oh | |
1772 | * | |
1773 | * Intended to be called by drivers and core code when all posted | |
1774 | * writes to a device must complete before continuing further | |
1775 | * execution (for example, after clearing some device IRQSTATUS | |
1776 | * register bits) | |
1777 | * | |
1778 | * XXX what about targets with multiple OCP threads? | |
1779 | */ | |
1780 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
1781 | { | |
1782 | BUG_ON(!oh); | |
1783 | ||
43b40992 | 1784 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
63c85238 PW |
1785 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
1786 | "device configuration\n", oh->name); | |
1787 | return; | |
1788 | } | |
1789 | ||
1790 | /* | |
1791 | * Forces posted writes to complete on the OCP thread handling | |
1792 | * register writes | |
1793 | */ | |
cc7a1d2a | 1794 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
1795 | } |
1796 | ||
1797 | /** | |
1798 | * omap_hwmod_reset - reset the hwmod | |
1799 | * @oh: struct omap_hwmod * | |
1800 | * | |
1801 | * Under some conditions, a driver may wish to reset the entire device. | |
1802 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 1803 | * the return value from _reset(). |
63c85238 PW |
1804 | */ |
1805 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
1806 | { | |
1807 | int r; | |
dc6d1cda | 1808 | unsigned long flags; |
63c85238 | 1809 | |
9b579114 | 1810 | if (!oh) |
63c85238 PW |
1811 | return -EINVAL; |
1812 | ||
dc6d1cda | 1813 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 1814 | r = _reset(oh); |
dc6d1cda | 1815 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1816 | |
1817 | return r; | |
1818 | } | |
1819 | ||
1820 | /** | |
1821 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
1822 | * @oh: struct omap_hwmod * | |
1823 | * @res: pointer to the first element of an array of struct resource to fill | |
1824 | * | |
1825 | * Count the number of struct resource array elements necessary to | |
1826 | * contain omap_hwmod @oh resources. Intended to be called by code | |
1827 | * that registers omap_devices. Intended to be used to determine the | |
1828 | * size of a dynamically-allocated struct resource array, before | |
1829 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
1830 | * resource array elements needed. | |
1831 | * | |
1832 | * XXX This code is not optimized. It could attempt to merge adjacent | |
1833 | * resource IDs. | |
1834 | * | |
1835 | */ | |
1836 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
1837 | { | |
1838 | int ret, i; | |
1839 | ||
9ee9fff9 | 1840 | ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; |
63c85238 PW |
1841 | |
1842 | for (i = 0; i < oh->slaves_cnt; i++) | |
682fdc96 | 1843 | ret += oh->slaves[i]->addr_cnt; |
63c85238 PW |
1844 | |
1845 | return ret; | |
1846 | } | |
1847 | ||
1848 | /** | |
1849 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
1850 | * @oh: struct omap_hwmod * | |
1851 | * @res: pointer to the first element of an array of struct resource to fill | |
1852 | * | |
1853 | * Fill the struct resource array @res with resource data from the | |
1854 | * omap_hwmod @oh. Intended to be called by code that registers | |
1855 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
1856 | * number of array elements filled. | |
1857 | */ | |
1858 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
1859 | { | |
1860 | int i, j; | |
1861 | int r = 0; | |
1862 | ||
1863 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
1864 | ||
1865 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { | |
718bfd76 PW |
1866 | (res + r)->name = (oh->mpu_irqs + i)->name; |
1867 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
1868 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
1869 | (res + r)->flags = IORESOURCE_IRQ; |
1870 | r++; | |
1871 | } | |
1872 | ||
9ee9fff9 BC |
1873 | for (i = 0; i < oh->sdma_reqs_cnt; i++) { |
1874 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
1875 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
1876 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
1877 | (res + r)->flags = IORESOURCE_DMA; |
1878 | r++; | |
1879 | } | |
1880 | ||
1881 | for (i = 0; i < oh->slaves_cnt; i++) { | |
1882 | struct omap_hwmod_ocp_if *os; | |
1883 | ||
682fdc96 | 1884 | os = oh->slaves[i]; |
63c85238 PW |
1885 | |
1886 | for (j = 0; j < os->addr_cnt; j++) { | |
1887 | (res + r)->start = (os->addr + j)->pa_start; | |
1888 | (res + r)->end = (os->addr + j)->pa_end; | |
1889 | (res + r)->flags = IORESOURCE_MEM; | |
1890 | r++; | |
1891 | } | |
1892 | } | |
1893 | ||
1894 | return r; | |
1895 | } | |
1896 | ||
1897 | /** | |
1898 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
1899 | * @oh: struct omap_hwmod * | |
1900 | * | |
1901 | * Return the powerdomain pointer associated with the OMAP module | |
1902 | * @oh's main clock. If @oh does not have a main clk, return the | |
1903 | * powerdomain associated with the interface clock associated with the | |
1904 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
1905 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
1906 | * success. | |
1907 | */ | |
1908 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
1909 | { | |
1910 | struct clk *c; | |
1911 | ||
1912 | if (!oh) | |
1913 | return NULL; | |
1914 | ||
1915 | if (oh->_clk) { | |
1916 | c = oh->_clk; | |
1917 | } else { | |
1918 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1919 | return NULL; | |
1920 | c = oh->slaves[oh->_mpu_port_index]->_clk; | |
1921 | } | |
1922 | ||
d5647c18 TG |
1923 | if (!c->clkdm) |
1924 | return NULL; | |
1925 | ||
63c85238 PW |
1926 | return c->clkdm->pwrdm.ptr; |
1927 | ||
1928 | } | |
1929 | ||
db2a60bf PW |
1930 | /** |
1931 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
1932 | * @oh: struct omap_hwmod * | |
1933 | * | |
1934 | * Returns the virtual address corresponding to the beginning of the | |
1935 | * module's register target, in the address range that is intended to | |
1936 | * be used by the MPU. Returns the virtual address upon success or NULL | |
1937 | * upon error. | |
1938 | */ | |
1939 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
1940 | { | |
1941 | if (!oh) | |
1942 | return NULL; | |
1943 | ||
1944 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1945 | return NULL; | |
1946 | ||
1947 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
1948 | return NULL; | |
1949 | ||
1950 | return oh->_mpu_rt_va; | |
1951 | } | |
1952 | ||
63c85238 PW |
1953 | /** |
1954 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
1955 | * @oh: struct omap_hwmod * | |
1956 | * @init_oh: struct omap_hwmod * (initiator) | |
1957 | * | |
1958 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
1959 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1960 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1961 | * code needs to add/del initiator dependencies dynamically | |
1962 | * before/after accessing a device. Returns the return value from | |
1963 | * _add_initiator_dep(). | |
1964 | * | |
1965 | * XXX Keep a usecount in the clockdomain code | |
1966 | */ | |
1967 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
1968 | struct omap_hwmod *init_oh) | |
1969 | { | |
1970 | return _add_initiator_dep(oh, init_oh); | |
1971 | } | |
1972 | ||
1973 | /* | |
1974 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
1975 | * for context save/restore operations? | |
1976 | */ | |
1977 | ||
1978 | /** | |
1979 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
1980 | * @oh: struct omap_hwmod * | |
1981 | * @init_oh: struct omap_hwmod * (initiator) | |
1982 | * | |
1983 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
1984 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1985 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1986 | * code needs to add/del initiator dependencies dynamically | |
1987 | * before/after accessing a device. Returns the return value from | |
1988 | * _del_initiator_dep(). | |
1989 | * | |
1990 | * XXX Keep a usecount in the clockdomain code | |
1991 | */ | |
1992 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
1993 | struct omap_hwmod *init_oh) | |
1994 | { | |
1995 | return _del_initiator_dep(oh, init_oh); | |
1996 | } | |
1997 | ||
63c85238 PW |
1998 | /** |
1999 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
2000 | * @oh: struct omap_hwmod * | |
2001 | * | |
2002 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2003 | * send wakeups to the PRCM. Eventually this should sets PRCM wakeup | |
2004 | * registers to cause the PRCM to receive wakeup events from the | |
2005 | * module. Does not set any wakeup routing registers beyond this | |
2006 | * point - if the module is to wake up any other module or subsystem, | |
2007 | * that must be set separately. Called by omap_device code. Returns | |
2008 | * -EINVAL on error or 0 upon success. | |
2009 | */ | |
2010 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
2011 | { | |
dc6d1cda PW |
2012 | unsigned long flags; |
2013 | ||
43b40992 PW |
2014 | if (!oh->class->sysc || |
2015 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
2016 | return -EINVAL; |
2017 | ||
dc6d1cda | 2018 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2019 | _enable_wakeup(oh); |
dc6d1cda | 2020 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2021 | |
2022 | return 0; | |
2023 | } | |
2024 | ||
2025 | /** | |
2026 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
2027 | * @oh: struct omap_hwmod * | |
2028 | * | |
2029 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2030 | * from sending wakeups to the PRCM. Eventually this should clear | |
2031 | * PRCM wakeup registers to cause the PRCM to ignore wakeup events | |
2032 | * from the module. Does not set any wakeup routing registers beyond | |
2033 | * this point - if the module is to wake up any other module or | |
2034 | * subsystem, that must be set separately. Called by omap_device | |
2035 | * code. Returns -EINVAL on error or 0 upon success. | |
2036 | */ | |
2037 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
2038 | { | |
dc6d1cda PW |
2039 | unsigned long flags; |
2040 | ||
43b40992 PW |
2041 | if (!oh->class->sysc || |
2042 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
2043 | return -EINVAL; |
2044 | ||
dc6d1cda | 2045 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2046 | _disable_wakeup(oh); |
dc6d1cda | 2047 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2048 | |
2049 | return 0; | |
2050 | } | |
43b40992 | 2051 | |
aee48e3c PW |
2052 | /** |
2053 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
2054 | * contained in the hwmod module. | |
2055 | * @oh: struct omap_hwmod * | |
2056 | * @name: name of the reset line to lookup and assert | |
2057 | * | |
2058 | * Some IP like dsp, ipu or iva contain processor that require | |
2059 | * an HW reset line to be assert / deassert in order to enable fully | |
2060 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2061 | * yet supported on this OMAP; otherwise, passes along the return value | |
2062 | * from _assert_hardreset(). | |
2063 | */ | |
2064 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
2065 | { | |
2066 | int ret; | |
dc6d1cda | 2067 | unsigned long flags; |
aee48e3c PW |
2068 | |
2069 | if (!oh) | |
2070 | return -EINVAL; | |
2071 | ||
dc6d1cda | 2072 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2073 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 2074 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2075 | |
2076 | return ret; | |
2077 | } | |
2078 | ||
2079 | /** | |
2080 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
2081 | * contained in the hwmod module. | |
2082 | * @oh: struct omap_hwmod * | |
2083 | * @name: name of the reset line to look up and deassert | |
2084 | * | |
2085 | * Some IP like dsp, ipu or iva contain processor that require | |
2086 | * an HW reset line to be assert / deassert in order to enable fully | |
2087 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2088 | * yet supported on this OMAP; otherwise, passes along the return value | |
2089 | * from _deassert_hardreset(). | |
2090 | */ | |
2091 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
2092 | { | |
2093 | int ret; | |
dc6d1cda | 2094 | unsigned long flags; |
aee48e3c PW |
2095 | |
2096 | if (!oh) | |
2097 | return -EINVAL; | |
2098 | ||
dc6d1cda | 2099 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2100 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 2101 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2102 | |
2103 | return ret; | |
2104 | } | |
2105 | ||
2106 | /** | |
2107 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
2108 | * contained in the hwmod module | |
2109 | * @oh: struct omap_hwmod * | |
2110 | * @name: name of the reset line to look up and read | |
2111 | * | |
2112 | * Return the current state of the hwmod @oh's reset line named @name: | |
2113 | * returns -EINVAL upon parameter error or if this operation | |
2114 | * is unsupported on the current OMAP; otherwise, passes along the return | |
2115 | * value from _read_hardreset(). | |
2116 | */ | |
2117 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
2118 | { | |
2119 | int ret; | |
dc6d1cda | 2120 | unsigned long flags; |
aee48e3c PW |
2121 | |
2122 | if (!oh) | |
2123 | return -EINVAL; | |
2124 | ||
dc6d1cda | 2125 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2126 | ret = _read_hardreset(oh, name); |
dc6d1cda | 2127 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2128 | |
2129 | return ret; | |
2130 | } | |
2131 | ||
2132 | ||
43b40992 PW |
2133 | /** |
2134 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
2135 | * @classname: struct omap_hwmod_class name to search for | |
2136 | * @fn: callback function pointer to call for each hwmod in class @classname | |
2137 | * @user: arbitrary context data to pass to the callback function | |
2138 | * | |
2139 | * For each omap_hwmod of class @classname, call @fn. Takes | |
2140 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | |
2141 | * iteration. If the callback function returns something other than | |
2142 | * zero, the iterator is terminated, and the callback function's return | |
2143 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
2144 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
2145 | */ | |
2146 | int omap_hwmod_for_each_by_class(const char *classname, | |
2147 | int (*fn)(struct omap_hwmod *oh, | |
2148 | void *user), | |
2149 | void *user) | |
2150 | { | |
2151 | struct omap_hwmod *temp_oh; | |
2152 | int ret = 0; | |
2153 | ||
2154 | if (!classname || !fn) | |
2155 | return -EINVAL; | |
2156 | ||
2157 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
2158 | __func__, classname); | |
2159 | ||
2160 | mutex_lock(&omap_hwmod_mutex); | |
2161 | ||
2162 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
2163 | if (!strcmp(temp_oh->class->name, classname)) { | |
2164 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
2165 | __func__, temp_oh->name); | |
2166 | ret = (*fn)(temp_oh, user); | |
2167 | if (ret) | |
2168 | break; | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | mutex_unlock(&omap_hwmod_mutex); | |
2173 | ||
2174 | if (ret) | |
2175 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
2176 | __func__, ret); | |
2177 | ||
2178 | return ret; | |
2179 | } | |
2180 | ||
2092e5cc PW |
2181 | /** |
2182 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
2183 | * @oh: struct omap_hwmod * | |
2184 | * @state: state that _setup() should leave the hwmod in | |
2185 | * | |
2186 | * Sets the hwmod state that @oh will enter at the end of _setup() (called by | |
2187 | * omap_hwmod_late_init()). Only valid to call between calls to | |
2188 | * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or | |
2189 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
2190 | * in the wrong state. | |
2191 | */ | |
2192 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
2193 | { | |
2194 | int ret; | |
dc6d1cda | 2195 | unsigned long flags; |
2092e5cc PW |
2196 | |
2197 | if (!oh) | |
2198 | return -EINVAL; | |
2199 | ||
2200 | if (state != _HWMOD_STATE_DISABLED && | |
2201 | state != _HWMOD_STATE_ENABLED && | |
2202 | state != _HWMOD_STATE_IDLE) | |
2203 | return -EINVAL; | |
2204 | ||
dc6d1cda | 2205 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
2206 | |
2207 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
2208 | ret = -EINVAL; | |
2209 | goto ohsps_unlock; | |
2210 | } | |
2211 | ||
2212 | oh->_postsetup_state = state; | |
2213 | ret = 0; | |
2214 | ||
2215 | ohsps_unlock: | |
dc6d1cda | 2216 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
2217 | |
2218 | return ret; | |
2219 | } |