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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
63c85238 PW |
2 | /* |
3 | * omap_hwmod macros, structures | |
4 | * | |
550c8092 | 5 | * Copyright (C) 2009-2011 Nokia Corporation |
e6d3a8b0 | 6 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 PW |
7 | * Paul Walmsley |
8 | * | |
43b40992 | 9 | * Created in collaboration with (alphabetical order): Benoît Cousson, |
63c85238 PW |
10 | * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari |
11 | * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff | |
12 | * | |
63c85238 PW |
13 | * These headers and macros are used to define OMAP on-chip module |
14 | * data and their integration with other OMAP modules and Linux. | |
74ff3a68 PW |
15 | * Copious documentation and references can also be found in the |
16 | * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this | |
17 | * writing). | |
63c85238 PW |
18 | * |
19 | * To do: | |
20 | * - add interconnect error log structures | |
63c85238 PW |
21 | * - init_conn_id_bit (CONNID_BIT_VECTOR) |
22 | * - implement default hwmod SMS/SDRC flags? | |
b56b7bc8 | 23 | * - move Linux-specific data ("non-ROM data") out |
63c85238 PW |
24 | */ |
25 | #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
26 | #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H | |
27 | ||
28 | #include <linux/kernel.h> | |
a2debdbd | 29 | #include <linux/init.h> |
358f0e63 | 30 | #include <linux/list.h> |
63c85238 | 31 | #include <linux/ioport.h> |
dc6d1cda | 32 | #include <linux/spinlock.h> |
63c85238 PW |
33 | |
34 | struct omap_device; | |
35 | ||
49a0a3d8 TL |
36 | extern struct sysc_regbits omap_hwmod_sysc_type1; |
37 | extern struct sysc_regbits omap_hwmod_sysc_type2; | |
38 | extern struct sysc_regbits omap_hwmod_sysc_type3; | |
39 | extern struct sysc_regbits omap34xx_sr_sysc_fields; | |
40 | extern struct sysc_regbits omap36xx_sr_sysc_fields; | |
41 | extern struct sysc_regbits omap3_sham_sysc_fields; | |
42 | extern struct sysc_regbits omap3xxx_aes_sysc_fields; | |
43 | extern struct sysc_regbits omap_hwmod_sysc_type_mcasp; | |
44 | extern struct sysc_regbits omap_hwmod_sysc_type_usb_host_fs; | |
358f0e63 TG |
45 | |
46 | /* | |
47 | * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant | |
48 | * with the original PRCM protocol defined for OMAP2420 | |
49 | */ | |
50 | #define SYSC_TYPE1_MIDLEMODE_SHIFT 12 | |
4ce107cc | 51 | #define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT) |
358f0e63 | 52 | #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8 |
4ce107cc | 53 | #define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT) |
358f0e63 | 54 | #define SYSC_TYPE1_SIDLEMODE_SHIFT 3 |
4ce107cc | 55 | #define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT) |
358f0e63 | 56 | #define SYSC_TYPE1_ENAWAKEUP_SHIFT 2 |
4ce107cc | 57 | #define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT) |
358f0e63 | 58 | #define SYSC_TYPE1_SOFTRESET_SHIFT 1 |
4ce107cc | 59 | #define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT) |
358f0e63 | 60 | #define SYSC_TYPE1_AUTOIDLE_SHIFT 0 |
4ce107cc | 61 | #define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT) |
358f0e63 TG |
62 | |
63 | /* | |
64 | * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant | |
65 | * with the new PRCM protocol defined for new OMAP4 IPs. | |
66 | */ | |
67 | #define SYSC_TYPE2_SOFTRESET_SHIFT 0 | |
68 | #define SYSC_TYPE2_SOFTRESET_MASK (1 << SYSC_TYPE2_SOFTRESET_SHIFT) | |
69 | #define SYSC_TYPE2_SIDLEMODE_SHIFT 2 | |
70 | #define SYSC_TYPE2_SIDLEMODE_MASK (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT) | |
71 | #define SYSC_TYPE2_MIDLEMODE_SHIFT 4 | |
72 | #define SYSC_TYPE2_MIDLEMODE_MASK (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT) | |
6668546f KVA |
73 | #define SYSC_TYPE2_DMADISABLE_SHIFT 16 |
74 | #define SYSC_TYPE2_DMADISABLE_MASK (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT) | |
63c85238 | 75 | |
248b3b3d VH |
76 | /* |
77 | * OCP SYSCONFIG bit shifts/masks TYPE3. | |
78 | * This is applicable for some IPs present in AM33XX | |
79 | */ | |
80 | #define SYSC_TYPE3_SIDLEMODE_SHIFT 0 | |
81 | #define SYSC_TYPE3_SIDLEMODE_MASK (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT) | |
82 | #define SYSC_TYPE3_MIDLEMODE_SHIFT 2 | |
83 | #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) | |
63c85238 PW |
84 | |
85 | /* OCP SYSSTATUS bit shifts/masks */ | |
86 | #define SYSS_RESETDONE_SHIFT 0 | |
87 | #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) | |
88 | ||
89 | /* Master standby/slave idle mode flags */ | |
90 | #define HWMOD_IDLEMODE_FORCE (1 << 0) | |
91 | #define HWMOD_IDLEMODE_NO (1 << 1) | |
92 | #define HWMOD_IDLEMODE_SMART (1 << 2) | |
86009eb3 | 93 | #define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) |
63c85238 | 94 | |
03fdefe5 BC |
95 | /* modulemode control type (SW or HW) */ |
96 | #define MODULEMODE_HWCTRL 1 | |
97 | #define MODULEMODE_SWCTRL 2 | |
98 | ||
7dedd346 RN |
99 | #define DEBUG_OMAP2UART1_FLAGS 0 |
100 | #define DEBUG_OMAP2UART2_FLAGS 0 | |
101 | #define DEBUG_OMAP2UART3_FLAGS 0 | |
102 | #define DEBUG_OMAP3UART3_FLAGS 0 | |
103 | #define DEBUG_OMAP3UART4_FLAGS 0 | |
104 | #define DEBUG_OMAP4UART3_FLAGS 0 | |
105 | #define DEBUG_OMAP4UART4_FLAGS 0 | |
106 | #define DEBUG_TI81XXUART1_FLAGS 0 | |
107 | #define DEBUG_TI81XXUART2_FLAGS 0 | |
108 | #define DEBUG_TI81XXUART3_FLAGS 0 | |
109 | #define DEBUG_AM33XXUART1_FLAGS 0 | |
110 | ||
111 | #define DEBUG_OMAPUART_FLAGS (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET) | |
112 | ||
63aa945b TL |
113 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
114 | #define DEBUG_OMAP_GPMC_HWMOD_FLAGS HWMOD_INIT_NO_RESET | |
115 | #else | |
116 | #define DEBUG_OMAP_GPMC_HWMOD_FLAGS 0 | |
117 | #endif | |
118 | ||
7dedd346 RN |
119 | #if defined(CONFIG_DEBUG_OMAP2UART1) |
120 | #undef DEBUG_OMAP2UART1_FLAGS | |
121 | #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS | |
122 | #elif defined(CONFIG_DEBUG_OMAP2UART2) | |
123 | #undef DEBUG_OMAP2UART2_FLAGS | |
124 | #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS | |
125 | #elif defined(CONFIG_DEBUG_OMAP2UART3) | |
126 | #undef DEBUG_OMAP2UART3_FLAGS | |
127 | #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS | |
128 | #elif defined(CONFIG_DEBUG_OMAP3UART3) | |
129 | #undef DEBUG_OMAP3UART3_FLAGS | |
130 | #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS | |
131 | #elif defined(CONFIG_DEBUG_OMAP3UART4) | |
132 | #undef DEBUG_OMAP3UART4_FLAGS | |
133 | #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS | |
134 | #elif defined(CONFIG_DEBUG_OMAP4UART3) | |
135 | #undef DEBUG_OMAP4UART3_FLAGS | |
136 | #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS | |
137 | #elif defined(CONFIG_DEBUG_OMAP4UART4) | |
138 | #undef DEBUG_OMAP4UART4_FLAGS | |
139 | #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS | |
140 | #elif defined(CONFIG_DEBUG_TI81XXUART1) | |
141 | #undef DEBUG_TI81XXUART1_FLAGS | |
142 | #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS | |
143 | #elif defined(CONFIG_DEBUG_TI81XXUART2) | |
144 | #undef DEBUG_TI81XXUART2_FLAGS | |
145 | #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS | |
146 | #elif defined(CONFIG_DEBUG_TI81XXUART3) | |
147 | #undef DEBUG_TI81XXUART3_FLAGS | |
148 | #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS | |
149 | #elif defined(CONFIG_DEBUG_AM33XXUART1) | |
150 | #undef DEBUG_AM33XXUART1_FLAGS | |
151 | #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS | |
152 | #endif | |
03fdefe5 | 153 | |
5365efbe BC |
154 | /** |
155 | * struct omap_hwmod_rst_info - IPs reset lines use by hwmod | |
156 | * @name: name of the reset line (module local name) | |
157 | * @rst_shift: Offset of the reset bit | |
cc1226e7 | 158 | * @st_shift: Offset of the reset status bit (OMAP2/3 only) |
5365efbe BC |
159 | * |
160 | * @name should be something short, e.g., "cpu0" or "rst". It is defined | |
161 | * locally to the hwmod. | |
162 | */ | |
163 | struct omap_hwmod_rst_info { | |
164 | const char *name; | |
165 | u8 rst_shift; | |
cc1226e7 | 166 | u8 st_shift; |
5365efbe BC |
167 | }; |
168 | ||
63c85238 PW |
169 | /** |
170 | * struct omap_hwmod_opt_clk - optional clocks used by this hwmod | |
171 | * @role: "sys", "32k", "tv", etc -- for use in clk_get() | |
50ebdac2 | 172 | * @clk: opt clock: OMAP clock name |
63c85238 PW |
173 | * @_clk: pointer to the struct clk (filled in at runtime) |
174 | * | |
175 | * The module's interface clock and main functional clock should not | |
176 | * be added as optional clocks. | |
177 | */ | |
178 | struct omap_hwmod_opt_clk { | |
179 | const char *role; | |
50ebdac2 | 180 | const char *clk; |
63c85238 PW |
181 | struct clk *_clk; |
182 | }; | |
183 | ||
184 | ||
185 | /* omap_hwmod_omap2_firewall.flags bits */ | |
186 | #define OMAP_FIREWALL_L3 (1 << 0) | |
187 | #define OMAP_FIREWALL_L4 (1 << 1) | |
188 | ||
189 | /** | |
190 | * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data | |
191 | * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_* | |
192 | * @l4_fw_region: L4 firewall region ID | |
193 | * @l4_prot_group: L4 protection group ID | |
194 | * @flags: (see omap_hwmod_omap2_firewall.flags macros above) | |
195 | */ | |
196 | struct omap_hwmod_omap2_firewall { | |
197 | u8 l3_perm_bit; | |
198 | u8 l4_fw_region; | |
199 | u8 l4_prot_group; | |
200 | u8 flags; | |
201 | }; | |
202 | ||
63c85238 PW |
203 | /* |
204 | * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this | |
205 | * interface to interact with the hwmod. Used to add sleep dependencies | |
206 | * when the module is enabled or disabled. | |
207 | */ | |
208 | #define OCP_USER_MPU (1 << 0) | |
209 | #define OCP_USER_SDMA (1 << 1) | |
3d10f0d6 | 210 | #define OCP_USER_DSP (1 << 2) |
42b9e387 | 211 | #define OCP_USER_IVA (1 << 3) |
63c85238 PW |
212 | |
213 | /* omap_hwmod_ocp_if.flags bits */ | |
33f7ec81 BC |
214 | #define OCPIF_SWSUP_IDLE (1 << 0) |
215 | #define OCPIF_CAN_BURST (1 << 1) | |
63c85238 | 216 | |
2221b5cd PW |
217 | /* omap_hwmod_ocp_if._int_flags possibilities */ |
218 | #define _OCPIF_INT_FLAGS_REGISTERED (1 << 0) | |
219 | ||
220 | ||
63c85238 PW |
221 | /** |
222 | * struct omap_hwmod_ocp_if - OCP interface data | |
223 | * @master: struct omap_hwmod that initiates OCP transactions on this link | |
224 | * @slave: struct omap_hwmod that responds to OCP transactions on this link | |
225 | * @addr: address space associated with this link | |
50ebdac2 | 226 | * @clk: interface clock: OMAP clock name |
63c85238 PW |
227 | * @_clk: pointer to the interface struct clk (filled in at runtime) |
228 | * @fw: interface firewall data | |
63c85238 | 229 | * @width: OCP data width |
63c85238 PW |
230 | * @user: initiators using this interface (see OCP_USER_* macros above) |
231 | * @flags: OCP interface flags (see OCPIF_* macros above) | |
2221b5cd | 232 | * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above) |
63c85238 PW |
233 | * |
234 | * It may also be useful to add a tag_cnt field for OCP2.x devices. | |
235 | * | |
236 | * Parameter names beginning with an underscore are managed internally by | |
237 | * the omap_hwmod code and should not be set during initialization. | |
238 | */ | |
239 | struct omap_hwmod_ocp_if { | |
240 | struct omap_hwmod *master; | |
241 | struct omap_hwmod *slave; | |
242 | struct omap_hwmod_addr_space *addr; | |
50ebdac2 | 243 | const char *clk; |
63c85238 | 244 | struct clk *_clk; |
a1e31235 | 245 | struct list_head node; |
63c85238 PW |
246 | union { |
247 | struct omap_hwmod_omap2_firewall omap2; | |
248 | } fw; | |
63c85238 | 249 | u8 width; |
63c85238 PW |
250 | u8 user; |
251 | u8 flags; | |
2221b5cd | 252 | u8 _int_flags; |
63c85238 PW |
253 | }; |
254 | ||
255 | ||
256 | /* Macros for use in struct omap_hwmod_sysconfig */ | |
257 | ||
258 | /* Flags for use in omap_hwmod_sysconfig.idlemodes */ | |
86009eb3 | 259 | #define MASTER_STANDBY_SHIFT 4 |
63c85238 PW |
260 | #define SLAVE_IDLE_SHIFT 0 |
261 | #define SIDLE_FORCE (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT) | |
262 | #define SIDLE_NO (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT) | |
263 | #define SIDLE_SMART (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT) | |
86009eb3 | 264 | #define SIDLE_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT) |
63c85238 PW |
265 | #define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) |
266 | #define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) | |
267 | #define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) | |
724019b0 | 268 | #define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT) |
63c85238 PW |
269 | |
270 | /* omap_hwmod_sysconfig.sysc_flags capability flags */ | |
271 | #define SYSC_HAS_AUTOIDLE (1 << 0) | |
272 | #define SYSC_HAS_SOFTRESET (1 << 1) | |
273 | #define SYSC_HAS_ENAWAKEUP (1 << 2) | |
274 | #define SYSC_HAS_EMUFREE (1 << 3) | |
275 | #define SYSC_HAS_CLOCKACTIVITY (1 << 4) | |
276 | #define SYSC_HAS_SIDLEMODE (1 << 5) | |
277 | #define SYSC_HAS_MIDLEMODE (1 << 6) | |
2cb06814 | 278 | #define SYSS_HAS_RESET_STATUS (1 << 7) |
883edfdd | 279 | #define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ |
2cb06814 | 280 | #define SYSC_HAS_RESET_STATUS (1 << 9) |
6668546f | 281 | #define SYSC_HAS_DMADISABLE (1 << 10) |
63c85238 PW |
282 | |
283 | /* omap_hwmod_sysconfig.clockact flags */ | |
284 | #define CLOCKACT_TEST_BOTH 0x0 | |
285 | #define CLOCKACT_TEST_MAIN 0x1 | |
286 | #define CLOCKACT_TEST_ICLK 0x2 | |
287 | #define CLOCKACT_TEST_NONE 0x3 | |
288 | ||
289 | /** | |
43b40992 | 290 | * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data |
63c85238 PW |
291 | * @rev_offs: IP block revision register offset (from module base addr) |
292 | * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) | |
293 | * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) | |
d99de7f5 | 294 | * @srst_udelay: Delay needed after doing a softreset in usecs |
63c85238 PW |
295 | * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} |
296 | * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported | |
297 | * @clockact: the default value of the module CLOCKACTIVITY bits | |
298 | * | |
299 | * @clockact describes to the module which clocks are likely to be | |
300 | * disabled when the PRCM issues its idle request to the module. Some | |
301 | * modules have separate clockdomains for the interface clock and main | |
302 | * functional clock, and can check whether they should acknowledge the | |
303 | * idle request based on the internal module functionality that has | |
304 | * been associated with the clocks marked in @clockact. This field is | |
305 | * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below) | |
306 | * | |
358f0e63 TG |
307 | * @sysc_fields: structure containing the offset positions of various bits in |
308 | * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or | |
309 | * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on | |
310 | * whether the device ip is compliant with the original PRCM protocol | |
43b40992 PW |
311 | * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs. |
312 | * If the device follows a different scheme for the sysconfig register , | |
358f0e63 | 313 | * then this field has to be populated with the correct offset structure. |
63c85238 | 314 | */ |
43b40992 | 315 | struct omap_hwmod_class_sysconfig { |
103fd8e7 TL |
316 | s32 rev_offs; |
317 | s32 sysc_offs; | |
318 | s32 syss_offs; | |
56dc79ab | 319 | u16 sysc_flags; |
49a0a3d8 | 320 | struct sysc_regbits *sysc_fields; |
d99de7f5 | 321 | u8 srst_udelay; |
63c85238 | 322 | u8 idlemodes; |
63c85238 PW |
323 | }; |
324 | ||
325 | /** | |
326 | * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data | |
327 | * @module_offs: PRCM submodule offset from the start of the PRM/CM | |
63c85238 PW |
328 | * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3) |
329 | * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit | |
63c85238 PW |
330 | * |
331 | * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST, | |
332 | * WKEN, GRPSEL registers. In an ideal world, no extra information | |
333 | * would be needed for IDLEST information, but alas, there are some | |
334 | * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit | |
335 | * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST) | |
336 | */ | |
337 | struct omap_hwmod_omap2_prcm { | |
338 | s16 module_offs; | |
63c85238 PW |
339 | u8 idlest_reg_id; |
340 | u8 idlest_idle_bit; | |
63c85238 PW |
341 | }; |
342 | ||
46b3af27 TK |
343 | /* |
344 | * Possible values for struct omap_hwmod_omap4_prcm.flags | |
345 | * | |
346 | * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM | |
347 | * module-level context loss register associated with them; this | |
348 | * flag bit should be set in those cases | |
60a5b875 DG |
349 | * HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL |
350 | * offset of zero; this flag bit should be set in those cases to | |
351 | * distinguish from hwmods that have no clkctrl offset. | |
8823ddf2 TL |
352 | * HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK: Module clockctrl clock is managed |
353 | * by the common clock framework and not hwmod. | |
46b3af27 TK |
354 | */ |
355 | #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0) | |
60a5b875 | 356 | #define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1) |
8823ddf2 | 357 | #define HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK (1 << 2) |
63c85238 PW |
358 | |
359 | /** | |
360 | * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data | |
e6d3a8b0 RN |
361 | * @clkctrl_offs: offset of the PRCM clock control register |
362 | * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM | |
363 | * @context_offs: offset of the RM_*_CONTEXT register | |
ce80979a | 364 | * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register |
768c69f5 | 365 | * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM |
63c85238 | 366 | * @submodule_wkdep_bit: bit shift of the WKDEP range |
46b3af27 | 367 | * @flags: PRCM register capabilities for this IP block |
e6d3a8b0 RN |
368 | * @modulemode: allowable modulemodes |
369 | * @context_lost_counter: Count of module level context lost | |
ce80979a TK |
370 | * |
371 | * If @lostcontext_mask is not defined, context loss check code uses | |
372 | * whole register without masking. @lostcontext_mask should only be | |
373 | * defined in cases where @context_offs register is shared by two or | |
374 | * more hwmods. | |
63c85238 PW |
375 | */ |
376 | struct omap_hwmod_omap4_prcm { | |
d0f0631d | 377 | u16 clkctrl_offs; |
eaac329d | 378 | u16 rstctrl_offs; |
768c69f5 | 379 | u16 rstst_offs; |
27bb00b5 | 380 | u16 context_offs; |
ce80979a | 381 | u32 lostcontext_mask; |
53934aa7 | 382 | u8 submodule_wkdep_bit; |
03fdefe5 | 383 | u8 modulemode; |
46b3af27 | 384 | u8 flags; |
e6d3a8b0 | 385 | int context_lost_counter; |
63c85238 PW |
386 | }; |
387 | ||
388 | ||
389 | /* | |
390 | * omap_hwmod.flags definitions | |
391 | * | |
392 | * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out | |
393 | * of idle, rather than relying on module smart-idle | |
092bc089 GI |
394 | * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and |
395 | * out of standby, rather than relying on module smart-standby | |
63c85238 | 396 | * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for |
b56b7bc8 | 397 | * SDRAM controller, etc. XXX probably belongs outside the main hwmod file |
550c8092 | 398 | * XXX Should be HWMOD_SETUP_NO_RESET |
63c85238 | 399 | * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM |
b56b7bc8 | 400 | * controller, etc. XXX probably belongs outside the main hwmod file |
550c8092 | 401 | * XXX Should be HWMOD_SETUP_NO_IDLE |
4d2274c5 | 402 | * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) |
726072e5 PW |
403 | * when module is enabled, rather than the default, which is to |
404 | * enable autoidle | |
63c85238 | 405 | * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup |
bd36179e | 406 | * HWMOD_NO_IDLEST: this module does not have idle status - this is the case |
33f7ec81 | 407 | * only for few initiator modules on OMAP2 & 3. |
96835af9 BC |
408 | * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset. |
409 | * This is needed for devices like DSS that require optional clocks enabled | |
410 | * in order to complete the reset. Optional clocks will be disabled | |
411 | * again after the reset. | |
cc7a1d2a | 412 | * HWMOD_16BIT_REG: Module has 16bit registers |
5fb3d522 PW |
413 | * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for |
414 | * this IP block comes from an off-chip source and is not always | |
415 | * enabled. This prevents the hwmod code from being able to | |
416 | * enable and reset the IP block early. XXX Eventually it should | |
417 | * be possible to query the clock framework for this information. | |
fa200222 PW |
418 | * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work |
419 | * correctly if the MPU is allowed to go idle while the | |
420 | * peripherals are active. This is apparently true for the I2C on | |
421 | * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that | |
422 | * this is really true -- we're probably not configuring something | |
423 | * correctly, or this is being abused to deal with some PM latency | |
424 | * issues -- but we're currently suffering from a shortage of | |
425 | * folks who are able to track these issues down properly. | |
092bc089 GI |
426 | * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device |
427 | * is kept in force-standby mode. Failing to do so causes PM problems | |
428 | * with musb on OMAP3630 at least. Note that musb has a dedicated register | |
429 | * to control MSTANDBY signal when MIDLEMODE is set to force-standby. | |
ca43ea34 RN |
430 | * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module |
431 | * out of idle, but rely on smart-idle to the put it back in idle, | |
432 | * so the wakeups are still functional (Only known case for now is UART) | |
6a08b11a TL |
433 | * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up |
434 | * events by calling _reconfigure_io_chain() when a device is enabled | |
435 | * or idled. | |
c12ba8ce PU |
436 | * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to |
437 | * operate and they need to be handled at the same time as the main_clk. | |
2e18f5a1 LV |
438 | * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain |
439 | * IPs like CPSW on DRA7, where clocks to this module cannot be disabled. | |
8ff42da4 RQ |
440 | * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from |
441 | * entering HW_AUTO while hwmod is active. This is needed to workaround | |
442 | * some modules which don't function correctly with HW_AUTO. For example, | |
443 | * DCAN on DRA7x SoC needs this to workaround errata i893. | |
63c85238 PW |
444 | */ |
445 | #define HWMOD_SWSUP_SIDLE (1 << 0) | |
446 | #define HWMOD_SWSUP_MSTANDBY (1 << 1) | |
447 | #define HWMOD_INIT_NO_RESET (1 << 2) | |
448 | #define HWMOD_INIT_NO_IDLE (1 << 3) | |
726072e5 PW |
449 | #define HWMOD_NO_OCP_AUTOIDLE (1 << 4) |
450 | #define HWMOD_SET_DEFAULT_CLOCKACT (1 << 5) | |
33f7ec81 | 451 | #define HWMOD_NO_IDLEST (1 << 6) |
96835af9 | 452 | #define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) |
cc7a1d2a | 453 | #define HWMOD_16BIT_REG (1 << 8) |
5fb3d522 | 454 | #define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) |
fa200222 | 455 | #define HWMOD_BLOCK_WFI (1 << 10) |
092bc089 | 456 | #define HWMOD_FORCE_MSTANDBY (1 << 11) |
ca43ea34 | 457 | #define HWMOD_SWSUP_SIDLE_ACT (1 << 12) |
6a08b11a | 458 | #define HWMOD_RECONFIG_IO_CHAIN (1 << 13) |
c12ba8ce | 459 | #define HWMOD_OPT_CLKS_NEEDED (1 << 14) |
2e18f5a1 | 460 | #define HWMOD_NO_IDLE (1 << 15) |
8ff42da4 | 461 | #define HWMOD_CLKDM_NOAUTO (1 << 16) |
63c85238 PW |
462 | |
463 | /* | |
464 | * omap_hwmod._int_flags definitions | |
465 | * These are for internal use only and are managed by the omap_hwmod code. | |
466 | * | |
467 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module | |
63c85238 | 468 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached |
aacf0941 RN |
469 | * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - |
470 | * causes the first call to _enable() to only update the pinmux | |
63c85238 PW |
471 | */ |
472 | #define _HWMOD_NO_MPU_PORT (1 << 0) | |
4280943b RN |
473 | #define _HWMOD_SYSCONFIG_LOADED (1 << 1) |
474 | #define _HWMOD_SKIP_ENABLE (1 << 2) | |
63c85238 PW |
475 | |
476 | /* | |
477 | * omap_hwmod._state definitions | |
478 | * | |
479 | * INITIALIZED: reset (optionally), initialized, enabled, disabled | |
480 | * (optionally) | |
481 | * | |
482 | * | |
483 | */ | |
484 | #define _HWMOD_STATE_UNKNOWN 0 | |
485 | #define _HWMOD_STATE_REGISTERED 1 | |
486 | #define _HWMOD_STATE_CLKS_INITED 2 | |
487 | #define _HWMOD_STATE_INITIALIZED 3 | |
488 | #define _HWMOD_STATE_ENABLED 4 | |
489 | #define _HWMOD_STATE_IDLE 5 | |
490 | #define _HWMOD_STATE_DISABLED 6 | |
491 | ||
6d63b12d TL |
492 | #ifdef CONFIG_PM |
493 | #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_IDLE | |
494 | #else | |
495 | #define _HWMOD_STATE_DEFAULT _HWMOD_STATE_ENABLED | |
496 | #endif | |
497 | ||
43b40992 PW |
498 | /** |
499 | * struct omap_hwmod_class - the type of an IP block | |
500 | * @name: name of the hwmod_class | |
501 | * @sysc: device SYSCONFIG/SYSSTATUS register data | |
e4dc8f50 | 502 | * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown |
bd36179e | 503 | * @reset: ptr to fn to be executed in place of the standard hwmod reset fn |
6d266f63 | 504 | * @enable_preprogram: ptr to fn to be executed during device enable |
aaf2c0fb LV |
505 | * @lock: ptr to fn to be executed to lock IP registers |
506 | * @unlock: ptr to fn to be executed to unlock IP registers | |
43b40992 PW |
507 | * |
508 | * Represent the class of a OMAP hardware "modules" (e.g. timer, | |
509 | * smartreflex, gpio, uart...) | |
e4dc8f50 PW |
510 | * |
511 | * @pre_shutdown is a function that will be run immediately before | |
512 | * hwmod clocks are disabled, etc. It is intended for use for hwmods | |
513 | * like the MPU watchdog, which cannot be disabled with the standard | |
514 | * omap_hwmod_shutdown(). The function should return 0 upon success, | |
515 | * or some negative error upon failure. Returning an error will cause | |
516 | * omap_hwmod_shutdown() to abort the device shutdown and return an | |
517 | * error. | |
bd36179e PW |
518 | * |
519 | * If @reset is defined, then the function it points to will be | |
520 | * executed in place of the standard hwmod _reset() code in | |
521 | * mach-omap2/omap_hwmod.c. This is needed for IP blocks which have | |
522 | * unusual reset sequences - usually processor IP blocks like the IVA. | |
43b40992 PW |
523 | */ |
524 | struct omap_hwmod_class { | |
525 | const char *name; | |
526 | struct omap_hwmod_class_sysconfig *sysc; | |
e4dc8f50 | 527 | int (*pre_shutdown)(struct omap_hwmod *oh); |
bd36179e | 528 | int (*reset)(struct omap_hwmod *oh); |
6d266f63 | 529 | int (*enable_preprogram)(struct omap_hwmod *oh); |
aaf2c0fb LV |
530 | void (*lock)(struct omap_hwmod *oh); |
531 | void (*unlock)(struct omap_hwmod *oh); | |
43b40992 PW |
532 | }; |
533 | ||
63c85238 PW |
534 | /** |
535 | * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks) | |
536 | * @name: name of the hwmod | |
43b40992 | 537 | * @class: struct omap_hwmod_class * to the class of this hwmod |
63c85238 | 538 | * @od: struct omap_device currently associated with this hwmod (internal use) |
63c85238 | 539 | * @prcm: PRCM data pertaining to this hwmod |
50ebdac2 | 540 | * @main_clk: main clock: OMAP clock name |
63c85238 PW |
541 | * @_clk: pointer to the main struct clk (filled in at runtime) |
542 | * @opt_clks: other device clocks that drivers can request (0..*) | |
3b92408c | 543 | * @voltdm: pointer to voltage domain (filled in at runtime) |
63c85238 PW |
544 | * @dev_attr: arbitrary device attributes that can be passed to the driver |
545 | * @_sysc_cache: internal-use hwmod flags | |
130142d9 | 546 | * @mpu_rt_idx: index of device address space for register target (for DT boot) |
db2a60bf | 547 | * @_mpu_rt_va: cached register target start address (internal use) |
2221b5cd | 548 | * @_mpu_port: cached MPU register target slave (internal use) |
63c85238 PW |
549 | * @opt_clks_cnt: number of @opt_clks |
550 | * @master_cnt: number of @master entries | |
551 | * @slaves_cnt: number of @slave entries | |
552 | * @response_lat: device OCP response latency (in interface clock cycles) | |
553 | * @_int_flags: internal-use hwmod flags | |
554 | * @_state: internal-use hwmod state | |
2092e5cc | 555 | * @_postsetup_state: internal-use state to leave the hwmod in after _setup() |
63c85238 | 556 | * @flags: hwmod flags (documented below) |
dc6d1cda | 557 | * @_lock: spinlock serializing operations on this hwmod |
63c85238 | 558 | * @node: list node for hwmod list (internal use) |
f22d2545 | 559 | * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod |
63c85238 | 560 | * |
50ebdac2 PW |
561 | * @main_clk refers to this module's "main clock," which for our |
562 | * purposes is defined as "the functional clock needed for register | |
563 | * accesses to complete." Modules may not have a main clock if the | |
564 | * interface clock also serves as a main clock. | |
63c85238 PW |
565 | * |
566 | * Parameter names beginning with an underscore are managed internally by | |
567 | * the omap_hwmod code and should not be set during initialization. | |
2221b5cd PW |
568 | * |
569 | * @masters and @slaves are now deprecated. | |
f22d2545 TV |
570 | * |
571 | * @parent_hwmod is temporary; there should be no need for it, as this | |
572 | * information should already be expressed in the OCP interface | |
573 | * structures. @parent_hwmod is present as a workaround until we improve | |
574 | * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with | |
575 | * multiple register targets across different interconnects). | |
63c85238 PW |
576 | */ |
577 | struct omap_hwmod { | |
578 | const char *name; | |
43b40992 | 579 | struct omap_hwmod_class *class; |
63c85238 | 580 | struct omap_device *od; |
5365efbe | 581 | struct omap_hwmod_rst_info *rst_lines; |
63c85238 PW |
582 | union { |
583 | struct omap_hwmod_omap2_prcm omap2; | |
584 | struct omap_hwmod_omap4_prcm omap4; | |
585 | } prcm; | |
50ebdac2 | 586 | const char *main_clk; |
63c85238 PW |
587 | struct clk *_clk; |
588 | struct omap_hwmod_opt_clk *opt_clks; | |
3cdf2f80 | 589 | const char *clkdm_name; |
6ae76997 | 590 | struct clockdomain *clkdm; |
2221b5cd | 591 | struct list_head slave_ports; /* connect to *_TA */ |
63c85238 PW |
592 | void *dev_attr; |
593 | u32 _sysc_cache; | |
db2a60bf | 594 | void __iomem *_mpu_rt_va; |
dc6d1cda | 595 | spinlock_t _lock; |
69317952 | 596 | struct lock_class_key hwmod_key; /* unique lock class */ |
63c85238 | 597 | struct list_head node; |
2221b5cd | 598 | struct omap_hwmod_ocp_if *_mpu_port; |
390c0682 | 599 | u32 flags; |
130142d9 | 600 | u8 mpu_rt_idx; |
63c85238 | 601 | u8 response_lat; |
5365efbe | 602 | u8 rst_lines_cnt; |
63c85238 | 603 | u8 opt_clks_cnt; |
63c85238 PW |
604 | u8 slaves_cnt; |
605 | u8 hwmods_cnt; | |
606 | u8 _int_flags; | |
607 | u8 _state; | |
2092e5cc | 608 | u8 _postsetup_state; |
f22d2545 | 609 | struct omap_hwmod *parent_hwmod; |
63c85238 PW |
610 | }; |
611 | ||
6c72b355 TL |
612 | struct device_node; |
613 | ||
63c85238 | 614 | struct omap_hwmod *omap_hwmod_lookup(const char *name); |
97d60162 PW |
615 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
616 | void *data); | |
63c85238 | 617 | |
a2debdbd | 618 | int __init omap_hwmod_setup_one(const char *name); |
6c72b355 TL |
619 | int omap_hwmod_parse_module_range(struct omap_hwmod *oh, |
620 | struct device_node *np, | |
621 | struct resource *res); | |
63c85238 | 622 | |
8c879705 TL |
623 | struct ti_sysc_module_data; |
624 | struct ti_sysc_cookie; | |
625 | ||
626 | int omap_hwmod_init_module(struct device *dev, | |
627 | const struct ti_sysc_module_data *data, | |
628 | struct ti_sysc_cookie *cookie); | |
629 | ||
63c85238 PW |
630 | int omap_hwmod_enable(struct omap_hwmod *oh); |
631 | int omap_hwmod_idle(struct omap_hwmod *oh); | |
632 | int omap_hwmod_shutdown(struct omap_hwmod *oh); | |
633 | ||
aee48e3c PW |
634 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name); |
635 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name); | |
63c85238 | 636 | |
cc7a1d2a RN |
637 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs); |
638 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs); | |
6d3c55fd | 639 | int omap_hwmod_softreset(struct omap_hwmod *oh); |
63c85238 | 640 | |
dad4191d | 641 | int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags); |
63c85238 | 642 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res); |
5e8370f1 PW |
643 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, |
644 | const char *name, struct resource *res); | |
63c85238 PW |
645 | |
646 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh); | |
db2a60bf | 647 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh); |
63c85238 | 648 | |
63c85238 PW |
649 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh); |
650 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh); | |
651 | ||
43b40992 PW |
652 | int omap_hwmod_for_each_by_class(const char *classname, |
653 | int (*fn)(struct omap_hwmod *oh, | |
654 | void *user), | |
655 | void *user); | |
656 | ||
2092e5cc | 657 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state); |
fc013873 | 658 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh); |
2092e5cc | 659 | |
9ebfd285 KH |
660 | extern void __init omap_hwmod_init(void); |
661 | ||
68c9a95e TL |
662 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); |
663 | ||
c02060d8 PW |
664 | /* |
665 | * | |
666 | */ | |
667 | ||
668 | extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); | |
461932df LV |
669 | void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); |
670 | void omap_hwmod_rtc_lock(struct omap_hwmod *oh); | |
c02060d8 | 671 | |
7359154e PW |
672 | /* |
673 | * Chip variant-specific hwmod init routines - XXX should be converted | |
674 | * to use initcalls once the initial boot ordering is straightened out | |
675 | */ | |
676 | extern int omap2420_hwmod_init(void); | |
677 | extern int omap2430_hwmod_init(void); | |
678 | extern int omap3xxx_hwmod_init(void); | |
55d2cb08 | 679 | extern int omap44xx_hwmod_init(void); |
08e4830d | 680 | extern int omap54xx_hwmod_init(void); |
a2cfc509 | 681 | extern int am33xx_hwmod_init(void); |
0f3ccb24 TL |
682 | extern int dm814x_hwmod_init(void); |
683 | extern int dm816x_hwmod_init(void); | |
90020c7b | 684 | extern int dra7xx_hwmod_init(void); |
6913952f | 685 | int am43xx_hwmod_init(void); |
7359154e | 686 | |
2221b5cd PW |
687 | extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); |
688 | ||
63c85238 | 689 | #endif |