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Commit | Line | Data |
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02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
59c348c3 | 20 | #include <plat/gpio.h> |
617871de | 21 | #include <plat/mcspi.h> |
eddb1262 | 22 | #include <plat/dmtimer.h> |
996746ca SG |
23 | #include <plat/l3_2xxx.h> |
24 | #include <plat/l4_2xxx.h> | |
02bfc030 | 25 | |
43b40992 PW |
26 | #include "omap_hwmod_common_data.h" |
27 | ||
a714b9cf | 28 | #include "cm-regbits-24xx.h" |
2004290f | 29 | #include "prm-regbits-24xx.h" |
ff2516fb | 30 | #include "wd_timer.h" |
02bfc030 | 31 | |
7359154e PW |
32 | /* |
33 | * OMAP2420 hardware module integration data | |
34 | * | |
35 | * ALl of the data in this section should be autogeneratable from the | |
36 | * TI hardware database or other technical documentation. Data that | |
37 | * is driver-specific or driver-kernel integration-specific belongs | |
38 | * elsewhere. | |
39 | */ | |
40 | ||
02bfc030 | 41 | static struct omap_hwmod omap2420_mpu_hwmod; |
08072acf | 42 | static struct omap_hwmod omap2420_iva_hwmod; |
4a7cf90a | 43 | static struct omap_hwmod omap2420_l3_main_hwmod; |
02bfc030 | 44 | static struct omap_hwmod omap2420_l4_core_hwmod; |
996746ca SG |
45 | static struct omap_hwmod omap2420_dss_core_hwmod; |
46 | static struct omap_hwmod omap2420_dss_dispc_hwmod; | |
47 | static struct omap_hwmod omap2420_dss_rfbi_hwmod; | |
48 | static struct omap_hwmod omap2420_dss_venc_hwmod; | |
a714b9cf | 49 | static struct omap_hwmod omap2420_wd_timer2_hwmod; |
59c348c3 VC |
50 | static struct omap_hwmod omap2420_gpio1_hwmod; |
51 | static struct omap_hwmod omap2420_gpio2_hwmod; | |
52 | static struct omap_hwmod omap2420_gpio3_hwmod; | |
53 | static struct omap_hwmod omap2420_gpio4_hwmod; | |
745685df | 54 | static struct omap_hwmod omap2420_dma_system_hwmod; |
617871de C |
55 | static struct omap_hwmod omap2420_mcspi1_hwmod; |
56 | static struct omap_hwmod omap2420_mcspi2_hwmod; | |
02bfc030 PW |
57 | |
58 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
59 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
60 | .master = &omap2420_l3_main_hwmod, | |
02bfc030 PW |
61 | .slave = &omap2420_l4_core_hwmod, |
62 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
63 | }; | |
64 | ||
65 | /* MPU -> L3 interface */ | |
4a7cf90a | 66 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
02bfc030 | 67 | .master = &omap2420_mpu_hwmod, |
4a7cf90a | 68 | .slave = &omap2420_l3_main_hwmod, |
02bfc030 PW |
69 | .user = OCP_USER_MPU, |
70 | }; | |
71 | ||
72 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
73 | static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = { |
74 | &omap2420_mpu__l3_main, | |
02bfc030 PW |
75 | }; |
76 | ||
996746ca SG |
77 | /* DSS -> l3 */ |
78 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { | |
79 | .master = &omap2420_dss_core_hwmod, | |
80 | .slave = &omap2420_l3_main_hwmod, | |
81 | .fw = { | |
82 | .omap2 = { | |
83 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
84 | .flags = OMAP_FIREWALL_L3, | |
85 | } | |
86 | }, | |
87 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
88 | }; | |
89 | ||
02bfc030 | 90 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
91 | static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { |
92 | &omap2420_l3_main__l4_core, | |
02bfc030 PW |
93 | }; |
94 | ||
95 | /* L3 */ | |
4a7cf90a | 96 | static struct omap_hwmod omap2420_l3_main_hwmod = { |
fa98347e | 97 | .name = "l3_main", |
43b40992 | 98 | .class = &l3_hwmod_class, |
4a7cf90a KH |
99 | .masters = omap2420_l3_main_masters, |
100 | .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters), | |
101 | .slaves = omap2420_l3_main_slaves, | |
102 | .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves), | |
2eb1875d KH |
103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
104 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
105 | }; |
106 | ||
107 | static struct omap_hwmod omap2420_l4_wkup_hwmod; | |
046465b7 KH |
108 | static struct omap_hwmod omap2420_uart1_hwmod; |
109 | static struct omap_hwmod omap2420_uart2_hwmod; | |
110 | static struct omap_hwmod omap2420_uart3_hwmod; | |
2004290f PW |
111 | static struct omap_hwmod omap2420_i2c1_hwmod; |
112 | static struct omap_hwmod omap2420_i2c2_hwmod; | |
3cb72fa4 C |
113 | static struct omap_hwmod omap2420_mcbsp1_hwmod; |
114 | static struct omap_hwmod omap2420_mcbsp2_hwmod; | |
02bfc030 | 115 | |
617871de | 116 | /* l4 core -> mcspi1 interface */ |
617871de C |
117 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
118 | .master = &omap2420_l4_core_hwmod, | |
119 | .slave = &omap2420_mcspi1_hwmod, | |
120 | .clk = "mcspi1_ick", | |
ded11383 | 121 | .addr = omap2_mcspi1_addr_space, |
617871de C |
122 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
123 | }; | |
124 | ||
125 | /* l4 core -> mcspi2 interface */ | |
617871de C |
126 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
127 | .master = &omap2420_l4_core_hwmod, | |
128 | .slave = &omap2420_mcspi2_hwmod, | |
129 | .clk = "mcspi2_ick", | |
ded11383 | 130 | .addr = omap2_mcspi2_addr_space, |
617871de C |
131 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
132 | }; | |
133 | ||
02bfc030 PW |
134 | /* L4_CORE -> L4_WKUP interface */ |
135 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { | |
136 | .master = &omap2420_l4_core_hwmod, | |
137 | .slave = &omap2420_l4_wkup_hwmod, | |
138 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
139 | }; | |
140 | ||
046465b7 | 141 | /* L4 CORE -> UART1 interface */ |
046465b7 KH |
142 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
143 | .master = &omap2420_l4_core_hwmod, | |
144 | .slave = &omap2420_uart1_hwmod, | |
145 | .clk = "uart1_ick", | |
ded11383 | 146 | .addr = omap2xxx_uart1_addr_space, |
046465b7 KH |
147 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
148 | }; | |
149 | ||
150 | /* L4 CORE -> UART2 interface */ | |
046465b7 KH |
151 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
152 | .master = &omap2420_l4_core_hwmod, | |
153 | .slave = &omap2420_uart2_hwmod, | |
154 | .clk = "uart2_ick", | |
ded11383 | 155 | .addr = omap2xxx_uart2_addr_space, |
046465b7 KH |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
157 | }; | |
158 | ||
159 | /* L4 PER -> UART3 interface */ | |
046465b7 KH |
160 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
161 | .master = &omap2420_l4_core_hwmod, | |
162 | .slave = &omap2420_uart3_hwmod, | |
163 | .clk = "uart3_ick", | |
ded11383 | 164 | .addr = omap2xxx_uart3_addr_space, |
046465b7 KH |
165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
166 | }; | |
167 | ||
2004290f | 168 | /* L4 CORE -> I2C1 interface */ |
2004290f PW |
169 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
170 | .master = &omap2420_l4_core_hwmod, | |
171 | .slave = &omap2420_i2c1_hwmod, | |
172 | .clk = "i2c1_ick", | |
ded11383 | 173 | .addr = omap2_i2c1_addr_space, |
2004290f PW |
174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
175 | }; | |
176 | ||
177 | /* L4 CORE -> I2C2 interface */ | |
2004290f PW |
178 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
179 | .master = &omap2420_l4_core_hwmod, | |
180 | .slave = &omap2420_i2c2_hwmod, | |
181 | .clk = "i2c2_ick", | |
ded11383 | 182 | .addr = omap2_i2c2_addr_space, |
2004290f PW |
183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
184 | }; | |
185 | ||
02bfc030 PW |
186 | /* Slave interfaces on the L4_CORE interconnect */ |
187 | static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { | |
4a7cf90a | 188 | &omap2420_l3_main__l4_core, |
02bfc030 PW |
189 | }; |
190 | ||
191 | /* Master interfaces on the L4_CORE interconnect */ | |
192 | static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { | |
193 | &omap2420_l4_core__l4_wkup, | |
046465b7 KH |
194 | &omap2_l4_core__uart1, |
195 | &omap2_l4_core__uart2, | |
196 | &omap2_l4_core__uart3, | |
2004290f PW |
197 | &omap2420_l4_core__i2c1, |
198 | &omap2420_l4_core__i2c2 | |
02bfc030 PW |
199 | }; |
200 | ||
201 | /* L4 CORE */ | |
202 | static struct omap_hwmod omap2420_l4_core_hwmod = { | |
fa98347e | 203 | .name = "l4_core", |
43b40992 | 204 | .class = &l4_hwmod_class, |
02bfc030 PW |
205 | .masters = omap2420_l4_core_masters, |
206 | .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters), | |
207 | .slaves = omap2420_l4_core_slaves, | |
208 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves), | |
2eb1875d KH |
209 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
210 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
211 | }; |
212 | ||
213 | /* Slave interfaces on the L4_WKUP interconnect */ | |
214 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = { | |
215 | &omap2420_l4_core__l4_wkup, | |
216 | }; | |
217 | ||
218 | /* Master interfaces on the L4_WKUP interconnect */ | |
219 | static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = { | |
220 | }; | |
221 | ||
222 | /* L4 WKUP */ | |
223 | static struct omap_hwmod omap2420_l4_wkup_hwmod = { | |
fa98347e | 224 | .name = "l4_wkup", |
43b40992 | 225 | .class = &l4_hwmod_class, |
02bfc030 PW |
226 | .masters = omap2420_l4_wkup_masters, |
227 | .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters), | |
228 | .slaves = omap2420_l4_wkup_slaves, | |
229 | .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves), | |
2eb1875d KH |
230 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
231 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
232 | }; |
233 | ||
234 | /* Master interfaces on the MPU device */ | |
235 | static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = { | |
4a7cf90a | 236 | &omap2420_mpu__l3_main, |
02bfc030 PW |
237 | }; |
238 | ||
239 | /* MPU */ | |
240 | static struct omap_hwmod omap2420_mpu_hwmod = { | |
5c2c0296 | 241 | .name = "mpu", |
43b40992 | 242 | .class = &mpu_hwmod_class, |
50ebdac2 | 243 | .main_clk = "mpu_ck", |
02bfc030 PW |
244 | .masters = omap2420_mpu_masters, |
245 | .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters), | |
246 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
247 | }; | |
248 | ||
08072acf PW |
249 | /* |
250 | * IVA1 interface data | |
251 | */ | |
252 | ||
253 | /* IVA <- L3 interface */ | |
254 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { | |
255 | .master = &omap2420_l3_main_hwmod, | |
256 | .slave = &omap2420_iva_hwmod, | |
257 | .clk = "iva1_ifck", | |
258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
259 | }; | |
260 | ||
261 | static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = { | |
262 | &omap2420_l3__iva, | |
263 | }; | |
264 | ||
265 | /* | |
266 | * IVA2 (IVA2) | |
267 | */ | |
268 | ||
269 | static struct omap_hwmod omap2420_iva_hwmod = { | |
270 | .name = "iva", | |
271 | .class = &iva_hwmod_class, | |
272 | .masters = omap2420_iva_masters, | |
273 | .masters_cnt = ARRAY_SIZE(omap2420_iva_masters), | |
274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) | |
275 | }; | |
276 | ||
eddb1262 TG |
277 | /* timer1 */ |
278 | static struct omap_hwmod omap2420_timer1_hwmod; | |
eddb1262 TG |
279 | |
280 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { | |
281 | { | |
282 | .pa_start = 0x48028000, | |
283 | .pa_end = 0x48028000 + SZ_1K - 1, | |
284 | .flags = ADDR_TYPE_RT | |
285 | }, | |
78183f3f | 286 | { } |
eddb1262 TG |
287 | }; |
288 | ||
289 | /* l4_wkup -> timer1 */ | |
290 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { | |
291 | .master = &omap2420_l4_wkup_hwmod, | |
292 | .slave = &omap2420_timer1_hwmod, | |
293 | .clk = "gpt1_ick", | |
294 | .addr = omap2420_timer1_addrs, | |
eddb1262 TG |
295 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
296 | }; | |
297 | ||
298 | /* timer1 slave port */ | |
299 | static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { | |
300 | &omap2420_l4_wkup__timer1, | |
301 | }; | |
302 | ||
303 | /* timer1 hwmod */ | |
304 | static struct omap_hwmod omap2420_timer1_hwmod = { | |
305 | .name = "timer1", | |
0d619a89 | 306 | .mpu_irqs = omap2_timer1_mpu_irqs, |
eddb1262 TG |
307 | .main_clk = "gpt1_fck", |
308 | .prcm = { | |
309 | .omap2 = { | |
310 | .prcm_reg_id = 1, | |
311 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
312 | .module_offs = WKUP_MOD, | |
313 | .idlest_reg_id = 1, | |
314 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
315 | }, | |
316 | }, | |
317 | .slaves = omap2420_timer1_slaves, | |
318 | .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), | |
273b9465 | 319 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
320 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
321 | }; | |
322 | ||
323 | /* timer2 */ | |
324 | static struct omap_hwmod omap2420_timer2_hwmod; | |
eddb1262 TG |
325 | |
326 | /* l4_core -> timer2 */ | |
327 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { | |
328 | .master = &omap2420_l4_core_hwmod, | |
329 | .slave = &omap2420_timer2_hwmod, | |
330 | .clk = "gpt2_ick", | |
ded11383 | 331 | .addr = omap2xxx_timer2_addrs, |
eddb1262 TG |
332 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
333 | }; | |
334 | ||
335 | /* timer2 slave port */ | |
336 | static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { | |
337 | &omap2420_l4_core__timer2, | |
338 | }; | |
339 | ||
340 | /* timer2 hwmod */ | |
341 | static struct omap_hwmod omap2420_timer2_hwmod = { | |
342 | .name = "timer2", | |
0d619a89 | 343 | .mpu_irqs = omap2_timer2_mpu_irqs, |
eddb1262 TG |
344 | .main_clk = "gpt2_fck", |
345 | .prcm = { | |
346 | .omap2 = { | |
347 | .prcm_reg_id = 1, | |
348 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
349 | .module_offs = CORE_MOD, | |
350 | .idlest_reg_id = 1, | |
351 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
352 | }, | |
353 | }, | |
354 | .slaves = omap2420_timer2_slaves, | |
355 | .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), | |
273b9465 | 356 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
357 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
358 | }; | |
359 | ||
360 | /* timer3 */ | |
361 | static struct omap_hwmod omap2420_timer3_hwmod; | |
eddb1262 | 362 | |
eddb1262 TG |
363 | /* l4_core -> timer3 */ |
364 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { | |
365 | .master = &omap2420_l4_core_hwmod, | |
366 | .slave = &omap2420_timer3_hwmod, | |
367 | .clk = "gpt3_ick", | |
ded11383 | 368 | .addr = omap2xxx_timer3_addrs, |
eddb1262 TG |
369 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
370 | }; | |
371 | ||
372 | /* timer3 slave port */ | |
373 | static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { | |
374 | &omap2420_l4_core__timer3, | |
375 | }; | |
376 | ||
377 | /* timer3 hwmod */ | |
378 | static struct omap_hwmod omap2420_timer3_hwmod = { | |
379 | .name = "timer3", | |
0d619a89 | 380 | .mpu_irqs = omap2_timer3_mpu_irqs, |
eddb1262 TG |
381 | .main_clk = "gpt3_fck", |
382 | .prcm = { | |
383 | .omap2 = { | |
384 | .prcm_reg_id = 1, | |
385 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
386 | .module_offs = CORE_MOD, | |
387 | .idlest_reg_id = 1, | |
388 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
389 | }, | |
390 | }, | |
391 | .slaves = omap2420_timer3_slaves, | |
392 | .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), | |
273b9465 | 393 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
394 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
395 | }; | |
396 | ||
397 | /* timer4 */ | |
398 | static struct omap_hwmod omap2420_timer4_hwmod; | |
eddb1262 | 399 | |
eddb1262 TG |
400 | /* l4_core -> timer4 */ |
401 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { | |
402 | .master = &omap2420_l4_core_hwmod, | |
403 | .slave = &omap2420_timer4_hwmod, | |
404 | .clk = "gpt4_ick", | |
ded11383 | 405 | .addr = omap2xxx_timer4_addrs, |
eddb1262 TG |
406 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
407 | }; | |
408 | ||
409 | /* timer4 slave port */ | |
410 | static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { | |
411 | &omap2420_l4_core__timer4, | |
412 | }; | |
413 | ||
414 | /* timer4 hwmod */ | |
415 | static struct omap_hwmod omap2420_timer4_hwmod = { | |
416 | .name = "timer4", | |
0d619a89 | 417 | .mpu_irqs = omap2_timer4_mpu_irqs, |
eddb1262 TG |
418 | .main_clk = "gpt4_fck", |
419 | .prcm = { | |
420 | .omap2 = { | |
421 | .prcm_reg_id = 1, | |
422 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
423 | .module_offs = CORE_MOD, | |
424 | .idlest_reg_id = 1, | |
425 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
426 | }, | |
427 | }, | |
428 | .slaves = omap2420_timer4_slaves, | |
429 | .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), | |
273b9465 | 430 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
431 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
432 | }; | |
433 | ||
434 | /* timer5 */ | |
435 | static struct omap_hwmod omap2420_timer5_hwmod; | |
eddb1262 | 436 | |
eddb1262 TG |
437 | /* l4_core -> timer5 */ |
438 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { | |
439 | .master = &omap2420_l4_core_hwmod, | |
440 | .slave = &omap2420_timer5_hwmod, | |
441 | .clk = "gpt5_ick", | |
ded11383 | 442 | .addr = omap2xxx_timer5_addrs, |
eddb1262 TG |
443 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
444 | }; | |
445 | ||
446 | /* timer5 slave port */ | |
447 | static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { | |
448 | &omap2420_l4_core__timer5, | |
449 | }; | |
450 | ||
451 | /* timer5 hwmod */ | |
452 | static struct omap_hwmod omap2420_timer5_hwmod = { | |
453 | .name = "timer5", | |
0d619a89 | 454 | .mpu_irqs = omap2_timer5_mpu_irqs, |
eddb1262 TG |
455 | .main_clk = "gpt5_fck", |
456 | .prcm = { | |
457 | .omap2 = { | |
458 | .prcm_reg_id = 1, | |
459 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
460 | .module_offs = CORE_MOD, | |
461 | .idlest_reg_id = 1, | |
462 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
463 | }, | |
464 | }, | |
465 | .slaves = omap2420_timer5_slaves, | |
466 | .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), | |
273b9465 | 467 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
468 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
469 | }; | |
470 | ||
471 | ||
472 | /* timer6 */ | |
473 | static struct omap_hwmod omap2420_timer6_hwmod; | |
eddb1262 | 474 | |
eddb1262 TG |
475 | /* l4_core -> timer6 */ |
476 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { | |
477 | .master = &omap2420_l4_core_hwmod, | |
478 | .slave = &omap2420_timer6_hwmod, | |
479 | .clk = "gpt6_ick", | |
ded11383 | 480 | .addr = omap2xxx_timer6_addrs, |
eddb1262 TG |
481 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
482 | }; | |
483 | ||
484 | /* timer6 slave port */ | |
485 | static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { | |
486 | &omap2420_l4_core__timer6, | |
487 | }; | |
488 | ||
489 | /* timer6 hwmod */ | |
490 | static struct omap_hwmod omap2420_timer6_hwmod = { | |
491 | .name = "timer6", | |
0d619a89 | 492 | .mpu_irqs = omap2_timer6_mpu_irqs, |
eddb1262 TG |
493 | .main_clk = "gpt6_fck", |
494 | .prcm = { | |
495 | .omap2 = { | |
496 | .prcm_reg_id = 1, | |
497 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
498 | .module_offs = CORE_MOD, | |
499 | .idlest_reg_id = 1, | |
500 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
501 | }, | |
502 | }, | |
503 | .slaves = omap2420_timer6_slaves, | |
504 | .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), | |
273b9465 | 505 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
506 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
507 | }; | |
508 | ||
509 | /* timer7 */ | |
510 | static struct omap_hwmod omap2420_timer7_hwmod; | |
eddb1262 | 511 | |
eddb1262 TG |
512 | /* l4_core -> timer7 */ |
513 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { | |
514 | .master = &omap2420_l4_core_hwmod, | |
515 | .slave = &omap2420_timer7_hwmod, | |
516 | .clk = "gpt7_ick", | |
ded11383 | 517 | .addr = omap2xxx_timer7_addrs, |
eddb1262 TG |
518 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
519 | }; | |
520 | ||
521 | /* timer7 slave port */ | |
522 | static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { | |
523 | &omap2420_l4_core__timer7, | |
524 | }; | |
525 | ||
526 | /* timer7 hwmod */ | |
527 | static struct omap_hwmod omap2420_timer7_hwmod = { | |
528 | .name = "timer7", | |
0d619a89 | 529 | .mpu_irqs = omap2_timer7_mpu_irqs, |
eddb1262 TG |
530 | .main_clk = "gpt7_fck", |
531 | .prcm = { | |
532 | .omap2 = { | |
533 | .prcm_reg_id = 1, | |
534 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
535 | .module_offs = CORE_MOD, | |
536 | .idlest_reg_id = 1, | |
537 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
538 | }, | |
539 | }, | |
540 | .slaves = omap2420_timer7_slaves, | |
541 | .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), | |
273b9465 | 542 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
543 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
544 | }; | |
545 | ||
546 | /* timer8 */ | |
547 | static struct omap_hwmod omap2420_timer8_hwmod; | |
eddb1262 | 548 | |
eddb1262 TG |
549 | /* l4_core -> timer8 */ |
550 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { | |
551 | .master = &omap2420_l4_core_hwmod, | |
552 | .slave = &omap2420_timer8_hwmod, | |
553 | .clk = "gpt8_ick", | |
ded11383 | 554 | .addr = omap2xxx_timer8_addrs, |
eddb1262 TG |
555 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
556 | }; | |
557 | ||
558 | /* timer8 slave port */ | |
559 | static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { | |
560 | &omap2420_l4_core__timer8, | |
561 | }; | |
562 | ||
563 | /* timer8 hwmod */ | |
564 | static struct omap_hwmod omap2420_timer8_hwmod = { | |
565 | .name = "timer8", | |
0d619a89 | 566 | .mpu_irqs = omap2_timer8_mpu_irqs, |
eddb1262 TG |
567 | .main_clk = "gpt8_fck", |
568 | .prcm = { | |
569 | .omap2 = { | |
570 | .prcm_reg_id = 1, | |
571 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
572 | .module_offs = CORE_MOD, | |
573 | .idlest_reg_id = 1, | |
574 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
575 | }, | |
576 | }, | |
577 | .slaves = omap2420_timer8_slaves, | |
578 | .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), | |
273b9465 | 579 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
580 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
581 | }; | |
582 | ||
583 | /* timer9 */ | |
584 | static struct omap_hwmod omap2420_timer9_hwmod; | |
eddb1262 | 585 | |
eddb1262 TG |
586 | /* l4_core -> timer9 */ |
587 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { | |
588 | .master = &omap2420_l4_core_hwmod, | |
589 | .slave = &omap2420_timer9_hwmod, | |
590 | .clk = "gpt9_ick", | |
ded11383 | 591 | .addr = omap2xxx_timer9_addrs, |
eddb1262 TG |
592 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
593 | }; | |
594 | ||
595 | /* timer9 slave port */ | |
596 | static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { | |
597 | &omap2420_l4_core__timer9, | |
598 | }; | |
599 | ||
600 | /* timer9 hwmod */ | |
601 | static struct omap_hwmod omap2420_timer9_hwmod = { | |
602 | .name = "timer9", | |
0d619a89 | 603 | .mpu_irqs = omap2_timer9_mpu_irqs, |
eddb1262 TG |
604 | .main_clk = "gpt9_fck", |
605 | .prcm = { | |
606 | .omap2 = { | |
607 | .prcm_reg_id = 1, | |
608 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
609 | .module_offs = CORE_MOD, | |
610 | .idlest_reg_id = 1, | |
611 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
612 | }, | |
613 | }, | |
614 | .slaves = omap2420_timer9_slaves, | |
615 | .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), | |
273b9465 | 616 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
617 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
618 | }; | |
619 | ||
620 | /* timer10 */ | |
621 | static struct omap_hwmod omap2420_timer10_hwmod; | |
eddb1262 | 622 | |
eddb1262 TG |
623 | /* l4_core -> timer10 */ |
624 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { | |
625 | .master = &omap2420_l4_core_hwmod, | |
626 | .slave = &omap2420_timer10_hwmod, | |
627 | .clk = "gpt10_ick", | |
ded11383 | 628 | .addr = omap2_timer10_addrs, |
eddb1262 TG |
629 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
630 | }; | |
631 | ||
632 | /* timer10 slave port */ | |
633 | static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { | |
634 | &omap2420_l4_core__timer10, | |
635 | }; | |
636 | ||
637 | /* timer10 hwmod */ | |
638 | static struct omap_hwmod omap2420_timer10_hwmod = { | |
639 | .name = "timer10", | |
0d619a89 | 640 | .mpu_irqs = omap2_timer10_mpu_irqs, |
eddb1262 TG |
641 | .main_clk = "gpt10_fck", |
642 | .prcm = { | |
643 | .omap2 = { | |
644 | .prcm_reg_id = 1, | |
645 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
646 | .module_offs = CORE_MOD, | |
647 | .idlest_reg_id = 1, | |
648 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
649 | }, | |
650 | }, | |
651 | .slaves = omap2420_timer10_slaves, | |
652 | .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), | |
273b9465 | 653 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
654 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
655 | }; | |
656 | ||
657 | /* timer11 */ | |
658 | static struct omap_hwmod omap2420_timer11_hwmod; | |
eddb1262 | 659 | |
eddb1262 TG |
660 | /* l4_core -> timer11 */ |
661 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { | |
662 | .master = &omap2420_l4_core_hwmod, | |
663 | .slave = &omap2420_timer11_hwmod, | |
664 | .clk = "gpt11_ick", | |
ded11383 | 665 | .addr = omap2_timer11_addrs, |
eddb1262 TG |
666 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
667 | }; | |
668 | ||
669 | /* timer11 slave port */ | |
670 | static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { | |
671 | &omap2420_l4_core__timer11, | |
672 | }; | |
673 | ||
674 | /* timer11 hwmod */ | |
675 | static struct omap_hwmod omap2420_timer11_hwmod = { | |
676 | .name = "timer11", | |
0d619a89 | 677 | .mpu_irqs = omap2_timer11_mpu_irqs, |
eddb1262 TG |
678 | .main_clk = "gpt11_fck", |
679 | .prcm = { | |
680 | .omap2 = { | |
681 | .prcm_reg_id = 1, | |
682 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
683 | .module_offs = CORE_MOD, | |
684 | .idlest_reg_id = 1, | |
685 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
686 | }, | |
687 | }, | |
688 | .slaves = omap2420_timer11_slaves, | |
689 | .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), | |
273b9465 | 690 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
691 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
692 | }; | |
693 | ||
694 | /* timer12 */ | |
695 | static struct omap_hwmod omap2420_timer12_hwmod; | |
eddb1262 | 696 | |
eddb1262 TG |
697 | /* l4_core -> timer12 */ |
698 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { | |
699 | .master = &omap2420_l4_core_hwmod, | |
700 | .slave = &omap2420_timer12_hwmod, | |
701 | .clk = "gpt12_ick", | |
ded11383 | 702 | .addr = omap2xxx_timer12_addrs, |
eddb1262 TG |
703 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
704 | }; | |
705 | ||
706 | /* timer12 slave port */ | |
707 | static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { | |
708 | &omap2420_l4_core__timer12, | |
709 | }; | |
710 | ||
711 | /* timer12 hwmod */ | |
712 | static struct omap_hwmod omap2420_timer12_hwmod = { | |
713 | .name = "timer12", | |
0d619a89 | 714 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
eddb1262 TG |
715 | .main_clk = "gpt12_fck", |
716 | .prcm = { | |
717 | .omap2 = { | |
718 | .prcm_reg_id = 1, | |
719 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
720 | .module_offs = CORE_MOD, | |
721 | .idlest_reg_id = 1, | |
722 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
723 | }, | |
724 | }, | |
725 | .slaves = omap2420_timer12_slaves, | |
726 | .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), | |
273b9465 | 727 | .class = &omap2xxx_timer_hwmod_class, |
eddb1262 TG |
728 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) |
729 | }; | |
730 | ||
a714b9cf VC |
731 | /* l4_wkup -> wd_timer2 */ |
732 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { | |
733 | { | |
734 | .pa_start = 0x48022000, | |
735 | .pa_end = 0x4802207f, | |
736 | .flags = ADDR_TYPE_RT | |
737 | }, | |
78183f3f | 738 | { } |
a714b9cf VC |
739 | }; |
740 | ||
741 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { | |
742 | .master = &omap2420_l4_wkup_hwmod, | |
743 | .slave = &omap2420_wd_timer2_hwmod, | |
744 | .clk = "mpu_wdt_ick", | |
745 | .addr = omap2420_wd_timer2_addrs, | |
a714b9cf VC |
746 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
747 | }; | |
748 | ||
a714b9cf VC |
749 | /* wd_timer2 */ |
750 | static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { | |
751 | &omap2420_l4_wkup__wd_timer2, | |
752 | }; | |
753 | ||
754 | static struct omap_hwmod omap2420_wd_timer2_hwmod = { | |
755 | .name = "wd_timer2", | |
273b9465 | 756 | .class = &omap2xxx_wd_timer_hwmod_class, |
a714b9cf VC |
757 | .main_clk = "mpu_wdt_fck", |
758 | .prcm = { | |
759 | .omap2 = { | |
760 | .prcm_reg_id = 1, | |
761 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
762 | .module_offs = WKUP_MOD, | |
763 | .idlest_reg_id = 1, | |
764 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
765 | }, | |
766 | }, | |
767 | .slaves = omap2420_wd_timer2_slaves, | |
768 | .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves), | |
769 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
770 | }; | |
771 | ||
046465b7 KH |
772 | /* UART1 */ |
773 | ||
046465b7 KH |
774 | static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { |
775 | &omap2_l4_core__uart1, | |
776 | }; | |
777 | ||
778 | static struct omap_hwmod omap2420_uart1_hwmod = { | |
779 | .name = "uart1", | |
0d619a89 | 780 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 781 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 KH |
782 | .main_clk = "uart1_fck", |
783 | .prcm = { | |
784 | .omap2 = { | |
785 | .module_offs = CORE_MOD, | |
786 | .prcm_reg_id = 1, | |
787 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
788 | .idlest_reg_id = 1, | |
789 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
790 | }, | |
791 | }, | |
792 | .slaves = omap2420_uart1_slaves, | |
793 | .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), | |
273b9465 | 794 | .class = &omap2_uart_class, |
046465b7 KH |
795 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
796 | }; | |
797 | ||
798 | /* UART2 */ | |
799 | ||
046465b7 KH |
800 | static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { |
801 | &omap2_l4_core__uart2, | |
802 | }; | |
803 | ||
804 | static struct omap_hwmod omap2420_uart2_hwmod = { | |
805 | .name = "uart2", | |
0d619a89 | 806 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 807 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 KH |
808 | .main_clk = "uart2_fck", |
809 | .prcm = { | |
810 | .omap2 = { | |
811 | .module_offs = CORE_MOD, | |
812 | .prcm_reg_id = 1, | |
813 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
814 | .idlest_reg_id = 1, | |
815 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
816 | }, | |
817 | }, | |
818 | .slaves = omap2420_uart2_slaves, | |
819 | .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), | |
273b9465 | 820 | .class = &omap2_uart_class, |
046465b7 KH |
821 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
822 | }; | |
823 | ||
824 | /* UART3 */ | |
825 | ||
046465b7 KH |
826 | static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { |
827 | &omap2_l4_core__uart3, | |
828 | }; | |
829 | ||
830 | static struct omap_hwmod omap2420_uart3_hwmod = { | |
831 | .name = "uart3", | |
0d619a89 | 832 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 833 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
834 | .main_clk = "uart3_fck", |
835 | .prcm = { | |
836 | .omap2 = { | |
837 | .module_offs = CORE_MOD, | |
838 | .prcm_reg_id = 2, | |
839 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
840 | .idlest_reg_id = 2, | |
841 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
842 | }, | |
843 | }, | |
844 | .slaves = omap2420_uart3_slaves, | |
845 | .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), | |
273b9465 | 846 | .class = &omap2_uart_class, |
046465b7 KH |
847 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
848 | }; | |
849 | ||
996746ca SG |
850 | /* dss */ |
851 | /* dss master ports */ | |
852 | static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { | |
853 | &omap2420_dss__l3, | |
854 | }; | |
855 | ||
996746ca SG |
856 | /* l4_core -> dss */ |
857 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { | |
858 | .master = &omap2420_l4_core_hwmod, | |
859 | .slave = &omap2420_dss_core_hwmod, | |
860 | .clk = "dss_ick", | |
ded11383 | 861 | .addr = omap2_dss_addrs, |
996746ca SG |
862 | .fw = { |
863 | .omap2 = { | |
864 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
865 | .flags = OMAP_FIREWALL_L4, | |
866 | } | |
867 | }, | |
868 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
869 | }; | |
870 | ||
871 | /* dss slave ports */ | |
872 | static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { | |
873 | &omap2420_l4_core__dss, | |
874 | }; | |
875 | ||
876 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
877 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
878 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
879 | }; | |
880 | ||
881 | static struct omap_hwmod omap2420_dss_core_hwmod = { | |
882 | .name = "dss_core", | |
273b9465 | 883 | .class = &omap2_dss_hwmod_class, |
996746ca | 884 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
d826ebfa | 885 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
996746ca SG |
886 | .prcm = { |
887 | .omap2 = { | |
888 | .prcm_reg_id = 1, | |
889 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
890 | .module_offs = CORE_MOD, | |
891 | .idlest_reg_id = 1, | |
892 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
893 | }, | |
894 | }, | |
895 | .opt_clks = dss_opt_clks, | |
896 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
897 | .slaves = omap2420_dss_slaves, | |
898 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), | |
899 | .masters = omap2420_dss_masters, | |
900 | .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), | |
901 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
902 | .flags = HWMOD_NO_IDLEST, | |
903 | }; | |
904 | ||
996746ca SG |
905 | /* l4_core -> dss_dispc */ |
906 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { | |
907 | .master = &omap2420_l4_core_hwmod, | |
908 | .slave = &omap2420_dss_dispc_hwmod, | |
909 | .clk = "dss_ick", | |
ded11383 | 910 | .addr = omap2_dss_dispc_addrs, |
996746ca SG |
911 | .fw = { |
912 | .omap2 = { | |
913 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, | |
914 | .flags = OMAP_FIREWALL_L4, | |
915 | } | |
916 | }, | |
917 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
918 | }; | |
919 | ||
920 | /* dss_dispc slave ports */ | |
921 | static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { | |
922 | &omap2420_l4_core__dss_dispc, | |
923 | }; | |
924 | ||
925 | static struct omap_hwmod omap2420_dss_dispc_hwmod = { | |
926 | .name = "dss_dispc", | |
273b9465 | 927 | .class = &omap2_dispc_hwmod_class, |
0d619a89 | 928 | .mpu_irqs = omap2_dispc_irqs, |
996746ca SG |
929 | .main_clk = "dss1_fck", |
930 | .prcm = { | |
931 | .omap2 = { | |
932 | .prcm_reg_id = 1, | |
933 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
934 | .module_offs = CORE_MOD, | |
935 | .idlest_reg_id = 1, | |
936 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
937 | }, | |
938 | }, | |
939 | .slaves = omap2420_dss_dispc_slaves, | |
940 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), | |
941 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
942 | .flags = HWMOD_NO_IDLEST, | |
943 | }; | |
944 | ||
996746ca SG |
945 | /* l4_core -> dss_rfbi */ |
946 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { | |
947 | .master = &omap2420_l4_core_hwmod, | |
948 | .slave = &omap2420_dss_rfbi_hwmod, | |
949 | .clk = "dss_ick", | |
ded11383 | 950 | .addr = omap2_dss_rfbi_addrs, |
996746ca SG |
951 | .fw = { |
952 | .omap2 = { | |
953 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, | |
954 | .flags = OMAP_FIREWALL_L4, | |
955 | } | |
956 | }, | |
957 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
958 | }; | |
959 | ||
960 | /* dss_rfbi slave ports */ | |
961 | static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { | |
962 | &omap2420_l4_core__dss_rfbi, | |
963 | }; | |
964 | ||
965 | static struct omap_hwmod omap2420_dss_rfbi_hwmod = { | |
966 | .name = "dss_rfbi", | |
273b9465 | 967 | .class = &omap2_rfbi_hwmod_class, |
996746ca SG |
968 | .main_clk = "dss1_fck", |
969 | .prcm = { | |
970 | .omap2 = { | |
971 | .prcm_reg_id = 1, | |
972 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
973 | .module_offs = CORE_MOD, | |
974 | }, | |
975 | }, | |
976 | .slaves = omap2420_dss_rfbi_slaves, | |
977 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), | |
978 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
979 | .flags = HWMOD_NO_IDLEST, | |
980 | }; | |
981 | ||
996746ca SG |
982 | /* l4_core -> dss_venc */ |
983 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { | |
984 | .master = &omap2420_l4_core_hwmod, | |
985 | .slave = &omap2420_dss_venc_hwmod, | |
986 | .clk = "dss_54m_fck", | |
ded11383 | 987 | .addr = omap2_dss_venc_addrs, |
996746ca SG |
988 | .fw = { |
989 | .omap2 = { | |
990 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, | |
991 | .flags = OMAP_FIREWALL_L4, | |
992 | } | |
993 | }, | |
c39bee8a | 994 | .flags = OCPIF_SWSUP_IDLE, |
996746ca SG |
995 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
996 | }; | |
997 | ||
998 | /* dss_venc slave ports */ | |
999 | static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { | |
1000 | &omap2420_l4_core__dss_venc, | |
1001 | }; | |
1002 | ||
1003 | static struct omap_hwmod omap2420_dss_venc_hwmod = { | |
1004 | .name = "dss_venc", | |
273b9465 | 1005 | .class = &omap2_venc_hwmod_class, |
996746ca SG |
1006 | .main_clk = "dss1_fck", |
1007 | .prcm = { | |
1008 | .omap2 = { | |
1009 | .prcm_reg_id = 1, | |
1010 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1011 | .module_offs = CORE_MOD, | |
1012 | }, | |
1013 | }, | |
1014 | .slaves = omap2420_dss_venc_slaves, | |
1015 | .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), | |
1016 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1017 | .flags = HWMOD_NO_IDLEST, | |
1018 | }; | |
1019 | ||
2004290f PW |
1020 | /* I2C common */ |
1021 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1022 | .rev_offs = 0x00, | |
1023 | .sysc_offs = 0x20, | |
1024 | .syss_offs = 0x10, | |
d73d65fa | 1025 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
2004290f PW |
1026 | .sysc_fields = &omap_hwmod_sysc_type1, |
1027 | }; | |
1028 | ||
1029 | static struct omap_hwmod_class i2c_class = { | |
1030 | .name = "i2c", | |
1031 | .sysc = &i2c_sysc, | |
db791a75 | 1032 | .rev = OMAP_I2C_IP_VERSION_1, |
2004290f PW |
1033 | }; |
1034 | ||
4d4441a6 AG |
1035 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
1036 | .flags = OMAP_I2C_FLAG_NO_FIFO | | |
1037 | OMAP_I2C_FLAG_SIMPLE_CLOCK | | |
1038 | OMAP_I2C_FLAG_16BIT_DATA_REG | | |
1039 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
1040 | }; | |
2004290f PW |
1041 | |
1042 | /* I2C1 */ | |
1043 | ||
2004290f PW |
1044 | static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { |
1045 | &omap2420_l4_core__i2c1, | |
1046 | }; | |
1047 | ||
1048 | static struct omap_hwmod omap2420_i2c1_hwmod = { | |
1049 | .name = "i2c1", | |
0d619a89 | 1050 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 1051 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
1052 | .main_clk = "i2c1_fck", |
1053 | .prcm = { | |
1054 | .omap2 = { | |
1055 | .module_offs = CORE_MOD, | |
1056 | .prcm_reg_id = 1, | |
1057 | .module_bit = OMAP2420_EN_I2C1_SHIFT, | |
1058 | .idlest_reg_id = 1, | |
1059 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, | |
1060 | }, | |
1061 | }, | |
1062 | .slaves = omap2420_i2c1_slaves, | |
1063 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), | |
1064 | .class = &i2c_class, | |
1065 | .dev_attr = &i2c_dev_attr, | |
1066 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1067 | .flags = HWMOD_16BIT_REG, | |
1068 | }; | |
1069 | ||
1070 | /* I2C2 */ | |
1071 | ||
2004290f PW |
1072 | static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { |
1073 | &omap2420_l4_core__i2c2, | |
1074 | }; | |
1075 | ||
1076 | static struct omap_hwmod omap2420_i2c2_hwmod = { | |
1077 | .name = "i2c2", | |
0d619a89 | 1078 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 1079 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
1080 | .main_clk = "i2c2_fck", |
1081 | .prcm = { | |
1082 | .omap2 = { | |
1083 | .module_offs = CORE_MOD, | |
1084 | .prcm_reg_id = 1, | |
1085 | .module_bit = OMAP2420_EN_I2C2_SHIFT, | |
1086 | .idlest_reg_id = 1, | |
1087 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, | |
1088 | }, | |
1089 | }, | |
1090 | .slaves = omap2420_i2c2_slaves, | |
1091 | .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), | |
1092 | .class = &i2c_class, | |
1093 | .dev_attr = &i2c_dev_attr, | |
1094 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1095 | .flags = HWMOD_16BIT_REG, | |
1096 | }; | |
1097 | ||
59c348c3 VC |
1098 | /* l4_wkup -> gpio1 */ |
1099 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { | |
1100 | { | |
1101 | .pa_start = 0x48018000, | |
1102 | .pa_end = 0x480181ff, | |
1103 | .flags = ADDR_TYPE_RT | |
1104 | }, | |
78183f3f | 1105 | { } |
59c348c3 VC |
1106 | }; |
1107 | ||
1108 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { | |
1109 | .master = &omap2420_l4_wkup_hwmod, | |
1110 | .slave = &omap2420_gpio1_hwmod, | |
1111 | .clk = "gpios_ick", | |
1112 | .addr = omap2420_gpio1_addr_space, | |
59c348c3 VC |
1113 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1114 | }; | |
1115 | ||
1116 | /* l4_wkup -> gpio2 */ | |
1117 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { | |
1118 | { | |
1119 | .pa_start = 0x4801a000, | |
1120 | .pa_end = 0x4801a1ff, | |
1121 | .flags = ADDR_TYPE_RT | |
1122 | }, | |
78183f3f | 1123 | { } |
59c348c3 VC |
1124 | }; |
1125 | ||
1126 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { | |
1127 | .master = &omap2420_l4_wkup_hwmod, | |
1128 | .slave = &omap2420_gpio2_hwmod, | |
1129 | .clk = "gpios_ick", | |
1130 | .addr = omap2420_gpio2_addr_space, | |
59c348c3 VC |
1131 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1132 | }; | |
1133 | ||
1134 | /* l4_wkup -> gpio3 */ | |
1135 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { | |
1136 | { | |
1137 | .pa_start = 0x4801c000, | |
1138 | .pa_end = 0x4801c1ff, | |
1139 | .flags = ADDR_TYPE_RT | |
1140 | }, | |
78183f3f | 1141 | { } |
59c348c3 VC |
1142 | }; |
1143 | ||
1144 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { | |
1145 | .master = &omap2420_l4_wkup_hwmod, | |
1146 | .slave = &omap2420_gpio3_hwmod, | |
1147 | .clk = "gpios_ick", | |
1148 | .addr = omap2420_gpio3_addr_space, | |
59c348c3 VC |
1149 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1150 | }; | |
1151 | ||
1152 | /* l4_wkup -> gpio4 */ | |
1153 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { | |
1154 | { | |
1155 | .pa_start = 0x4801e000, | |
1156 | .pa_end = 0x4801e1ff, | |
1157 | .flags = ADDR_TYPE_RT | |
1158 | }, | |
78183f3f | 1159 | { } |
59c348c3 VC |
1160 | }; |
1161 | ||
1162 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { | |
1163 | .master = &omap2420_l4_wkup_hwmod, | |
1164 | .slave = &omap2420_gpio4_hwmod, | |
1165 | .clk = "gpios_ick", | |
1166 | .addr = omap2420_gpio4_addr_space, | |
59c348c3 VC |
1167 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1168 | }; | |
1169 | ||
1170 | /* gpio dev_attr */ | |
1171 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1172 | .bank_width = 32, | |
1173 | .dbck_flag = false, | |
1174 | }; | |
1175 | ||
59c348c3 | 1176 | /* gpio1 */ |
59c348c3 VC |
1177 | static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { |
1178 | &omap2420_l4_wkup__gpio1, | |
1179 | }; | |
1180 | ||
1181 | static struct omap_hwmod omap2420_gpio1_hwmod = { | |
1182 | .name = "gpio1", | |
f95440ca | 1183 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1184 | .mpu_irqs = omap2_gpio1_irqs, |
59c348c3 VC |
1185 | .main_clk = "gpios_fck", |
1186 | .prcm = { | |
1187 | .omap2 = { | |
1188 | .prcm_reg_id = 1, | |
1189 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1190 | .module_offs = WKUP_MOD, | |
1191 | .idlest_reg_id = 1, | |
1192 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1193 | }, | |
1194 | }, | |
1195 | .slaves = omap2420_gpio1_slaves, | |
1196 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), | |
273b9465 | 1197 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 VC |
1198 | .dev_attr = &gpio_dev_attr, |
1199 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1200 | }; | |
1201 | ||
1202 | /* gpio2 */ | |
59c348c3 VC |
1203 | static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { |
1204 | &omap2420_l4_wkup__gpio2, | |
1205 | }; | |
1206 | ||
1207 | static struct omap_hwmod omap2420_gpio2_hwmod = { | |
1208 | .name = "gpio2", | |
f95440ca | 1209 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1210 | .mpu_irqs = omap2_gpio2_irqs, |
59c348c3 VC |
1211 | .main_clk = "gpios_fck", |
1212 | .prcm = { | |
1213 | .omap2 = { | |
1214 | .prcm_reg_id = 1, | |
1215 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1216 | .module_offs = WKUP_MOD, | |
1217 | .idlest_reg_id = 1, | |
1218 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1219 | }, | |
1220 | }, | |
1221 | .slaves = omap2420_gpio2_slaves, | |
1222 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), | |
273b9465 | 1223 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 VC |
1224 | .dev_attr = &gpio_dev_attr, |
1225 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1226 | }; | |
1227 | ||
1228 | /* gpio3 */ | |
59c348c3 VC |
1229 | static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { |
1230 | &omap2420_l4_wkup__gpio3, | |
1231 | }; | |
1232 | ||
1233 | static struct omap_hwmod omap2420_gpio3_hwmod = { | |
1234 | .name = "gpio3", | |
f95440ca | 1235 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1236 | .mpu_irqs = omap2_gpio3_irqs, |
59c348c3 VC |
1237 | .main_clk = "gpios_fck", |
1238 | .prcm = { | |
1239 | .omap2 = { | |
1240 | .prcm_reg_id = 1, | |
1241 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1242 | .module_offs = WKUP_MOD, | |
1243 | .idlest_reg_id = 1, | |
1244 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1245 | }, | |
1246 | }, | |
1247 | .slaves = omap2420_gpio3_slaves, | |
1248 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), | |
273b9465 | 1249 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 VC |
1250 | .dev_attr = &gpio_dev_attr, |
1251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1252 | }; | |
1253 | ||
1254 | /* gpio4 */ | |
59c348c3 VC |
1255 | static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { |
1256 | &omap2420_l4_wkup__gpio4, | |
1257 | }; | |
1258 | ||
1259 | static struct omap_hwmod omap2420_gpio4_hwmod = { | |
1260 | .name = "gpio4", | |
f95440ca | 1261 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1262 | .mpu_irqs = omap2_gpio4_irqs, |
59c348c3 VC |
1263 | .main_clk = "gpios_fck", |
1264 | .prcm = { | |
1265 | .omap2 = { | |
1266 | .prcm_reg_id = 1, | |
1267 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1268 | .module_offs = WKUP_MOD, | |
1269 | .idlest_reg_id = 1, | |
1270 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1271 | }, | |
1272 | }, | |
1273 | .slaves = omap2420_gpio4_slaves, | |
1274 | .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), | |
273b9465 | 1275 | .class = &omap2xxx_gpio_hwmod_class, |
59c348c3 VC |
1276 | .dev_attr = &gpio_dev_attr, |
1277 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1278 | }; | |
1279 | ||
745685df MK |
1280 | /* dma attributes */ |
1281 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1282 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1283 | IS_CSSA_32 | IS_CDSA_32, | |
1284 | .lch_count = 32, | |
1285 | }; | |
1286 | ||
745685df MK |
1287 | /* dma_system -> L3 */ |
1288 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { | |
1289 | .master = &omap2420_dma_system_hwmod, | |
1290 | .slave = &omap2420_l3_main_hwmod, | |
1291 | .clk = "core_l3_ck", | |
1292 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1293 | }; | |
1294 | ||
1295 | /* dma_system master ports */ | |
1296 | static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = { | |
1297 | &omap2420_dma_system__l3, | |
1298 | }; | |
1299 | ||
1300 | /* l4_core -> dma_system */ | |
1301 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { | |
1302 | .master = &omap2420_l4_core_hwmod, | |
1303 | .slave = &omap2420_dma_system_hwmod, | |
1304 | .clk = "sdma_ick", | |
ded11383 | 1305 | .addr = omap2_dma_system_addrs, |
745685df MK |
1306 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1307 | }; | |
1308 | ||
1309 | /* dma_system slave ports */ | |
1310 | static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = { | |
1311 | &omap2420_l4_core__dma_system, | |
1312 | }; | |
1313 | ||
1314 | static struct omap_hwmod omap2420_dma_system_hwmod = { | |
1315 | .name = "dma", | |
273b9465 | 1316 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 1317 | .mpu_irqs = omap2_dma_system_irqs, |
745685df MK |
1318 | .main_clk = "core_l3_ck", |
1319 | .slaves = omap2420_dma_system_slaves, | |
1320 | .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), | |
1321 | .masters = omap2420_dma_system_masters, | |
1322 | .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters), | |
1323 | .dev_attr = &dma_dev_attr, | |
1324 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1325 | .flags = HWMOD_NO_IDLEST, | |
1326 | }; | |
1327 | ||
fca1ab55 ORL |
1328 | /* mailbox */ |
1329 | static struct omap_hwmod omap2420_mailbox_hwmod; | |
1330 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { | |
1331 | { .name = "dsp", .irq = 26 }, | |
1332 | { .name = "iva", .irq = 34 }, | |
212738a4 | 1333 | { .irq = -1 } |
fca1ab55 ORL |
1334 | }; |
1335 | ||
fca1ab55 ORL |
1336 | /* l4_core -> mailbox */ |
1337 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { | |
1338 | .master = &omap2420_l4_core_hwmod, | |
1339 | .slave = &omap2420_mailbox_hwmod, | |
ded11383 | 1340 | .addr = omap2_mailbox_addrs, |
fca1ab55 ORL |
1341 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1342 | }; | |
1343 | ||
1344 | /* mailbox slave ports */ | |
1345 | static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { | |
1346 | &omap2420_l4_core__mailbox, | |
1347 | }; | |
1348 | ||
1349 | static struct omap_hwmod omap2420_mailbox_hwmod = { | |
1350 | .name = "mailbox", | |
273b9465 | 1351 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 1352 | .mpu_irqs = omap2420_mailbox_irqs, |
fca1ab55 ORL |
1353 | .main_clk = "mailboxes_ick", |
1354 | .prcm = { | |
1355 | .omap2 = { | |
1356 | .prcm_reg_id = 1, | |
1357 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1358 | .module_offs = CORE_MOD, | |
1359 | .idlest_reg_id = 1, | |
1360 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
1361 | }, | |
1362 | }, | |
1363 | .slaves = omap2420_mailbox_slaves, | |
1364 | .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), | |
1365 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1366 | }; | |
1367 | ||
617871de | 1368 | /* mcspi1 */ |
617871de C |
1369 | static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { |
1370 | &omap2420_l4_core__mcspi1, | |
1371 | }; | |
1372 | ||
1373 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1374 | .num_chipselect = 4, | |
1375 | }; | |
1376 | ||
1377 | static struct omap_hwmod omap2420_mcspi1_hwmod = { | |
1378 | .name = "mcspi1_hwmod", | |
0d619a89 | 1379 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 1380 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
617871de C |
1381 | .main_clk = "mcspi1_fck", |
1382 | .prcm = { | |
1383 | .omap2 = { | |
1384 | .module_offs = CORE_MOD, | |
1385 | .prcm_reg_id = 1, | |
1386 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1387 | .idlest_reg_id = 1, | |
1388 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1389 | }, | |
1390 | }, | |
1391 | .slaves = omap2420_mcspi1_slaves, | |
1392 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), | |
273b9465 PW |
1393 | .class = &omap2xxx_mcspi_class, |
1394 | .dev_attr = &omap_mcspi1_dev_attr, | |
617871de C |
1395 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
1396 | }; | |
1397 | ||
1398 | /* mcspi2 */ | |
617871de C |
1399 | static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { |
1400 | &omap2420_l4_core__mcspi2, | |
1401 | }; | |
1402 | ||
1403 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1404 | .num_chipselect = 2, | |
1405 | }; | |
1406 | ||
1407 | static struct omap_hwmod omap2420_mcspi2_hwmod = { | |
1408 | .name = "mcspi2_hwmod", | |
0d619a89 | 1409 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 1410 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
617871de C |
1411 | .main_clk = "mcspi2_fck", |
1412 | .prcm = { | |
1413 | .omap2 = { | |
1414 | .module_offs = CORE_MOD, | |
1415 | .prcm_reg_id = 1, | |
1416 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1417 | .idlest_reg_id = 1, | |
1418 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1419 | }, | |
1420 | }, | |
1421 | .slaves = omap2420_mcspi2_slaves, | |
1422 | .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), | |
273b9465 PW |
1423 | .class = &omap2xxx_mcspi_class, |
1424 | .dev_attr = &omap_mcspi2_dev_attr, | |
617871de C |
1425 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
1426 | }; | |
1427 | ||
3cb72fa4 C |
1428 | /* |
1429 | * 'mcbsp' class | |
1430 | * multi channel buffered serial port controller | |
1431 | */ | |
1432 | ||
1433 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |
1434 | .name = "mcbsp", | |
1435 | }; | |
1436 | ||
1437 | /* mcbsp1 */ | |
1438 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | |
1439 | { .name = "tx", .irq = 59 }, | |
1440 | { .name = "rx", .irq = 60 }, | |
212738a4 | 1441 | { .irq = -1 } |
3cb72fa4 C |
1442 | }; |
1443 | ||
3cb72fa4 C |
1444 | /* l4_core -> mcbsp1 */ |
1445 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { | |
1446 | .master = &omap2420_l4_core_hwmod, | |
1447 | .slave = &omap2420_mcbsp1_hwmod, | |
1448 | .clk = "mcbsp1_ick", | |
ded11383 | 1449 | .addr = omap2_mcbsp1_addrs, |
3cb72fa4 C |
1450 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1451 | }; | |
1452 | ||
1453 | /* mcbsp1 slave ports */ | |
1454 | static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { | |
1455 | &omap2420_l4_core__mcbsp1, | |
1456 | }; | |
1457 | ||
1458 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { | |
1459 | .name = "mcbsp1", | |
1460 | .class = &omap2420_mcbsp_hwmod_class, | |
1461 | .mpu_irqs = omap2420_mcbsp1_irqs, | |
d826ebfa | 1462 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
3cb72fa4 C |
1463 | .main_clk = "mcbsp1_fck", |
1464 | .prcm = { | |
1465 | .omap2 = { | |
1466 | .prcm_reg_id = 1, | |
1467 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1468 | .module_offs = CORE_MOD, | |
1469 | .idlest_reg_id = 1, | |
1470 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
1471 | }, | |
1472 | }, | |
1473 | .slaves = omap2420_mcbsp1_slaves, | |
1474 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), | |
1475 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1476 | }; | |
1477 | ||
1478 | /* mcbsp2 */ | |
1479 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { | |
1480 | { .name = "tx", .irq = 62 }, | |
1481 | { .name = "rx", .irq = 63 }, | |
212738a4 | 1482 | { .irq = -1 } |
3cb72fa4 C |
1483 | }; |
1484 | ||
3cb72fa4 C |
1485 | /* l4_core -> mcbsp2 */ |
1486 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { | |
1487 | .master = &omap2420_l4_core_hwmod, | |
1488 | .slave = &omap2420_mcbsp2_hwmod, | |
1489 | .clk = "mcbsp2_ick", | |
ded11383 | 1490 | .addr = omap2xxx_mcbsp2_addrs, |
3cb72fa4 C |
1491 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1492 | }; | |
1493 | ||
1494 | /* mcbsp2 slave ports */ | |
1495 | static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { | |
1496 | &omap2420_l4_core__mcbsp2, | |
1497 | }; | |
1498 | ||
1499 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { | |
1500 | .name = "mcbsp2", | |
1501 | .class = &omap2420_mcbsp_hwmod_class, | |
1502 | .mpu_irqs = omap2420_mcbsp2_irqs, | |
d826ebfa | 1503 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
3cb72fa4 C |
1504 | .main_clk = "mcbsp2_fck", |
1505 | .prcm = { | |
1506 | .omap2 = { | |
1507 | .prcm_reg_id = 1, | |
1508 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1509 | .module_offs = CORE_MOD, | |
1510 | .idlest_reg_id = 1, | |
1511 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
1512 | }, | |
1513 | }, | |
1514 | .slaves = omap2420_mcbsp2_slaves, | |
1515 | .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), | |
1516 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | |
1517 | }; | |
1518 | ||
02bfc030 | 1519 | static __initdata struct omap_hwmod *omap2420_hwmods[] = { |
4a7cf90a | 1520 | &omap2420_l3_main_hwmod, |
02bfc030 PW |
1521 | &omap2420_l4_core_hwmod, |
1522 | &omap2420_l4_wkup_hwmod, | |
1523 | &omap2420_mpu_hwmod, | |
08072acf | 1524 | &omap2420_iva_hwmod, |
eddb1262 TG |
1525 | |
1526 | &omap2420_timer1_hwmod, | |
1527 | &omap2420_timer2_hwmod, | |
1528 | &omap2420_timer3_hwmod, | |
1529 | &omap2420_timer4_hwmod, | |
1530 | &omap2420_timer5_hwmod, | |
1531 | &omap2420_timer6_hwmod, | |
1532 | &omap2420_timer7_hwmod, | |
1533 | &omap2420_timer8_hwmod, | |
1534 | &omap2420_timer9_hwmod, | |
1535 | &omap2420_timer10_hwmod, | |
1536 | &omap2420_timer11_hwmod, | |
1537 | &omap2420_timer12_hwmod, | |
1538 | ||
a714b9cf | 1539 | &omap2420_wd_timer2_hwmod, |
046465b7 KH |
1540 | &omap2420_uart1_hwmod, |
1541 | &omap2420_uart2_hwmod, | |
1542 | &omap2420_uart3_hwmod, | |
996746ca SG |
1543 | /* dss class */ |
1544 | &omap2420_dss_core_hwmod, | |
1545 | &omap2420_dss_dispc_hwmod, | |
1546 | &omap2420_dss_rfbi_hwmod, | |
1547 | &omap2420_dss_venc_hwmod, | |
1548 | /* i2c class */ | |
2004290f PW |
1549 | &omap2420_i2c1_hwmod, |
1550 | &omap2420_i2c2_hwmod, | |
59c348c3 VC |
1551 | |
1552 | /* gpio class */ | |
1553 | &omap2420_gpio1_hwmod, | |
1554 | &omap2420_gpio2_hwmod, | |
1555 | &omap2420_gpio3_hwmod, | |
1556 | &omap2420_gpio4_hwmod, | |
745685df MK |
1557 | |
1558 | /* dma_system class*/ | |
1559 | &omap2420_dma_system_hwmod, | |
617871de | 1560 | |
fca1ab55 ORL |
1561 | /* mailbox class */ |
1562 | &omap2420_mailbox_hwmod, | |
1563 | ||
3cb72fa4 C |
1564 | /* mcbsp class */ |
1565 | &omap2420_mcbsp1_hwmod, | |
1566 | &omap2420_mcbsp2_hwmod, | |
1567 | ||
617871de C |
1568 | /* mcspi class */ |
1569 | &omap2420_mcspi1_hwmod, | |
1570 | &omap2420_mcspi2_hwmod, | |
02bfc030 PW |
1571 | NULL, |
1572 | }; | |
1573 | ||
7359154e PW |
1574 | int __init omap2420_hwmod_init(void) |
1575 | { | |
550c8092 | 1576 | return omap_hwmod_register(omap2420_hwmods); |
7359154e | 1577 | } |