[mirror_ubuntu-eoan-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_2420_data.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
 * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */

#include <linux/platform_data/i2c-omap.h>
#include <linux/omap-dma.h>

#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include "l4_2xxx.h"

#include "omap_hwmod_common_data.h"

#include "cm-regbits-24xx.h"
#include "prm-regbits-24xx.h"
#include "i2c.h"
#include "mmc.h"
#include "serial.h"
#include "wd_timer.h"

/*
 * OMAP2420 hardware module integration data
 *
 * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

/*
 * IP blocks
 */

/* IVA1 (IVA1) */
static struct omap_hwmod_class iva1_hwmod_class = {
	.name		= "iva1",
};

static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	{ .name = "iva", .rst_shift = 8 },
};

static struct omap_hwmod omap2420_iva_hwmod = {
	.name		= "iva",
	.class		= &iva1_hwmod_class,
	.clkdm_name	= "iva1_clkdm",
	.rst_lines	= omap2420_iva_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
	.main_clk	= "iva1_ifck",
};

/* DSP */
static struct omap_hwmod_class dsp_hwmod_class = {
	.name		= "dsp",
};

static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	{ .name = "logic", .rst_shift = 0 },
	{ .name = "mmu", .rst_shift = 1 },
};

static struct omap_hwmod omap2420_dsp_hwmod = {
	.name		= "dsp",
	.class		= &dsp_hwmod_class,
	.clkdm_name	= "dsp_clkdm",
	.rst_lines	= omap2420_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
	.main_clk	= "dsp_fck",
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
	.reset		= &omap_i2c_reset,
};

/* I2C1 */
static struct omap_hwmod omap2420_i2c1_hwmod = {
	.name		= "i2c1",
	.main_clk	= "i2c1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
		},
	},
	.class		= &i2c_class,
	/*
	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	 * while a transfer is active seems to cause the I2C block to
	 * timeout. Why? Good question."
	 */
	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
};

/* I2C2 */
static struct omap_hwmod omap2420_i2c2_hwmod = {
	.name		= "i2c2",
	.main_clk	= "i2c2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
		},
	},
	.class		= &i2c_class,
	.flags		= HWMOD_16BIT_REG,
};

/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
						IS_CSSA_32 | IS_CDSA_32,
	.lch_count = 32,
};

static struct omap_hwmod omap2420_dma_system_hwmod = {
	.name		= "dma",
	.class		= &omap2xxx_dma_hwmod_class,
	.main_clk	= "core_l3_ck",
	.dev_attr	= &dma_dev_attr,
	.flags		= HWMOD_NO_IDLEST,
};

/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod = {
	.name		= "mailbox",
	.class		= &omap2xxx_mailbox_hwmod_class,
	.main_clk	= "mailboxes_ick",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
		},
	},
};

/*
 * 'mcbsp' class
 * multi channel buffered serial port controller
 */

static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	.name = "mcbsp",
};

static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	{ .role = "prcm_fck", .clk = "func_96m_ck" },
};

/* mcbsp1 */
static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	.name		= "mcbsp1",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

/* mcbsp2 */
static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	.name		= "mcbsp2",
	.class		= &omap2420_mcbsp_hwmod_class,
	.main_clk	= "mcbsp2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
		},
	},
	.opt_clks	= mcbsp_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
};

static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	.rev_offs	= 0x3c,
	.sysc_offs	= 0x64,
	.syss_offs	= 0x68,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	.name	= "msdi",
	.sysc	= &omap2420_msdi_sysc,
	.reset	= &omap_msdi_reset,
};

/* msdi1 */
static struct omap_hwmod omap2420_msdi1_hwmod = {
	.name		= "msdi1",
	.class		= &omap2420_msdi_hwmod_class,
	.main_clk	= "mmc_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
		},
	},
	.flags		= HWMOD_16BIT_REG,
};

/* HDQ1W/1-wire */
static struct omap_hwmod omap2420_hdq1w_hwmod = {
	.name		= "hdq1w",
	.main_clk	= "hdq_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
		},
	},
	.class		= &omap2_hdq1w_class,
};

/*
 * interfaces
 */

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* IVA <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__iva = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_iva_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* DSP <- L3 interface */
static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2420_dsp_hwmod,
	.clk		= "dsp_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> timer1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_timer1_hwmod,
	.clk		= "gpt1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio1_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio2 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio2_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio3 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio3_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup -> gpio4 */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_gpio4_hwmod,
	.clk		= "gpios_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	.master		= &omap2420_dma_system_hwmod,
	.slave		= &omap2xxx_l3_main_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_dma_system_hwmod,
	.clk		= "sdma_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mailbox_hwmod,
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp1_hwmod,
	.clk		= "mcbsp1_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> mcbsp2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_mcbsp2_hwmod,
	.clk		= "mcbsp2_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> msdi1 */
static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_msdi1_hwmod,
	.clk		= "mmc_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_core -> hdq1w interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	.master		= &omap2xxx_l4_core_hwmod,
	.slave		= &omap2420_hdq1w_hwmod,
	.clk		= "hdq_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
};


/* l4_wkup -> 32ksync_counter */
static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	.master		= &omap2xxx_l4_wkup_hwmod,
	.slave		= &omap2xxx_counter_32k_hwmod,
	.clk		= "sync_32k_ick",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	.master		= &omap2xxx_l3_main_hwmod,
	.slave		= &omap2xxx_gpmc_hwmod,
	.clk		= "core_l3_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
	&omap2xxx_l3_main__l4_core,
	&omap2xxx_mpu__l3_main,
	&omap2xxx_dss__l3,
	&omap2xxx_l4_core__mcspi1,
	&omap2xxx_l4_core__mcspi2,
	&omap2xxx_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
	&omap2420_l4_core__i2c1,
	&omap2420_l4_core__i2c2,
	&omap2420_l3__iva,
	&omap2420_l3__dsp,
	&omap2420_l4_wkup__timer1,
	&omap2xxx_l4_core__timer2,
	&omap2xxx_l4_core__timer3,
	&omap2xxx_l4_core__timer4,
	&omap2xxx_l4_core__timer5,
	&omap2xxx_l4_core__timer6,
	&omap2xxx_l4_core__timer7,
	&omap2xxx_l4_core__timer8,
	&omap2xxx_l4_core__timer9,
	&omap2xxx_l4_core__timer10,
	&omap2xxx_l4_core__timer11,
	&omap2xxx_l4_core__timer12,
	&omap2420_l4_wkup__wd_timer2,
	&omap2xxx_l4_core__dss,
	&omap2xxx_l4_core__dss_dispc,
	&omap2xxx_l4_core__dss_rfbi,
	&omap2xxx_l4_core__dss_venc,
	&omap2420_l4_wkup__gpio1,
	&omap2420_l4_wkup__gpio2,
	&omap2420_l4_wkup__gpio3,
	&omap2420_l4_wkup__gpio4,
	&omap2420_dma_system__l3,
	&omap2420_l4_core__dma_system,
	&omap2420_l4_core__mailbox,
	&omap2420_l4_core__mcbsp1,
	&omap2420_l4_core__mcbsp2,
	&omap2420_l4_core__msdi1,
	&omap2xxx_l4_core__rng,
	&omap2xxx_l4_core__sham,
	&omap2xxx_l4_core__aes,
	&omap2420_l4_core__hdq1w,
	&omap2420_l4_wkup__counter_32k,
	&omap2420_l3__gpmc,
	NULL,
};

int __init omap2420_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
02bfc030	2	/*
7359154e	3	* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
02bfc030	4	*
78183f3f	5	* Copyright (C) 2009-2011 Nokia Corporation
0a78c5c5	6	* Copyright (C) 2012 Texas Instruments, Inc.
02bfc030 PW	7	* Paul Walmsley
02bfc030 PW	8	*
02bfc030	9	* XXX handle crossbar/shared link difference for L3?
7359154e	10	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	11	*/
3a8761c0	12
79fc540f	13	#include <linux/platform_data/i2c-omap.h>
45c3eb7d	14	#include <linux/omap-dma.h>
2a296c8f TL	15
2a296c8f TL	16	#include "omap_hwmod.h"
1e0f51a9	17	#include "l3_2xxx.h"
70606b1c	18	#include "l4_2xxx.h"
02bfc030	19
43b40992 PW	20	#include "omap_hwmod_common_data.h"
43b40992 PW	21
a714b9cf	22	#include "cm-regbits-24xx.h"
2004290f	23	#include "prm-regbits-24xx.h"
3a8761c0	24	#include "i2c.h"
68f39e74	25	#include "mmc.h"
3d82cbbb	26	#include "serial.h"
ff2516fb	27	#include "wd_timer.h"
02bfc030	28
7359154e PW	29	/*
	30	* OMAP2420 hardware module integration data
	31	*
844a3b63	32	* All of the data in this section should be autogeneratable from the
7359154e PW	33	* TI hardware database or other technical documentation. Data that
	34	* is driver-specific or driver-kernel integration-specific belongs
	35	* elsewhere.
	36	*/
	37
844a3b63 PW	38	/*
	39	* IP blocks
	40	*/
996746ca	41
3af35fbc PW	42	/* IVA1 (IVA1) */
	43	static struct omap_hwmod_class iva1_hwmod_class = {
	44	.name = "iva1",
	45	};
	46
	47	static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
	48	{ .name = "iva", .rst_shift = 8 },
	49	};
	50
08072acf PW	51	static struct omap_hwmod omap2420_iva_hwmod = {
08072acf PW	52	.name = "iva",
3af35fbc PW	53	.class = &iva1_hwmod_class,
	54	.clkdm_name = "iva1_clkdm",
	55	.rst_lines = omap2420_iva_resets,
	56	.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
	57	.main_clk = "iva1_ifck",
	58	};
	59
	60	/* DSP */
	61	static struct omap_hwmod_class dsp_hwmod_class = {
	62	.name = "dsp",
	63	};
	64
	65	static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
	66	{ .name = "logic", .rst_shift = 0 },
	67	{ .name = "mmu", .rst_shift = 1 },
	68	};
	69
	70	static struct omap_hwmod omap2420_dsp_hwmod = {
	71	.name = "dsp",
	72	.class = &dsp_hwmod_class,
	73	.clkdm_name = "dsp_clkdm",
	74	.rst_lines = omap2420_dsp_resets,
	75	.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
	76	.main_clk = "dsp_fck",
08072acf PW	77	};
08072acf PW	78
2004290f PW	79	/* I2C common */
	80	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	81	.rev_offs = 0x00,
	82	.sysc_offs = 0x20,
	83	.syss_offs = 0x10,
d73d65fa	84	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
2004290f PW	85	.sysc_fields = &omap_hwmod_sysc_type1,
	86	};
	87
	88	static struct omap_hwmod_class i2c_class = {
	89	.name = "i2c",
	90	.sysc = &i2c_sysc,
6d3c55fd	91	.reset = &omap_i2c_reset,
2004290f PW	92	};
2004290f PW	93
2004290f	94	/* I2C1 */
2004290f PW	95	static struct omap_hwmod omap2420_i2c1_hwmod = {
2004290f PW	96	.name = "i2c1",
2004290f PW	97	.main_clk = "i2c1_fck",
	98	.prcm = {
	99	.omap2 = {
	100	.module_offs = CORE_MOD,
2004290f PW	101	.idlest_reg_id = 1,
	102	.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
	103	},
	104	},
2004290f	105	.class = &i2c_class,
aff2f7d9 PW	106	/*
	107	* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
	108	* while a transfer is active seems to cause the I2C block to
	109	* timeout. Why? Good question."
	110	*/
	111	.flags = (HWMOD_16BIT_REG \| HWMOD_BLOCK_WFI),
2004290f PW	112	};
	113
	114	/* I2C2 */
2004290f PW	115	static struct omap_hwmod omap2420_i2c2_hwmod = {
2004290f PW	116	.name = "i2c2",
2004290f PW	117	.main_clk = "i2c2_fck",
	118	.prcm = {
	119	.omap2 = {
	120	.module_offs = CORE_MOD,
2004290f PW	121	.idlest_reg_id = 1,
	122	.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
	123	},
	124	},
2004290f	125	.class = &i2c_class,
2004290f PW	126	.flags = HWMOD_16BIT_REG,
	127	};
	128
745685df MK	129	/* dma attributes */
	130	static struct omap_dma_dev_attr dma_dev_attr = {
	131	.dev_caps = RESERVE_CHANNEL \| DMA_LINKED_LCH \| GLOBAL_PRIORITY \|
	132	IS_CSSA_32 \| IS_CDSA_32,
	133	.lch_count = 32,
	134	};
	135
745685df MK	136	static struct omap_hwmod omap2420_dma_system_hwmod = {
745685df MK	137	.name = "dma",
273b9465	138	.class = &omap2xxx_dma_hwmod_class,
745685df	139	.main_clk = "core_l3_ck",
745685df	140	.dev_attr = &dma_dev_attr,
745685df MK	141	.flags = HWMOD_NO_IDLEST,
	142	};
	143
fca1ab55	144	/* mailbox */
fca1ab55 ORL	145	static struct omap_hwmod omap2420_mailbox_hwmod = {
fca1ab55 ORL	146	.name = "mailbox",
273b9465	147	.class = &omap2xxx_mailbox_hwmod_class,
fca1ab55 ORL	148	.main_clk = "mailboxes_ick",
	149	.prcm = {
	150	.omap2 = {
fca1ab55 ORL	151	.module_offs = CORE_MOD,
	152	.idlest_reg_id = 1,
	153	.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
	154	},
	155	},
fca1ab55 ORL	156	};
fca1ab55 ORL	157
3cb72fa4 C	158	/*
	159	* 'mcbsp' class
	160	* multi channel buffered serial port controller
	161	*/
	162
	163	static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
	164	.name = "mcbsp",
	165	};
	166
b3153100 PU	167	static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
	168	{ .role = "pad_fck", .clk = "mcbsp_clks" },
	169	{ .role = "prcm_fck", .clk = "func_96m_ck" },
	170	};
	171
3cb72fa4	172	/* mcbsp1 */
3cb72fa4 C	173	static struct omap_hwmod omap2420_mcbsp1_hwmod = {
	174	.name = "mcbsp1",
	175	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	176	.main_clk = "mcbsp1_fck",
	177	.prcm = {
	178	.omap2 = {
3cb72fa4 C	179	.module_offs = CORE_MOD,
	180	.idlest_reg_id = 1,
	181	.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
	182	},
	183	},
b3153100 PU	184	.opt_clks = mcbsp_opt_clks,
b3153100 PU	185	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
3cb72fa4 C	186	};
	187
	188	/* mcbsp2 */
3cb72fa4 C	189	static struct omap_hwmod omap2420_mcbsp2_hwmod = {
	190	.name = "mcbsp2",
	191	.class = &omap2420_mcbsp_hwmod_class,
3cb72fa4 C	192	.main_clk = "mcbsp2_fck",
	193	.prcm = {
	194	.omap2 = {
3cb72fa4 C	195	.module_offs = CORE_MOD,
	196	.idlest_reg_id = 1,
	197	.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
	198	},
	199	},
b3153100 PU	200	.opt_clks = mcbsp_opt_clks,
b3153100 PU	201	.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
0a78c5c5 PW	202	};
0a78c5c5 PW	203
ad1b6662 TL	204	static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
	205	.rev_offs = 0x3c,
	206	.sysc_offs = 0x64,
	207	.syss_offs = 0x68,
	208	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSS_HAS_RESET_STATUS),
	209	.sysc_fields = &omap_hwmod_sysc_type1,
	210	};
	211
	212	static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
	213	.name = "msdi",
	214	.sysc = &omap2420_msdi_sysc,
	215	.reset = &omap_msdi_reset,
	216	};
	217
	218	/* msdi1 */
ad1b6662 TL	219	static struct omap_hwmod omap2420_msdi1_hwmod = {
	220	.name = "msdi1",
	221	.class = &omap2420_msdi_hwmod_class,
ad1b6662 TL	222	.main_clk = "mmc_fck",
	223	.prcm = {
	224	.omap2 = {
ad1b6662 TL	225	.module_offs = CORE_MOD,
	226	.idlest_reg_id = 1,
	227	.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
	228	},
	229	},
	230	.flags = HWMOD_16BIT_REG,
	231	};
	232
f32bd778 PW	233	/* HDQ1W/1-wire */
	234	static struct omap_hwmod omap2420_hdq1w_hwmod = {
	235	.name = "hdq1w",
f32bd778 PW	236	.main_clk = "hdq_fck",
	237	.prcm = {
	238	.omap2 = {
	239	.module_offs = CORE_MOD,
f32bd778 PW	240	.idlest_reg_id = 1,
	241	.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
	242	},
	243	},
	244	.class = &omap2_hdq1w_class,
	245	};
	246
844a3b63 PW	247	/*
	248	* interfaces
	249	*/
	250
844a3b63 PW	251	/* L4 CORE -> I2C1 interface */
844a3b63 PW	252	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
cb48427e	253	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	254	.slave = &omap2420_i2c1_hwmod,
844a3b63 PW	255	.clk = "i2c1_ick",
844a3b63 PW	256	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	257	};
	258
	259	/* L4 CORE -> I2C2 interface */
	260	static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
cb48427e	261	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	262	.slave = &omap2420_i2c2_hwmod,
844a3b63 PW	263	.clk = "i2c2_ick",
844a3b63 PW	264	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	265	};
	266
	267	/* IVA <- L3 interface */
	268	static struct omap_hwmod_ocp_if omap2420_l3__iva = {
cb48427e	269	.master = &omap2xxx_l3_main_hwmod,
844a3b63	270	.slave = &omap2420_iva_hwmod,
3af35fbc PW	271	.clk = "core_l3_ck",
	272	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	273	};
	274
	275	/* DSP <- L3 interface */
	276	static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
	277	.master = &omap2xxx_l3_main_hwmod,
	278	.slave = &omap2420_dsp_hwmod,
	279	.clk = "dsp_ick",
844a3b63 PW	280	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	281	};
	282
844a3b63 PW	283	/* l4_wkup -> timer1 */
844a3b63 PW	284	static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
cb48427e PW	285	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	286	.slave = &omap2xxx_timer1_hwmod,
844a3b63	287	.clk = "gpt1_ick",
844a3b63 PW	288	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	289	};
	290
844a3b63	291	/* l4_wkup -> wd_timer2 */
844a3b63	292	static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
cb48427e PW	293	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	294	.slave = &omap2xxx_wd_timer2_hwmod,
844a3b63	295	.clk = "mpu_wdt_ick",
844a3b63 PW	296	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	297	};
	298
844a3b63	299	/* l4_wkup -> gpio1 */
844a3b63	300	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
cb48427e PW	301	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	302	.slave = &omap2xxx_gpio1_hwmod,
844a3b63	303	.clk = "gpios_ick",
844a3b63 PW	304	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	305	};
	306
	307	/* l4_wkup -> gpio2 */
844a3b63	308	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
cb48427e PW	309	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	310	.slave = &omap2xxx_gpio2_hwmod,
844a3b63	311	.clk = "gpios_ick",
844a3b63 PW	312	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	313	};
	314
	315	/* l4_wkup -> gpio3 */
844a3b63	316	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
cb48427e PW	317	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	318	.slave = &omap2xxx_gpio3_hwmod,
844a3b63	319	.clk = "gpios_ick",
844a3b63 PW	320	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	321	};
	322
	323	/* l4_wkup -> gpio4 */
844a3b63	324	static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
cb48427e PW	325	.master = &omap2xxx_l4_wkup_hwmod,
cb48427e PW	326	.slave = &omap2xxx_gpio4_hwmod,
844a3b63	327	.clk = "gpios_ick",
844a3b63 PW	328	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	329	};
	330
	331	/* dma_system -> L3 */
	332	static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
	333	.master = &omap2420_dma_system_hwmod,
cb48427e	334	.slave = &omap2xxx_l3_main_hwmod,
844a3b63 PW	335	.clk = "core_l3_ck",
	336	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	337	};
	338
	339	/* l4_core -> dma_system */
	340	static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
cb48427e	341	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	342	.slave = &omap2420_dma_system_hwmod,
844a3b63 PW	343	.clk = "sdma_ick",
844a3b63 PW	344	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	345	};
	346
	347	/* l4_core -> mailbox */
	348	static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
cb48427e	349	.master = &omap2xxx_l4_core_hwmod,
844a3b63	350	.slave = &omap2420_mailbox_hwmod,
844a3b63 PW	351	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	352	};
	353
	354	/* l4_core -> mcbsp1 */
	355	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
cb48427e	356	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	357	.slave = &omap2420_mcbsp1_hwmod,
844a3b63 PW	358	.clk = "mcbsp1_ick",
844a3b63 PW	359	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	360	};
	361
	362	/* l4_core -> mcbsp2 */
	363	static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
cb48427e	364	.master = &omap2xxx_l4_core_hwmod,
844a3b63 PW	365	.slave = &omap2420_mcbsp2_hwmod,
844a3b63 PW	366	.clk = "mcbsp2_ick",
844a3b63 PW	367	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	368	};
	369
ad1b6662 TL	370	/* l4_core -> msdi1 */
	371	static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
	372	.master = &omap2xxx_l4_core_hwmod,
	373	.slave = &omap2420_msdi1_hwmod,
	374	.clk = "mmc_ick",
ad1b6662 TL	375	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	376	};
	377
f32bd778 PW	378	/* l4_core -> hdq1w interface */
	379	static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
	380	.master = &omap2xxx_l4_core_hwmod,
	381	.slave = &omap2420_hdq1w_hwmod,
	382	.clk = "hdq_ick",
f32bd778 PW	383	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	384	.flags = OMAP_FIREWALL_L4 \| OCPIF_SWSUP_IDLE,
	385	};
	386
	387
c8d82ff6	388	/* l4_wkup -> 32ksync_counter */
c8d82ff6 VH	389	static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
	390	.master = &omap2xxx_l4_wkup_hwmod,
	391	.slave = &omap2xxx_counter_32k_hwmod,
	392	.clk = "sync_32k_ick",
c8d82ff6 VH	393	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	394	};
	395
49484a60 AM	396	static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
	397	.master = &omap2xxx_l3_main_hwmod,
	398	.slave = &omap2xxx_gpmc_hwmod,
	399	.clk = "core_l3_ck",
49484a60 AM	400	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	401	};
	402
0a78c5c5	403	static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
6a29755f PW	404	&omap2xxx_l3_main__l4_core,
	405	&omap2xxx_mpu__l3_main,
	406	&omap2xxx_dss__l3,
	407	&omap2xxx_l4_core__mcspi1,
	408	&omap2xxx_l4_core__mcspi2,
	409	&omap2xxx_l4_core__l4_wkup,
0a78c5c5 PW	410	&omap2_l4_core__uart1,
	411	&omap2_l4_core__uart2,
	412	&omap2_l4_core__uart3,
	413	&omap2420_l4_core__i2c1,
	414	&omap2420_l4_core__i2c2,
	415	&omap2420_l3__iva,
3af35fbc	416	&omap2420_l3__dsp,
0a78c5c5	417	&omap2420_l4_wkup__timer1,
6a29755f PW	418	&omap2xxx_l4_core__timer2,
	419	&omap2xxx_l4_core__timer3,
	420	&omap2xxx_l4_core__timer4,
	421	&omap2xxx_l4_core__timer5,
	422	&omap2xxx_l4_core__timer6,
	423	&omap2xxx_l4_core__timer7,
	424	&omap2xxx_l4_core__timer8,
	425	&omap2xxx_l4_core__timer9,
	426	&omap2xxx_l4_core__timer10,
	427	&omap2xxx_l4_core__timer11,
	428	&omap2xxx_l4_core__timer12,
0a78c5c5	429	&omap2420_l4_wkup__wd_timer2,
6a29755f PW	430	&omap2xxx_l4_core__dss,
	431	&omap2xxx_l4_core__dss_dispc,
	432	&omap2xxx_l4_core__dss_rfbi,
	433	&omap2xxx_l4_core__dss_venc,
0a78c5c5 PW	434	&omap2420_l4_wkup__gpio1,
	435	&omap2420_l4_wkup__gpio2,
	436	&omap2420_l4_wkup__gpio3,
	437	&omap2420_l4_wkup__gpio4,
	438	&omap2420_dma_system__l3,
	439	&omap2420_l4_core__dma_system,
	440	&omap2420_l4_core__mailbox,
	441	&omap2420_l4_core__mcbsp1,
	442	&omap2420_l4_core__mcbsp2,
ad1b6662	443	&omap2420_l4_core__msdi1,
e9b0a2fb	444	&omap2xxx_l4_core__rng,
e569e994	445	&omap2xxx_l4_core__sham,
660ffd6b	446	&omap2xxx_l4_core__aes,
f32bd778	447	&omap2420_l4_core__hdq1w,
c8d82ff6	448	&omap2420_l4_wkup__counter_32k,
49484a60	449	&omap2420_l3__gpmc,
02bfc030 PW	450	NULL,
	451	};
	452
7359154e PW	453	int __init omap2420_hwmod_init(void)
7359154e PW	454	{
9ebfd285	455	omap_hwmod_init();
0a78c5c5	456	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
7359154e	457	}