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Commit | Line | Data |
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02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
37801b3d | 21 | #include <plat/mcbsp.h> |
7f904c78 | 22 | #include <plat/mcspi.h> |
b6b58229 | 23 | #include <plat/dmtimer.h> |
6ab8946f | 24 | #include <plat/mmc.h> |
de56dbb6 | 25 | #include <plat/l3_2xxx.h> |
02bfc030 | 26 | |
43b40992 PW |
27 | #include "omap_hwmod_common_data.h" |
28 | ||
02bfc030 | 29 | #include "prm-regbits-24xx.h" |
165e2161 | 30 | #include "cm-regbits-24xx.h" |
ff2516fb | 31 | #include "wd_timer.h" |
02bfc030 | 32 | |
7359154e PW |
33 | /* |
34 | * OMAP2430 hardware module integration data | |
35 | * | |
36 | * ALl of the data in this section should be autogeneratable from the | |
37 | * TI hardware database or other technical documentation. Data that | |
38 | * is driver-specific or driver-kernel integration-specific belongs | |
39 | * elsewhere. | |
40 | */ | |
41 | ||
02bfc030 | 42 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 43 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 44 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 45 | static struct omap_hwmod omap2430_l4_core_hwmod; |
de56dbb6 SG |
46 | static struct omap_hwmod omap2430_dss_core_hwmod; |
47 | static struct omap_hwmod omap2430_dss_dispc_hwmod; | |
48 | static struct omap_hwmod omap2430_dss_rfbi_hwmod; | |
49 | static struct omap_hwmod omap2430_dss_venc_hwmod; | |
165e2161 | 50 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
51 | static struct omap_hwmod omap2430_gpio1_hwmod; |
52 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
53 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
54 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
55 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 56 | static struct omap_hwmod omap2430_dma_system_hwmod; |
37801b3d C |
57 | static struct omap_hwmod omap2430_mcbsp1_hwmod; |
58 | static struct omap_hwmod omap2430_mcbsp2_hwmod; | |
59 | static struct omap_hwmod omap2430_mcbsp3_hwmod; | |
60 | static struct omap_hwmod omap2430_mcbsp4_hwmod; | |
61 | static struct omap_hwmod omap2430_mcbsp5_hwmod; | |
7f904c78 C |
62 | static struct omap_hwmod omap2430_mcspi1_hwmod; |
63 | static struct omap_hwmod omap2430_mcspi2_hwmod; | |
64 | static struct omap_hwmod omap2430_mcspi3_hwmod; | |
bce06f37 PW |
65 | static struct omap_hwmod omap2430_mmc1_hwmod; |
66 | static struct omap_hwmod omap2430_mmc2_hwmod; | |
02bfc030 PW |
67 | |
68 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
69 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
70 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
71 | .slave = &omap2430_l4_core_hwmod, |
72 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
73 | }; | |
74 | ||
75 | /* MPU -> L3 interface */ | |
4a7cf90a | 76 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 77 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 78 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
79 | .user = OCP_USER_MPU, |
80 | }; | |
81 | ||
82 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
83 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
84 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
85 | }; |
86 | ||
de56dbb6 SG |
87 | /* DSS -> l3 */ |
88 | static struct omap_hwmod_ocp_if omap2430_dss__l3 = { | |
89 | .master = &omap2430_dss_core_hwmod, | |
90 | .slave = &omap2430_l3_main_hwmod, | |
91 | .fw = { | |
92 | .omap2 = { | |
93 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
94 | .flags = OMAP_FIREWALL_L3, | |
95 | } | |
96 | }, | |
97 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
98 | }; | |
99 | ||
02bfc030 | 100 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
101 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
102 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
103 | }; |
104 | ||
105 | /* L3 */ | |
4a7cf90a | 106 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 107 | .name = "l3_main", |
43b40992 | 108 | .class = &l3_hwmod_class, |
4a7cf90a KH |
109 | .masters = omap2430_l3_main_masters, |
110 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
111 | .slaves = omap2430_l3_main_slaves, | |
112 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
113 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
114 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
115 | }; |
116 | ||
117 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
118 | static struct omap_hwmod omap2430_uart1_hwmod; |
119 | static struct omap_hwmod omap2430_uart2_hwmod; | |
120 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
121 | static struct omap_hwmod omap2430_i2c1_hwmod; |
122 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
123 | ||
44d02acf HH |
124 | static struct omap_hwmod omap2430_usbhsotg_hwmod; |
125 | ||
126 | /* l3_core -> usbhsotg interface */ | |
127 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
128 | .master = &omap2430_usbhsotg_hwmod, | |
129 | .slave = &omap2430_l3_main_hwmod, | |
130 | .clk = "core_l3_ck", | |
131 | .user = OCP_USER_MPU, | |
132 | }; | |
133 | ||
2004290f | 134 | /* L4 CORE -> I2C1 interface */ |
2004290f PW |
135 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { |
136 | .master = &omap2430_l4_core_hwmod, | |
137 | .slave = &omap2430_i2c1_hwmod, | |
138 | .clk = "i2c1_ick", | |
ded11383 | 139 | .addr = omap2_i2c1_addr_space, |
2004290f PW |
140 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
141 | }; | |
142 | ||
143 | /* L4 CORE -> I2C2 interface */ | |
2004290f PW |
144 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { |
145 | .master = &omap2430_l4_core_hwmod, | |
146 | .slave = &omap2430_i2c2_hwmod, | |
147 | .clk = "i2c2_ick", | |
ded11383 | 148 | .addr = omap2_i2c2_addr_space, |
2004290f PW |
149 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
150 | }; | |
02bfc030 PW |
151 | |
152 | /* L4_CORE -> L4_WKUP interface */ | |
153 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
154 | .master = &omap2430_l4_core_hwmod, | |
155 | .slave = &omap2430_l4_wkup_hwmod, | |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
157 | }; | |
158 | ||
046465b7 | 159 | /* L4 CORE -> UART1 interface */ |
046465b7 KH |
160 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
161 | .master = &omap2430_l4_core_hwmod, | |
162 | .slave = &omap2430_uart1_hwmod, | |
163 | .clk = "uart1_ick", | |
ded11383 | 164 | .addr = omap2xxx_uart1_addr_space, |
046465b7 KH |
165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
166 | }; | |
167 | ||
168 | /* L4 CORE -> UART2 interface */ | |
046465b7 KH |
169 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
170 | .master = &omap2430_l4_core_hwmod, | |
171 | .slave = &omap2430_uart2_hwmod, | |
172 | .clk = "uart2_ick", | |
ded11383 | 173 | .addr = omap2xxx_uart2_addr_space, |
046465b7 KH |
174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
175 | }; | |
176 | ||
177 | /* L4 PER -> UART3 interface */ | |
046465b7 KH |
178 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
179 | .master = &omap2430_l4_core_hwmod, | |
180 | .slave = &omap2430_uart3_hwmod, | |
181 | .clk = "uart3_ick", | |
ded11383 | 182 | .addr = omap2xxx_uart3_addr_space, |
046465b7 KH |
183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
184 | }; | |
185 | ||
44d02acf HH |
186 | /* |
187 | * usbhsotg interface data | |
188 | */ | |
189 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { | |
190 | { | |
191 | .pa_start = OMAP243X_HS_BASE, | |
192 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
193 | .flags = ADDR_TYPE_RT | |
194 | }, | |
195 | }; | |
196 | ||
197 | /* l4_core ->usbhsotg interface */ | |
198 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
199 | .master = &omap2430_l4_core_hwmod, | |
200 | .slave = &omap2430_usbhsotg_hwmod, | |
201 | .clk = "usb_l4_ick", | |
202 | .addr = omap2430_usbhsotg_addrs, | |
44d02acf HH |
203 | .user = OCP_USER_MPU, |
204 | }; | |
205 | ||
206 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { | |
207 | &omap2430_usbhsotg__l3, | |
208 | }; | |
209 | ||
210 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { | |
211 | &omap2430_l4_core__usbhsotg, | |
212 | }; | |
213 | ||
bce06f37 | 214 | /* L4 CORE -> MMC1 interface */ |
bce06f37 PW |
215 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { |
216 | .master = &omap2430_l4_core_hwmod, | |
217 | .slave = &omap2430_mmc1_hwmod, | |
218 | .clk = "mmchs1_ick", | |
219 | .addr = omap2430_mmc1_addr_space, | |
bce06f37 PW |
220 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
221 | }; | |
222 | ||
223 | /* L4 CORE -> MMC2 interface */ | |
bce06f37 PW |
224 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { |
225 | .master = &omap2430_l4_core_hwmod, | |
226 | .slave = &omap2430_mmc2_hwmod, | |
bce06f37 | 227 | .clk = "mmchs2_ick", |
78183f3f | 228 | .addr = omap2430_mmc2_addr_space, |
bce06f37 PW |
229 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
230 | }; | |
231 | ||
02bfc030 PW |
232 | /* Slave interfaces on the L4_CORE interconnect */ |
233 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 234 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
235 | }; |
236 | ||
237 | /* Master interfaces on the L4_CORE interconnect */ | |
238 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
239 | &omap2430_l4_core__l4_wkup, | |
bce06f37 PW |
240 | &omap2430_l4_core__mmc1, |
241 | &omap2430_l4_core__mmc2, | |
02bfc030 PW |
242 | }; |
243 | ||
244 | /* L4 CORE */ | |
245 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 246 | .name = "l4_core", |
43b40992 | 247 | .class = &l4_hwmod_class, |
02bfc030 PW |
248 | .masters = omap2430_l4_core_masters, |
249 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
250 | .slaves = omap2430_l4_core_slaves, | |
251 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
252 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
253 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
254 | }; |
255 | ||
256 | /* Slave interfaces on the L4_WKUP interconnect */ | |
257 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
258 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
259 | &omap2_l4_core__uart1, |
260 | &omap2_l4_core__uart2, | |
261 | &omap2_l4_core__uart3, | |
02bfc030 PW |
262 | }; |
263 | ||
264 | /* Master interfaces on the L4_WKUP interconnect */ | |
265 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
266 | }; | |
267 | ||
7f904c78 | 268 | /* l4 core -> mcspi1 interface */ |
7f904c78 C |
269 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { |
270 | .master = &omap2430_l4_core_hwmod, | |
271 | .slave = &omap2430_mcspi1_hwmod, | |
272 | .clk = "mcspi1_ick", | |
ded11383 | 273 | .addr = omap2_mcspi1_addr_space, |
7f904c78 C |
274 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
275 | }; | |
276 | ||
277 | /* l4 core -> mcspi2 interface */ | |
7f904c78 C |
278 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { |
279 | .master = &omap2430_l4_core_hwmod, | |
280 | .slave = &omap2430_mcspi2_hwmod, | |
281 | .clk = "mcspi2_ick", | |
ded11383 | 282 | .addr = omap2_mcspi2_addr_space, |
7f904c78 C |
283 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
284 | }; | |
285 | ||
286 | /* l4 core -> mcspi3 interface */ | |
7f904c78 C |
287 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { |
288 | .master = &omap2430_l4_core_hwmod, | |
289 | .slave = &omap2430_mcspi3_hwmod, | |
290 | .clk = "mcspi3_ick", | |
291 | .addr = omap2430_mcspi3_addr_space, | |
7f904c78 C |
292 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
293 | }; | |
294 | ||
02bfc030 PW |
295 | /* L4 WKUP */ |
296 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 297 | .name = "l4_wkup", |
43b40992 | 298 | .class = &l4_hwmod_class, |
02bfc030 PW |
299 | .masters = omap2430_l4_wkup_masters, |
300 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
301 | .slaves = omap2430_l4_wkup_slaves, | |
302 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
303 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
304 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
305 | }; |
306 | ||
307 | /* Master interfaces on the MPU device */ | |
308 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 309 | &omap2430_mpu__l3_main, |
02bfc030 PW |
310 | }; |
311 | ||
312 | /* MPU */ | |
313 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 314 | .name = "mpu", |
43b40992 | 315 | .class = &mpu_hwmod_class, |
50ebdac2 | 316 | .main_clk = "mpu_ck", |
02bfc030 PW |
317 | .masters = omap2430_mpu_masters, |
318 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
319 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
320 | }; | |
321 | ||
08072acf PW |
322 | /* |
323 | * IVA2_1 interface data | |
324 | */ | |
325 | ||
326 | /* IVA2 <- L3 interface */ | |
327 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
328 | .master = &omap2430_l3_main_hwmod, | |
329 | .slave = &omap2430_iva_hwmod, | |
330 | .clk = "dsp_fck", | |
331 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
332 | }; | |
333 | ||
334 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
335 | &omap2430_l3__iva, | |
336 | }; | |
337 | ||
338 | /* | |
339 | * IVA2 (IVA2) | |
340 | */ | |
341 | ||
342 | static struct omap_hwmod omap2430_iva_hwmod = { | |
343 | .name = "iva", | |
344 | .class = &iva_hwmod_class, | |
345 | .masters = omap2430_iva_masters, | |
346 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
347 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
348 | }; | |
349 | ||
b6b58229 TG |
350 | /* timer1 */ |
351 | static struct omap_hwmod omap2430_timer1_hwmod; | |
b6b58229 TG |
352 | |
353 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { | |
354 | { | |
355 | .pa_start = 0x49018000, | |
356 | .pa_end = 0x49018000 + SZ_1K - 1, | |
357 | .flags = ADDR_TYPE_RT | |
358 | }, | |
78183f3f | 359 | { } |
b6b58229 TG |
360 | }; |
361 | ||
362 | /* l4_wkup -> timer1 */ | |
363 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
364 | .master = &omap2430_l4_wkup_hwmod, | |
365 | .slave = &omap2430_timer1_hwmod, | |
366 | .clk = "gpt1_ick", | |
367 | .addr = omap2430_timer1_addrs, | |
b6b58229 TG |
368 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
369 | }; | |
370 | ||
371 | /* timer1 slave port */ | |
372 | static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { | |
373 | &omap2430_l4_wkup__timer1, | |
374 | }; | |
375 | ||
376 | /* timer1 hwmod */ | |
377 | static struct omap_hwmod omap2430_timer1_hwmod = { | |
378 | .name = "timer1", | |
0d619a89 | 379 | .mpu_irqs = omap2_timer1_mpu_irqs, |
b6b58229 TG |
380 | .main_clk = "gpt1_fck", |
381 | .prcm = { | |
382 | .omap2 = { | |
383 | .prcm_reg_id = 1, | |
384 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
385 | .module_offs = WKUP_MOD, | |
386 | .idlest_reg_id = 1, | |
387 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
388 | }, | |
389 | }, | |
390 | .slaves = omap2430_timer1_slaves, | |
391 | .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), | |
273b9465 | 392 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
393 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
394 | }; | |
395 | ||
396 | /* timer2 */ | |
397 | static struct omap_hwmod omap2430_timer2_hwmod; | |
b6b58229 | 398 | |
b6b58229 TG |
399 | /* l4_core -> timer2 */ |
400 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { | |
401 | .master = &omap2430_l4_core_hwmod, | |
402 | .slave = &omap2430_timer2_hwmod, | |
403 | .clk = "gpt2_ick", | |
ded11383 | 404 | .addr = omap2xxx_timer2_addrs, |
b6b58229 TG |
405 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
406 | }; | |
407 | ||
408 | /* timer2 slave port */ | |
409 | static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { | |
410 | &omap2430_l4_core__timer2, | |
411 | }; | |
412 | ||
413 | /* timer2 hwmod */ | |
414 | static struct omap_hwmod omap2430_timer2_hwmod = { | |
415 | .name = "timer2", | |
0d619a89 | 416 | .mpu_irqs = omap2_timer2_mpu_irqs, |
b6b58229 TG |
417 | .main_clk = "gpt2_fck", |
418 | .prcm = { | |
419 | .omap2 = { | |
420 | .prcm_reg_id = 1, | |
421 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
422 | .module_offs = CORE_MOD, | |
423 | .idlest_reg_id = 1, | |
424 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
425 | }, | |
426 | }, | |
427 | .slaves = omap2430_timer2_slaves, | |
428 | .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), | |
273b9465 | 429 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
430 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
431 | }; | |
432 | ||
433 | /* timer3 */ | |
434 | static struct omap_hwmod omap2430_timer3_hwmod; | |
b6b58229 | 435 | |
b6b58229 TG |
436 | /* l4_core -> timer3 */ |
437 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { | |
438 | .master = &omap2430_l4_core_hwmod, | |
439 | .slave = &omap2430_timer3_hwmod, | |
440 | .clk = "gpt3_ick", | |
ded11383 | 441 | .addr = omap2xxx_timer3_addrs, |
b6b58229 TG |
442 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
443 | }; | |
444 | ||
445 | /* timer3 slave port */ | |
446 | static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { | |
447 | &omap2430_l4_core__timer3, | |
448 | }; | |
449 | ||
450 | /* timer3 hwmod */ | |
451 | static struct omap_hwmod omap2430_timer3_hwmod = { | |
452 | .name = "timer3", | |
0d619a89 | 453 | .mpu_irqs = omap2_timer3_mpu_irqs, |
b6b58229 TG |
454 | .main_clk = "gpt3_fck", |
455 | .prcm = { | |
456 | .omap2 = { | |
457 | .prcm_reg_id = 1, | |
458 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
459 | .module_offs = CORE_MOD, | |
460 | .idlest_reg_id = 1, | |
461 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
462 | }, | |
463 | }, | |
464 | .slaves = omap2430_timer3_slaves, | |
465 | .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), | |
273b9465 | 466 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
467 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
468 | }; | |
469 | ||
470 | /* timer4 */ | |
471 | static struct omap_hwmod omap2430_timer4_hwmod; | |
b6b58229 | 472 | |
b6b58229 TG |
473 | /* l4_core -> timer4 */ |
474 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { | |
475 | .master = &omap2430_l4_core_hwmod, | |
476 | .slave = &omap2430_timer4_hwmod, | |
477 | .clk = "gpt4_ick", | |
ded11383 | 478 | .addr = omap2xxx_timer4_addrs, |
b6b58229 TG |
479 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
480 | }; | |
481 | ||
482 | /* timer4 slave port */ | |
483 | static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { | |
484 | &omap2430_l4_core__timer4, | |
485 | }; | |
486 | ||
487 | /* timer4 hwmod */ | |
488 | static struct omap_hwmod omap2430_timer4_hwmod = { | |
489 | .name = "timer4", | |
0d619a89 | 490 | .mpu_irqs = omap2_timer4_mpu_irqs, |
b6b58229 TG |
491 | .main_clk = "gpt4_fck", |
492 | .prcm = { | |
493 | .omap2 = { | |
494 | .prcm_reg_id = 1, | |
495 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
496 | .module_offs = CORE_MOD, | |
497 | .idlest_reg_id = 1, | |
498 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
499 | }, | |
500 | }, | |
501 | .slaves = omap2430_timer4_slaves, | |
502 | .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), | |
273b9465 | 503 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
504 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
505 | }; | |
506 | ||
507 | /* timer5 */ | |
508 | static struct omap_hwmod omap2430_timer5_hwmod; | |
b6b58229 | 509 | |
b6b58229 TG |
510 | /* l4_core -> timer5 */ |
511 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { | |
512 | .master = &omap2430_l4_core_hwmod, | |
513 | .slave = &omap2430_timer5_hwmod, | |
514 | .clk = "gpt5_ick", | |
ded11383 | 515 | .addr = omap2xxx_timer5_addrs, |
b6b58229 TG |
516 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
517 | }; | |
518 | ||
519 | /* timer5 slave port */ | |
520 | static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { | |
521 | &omap2430_l4_core__timer5, | |
522 | }; | |
523 | ||
524 | /* timer5 hwmod */ | |
525 | static struct omap_hwmod omap2430_timer5_hwmod = { | |
526 | .name = "timer5", | |
0d619a89 | 527 | .mpu_irqs = omap2_timer5_mpu_irqs, |
b6b58229 TG |
528 | .main_clk = "gpt5_fck", |
529 | .prcm = { | |
530 | .omap2 = { | |
531 | .prcm_reg_id = 1, | |
532 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
533 | .module_offs = CORE_MOD, | |
534 | .idlest_reg_id = 1, | |
535 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
536 | }, | |
537 | }, | |
538 | .slaves = omap2430_timer5_slaves, | |
539 | .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), | |
273b9465 | 540 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
541 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
542 | }; | |
543 | ||
544 | /* timer6 */ | |
545 | static struct omap_hwmod omap2430_timer6_hwmod; | |
b6b58229 | 546 | |
b6b58229 TG |
547 | /* l4_core -> timer6 */ |
548 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { | |
549 | .master = &omap2430_l4_core_hwmod, | |
550 | .slave = &omap2430_timer6_hwmod, | |
551 | .clk = "gpt6_ick", | |
ded11383 | 552 | .addr = omap2xxx_timer6_addrs, |
b6b58229 TG |
553 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
554 | }; | |
555 | ||
556 | /* timer6 slave port */ | |
557 | static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { | |
558 | &omap2430_l4_core__timer6, | |
559 | }; | |
560 | ||
561 | /* timer6 hwmod */ | |
562 | static struct omap_hwmod omap2430_timer6_hwmod = { | |
563 | .name = "timer6", | |
0d619a89 | 564 | .mpu_irqs = omap2_timer6_mpu_irqs, |
b6b58229 TG |
565 | .main_clk = "gpt6_fck", |
566 | .prcm = { | |
567 | .omap2 = { | |
568 | .prcm_reg_id = 1, | |
569 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
570 | .module_offs = CORE_MOD, | |
571 | .idlest_reg_id = 1, | |
572 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
573 | }, | |
574 | }, | |
575 | .slaves = omap2430_timer6_slaves, | |
576 | .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), | |
273b9465 | 577 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
578 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
579 | }; | |
580 | ||
581 | /* timer7 */ | |
582 | static struct omap_hwmod omap2430_timer7_hwmod; | |
b6b58229 | 583 | |
b6b58229 TG |
584 | /* l4_core -> timer7 */ |
585 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { | |
586 | .master = &omap2430_l4_core_hwmod, | |
587 | .slave = &omap2430_timer7_hwmod, | |
588 | .clk = "gpt7_ick", | |
ded11383 | 589 | .addr = omap2xxx_timer7_addrs, |
b6b58229 TG |
590 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
591 | }; | |
592 | ||
593 | /* timer7 slave port */ | |
594 | static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { | |
595 | &omap2430_l4_core__timer7, | |
596 | }; | |
597 | ||
598 | /* timer7 hwmod */ | |
599 | static struct omap_hwmod omap2430_timer7_hwmod = { | |
600 | .name = "timer7", | |
0d619a89 | 601 | .mpu_irqs = omap2_timer7_mpu_irqs, |
b6b58229 TG |
602 | .main_clk = "gpt7_fck", |
603 | .prcm = { | |
604 | .omap2 = { | |
605 | .prcm_reg_id = 1, | |
606 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
607 | .module_offs = CORE_MOD, | |
608 | .idlest_reg_id = 1, | |
609 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
610 | }, | |
611 | }, | |
612 | .slaves = omap2430_timer7_slaves, | |
613 | .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), | |
273b9465 | 614 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
615 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
616 | }; | |
617 | ||
618 | /* timer8 */ | |
619 | static struct omap_hwmod omap2430_timer8_hwmod; | |
b6b58229 | 620 | |
b6b58229 TG |
621 | /* l4_core -> timer8 */ |
622 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { | |
623 | .master = &omap2430_l4_core_hwmod, | |
624 | .slave = &omap2430_timer8_hwmod, | |
625 | .clk = "gpt8_ick", | |
ded11383 | 626 | .addr = omap2xxx_timer8_addrs, |
b6b58229 TG |
627 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
628 | }; | |
629 | ||
630 | /* timer8 slave port */ | |
631 | static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { | |
632 | &omap2430_l4_core__timer8, | |
633 | }; | |
634 | ||
635 | /* timer8 hwmod */ | |
636 | static struct omap_hwmod omap2430_timer8_hwmod = { | |
637 | .name = "timer8", | |
0d619a89 | 638 | .mpu_irqs = omap2_timer8_mpu_irqs, |
b6b58229 TG |
639 | .main_clk = "gpt8_fck", |
640 | .prcm = { | |
641 | .omap2 = { | |
642 | .prcm_reg_id = 1, | |
643 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
644 | .module_offs = CORE_MOD, | |
645 | .idlest_reg_id = 1, | |
646 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
647 | }, | |
648 | }, | |
649 | .slaves = omap2430_timer8_slaves, | |
650 | .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), | |
273b9465 | 651 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
652 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
653 | }; | |
654 | ||
655 | /* timer9 */ | |
656 | static struct omap_hwmod omap2430_timer9_hwmod; | |
b6b58229 | 657 | |
b6b58229 TG |
658 | /* l4_core -> timer9 */ |
659 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { | |
660 | .master = &omap2430_l4_core_hwmod, | |
661 | .slave = &omap2430_timer9_hwmod, | |
662 | .clk = "gpt9_ick", | |
ded11383 | 663 | .addr = omap2xxx_timer9_addrs, |
b6b58229 TG |
664 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
665 | }; | |
666 | ||
667 | /* timer9 slave port */ | |
668 | static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { | |
669 | &omap2430_l4_core__timer9, | |
670 | }; | |
671 | ||
672 | /* timer9 hwmod */ | |
673 | static struct omap_hwmod omap2430_timer9_hwmod = { | |
674 | .name = "timer9", | |
0d619a89 | 675 | .mpu_irqs = omap2_timer9_mpu_irqs, |
b6b58229 TG |
676 | .main_clk = "gpt9_fck", |
677 | .prcm = { | |
678 | .omap2 = { | |
679 | .prcm_reg_id = 1, | |
680 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
681 | .module_offs = CORE_MOD, | |
682 | .idlest_reg_id = 1, | |
683 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
684 | }, | |
685 | }, | |
686 | .slaves = omap2430_timer9_slaves, | |
687 | .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), | |
273b9465 | 688 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
689 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
690 | }; | |
691 | ||
692 | /* timer10 */ | |
693 | static struct omap_hwmod omap2430_timer10_hwmod; | |
b6b58229 | 694 | |
b6b58229 TG |
695 | /* l4_core -> timer10 */ |
696 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { | |
697 | .master = &omap2430_l4_core_hwmod, | |
698 | .slave = &omap2430_timer10_hwmod, | |
699 | .clk = "gpt10_ick", | |
ded11383 | 700 | .addr = omap2_timer10_addrs, |
b6b58229 TG |
701 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
702 | }; | |
703 | ||
704 | /* timer10 slave port */ | |
705 | static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { | |
706 | &omap2430_l4_core__timer10, | |
707 | }; | |
708 | ||
709 | /* timer10 hwmod */ | |
710 | static struct omap_hwmod omap2430_timer10_hwmod = { | |
711 | .name = "timer10", | |
0d619a89 | 712 | .mpu_irqs = omap2_timer10_mpu_irqs, |
b6b58229 TG |
713 | .main_clk = "gpt10_fck", |
714 | .prcm = { | |
715 | .omap2 = { | |
716 | .prcm_reg_id = 1, | |
717 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
718 | .module_offs = CORE_MOD, | |
719 | .idlest_reg_id = 1, | |
720 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
721 | }, | |
722 | }, | |
723 | .slaves = omap2430_timer10_slaves, | |
724 | .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), | |
273b9465 | 725 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
726 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
727 | }; | |
728 | ||
729 | /* timer11 */ | |
730 | static struct omap_hwmod omap2430_timer11_hwmod; | |
b6b58229 | 731 | |
b6b58229 TG |
732 | /* l4_core -> timer11 */ |
733 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { | |
734 | .master = &omap2430_l4_core_hwmod, | |
735 | .slave = &omap2430_timer11_hwmod, | |
736 | .clk = "gpt11_ick", | |
ded11383 | 737 | .addr = omap2_timer11_addrs, |
b6b58229 TG |
738 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
739 | }; | |
740 | ||
741 | /* timer11 slave port */ | |
742 | static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { | |
743 | &omap2430_l4_core__timer11, | |
744 | }; | |
745 | ||
746 | /* timer11 hwmod */ | |
747 | static struct omap_hwmod omap2430_timer11_hwmod = { | |
748 | .name = "timer11", | |
0d619a89 | 749 | .mpu_irqs = omap2_timer11_mpu_irqs, |
b6b58229 TG |
750 | .main_clk = "gpt11_fck", |
751 | .prcm = { | |
752 | .omap2 = { | |
753 | .prcm_reg_id = 1, | |
754 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
755 | .module_offs = CORE_MOD, | |
756 | .idlest_reg_id = 1, | |
757 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
758 | }, | |
759 | }, | |
760 | .slaves = omap2430_timer11_slaves, | |
761 | .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), | |
273b9465 | 762 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
763 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
764 | }; | |
765 | ||
766 | /* timer12 */ | |
767 | static struct omap_hwmod omap2430_timer12_hwmod; | |
b6b58229 | 768 | |
b6b58229 TG |
769 | /* l4_core -> timer12 */ |
770 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { | |
771 | .master = &omap2430_l4_core_hwmod, | |
772 | .slave = &omap2430_timer12_hwmod, | |
773 | .clk = "gpt12_ick", | |
ded11383 | 774 | .addr = omap2xxx_timer12_addrs, |
b6b58229 TG |
775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
776 | }; | |
777 | ||
778 | /* timer12 slave port */ | |
779 | static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { | |
780 | &omap2430_l4_core__timer12, | |
781 | }; | |
782 | ||
783 | /* timer12 hwmod */ | |
784 | static struct omap_hwmod omap2430_timer12_hwmod = { | |
785 | .name = "timer12", | |
0d619a89 | 786 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
b6b58229 TG |
787 | .main_clk = "gpt12_fck", |
788 | .prcm = { | |
789 | .omap2 = { | |
790 | .prcm_reg_id = 1, | |
791 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
792 | .module_offs = CORE_MOD, | |
793 | .idlest_reg_id = 1, | |
794 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
795 | }, | |
796 | }, | |
797 | .slaves = omap2430_timer12_slaves, | |
798 | .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), | |
273b9465 | 799 | .class = &omap2xxx_timer_hwmod_class, |
b6b58229 TG |
800 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) |
801 | }; | |
802 | ||
165e2161 VC |
803 | /* l4_wkup -> wd_timer2 */ |
804 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
805 | { | |
806 | .pa_start = 0x49016000, | |
807 | .pa_end = 0x4901607f, | |
808 | .flags = ADDR_TYPE_RT | |
809 | }, | |
78183f3f | 810 | { } |
165e2161 VC |
811 | }; |
812 | ||
813 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
814 | .master = &omap2430_l4_wkup_hwmod, | |
815 | .slave = &omap2430_wd_timer2_hwmod, | |
816 | .clk = "mpu_wdt_ick", | |
817 | .addr = omap2430_wd_timer2_addrs, | |
165e2161 VC |
818 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
819 | }; | |
820 | ||
165e2161 VC |
821 | /* wd_timer2 */ |
822 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
823 | &omap2430_l4_wkup__wd_timer2, | |
824 | }; | |
825 | ||
826 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
827 | .name = "wd_timer2", | |
273b9465 | 828 | .class = &omap2xxx_wd_timer_hwmod_class, |
165e2161 VC |
829 | .main_clk = "mpu_wdt_fck", |
830 | .prcm = { | |
831 | .omap2 = { | |
832 | .prcm_reg_id = 1, | |
833 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
834 | .module_offs = WKUP_MOD, | |
835 | .idlest_reg_id = 1, | |
836 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
837 | }, | |
838 | }, | |
839 | .slaves = omap2430_wd_timer2_slaves, | |
840 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
841 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
842 | }; | |
843 | ||
046465b7 KH |
844 | /* UART1 */ |
845 | ||
046465b7 KH |
846 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { |
847 | &omap2_l4_core__uart1, | |
848 | }; | |
849 | ||
850 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
851 | .name = "uart1", | |
0d619a89 | 852 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 853 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 KH |
854 | .main_clk = "uart1_fck", |
855 | .prcm = { | |
856 | .omap2 = { | |
857 | .module_offs = CORE_MOD, | |
858 | .prcm_reg_id = 1, | |
859 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
860 | .idlest_reg_id = 1, | |
861 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
862 | }, | |
863 | }, | |
864 | .slaves = omap2430_uart1_slaves, | |
865 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
273b9465 | 866 | .class = &omap2_uart_class, |
046465b7 KH |
867 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
868 | }; | |
869 | ||
870 | /* UART2 */ | |
871 | ||
046465b7 KH |
872 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { |
873 | &omap2_l4_core__uart2, | |
874 | }; | |
875 | ||
876 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
877 | .name = "uart2", | |
0d619a89 | 878 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 879 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 KH |
880 | .main_clk = "uart2_fck", |
881 | .prcm = { | |
882 | .omap2 = { | |
883 | .module_offs = CORE_MOD, | |
884 | .prcm_reg_id = 1, | |
885 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
886 | .idlest_reg_id = 1, | |
887 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
888 | }, | |
889 | }, | |
890 | .slaves = omap2430_uart2_slaves, | |
891 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
273b9465 | 892 | .class = &omap2_uart_class, |
046465b7 KH |
893 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
894 | }; | |
895 | ||
896 | /* UART3 */ | |
897 | ||
046465b7 KH |
898 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { |
899 | &omap2_l4_core__uart3, | |
900 | }; | |
901 | ||
902 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
903 | .name = "uart3", | |
0d619a89 | 904 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 905 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
906 | .main_clk = "uart3_fck", |
907 | .prcm = { | |
908 | .omap2 = { | |
909 | .module_offs = CORE_MOD, | |
910 | .prcm_reg_id = 2, | |
911 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
912 | .idlest_reg_id = 2, | |
913 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
914 | }, | |
915 | }, | |
916 | .slaves = omap2430_uart3_slaves, | |
917 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
273b9465 | 918 | .class = &omap2_uart_class, |
046465b7 KH |
919 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
920 | }; | |
921 | ||
de56dbb6 SG |
922 | /* dss */ |
923 | /* dss master ports */ | |
924 | static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { | |
925 | &omap2430_dss__l3, | |
926 | }; | |
927 | ||
de56dbb6 SG |
928 | /* l4_core -> dss */ |
929 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { | |
930 | .master = &omap2430_l4_core_hwmod, | |
931 | .slave = &omap2430_dss_core_hwmod, | |
932 | .clk = "dss_ick", | |
ded11383 | 933 | .addr = omap2_dss_addrs, |
de56dbb6 SG |
934 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
935 | }; | |
936 | ||
937 | /* dss slave ports */ | |
938 | static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { | |
939 | &omap2430_l4_core__dss, | |
940 | }; | |
941 | ||
942 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
943 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
944 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
945 | }; | |
946 | ||
947 | static struct omap_hwmod omap2430_dss_core_hwmod = { | |
948 | .name = "dss_core", | |
273b9465 | 949 | .class = &omap2_dss_hwmod_class, |
de56dbb6 | 950 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
d826ebfa | 951 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
de56dbb6 SG |
952 | .prcm = { |
953 | .omap2 = { | |
954 | .prcm_reg_id = 1, | |
955 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
956 | .module_offs = CORE_MOD, | |
957 | .idlest_reg_id = 1, | |
958 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
959 | }, | |
960 | }, | |
961 | .opt_clks = dss_opt_clks, | |
962 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
963 | .slaves = omap2430_dss_slaves, | |
964 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), | |
965 | .masters = omap2430_dss_masters, | |
966 | .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), | |
967 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
968 | .flags = HWMOD_NO_IDLEST, | |
969 | }; | |
970 | ||
de56dbb6 SG |
971 | /* l4_core -> dss_dispc */ |
972 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { | |
973 | .master = &omap2430_l4_core_hwmod, | |
974 | .slave = &omap2430_dss_dispc_hwmod, | |
975 | .clk = "dss_ick", | |
ded11383 | 976 | .addr = omap2_dss_dispc_addrs, |
de56dbb6 SG |
977 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
978 | }; | |
979 | ||
980 | /* dss_dispc slave ports */ | |
981 | static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { | |
982 | &omap2430_l4_core__dss_dispc, | |
983 | }; | |
984 | ||
985 | static struct omap_hwmod omap2430_dss_dispc_hwmod = { | |
986 | .name = "dss_dispc", | |
273b9465 | 987 | .class = &omap2_dispc_hwmod_class, |
0d619a89 | 988 | .mpu_irqs = omap2_dispc_irqs, |
de56dbb6 SG |
989 | .main_clk = "dss1_fck", |
990 | .prcm = { | |
991 | .omap2 = { | |
992 | .prcm_reg_id = 1, | |
993 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
994 | .module_offs = CORE_MOD, | |
995 | .idlest_reg_id = 1, | |
996 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
997 | }, | |
998 | }, | |
999 | .slaves = omap2430_dss_dispc_slaves, | |
1000 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), | |
1001 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1002 | .flags = HWMOD_NO_IDLEST, | |
1003 | }; | |
1004 | ||
de56dbb6 SG |
1005 | /* l4_core -> dss_rfbi */ |
1006 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { | |
1007 | .master = &omap2430_l4_core_hwmod, | |
1008 | .slave = &omap2430_dss_rfbi_hwmod, | |
1009 | .clk = "dss_ick", | |
ded11383 | 1010 | .addr = omap2_dss_rfbi_addrs, |
de56dbb6 SG |
1011 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1012 | }; | |
1013 | ||
1014 | /* dss_rfbi slave ports */ | |
1015 | static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { | |
1016 | &omap2430_l4_core__dss_rfbi, | |
1017 | }; | |
1018 | ||
1019 | static struct omap_hwmod omap2430_dss_rfbi_hwmod = { | |
1020 | .name = "dss_rfbi", | |
273b9465 | 1021 | .class = &omap2_rfbi_hwmod_class, |
de56dbb6 SG |
1022 | .main_clk = "dss1_fck", |
1023 | .prcm = { | |
1024 | .omap2 = { | |
1025 | .prcm_reg_id = 1, | |
1026 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1027 | .module_offs = CORE_MOD, | |
1028 | }, | |
1029 | }, | |
1030 | .slaves = omap2430_dss_rfbi_slaves, | |
1031 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), | |
1032 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1033 | .flags = HWMOD_NO_IDLEST, | |
1034 | }; | |
1035 | ||
de56dbb6 SG |
1036 | /* l4_core -> dss_venc */ |
1037 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { | |
1038 | .master = &omap2430_l4_core_hwmod, | |
1039 | .slave = &omap2430_dss_venc_hwmod, | |
1040 | .clk = "dss_54m_fck", | |
ded11383 | 1041 | .addr = omap2_dss_venc_addrs, |
c39bee8a | 1042 | .flags = OCPIF_SWSUP_IDLE, |
de56dbb6 SG |
1043 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1044 | }; | |
1045 | ||
1046 | /* dss_venc slave ports */ | |
1047 | static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { | |
1048 | &omap2430_l4_core__dss_venc, | |
1049 | }; | |
1050 | ||
1051 | static struct omap_hwmod omap2430_dss_venc_hwmod = { | |
1052 | .name = "dss_venc", | |
273b9465 | 1053 | .class = &omap2_venc_hwmod_class, |
de56dbb6 SG |
1054 | .main_clk = "dss1_fck", |
1055 | .prcm = { | |
1056 | .omap2 = { | |
1057 | .prcm_reg_id = 1, | |
1058 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1059 | .module_offs = CORE_MOD, | |
1060 | }, | |
1061 | }, | |
1062 | .slaves = omap2430_dss_venc_slaves, | |
1063 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), | |
1064 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1065 | .flags = HWMOD_NO_IDLEST, | |
1066 | }; | |
1067 | ||
2004290f PW |
1068 | /* I2C common */ |
1069 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1070 | .rev_offs = 0x00, | |
1071 | .sysc_offs = 0x20, | |
1072 | .syss_offs = 0x10, | |
2d403fe0 PW |
1073 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1074 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
1075 | .sysc_fields = &omap_hwmod_sysc_type1, |
1076 | }; | |
1077 | ||
1078 | static struct omap_hwmod_class i2c_class = { | |
1079 | .name = "i2c", | |
1080 | .sysc = &i2c_sysc, | |
db791a75 | 1081 | .rev = OMAP_I2C_IP_VERSION_1, |
2004290f PW |
1082 | }; |
1083 | ||
50ebb777 | 1084 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f | 1085 | .fifo_depth = 8, /* bytes */ |
4d4441a6 AG |
1086 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | |
1087 | OMAP_I2C_FLAG_BUS_SHIFT_2 | | |
1088 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, | |
2004290f PW |
1089 | }; |
1090 | ||
50ebb777 BC |
1091 | /* I2C1 */ |
1092 | ||
2004290f PW |
1093 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { |
1094 | &omap2430_l4_core__i2c1, | |
1095 | }; | |
1096 | ||
1097 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
1098 | .name = "i2c1", | |
3e600522 | 1099 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 1100 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 1101 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
1102 | .main_clk = "i2chs1_fck", |
1103 | .prcm = { | |
1104 | .omap2 = { | |
1105 | /* | |
1106 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
1107 | * I2CHS IP's do not follow the usual pattern. | |
1108 | * prcm_reg_id alone cannot be used to program | |
1109 | * the iclk and fclk. Needs to be handled using | |
25985edc | 1110 | * additional flags when clk handling is moved |
2004290f PW |
1111 | * to hwmod framework. |
1112 | */ | |
1113 | .module_offs = CORE_MOD, | |
1114 | .prcm_reg_id = 1, | |
1115 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
1116 | .idlest_reg_id = 1, | |
1117 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
1118 | }, | |
1119 | }, | |
1120 | .slaves = omap2430_i2c1_slaves, | |
1121 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
1122 | .class = &i2c_class, | |
50ebb777 | 1123 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
1124 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1125 | }; | |
1126 | ||
1127 | /* I2C2 */ | |
1128 | ||
2004290f PW |
1129 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { |
1130 | &omap2430_l4_core__i2c2, | |
1131 | }; | |
1132 | ||
1133 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
1134 | .name = "i2c2", | |
3e600522 | 1135 | .flags = HWMOD_16BIT_REG, |
0d619a89 | 1136 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 1137 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
1138 | .main_clk = "i2chs2_fck", |
1139 | .prcm = { | |
1140 | .omap2 = { | |
1141 | .module_offs = CORE_MOD, | |
1142 | .prcm_reg_id = 1, | |
1143 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
1144 | .idlest_reg_id = 1, | |
1145 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
1146 | }, | |
1147 | }, | |
1148 | .slaves = omap2430_i2c2_slaves, | |
1149 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
1150 | .class = &i2c_class, | |
50ebb777 | 1151 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
1152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1153 | }; | |
1154 | ||
aeac0e44 VC |
1155 | /* l4_wkup -> gpio1 */ |
1156 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
1157 | { | |
1158 | .pa_start = 0x4900C000, | |
1159 | .pa_end = 0x4900C1ff, | |
1160 | .flags = ADDR_TYPE_RT | |
1161 | }, | |
78183f3f | 1162 | { } |
aeac0e44 VC |
1163 | }; |
1164 | ||
1165 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
1166 | .master = &omap2430_l4_wkup_hwmod, | |
1167 | .slave = &omap2430_gpio1_hwmod, | |
1168 | .clk = "gpios_ick", | |
1169 | .addr = omap2430_gpio1_addr_space, | |
aeac0e44 VC |
1170 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1171 | }; | |
1172 | ||
1173 | /* l4_wkup -> gpio2 */ | |
1174 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
1175 | { | |
1176 | .pa_start = 0x4900E000, | |
1177 | .pa_end = 0x4900E1ff, | |
1178 | .flags = ADDR_TYPE_RT | |
1179 | }, | |
78183f3f | 1180 | { } |
aeac0e44 VC |
1181 | }; |
1182 | ||
1183 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
1184 | .master = &omap2430_l4_wkup_hwmod, | |
1185 | .slave = &omap2430_gpio2_hwmod, | |
1186 | .clk = "gpios_ick", | |
1187 | .addr = omap2430_gpio2_addr_space, | |
aeac0e44 VC |
1188 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1189 | }; | |
1190 | ||
1191 | /* l4_wkup -> gpio3 */ | |
1192 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
1193 | { | |
1194 | .pa_start = 0x49010000, | |
1195 | .pa_end = 0x490101ff, | |
1196 | .flags = ADDR_TYPE_RT | |
1197 | }, | |
78183f3f | 1198 | { } |
aeac0e44 VC |
1199 | }; |
1200 | ||
1201 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
1202 | .master = &omap2430_l4_wkup_hwmod, | |
1203 | .slave = &omap2430_gpio3_hwmod, | |
1204 | .clk = "gpios_ick", | |
1205 | .addr = omap2430_gpio3_addr_space, | |
aeac0e44 VC |
1206 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1207 | }; | |
1208 | ||
1209 | /* l4_wkup -> gpio4 */ | |
1210 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
1211 | { | |
1212 | .pa_start = 0x49012000, | |
1213 | .pa_end = 0x490121ff, | |
1214 | .flags = ADDR_TYPE_RT | |
1215 | }, | |
78183f3f | 1216 | { } |
aeac0e44 VC |
1217 | }; |
1218 | ||
1219 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
1220 | .master = &omap2430_l4_wkup_hwmod, | |
1221 | .slave = &omap2430_gpio4_hwmod, | |
1222 | .clk = "gpios_ick", | |
1223 | .addr = omap2430_gpio4_addr_space, | |
aeac0e44 VC |
1224 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1225 | }; | |
1226 | ||
1227 | /* l4_core -> gpio5 */ | |
1228 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
1229 | { | |
1230 | .pa_start = 0x480B6000, | |
1231 | .pa_end = 0x480B61ff, | |
1232 | .flags = ADDR_TYPE_RT | |
1233 | }, | |
78183f3f | 1234 | { } |
aeac0e44 VC |
1235 | }; |
1236 | ||
1237 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
1238 | .master = &omap2430_l4_core_hwmod, | |
1239 | .slave = &omap2430_gpio5_hwmod, | |
1240 | .clk = "gpio5_ick", | |
1241 | .addr = omap2430_gpio5_addr_space, | |
aeac0e44 VC |
1242 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1243 | }; | |
1244 | ||
1245 | /* gpio dev_attr */ | |
1246 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1247 | .bank_width = 32, | |
1248 | .dbck_flag = false, | |
1249 | }; | |
1250 | ||
aeac0e44 | 1251 | /* gpio1 */ |
aeac0e44 VC |
1252 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { |
1253 | &omap2430_l4_wkup__gpio1, | |
1254 | }; | |
1255 | ||
1256 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
1257 | .name = "gpio1", | |
f95440ca | 1258 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1259 | .mpu_irqs = omap2_gpio1_irqs, |
aeac0e44 VC |
1260 | .main_clk = "gpios_fck", |
1261 | .prcm = { | |
1262 | .omap2 = { | |
1263 | .prcm_reg_id = 1, | |
1264 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1265 | .module_offs = WKUP_MOD, | |
1266 | .idlest_reg_id = 1, | |
1267 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1268 | }, | |
1269 | }, | |
1270 | .slaves = omap2430_gpio1_slaves, | |
1271 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
273b9465 | 1272 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 VC |
1273 | .dev_attr = &gpio_dev_attr, |
1274 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1275 | }; | |
1276 | ||
1277 | /* gpio2 */ | |
aeac0e44 VC |
1278 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { |
1279 | &omap2430_l4_wkup__gpio2, | |
1280 | }; | |
1281 | ||
1282 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
1283 | .name = "gpio2", | |
f95440ca | 1284 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1285 | .mpu_irqs = omap2_gpio2_irqs, |
aeac0e44 VC |
1286 | .main_clk = "gpios_fck", |
1287 | .prcm = { | |
1288 | .omap2 = { | |
1289 | .prcm_reg_id = 1, | |
1290 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1291 | .module_offs = WKUP_MOD, | |
1292 | .idlest_reg_id = 1, | |
1293 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1294 | }, | |
1295 | }, | |
1296 | .slaves = omap2430_gpio2_slaves, | |
1297 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
273b9465 | 1298 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 VC |
1299 | .dev_attr = &gpio_dev_attr, |
1300 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1301 | }; | |
1302 | ||
1303 | /* gpio3 */ | |
aeac0e44 VC |
1304 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { |
1305 | &omap2430_l4_wkup__gpio3, | |
1306 | }; | |
1307 | ||
1308 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
1309 | .name = "gpio3", | |
f95440ca | 1310 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1311 | .mpu_irqs = omap2_gpio3_irqs, |
aeac0e44 VC |
1312 | .main_clk = "gpios_fck", |
1313 | .prcm = { | |
1314 | .omap2 = { | |
1315 | .prcm_reg_id = 1, | |
1316 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1317 | .module_offs = WKUP_MOD, | |
1318 | .idlest_reg_id = 1, | |
1319 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1320 | }, | |
1321 | }, | |
1322 | .slaves = omap2430_gpio3_slaves, | |
1323 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
273b9465 | 1324 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 VC |
1325 | .dev_attr = &gpio_dev_attr, |
1326 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1327 | }; | |
1328 | ||
1329 | /* gpio4 */ | |
aeac0e44 VC |
1330 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { |
1331 | &omap2430_l4_wkup__gpio4, | |
1332 | }; | |
1333 | ||
1334 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
1335 | .name = "gpio4", | |
f95440ca | 1336 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1337 | .mpu_irqs = omap2_gpio4_irqs, |
aeac0e44 VC |
1338 | .main_clk = "gpios_fck", |
1339 | .prcm = { | |
1340 | .omap2 = { | |
1341 | .prcm_reg_id = 1, | |
1342 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1343 | .module_offs = WKUP_MOD, | |
1344 | .idlest_reg_id = 1, | |
1345 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1346 | }, | |
1347 | }, | |
1348 | .slaves = omap2430_gpio4_slaves, | |
1349 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
273b9465 | 1350 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 VC |
1351 | .dev_attr = &gpio_dev_attr, |
1352 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1353 | }; | |
1354 | ||
1355 | /* gpio5 */ | |
1356 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
1357 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
212738a4 | 1358 | { .irq = -1 } |
aeac0e44 VC |
1359 | }; |
1360 | ||
1361 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
1362 | &omap2430_l4_core__gpio5, | |
1363 | }; | |
1364 | ||
1365 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
1366 | .name = "gpio5", | |
f95440ca | 1367 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 | 1368 | .mpu_irqs = omap243x_gpio5_irqs, |
aeac0e44 VC |
1369 | .main_clk = "gpio5_fck", |
1370 | .prcm = { | |
1371 | .omap2 = { | |
1372 | .prcm_reg_id = 2, | |
1373 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1374 | .module_offs = CORE_MOD, | |
1375 | .idlest_reg_id = 2, | |
1376 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
1377 | }, | |
1378 | }, | |
1379 | .slaves = omap2430_gpio5_slaves, | |
1380 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
273b9465 | 1381 | .class = &omap2xxx_gpio_hwmod_class, |
aeac0e44 VC |
1382 | .dev_attr = &gpio_dev_attr, |
1383 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1384 | }; | |
1385 | ||
82cbd1ae MK |
1386 | /* dma attributes */ |
1387 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1388 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1389 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1390 | .lch_count = 32, | |
1391 | }; | |
1392 | ||
82cbd1ae MK |
1393 | /* dma_system -> L3 */ |
1394 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
1395 | .master = &omap2430_dma_system_hwmod, | |
1396 | .slave = &omap2430_l3_main_hwmod, | |
1397 | .clk = "core_l3_ck", | |
1398 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1399 | }; | |
1400 | ||
1401 | /* dma_system master ports */ | |
1402 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
1403 | &omap2430_dma_system__l3, | |
1404 | }; | |
1405 | ||
1406 | /* l4_core -> dma_system */ | |
1407 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
1408 | .master = &omap2430_l4_core_hwmod, | |
1409 | .slave = &omap2430_dma_system_hwmod, | |
1410 | .clk = "sdma_ick", | |
ded11383 | 1411 | .addr = omap2_dma_system_addrs, |
82cbd1ae MK |
1412 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1413 | }; | |
1414 | ||
1415 | /* dma_system slave ports */ | |
1416 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
1417 | &omap2430_l4_core__dma_system, | |
1418 | }; | |
1419 | ||
1420 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
1421 | .name = "dma", | |
273b9465 | 1422 | .class = &omap2xxx_dma_hwmod_class, |
0d619a89 | 1423 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae MK |
1424 | .main_clk = "core_l3_ck", |
1425 | .slaves = omap2430_dma_system_slaves, | |
1426 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
1427 | .masters = omap2430_dma_system_masters, | |
1428 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
1429 | .dev_attr = &dma_dev_attr, | |
1430 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1431 | .flags = HWMOD_NO_IDLEST, | |
1432 | }; | |
1433 | ||
fca1ab55 ORL |
1434 | /* mailbox */ |
1435 | static struct omap_hwmod omap2430_mailbox_hwmod; | |
1436 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { | |
1437 | { .irq = 26 }, | |
212738a4 | 1438 | { .irq = -1 } |
fca1ab55 ORL |
1439 | }; |
1440 | ||
fca1ab55 ORL |
1441 | /* l4_core -> mailbox */ |
1442 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
1443 | .master = &omap2430_l4_core_hwmod, | |
1444 | .slave = &omap2430_mailbox_hwmod, | |
ded11383 | 1445 | .addr = omap2_mailbox_addrs, |
fca1ab55 ORL |
1446 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1447 | }; | |
1448 | ||
1449 | /* mailbox slave ports */ | |
1450 | static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { | |
1451 | &omap2430_l4_core__mailbox, | |
1452 | }; | |
1453 | ||
1454 | static struct omap_hwmod omap2430_mailbox_hwmod = { | |
1455 | .name = "mailbox", | |
273b9465 | 1456 | .class = &omap2xxx_mailbox_hwmod_class, |
fca1ab55 | 1457 | .mpu_irqs = omap2430_mailbox_irqs, |
fca1ab55 ORL |
1458 | .main_clk = "mailboxes_ick", |
1459 | .prcm = { | |
1460 | .omap2 = { | |
1461 | .prcm_reg_id = 1, | |
1462 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1463 | .module_offs = CORE_MOD, | |
1464 | .idlest_reg_id = 1, | |
1465 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
1466 | }, | |
1467 | }, | |
1468 | .slaves = omap2430_mailbox_slaves, | |
1469 | .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), | |
1470 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1471 | }; | |
1472 | ||
7f904c78 | 1473 | /* mcspi1 */ |
7f904c78 C |
1474 | static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { |
1475 | &omap2430_l4_core__mcspi1, | |
1476 | }; | |
1477 | ||
1478 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1479 | .num_chipselect = 4, | |
1480 | }; | |
1481 | ||
1482 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
1483 | .name = "mcspi1_hwmod", | |
0d619a89 | 1484 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 1485 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
7f904c78 C |
1486 | .main_clk = "mcspi1_fck", |
1487 | .prcm = { | |
1488 | .omap2 = { | |
1489 | .module_offs = CORE_MOD, | |
1490 | .prcm_reg_id = 1, | |
1491 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1492 | .idlest_reg_id = 1, | |
1493 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1494 | }, | |
1495 | }, | |
1496 | .slaves = omap2430_mcspi1_slaves, | |
1497 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), | |
273b9465 PW |
1498 | .class = &omap2xxx_mcspi_class, |
1499 | .dev_attr = &omap_mcspi1_dev_attr, | |
7f904c78 C |
1500 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1501 | }; | |
1502 | ||
1503 | /* mcspi2 */ | |
7f904c78 C |
1504 | static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { |
1505 | &omap2430_l4_core__mcspi2, | |
1506 | }; | |
1507 | ||
1508 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1509 | .num_chipselect = 2, | |
1510 | }; | |
1511 | ||
1512 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
1513 | .name = "mcspi2_hwmod", | |
0d619a89 | 1514 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 1515 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
7f904c78 C |
1516 | .main_clk = "mcspi2_fck", |
1517 | .prcm = { | |
1518 | .omap2 = { | |
1519 | .module_offs = CORE_MOD, | |
1520 | .prcm_reg_id = 1, | |
1521 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1522 | .idlest_reg_id = 1, | |
1523 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1524 | }, | |
1525 | }, | |
1526 | .slaves = omap2430_mcspi2_slaves, | |
1527 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), | |
273b9465 PW |
1528 | .class = &omap2xxx_mcspi_class, |
1529 | .dev_attr = &omap_mcspi2_dev_attr, | |
7f904c78 C |
1530 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1531 | }; | |
1532 | ||
1533 | /* mcspi3 */ | |
1534 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
1535 | { .irq = 91 }, | |
212738a4 | 1536 | { .irq = -1 } |
7f904c78 C |
1537 | }; |
1538 | ||
1539 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
1540 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
1541 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
1542 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
1543 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
bc614958 | 1544 | { .dma_req = -1 } |
7f904c78 C |
1545 | }; |
1546 | ||
1547 | static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { | |
1548 | &omap2430_l4_core__mcspi3, | |
1549 | }; | |
1550 | ||
1551 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1552 | .num_chipselect = 2, | |
1553 | }; | |
1554 | ||
1555 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
1556 | .name = "mcspi3_hwmod", | |
1557 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, | |
7f904c78 | 1558 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
7f904c78 C |
1559 | .main_clk = "mcspi3_fck", |
1560 | .prcm = { | |
1561 | .omap2 = { | |
1562 | .module_offs = CORE_MOD, | |
1563 | .prcm_reg_id = 2, | |
1564 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1565 | .idlest_reg_id = 2, | |
1566 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
1567 | }, | |
1568 | }, | |
1569 | .slaves = omap2430_mcspi3_slaves, | |
1570 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), | |
273b9465 PW |
1571 | .class = &omap2xxx_mcspi_class, |
1572 | .dev_attr = &omap_mcspi3_dev_attr, | |
7f904c78 C |
1573 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1574 | }; | |
1575 | ||
44d02acf HH |
1576 | /* |
1577 | * usbhsotg | |
1578 | */ | |
1579 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { | |
1580 | .rev_offs = 0x0400, | |
1581 | .sysc_offs = 0x0404, | |
1582 | .syss_offs = 0x0408, | |
1583 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1584 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1585 | SYSC_HAS_AUTOIDLE), | |
1586 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1587 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1588 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1589 | }; | |
1590 | ||
1591 | static struct omap_hwmod_class usbotg_class = { | |
1592 | .name = "usbotg", | |
1593 | .sysc = &omap2430_usbhsotg_sysc, | |
1594 | }; | |
1595 | ||
1596 | /* usb_otg_hs */ | |
1597 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
1598 | ||
1599 | { .name = "mc", .irq = 92 }, | |
1600 | { .name = "dma", .irq = 93 }, | |
212738a4 | 1601 | { .irq = -1 } |
44d02acf HH |
1602 | }; |
1603 | ||
1604 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
1605 | .name = "usb_otg_hs", | |
1606 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
44d02acf HH |
1607 | .main_clk = "usbhs_ick", |
1608 | .prcm = { | |
1609 | .omap2 = { | |
1610 | .prcm_reg_id = 1, | |
1611 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
1612 | .module_offs = CORE_MOD, | |
1613 | .idlest_reg_id = 1, | |
1614 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
1615 | }, | |
1616 | }, | |
1617 | .masters = omap2430_usbhsotg_masters, | |
1618 | .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), | |
1619 | .slaves = omap2430_usbhsotg_slaves, | |
1620 | .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), | |
1621 | .class = &usbotg_class, | |
1622 | /* | |
1623 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1624 | * broken when autoidle is enabled | |
1625 | * workaround is to disable the autoidle bit at module level. | |
1626 | */ | |
1627 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1628 | | HWMOD_SWSUP_MSTANDBY, | |
1629 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
1630 | }; | |
1631 | ||
37801b3d C |
1632 | /* |
1633 | * 'mcbsp' class | |
1634 | * multi channel buffered serial port controller | |
1635 | */ | |
1636 | ||
1637 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
1638 | .rev_offs = 0x007C, | |
1639 | .sysc_offs = 0x008C, | |
1640 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
1641 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1642 | }; | |
1643 | ||
1644 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
1645 | .name = "mcbsp", | |
1646 | .sysc = &omap2430_mcbsp_sysc, | |
1647 | .rev = MCBSP_CONFIG_TYPE2, | |
1648 | }; | |
04aa67de | 1649 | |
37801b3d C |
1650 | /* mcbsp1 */ |
1651 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | |
1652 | { .name = "tx", .irq = 59 }, | |
1653 | { .name = "rx", .irq = 60 }, | |
1654 | { .name = "ovr", .irq = 61 }, | |
1655 | { .name = "common", .irq = 64 }, | |
212738a4 | 1656 | { .irq = -1 } |
37801b3d C |
1657 | }; |
1658 | ||
37801b3d C |
1659 | /* l4_core -> mcbsp1 */ |
1660 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
1661 | .master = &omap2430_l4_core_hwmod, | |
1662 | .slave = &omap2430_mcbsp1_hwmod, | |
1663 | .clk = "mcbsp1_ick", | |
ded11383 | 1664 | .addr = omap2_mcbsp1_addrs, |
37801b3d C |
1665 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1666 | }; | |
1667 | ||
1668 | /* mcbsp1 slave ports */ | |
1669 | static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { | |
1670 | &omap2430_l4_core__mcbsp1, | |
1671 | }; | |
1672 | ||
1673 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { | |
1674 | .name = "mcbsp1", | |
1675 | .class = &omap2430_mcbsp_hwmod_class, | |
1676 | .mpu_irqs = omap2430_mcbsp1_irqs, | |
d826ebfa | 1677 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
37801b3d C |
1678 | .main_clk = "mcbsp1_fck", |
1679 | .prcm = { | |
1680 | .omap2 = { | |
1681 | .prcm_reg_id = 1, | |
1682 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1683 | .module_offs = CORE_MOD, | |
1684 | .idlest_reg_id = 1, | |
1685 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
1686 | }, | |
1687 | }, | |
1688 | .slaves = omap2430_mcbsp1_slaves, | |
1689 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), | |
1690 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1691 | }; | |
1692 | ||
1693 | /* mcbsp2 */ | |
1694 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | |
1695 | { .name = "tx", .irq = 62 }, | |
1696 | { .name = "rx", .irq = 63 }, | |
1697 | { .name = "common", .irq = 16 }, | |
212738a4 | 1698 | { .irq = -1 } |
37801b3d C |
1699 | }; |
1700 | ||
37801b3d C |
1701 | /* l4_core -> mcbsp2 */ |
1702 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
1703 | .master = &omap2430_l4_core_hwmod, | |
1704 | .slave = &omap2430_mcbsp2_hwmod, | |
1705 | .clk = "mcbsp2_ick", | |
ded11383 | 1706 | .addr = omap2xxx_mcbsp2_addrs, |
37801b3d C |
1707 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1708 | }; | |
1709 | ||
1710 | /* mcbsp2 slave ports */ | |
1711 | static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { | |
1712 | &omap2430_l4_core__mcbsp2, | |
1713 | }; | |
1714 | ||
1715 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { | |
1716 | .name = "mcbsp2", | |
1717 | .class = &omap2430_mcbsp_hwmod_class, | |
1718 | .mpu_irqs = omap2430_mcbsp2_irqs, | |
d826ebfa | 1719 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
37801b3d C |
1720 | .main_clk = "mcbsp2_fck", |
1721 | .prcm = { | |
1722 | .omap2 = { | |
1723 | .prcm_reg_id = 1, | |
1724 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1725 | .module_offs = CORE_MOD, | |
1726 | .idlest_reg_id = 1, | |
1727 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
1728 | }, | |
1729 | }, | |
1730 | .slaves = omap2430_mcbsp2_slaves, | |
1731 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), | |
1732 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1733 | }; | |
1734 | ||
1735 | /* mcbsp3 */ | |
1736 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | |
1737 | { .name = "tx", .irq = 89 }, | |
1738 | { .name = "rx", .irq = 90 }, | |
1739 | { .name = "common", .irq = 17 }, | |
212738a4 | 1740 | { .irq = -1 } |
37801b3d C |
1741 | }; |
1742 | ||
37801b3d C |
1743 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { |
1744 | { | |
1745 | .name = "mpu", | |
1746 | .pa_start = 0x4808C000, | |
1747 | .pa_end = 0x4808C0ff, | |
1748 | .flags = ADDR_TYPE_RT | |
1749 | }, | |
78183f3f | 1750 | { } |
37801b3d | 1751 | }; |
04aa67de | 1752 | |
37801b3d C |
1753 | /* l4_core -> mcbsp3 */ |
1754 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
1755 | .master = &omap2430_l4_core_hwmod, | |
1756 | .slave = &omap2430_mcbsp3_hwmod, | |
1757 | .clk = "mcbsp3_ick", | |
1758 | .addr = omap2430_mcbsp3_addrs, | |
37801b3d C |
1759 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1760 | }; | |
1761 | ||
1762 | /* mcbsp3 slave ports */ | |
1763 | static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { | |
1764 | &omap2430_l4_core__mcbsp3, | |
1765 | }; | |
1766 | ||
1767 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { | |
1768 | .name = "mcbsp3", | |
1769 | .class = &omap2430_mcbsp_hwmod_class, | |
1770 | .mpu_irqs = omap2430_mcbsp3_irqs, | |
d826ebfa | 1771 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
37801b3d C |
1772 | .main_clk = "mcbsp3_fck", |
1773 | .prcm = { | |
1774 | .omap2 = { | |
1775 | .prcm_reg_id = 1, | |
1776 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1777 | .module_offs = CORE_MOD, | |
1778 | .idlest_reg_id = 2, | |
1779 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
1780 | }, | |
1781 | }, | |
1782 | .slaves = omap2430_mcbsp3_slaves, | |
1783 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), | |
1784 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1785 | }; | |
1786 | ||
1787 | /* mcbsp4 */ | |
1788 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | |
1789 | { .name = "tx", .irq = 54 }, | |
1790 | { .name = "rx", .irq = 55 }, | |
1791 | { .name = "common", .irq = 18 }, | |
212738a4 | 1792 | { .irq = -1 } |
37801b3d C |
1793 | }; |
1794 | ||
1795 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | |
1796 | { .name = "rx", .dma_req = 20 }, | |
1797 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 1798 | { .dma_req = -1 } |
37801b3d C |
1799 | }; |
1800 | ||
1801 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { | |
1802 | { | |
1803 | .name = "mpu", | |
1804 | .pa_start = 0x4808E000, | |
1805 | .pa_end = 0x4808E0ff, | |
1806 | .flags = ADDR_TYPE_RT | |
1807 | }, | |
78183f3f | 1808 | { } |
37801b3d C |
1809 | }; |
1810 | ||
1811 | /* l4_core -> mcbsp4 */ | |
1812 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
1813 | .master = &omap2430_l4_core_hwmod, | |
1814 | .slave = &omap2430_mcbsp4_hwmod, | |
1815 | .clk = "mcbsp4_ick", | |
1816 | .addr = omap2430_mcbsp4_addrs, | |
37801b3d C |
1817 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1818 | }; | |
1819 | ||
1820 | /* mcbsp4 slave ports */ | |
1821 | static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { | |
1822 | &omap2430_l4_core__mcbsp4, | |
1823 | }; | |
1824 | ||
1825 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { | |
1826 | .name = "mcbsp4", | |
1827 | .class = &omap2430_mcbsp_hwmod_class, | |
1828 | .mpu_irqs = omap2430_mcbsp4_irqs, | |
37801b3d | 1829 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
37801b3d C |
1830 | .main_clk = "mcbsp4_fck", |
1831 | .prcm = { | |
1832 | .omap2 = { | |
1833 | .prcm_reg_id = 1, | |
1834 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
1835 | .module_offs = CORE_MOD, | |
1836 | .idlest_reg_id = 2, | |
1837 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
1838 | }, | |
1839 | }, | |
1840 | .slaves = omap2430_mcbsp4_slaves, | |
1841 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), | |
1842 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1843 | }; | |
1844 | ||
1845 | /* mcbsp5 */ | |
1846 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | |
1847 | { .name = "tx", .irq = 81 }, | |
1848 | { .name = "rx", .irq = 82 }, | |
1849 | { .name = "common", .irq = 19 }, | |
212738a4 | 1850 | { .irq = -1 } |
37801b3d C |
1851 | }; |
1852 | ||
1853 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | |
1854 | { .name = "rx", .dma_req = 22 }, | |
1855 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 1856 | { .dma_req = -1 } |
37801b3d C |
1857 | }; |
1858 | ||
1859 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { | |
1860 | { | |
1861 | .name = "mpu", | |
1862 | .pa_start = 0x48096000, | |
1863 | .pa_end = 0x480960ff, | |
1864 | .flags = ADDR_TYPE_RT | |
1865 | }, | |
78183f3f | 1866 | { } |
37801b3d C |
1867 | }; |
1868 | ||
1869 | /* l4_core -> mcbsp5 */ | |
1870 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
1871 | .master = &omap2430_l4_core_hwmod, | |
1872 | .slave = &omap2430_mcbsp5_hwmod, | |
1873 | .clk = "mcbsp5_ick", | |
1874 | .addr = omap2430_mcbsp5_addrs, | |
37801b3d C |
1875 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1876 | }; | |
1877 | ||
1878 | /* mcbsp5 slave ports */ | |
1879 | static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { | |
1880 | &omap2430_l4_core__mcbsp5, | |
1881 | }; | |
1882 | ||
1883 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { | |
1884 | .name = "mcbsp5", | |
1885 | .class = &omap2430_mcbsp_hwmod_class, | |
1886 | .mpu_irqs = omap2430_mcbsp5_irqs, | |
37801b3d | 1887 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
37801b3d C |
1888 | .main_clk = "mcbsp5_fck", |
1889 | .prcm = { | |
1890 | .omap2 = { | |
1891 | .prcm_reg_id = 1, | |
1892 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
1893 | .module_offs = CORE_MOD, | |
1894 | .idlest_reg_id = 2, | |
1895 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
1896 | }, | |
1897 | }, | |
1898 | .slaves = omap2430_mcbsp5_slaves, | |
1899 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), | |
1900 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1901 | }; | |
04aa67de | 1902 | |
bce06f37 | 1903 | /* MMC/SD/SDIO common */ |
04aa67de | 1904 | |
bce06f37 PW |
1905 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
1906 | .rev_offs = 0x1fc, | |
1907 | .sysc_offs = 0x10, | |
1908 | .syss_offs = 0x14, | |
1909 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1910 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1911 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1912 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1913 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1914 | }; | |
1915 | ||
1916 | static struct omap_hwmod_class omap2430_mmc_class = { | |
1917 | .name = "mmc", | |
1918 | .sysc = &omap2430_mmc_sysc, | |
1919 | }; | |
1920 | ||
1921 | /* MMC/SD/SDIO1 */ | |
1922 | ||
1923 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { | |
1924 | { .irq = 83 }, | |
212738a4 | 1925 | { .irq = -1 } |
bce06f37 PW |
1926 | }; |
1927 | ||
1928 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | |
1929 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ | |
1930 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ | |
bc614958 | 1931 | { .dma_req = -1 } |
bce06f37 PW |
1932 | }; |
1933 | ||
1934 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { | |
1935 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
1936 | }; | |
1937 | ||
1938 | static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { | |
1939 | &omap2430_l4_core__mmc1, | |
1940 | }; | |
1941 | ||
6ab8946f KK |
1942 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
1943 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1944 | }; | |
1945 | ||
bce06f37 PW |
1946 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
1947 | .name = "mmc1", | |
1948 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1949 | .mpu_irqs = omap2430_mmc1_mpu_irqs, | |
bce06f37 | 1950 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
bce06f37 PW |
1951 | .opt_clks = omap2430_mmc1_opt_clks, |
1952 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
1953 | .main_clk = "mmchs1_fck", | |
1954 | .prcm = { | |
1955 | .omap2 = { | |
1956 | .module_offs = CORE_MOD, | |
1957 | .prcm_reg_id = 2, | |
1958 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
1959 | .idlest_reg_id = 2, | |
1960 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
1961 | }, | |
1962 | }, | |
6ab8946f | 1963 | .dev_attr = &mmc1_dev_attr, |
bce06f37 PW |
1964 | .slaves = omap2430_mmc1_slaves, |
1965 | .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), | |
1966 | .class = &omap2430_mmc_class, | |
1967 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1968 | }; | |
1969 | ||
1970 | /* MMC/SD/SDIO2 */ | |
1971 | ||
1972 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { | |
1973 | { .irq = 86 }, | |
212738a4 | 1974 | { .irq = -1 } |
bce06f37 PW |
1975 | }; |
1976 | ||
1977 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | |
1978 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ | |
1979 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ | |
bc614958 | 1980 | { .dma_req = -1 } |
bce06f37 PW |
1981 | }; |
1982 | ||
1983 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { | |
1984 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
1985 | }; | |
1986 | ||
1987 | static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { | |
1988 | &omap2430_l4_core__mmc2, | |
1989 | }; | |
04aa67de | 1990 | |
bce06f37 PW |
1991 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
1992 | .name = "mmc2", | |
1993 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1994 | .mpu_irqs = omap2430_mmc2_mpu_irqs, | |
bce06f37 | 1995 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
bce06f37 PW |
1996 | .opt_clks = omap2430_mmc2_opt_clks, |
1997 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
1998 | .main_clk = "mmchs2_fck", | |
1999 | .prcm = { | |
2000 | .omap2 = { | |
2001 | .module_offs = CORE_MOD, | |
2002 | .prcm_reg_id = 2, | |
2003 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
2004 | .idlest_reg_id = 2, | |
2005 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
2006 | }, | |
2007 | }, | |
2008 | .slaves = omap2430_mmc2_slaves, | |
2009 | .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), | |
2010 | .class = &omap2430_mmc_class, | |
2011 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
2012 | }; | |
04aa67de | 2013 | |
02bfc030 | 2014 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 2015 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
2016 | &omap2430_l4_core_hwmod, |
2017 | &omap2430_l4_wkup_hwmod, | |
2018 | &omap2430_mpu_hwmod, | |
08072acf | 2019 | &omap2430_iva_hwmod, |
b6b58229 TG |
2020 | |
2021 | &omap2430_timer1_hwmod, | |
2022 | &omap2430_timer2_hwmod, | |
2023 | &omap2430_timer3_hwmod, | |
2024 | &omap2430_timer4_hwmod, | |
2025 | &omap2430_timer5_hwmod, | |
2026 | &omap2430_timer6_hwmod, | |
2027 | &omap2430_timer7_hwmod, | |
2028 | &omap2430_timer8_hwmod, | |
2029 | &omap2430_timer9_hwmod, | |
2030 | &omap2430_timer10_hwmod, | |
2031 | &omap2430_timer11_hwmod, | |
2032 | &omap2430_timer12_hwmod, | |
2033 | ||
165e2161 | 2034 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
2035 | &omap2430_uart1_hwmod, |
2036 | &omap2430_uart2_hwmod, | |
2037 | &omap2430_uart3_hwmod, | |
de56dbb6 SG |
2038 | /* dss class */ |
2039 | &omap2430_dss_core_hwmod, | |
2040 | &omap2430_dss_dispc_hwmod, | |
2041 | &omap2430_dss_rfbi_hwmod, | |
2042 | &omap2430_dss_venc_hwmod, | |
2043 | /* i2c class */ | |
2004290f PW |
2044 | &omap2430_i2c1_hwmod, |
2045 | &omap2430_i2c2_hwmod, | |
bce06f37 PW |
2046 | &omap2430_mmc1_hwmod, |
2047 | &omap2430_mmc2_hwmod, | |
aeac0e44 VC |
2048 | |
2049 | /* gpio class */ | |
2050 | &omap2430_gpio1_hwmod, | |
2051 | &omap2430_gpio2_hwmod, | |
2052 | &omap2430_gpio3_hwmod, | |
2053 | &omap2430_gpio4_hwmod, | |
2054 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
2055 | |
2056 | /* dma_system class*/ | |
2057 | &omap2430_dma_system_hwmod, | |
7f904c78 | 2058 | |
37801b3d C |
2059 | /* mcbsp class */ |
2060 | &omap2430_mcbsp1_hwmod, | |
2061 | &omap2430_mcbsp2_hwmod, | |
2062 | &omap2430_mcbsp3_hwmod, | |
2063 | &omap2430_mcbsp4_hwmod, | |
2064 | &omap2430_mcbsp5_hwmod, | |
2065 | ||
fca1ab55 ORL |
2066 | /* mailbox class */ |
2067 | &omap2430_mailbox_hwmod, | |
2068 | ||
7f904c78 C |
2069 | /* mcspi class */ |
2070 | &omap2430_mcspi1_hwmod, | |
2071 | &omap2430_mcspi2_hwmod, | |
2072 | &omap2430_mcspi3_hwmod, | |
04aa67de | 2073 | |
44d02acf HH |
2074 | /* usbotg class*/ |
2075 | &omap2430_usbhsotg_hwmod, | |
04aa67de | 2076 | |
02bfc030 PW |
2077 | NULL, |
2078 | }; | |
2079 | ||
7359154e PW |
2080 | int __init omap2430_hwmod_init(void) |
2081 | { | |
550c8092 | 2082 | return omap_hwmod_register(omap2430_hwmods); |
7359154e | 2083 | } |