[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / omap_hwmod_2430_data.c

/*
 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
 *
 * Copyright (C) 2009-2010 Nokia Corporation
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * XXX handle crossbar/shared link difference for L3?
 * XXX these should be marked initdata for multi-OMAP kernels
 */
#include <plat/omap_hwmod.h>
#include <mach/irqs.h>
#include <plat/cpu.h>
#include <plat/dma.h>
#include <plat/serial.h>
#include <plat/i2c.h>
#include <plat/omap24xx.h>

#include "omap_hwmod_common_data.h"

#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"

/*
 * OMAP2430 hardware module integration data
 *
 * ALl of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */

static struct omap_hwmod omap2430_mpu_hwmod;
static struct omap_hwmod omap2430_iva_hwmod;
static struct omap_hwmod omap2430_l3_main_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
static struct omap_hwmod omap2430_wd_timer2_hwmod;

/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
	.master	= &omap2430_l3_main_hwmod,
	.slave	= &omap2430_l4_core_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
	.master = &omap2430_mpu_hwmod,
	.slave	= &omap2430_l3_main_hwmod,
	.user	= OCP_USER_MPU,
};

/* Slave interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
	&omap2430_mpu__l3_main,
};

/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
	&omap2430_l3_main__l4_core,
};

/* L3 */
static struct omap_hwmod omap2430_l3_main_hwmod = {
	.name		= "l3_main",
	.class		= &l3_hwmod_class,
	.masters	= omap2430_l3_main_masters,
	.masters_cnt	= ARRAY_SIZE(omap2430_l3_main_masters),
	.slaves		= omap2430_l3_main_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_l3_main_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod omap2430_l4_wkup_hwmod;
static struct omap_hwmod omap2430_uart1_hwmod;
static struct omap_hwmod omap2430_uart2_hwmod;
static struct omap_hwmod omap2430_uart3_hwmod;
static struct omap_hwmod omap2430_i2c1_hwmod;
static struct omap_hwmod omap2430_i2c2_hwmod;

/* I2C IP block address space length (in bytes) */
#define OMAP2_I2C_AS_LEN		128

/* L4 CORE -> I2C1 interface */
static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
	{
		.pa_start	= 0x48070000,
		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,
		.flags		= ADDR_TYPE_RT,
	},
};

static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
	.master		= &omap2430_l4_core_hwmod,
	.slave		= &omap2430_i2c1_hwmod,
	.clk		= "i2c1_ick",
	.addr		= omap2430_i2c1_addr_space,
	.addr_cnt	= ARRAY_SIZE(omap2430_i2c1_addr_space),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> I2C2 interface */
static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
	{
		.pa_start	= 0x48072000,
		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,
		.flags		= ADDR_TYPE_RT,
	},
};

static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
	.master		= &omap2430_l4_core_hwmod,
	.slave		= &omap2430_i2c2_hwmod,
	.clk		= "i2c2_ick",
	.addr		= omap2430_i2c2_addr_space,
	.addr_cnt	= ARRAY_SIZE(omap2430_i2c2_addr_space),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
	.master	= &omap2430_l4_core_hwmod,
	.slave	= &omap2430_l4_wkup_hwmod,
	.user	= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART1 interface */
static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
	{
		.pa_start	= OMAP2_UART1_BASE,
		.pa_end		= OMAP2_UART1_BASE + SZ_8K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
};

static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	.master		= &omap2430_l4_core_hwmod,
	.slave		= &omap2430_uart1_hwmod,
	.clk		= "uart1_ick",
	.addr		= omap2430_uart1_addr_space,
	.addr_cnt	= ARRAY_SIZE(omap2430_uart1_addr_space),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 CORE -> UART2 interface */
static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
	{
		.pa_start	= OMAP2_UART2_BASE,
		.pa_end		= OMAP2_UART2_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
};

static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	.master		= &omap2430_l4_core_hwmod,
	.slave		= &omap2430_uart2_hwmod,
	.clk		= "uart2_ick",
	.addr		= omap2430_uart2_addr_space,
	.addr_cnt	= ARRAY_SIZE(omap2430_uart2_addr_space),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* L4 PER -> UART3 interface */
static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
	{
		.pa_start	= OMAP2_UART3_BASE,
		.pa_end		= OMAP2_UART3_BASE + SZ_1K - 1,
		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
	},
};

static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	.master		= &omap2430_l4_core_hwmod,
	.slave		= &omap2430_uart3_hwmod,
	.clk		= "uart3_ick",
	.addr		= omap2430_uart3_addr_space,
	.addr_cnt	= ARRAY_SIZE(omap2430_uart3_addr_space),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
	&omap2430_l3_main__l4_core,
};

/* Master interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
	&omap2430_l4_core__l4_wkup,
};

/* L4 CORE */
static struct omap_hwmod omap2430_l4_core_hwmod = {
	.name		= "l4_core",
	.class		= &l4_hwmod_class,
	.masters	= omap2430_l4_core_masters,
	.masters_cnt	= ARRAY_SIZE(omap2430_l4_core_masters),
	.slaves		= omap2430_l4_core_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_l4_core_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	.flags		= HWMOD_NO_IDLEST,
};

/* Slave interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
	&omap2430_l4_core__l4_wkup,
	&omap2_l4_core__uart1,
	&omap2_l4_core__uart2,
	&omap2_l4_core__uart3,
};

/* Master interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
};

/* L4 WKUP */
static struct omap_hwmod omap2430_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &l4_hwmod_class,
	.masters	= omap2430_l4_wkup_masters,
	.masters_cnt	= ARRAY_SIZE(omap2430_l4_wkup_masters),
	.slaves		= omap2430_l4_wkup_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_l4_wkup_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	.flags		= HWMOD_NO_IDLEST,
};

/* Master interfaces on the MPU device */
static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
	&omap2430_mpu__l3_main,
};

/* MPU */
static struct omap_hwmod omap2430_mpu_hwmod = {
	.name		= "mpu",
	.class		= &mpu_hwmod_class,
	.main_clk	= "mpu_ck",
	.masters	= omap2430_mpu_masters,
	.masters_cnt	= ARRAY_SIZE(omap2430_mpu_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/*
 * IVA2_1 interface data
 */

/* IVA2 <- L3 interface */
static struct omap_hwmod_ocp_if omap2430_l3__iva = {
	.master		= &omap2430_l3_main_hwmod,
	.slave		= &omap2430_iva_hwmod,
	.clk		= "dsp_fck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
	&omap2430_l3__iva,
};

/*
 * IVA2 (IVA2)
 */

static struct omap_hwmod omap2430_iva_hwmod = {
	.name		= "iva",
	.class		= &iva_hwmod_class,
	.masters	= omap2430_iva_masters,
	.masters_cnt	= ARRAY_SIZE(omap2430_iva_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};

/* l4_wkup -> wd_timer2 */
static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
	{
		.pa_start	= 0x49016000,
		.pa_end		= 0x4901607f,
		.flags		= ADDR_TYPE_RT
	},
};

static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
	.master		= &omap2430_l4_wkup_hwmod,
	.slave		= &omap2430_wd_timer2_hwmod,
	.clk		= "mpu_wdt_ick",
	.addr		= omap2430_wd_timer2_addrs,
	.addr_cnt	= ARRAY_SIZE(omap2430_wd_timer2_addrs),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 * overflow condition
 */

static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.sysc_fields    = &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
	.name = "wd_timer",
	.sysc = &omap2430_wd_timer_sysc,
};

/* wd_timer2 */
static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
	&omap2430_l4_wkup__wd_timer2,
};

static struct omap_hwmod omap2430_wd_timer2_hwmod = {
	.name		= "wd_timer2",
	.class		= &omap2430_wd_timer_hwmod_class,
	.main_clk	= "mpu_wdt_fck",
	.prcm		= {
		.omap2 = {
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
			.module_offs = WKUP_MOD,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
		},
	},
	.slaves		= omap2430_wd_timer2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_wd_timer2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/* UART */

static struct omap_hwmod_class_sysconfig uart_sysc = {
	.rev_offs	= 0x50,
	.sysc_offs	= 0x54,
	.syss_offs	= 0x58,
	.sysc_flags	= (SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
			   SYSC_HAS_AUTOIDLE),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields    = &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class uart_class = {
	.name = "uart",
	.sysc = &uart_sysc,
};

/* UART1 */

static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
	{ .irq = INT_24XX_UART1_IRQ, },
};

static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART1_RX, },
	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART1_TX, },
};

static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
	&omap2_l4_core__uart1,
};

static struct omap_hwmod omap2430_uart1_hwmod = {
	.name		= "uart1",
	.mpu_irqs	= uart1_mpu_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(uart1_mpu_irqs),
	.sdma_reqs	= uart1_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(uart1_sdma_reqs),
	.main_clk	= "uart1_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
		},
	},
	.slaves		= omap2430_uart1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_uart1_slaves),
	.class		= &uart_class,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/* UART2 */

static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
	{ .irq = INT_24XX_UART2_IRQ, },
};

static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART2_RX, },
	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART2_TX, },
};

static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
	&omap2_l4_core__uart2,
};

static struct omap_hwmod omap2430_uart2_hwmod = {
	.name		= "uart2",
	.mpu_irqs	= uart2_mpu_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(uart2_mpu_irqs),
	.sdma_reqs	= uart2_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(uart2_sdma_reqs),
	.main_clk	= "uart2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP24XX_EN_UART2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
		},
	},
	.slaves		= omap2430_uart2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_uart2_slaves),
	.class		= &uart_class,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/* UART3 */

static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
	{ .irq = INT_24XX_UART3_IRQ, },
};

static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
	{ .name = "rx",	.dma_req = OMAP24XX_DMA_UART3_RX, },
	{ .name = "tx",	.dma_req = OMAP24XX_DMA_UART3_TX, },
};

static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
	&omap2_l4_core__uart3,
};

static struct omap_hwmod omap2430_uart3_hwmod = {
	.name		= "uart3",
	.mpu_irqs	= uart3_mpu_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(uart3_mpu_irqs),
	.sdma_reqs	= uart3_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(uart3_sdma_reqs),
	.main_clk	= "uart3_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 2,
			.module_bit = OMAP24XX_EN_UART3_SHIFT,
			.idlest_reg_id = 2,
			.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
		},
	},
	.slaves		= omap2430_uart3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_uart3_slaves),
	.class		= &uart_class,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x00,
	.sysc_offs	= 0x20,
	.syss_offs	= 0x10,
	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name		= "i2c",
	.sysc		= &i2c_sysc,
};

static struct omap_i2c_dev_attr i2c_dev_attr;

/* I2C1 */

static struct omap_i2c_dev_attr i2c1_dev_attr = {
	.fifo_depth	= 8, /* bytes */
};

static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
	{ .irq = INT_24XX_I2C1_IRQ, },
};

static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
};

static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
	&omap2430_l4_core__i2c1,
};

static struct omap_hwmod omap2430_i2c1_hwmod = {
	.name		= "i2c1",
	.mpu_irqs	= i2c1_mpu_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),
	.sdma_reqs	= i2c1_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),
	.main_clk	= "i2chs1_fck",
	.prcm		= {
		.omap2 = {
			/*
			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
			 * I2CHS IP's do not follow the usual pattern.
			 * prcm_reg_id alone cannot be used to program
			 * the iclk and fclk. Needs to be handled using
			 * additonal flags when clk handling is moved
			 * to hwmod framework.
			 */
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
		},
	},
	.slaves		= omap2430_i2c1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),
	.class		= &i2c_class,
	.dev_attr	= &i2c1_dev_attr,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

/* I2C2 */

static struct omap_i2c_dev_attr i2c2_dev_attr = {
	.fifo_depth	= 8, /* bytes */
};

static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
	{ .irq = INT_24XX_I2C2_IRQ, },
};

static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
};

static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
	&omap2430_l4_core__i2c2,
};

static struct omap_hwmod omap2430_i2c2_hwmod = {
	.name		= "i2c2",
	.mpu_irqs	= i2c2_mpu_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),
	.sdma_reqs	= i2c2_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),
	.main_clk	= "i2chs2_fck",
	.prcm		= {
		.omap2 = {
			.module_offs = CORE_MOD,
			.prcm_reg_id = 1,
			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
			.idlest_reg_id = 1,
			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
		},
	},
	.slaves		= omap2430_i2c2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c2_slaves),
	.class		= &i2c_class,
	.dev_attr	= &i2c2_dev_attr,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};

static __initdata struct omap_hwmod *omap2430_hwmods[] = {
	&omap2430_l3_main_hwmod,
	&omap2430_l4_core_hwmod,
	&omap2430_l4_wkup_hwmod,
	&omap2430_mpu_hwmod,
	&omap2430_iva_hwmod,
	&omap2430_wd_timer2_hwmod,
	&omap2430_uart1_hwmod,
	&omap2430_uart2_hwmod,
	&omap2430_uart3_hwmod,
	&omap2430_i2c1_hwmod,
	&omap2430_i2c2_hwmod,
	NULL,
};

int __init omap2430_hwmod_init(void)
{
	return omap_hwmod_init(omap2430_hwmods);
}
Commit	Line	Data
02bfc030	1	/*
7359154e	2	* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
02bfc030	3	*
7359154e	4	* Copyright (C) 2009-2010 Nokia Corporation
02bfc030 PW	5	* Paul Walmsley
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* XXX handle crossbar/shared link difference for L3?
7359154e	12	* XXX these should be marked initdata for multi-OMAP kernels
02bfc030	13	*/
ce491cf8	14	#include <plat/omap_hwmod.h>
02bfc030	15	#include <mach/irqs.h>
ce491cf8 TL	16	#include <plat/cpu.h>
ce491cf8 TL	17	#include <plat/dma.h>
046465b7	18	#include <plat/serial.h>
2004290f PW	19	#include <plat/i2c.h>
2004290f PW	20	#include <plat/omap24xx.h>
02bfc030	21
43b40992 PW	22	#include "omap_hwmod_common_data.h"
43b40992 PW	23
02bfc030	24	#include "prm-regbits-24xx.h"
165e2161	25	#include "cm-regbits-24xx.h"
02bfc030	26
7359154e PW	27	/*
	28	* OMAP2430 hardware module integration data
	29	*
	30	* ALl of the data in this section should be autogeneratable from the
	31	* TI hardware database or other technical documentation. Data that
	32	* is driver-specific or driver-kernel integration-specific belongs
	33	* elsewhere.
	34	*/
	35
02bfc030	36	static struct omap_hwmod omap2430_mpu_hwmod;
08072acf	37	static struct omap_hwmod omap2430_iva_hwmod;
4a7cf90a	38	static struct omap_hwmod omap2430_l3_main_hwmod;
02bfc030	39	static struct omap_hwmod omap2430_l4_core_hwmod;
165e2161	40	static struct omap_hwmod omap2430_wd_timer2_hwmod;
02bfc030 PW	41
02bfc030 PW	42	/* L3 -> L4_CORE interface */
4a7cf90a KH	43	static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
4a7cf90a KH	44	.master = &omap2430_l3_main_hwmod,
02bfc030 PW	45	.slave = &omap2430_l4_core_hwmod,
	46	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	47	};
	48
	49	/* MPU -> L3 interface */
4a7cf90a	50	static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
02bfc030	51	.master = &omap2430_mpu_hwmod,
4a7cf90a	52	.slave = &omap2430_l3_main_hwmod,
02bfc030 PW	53	.user = OCP_USER_MPU,
	54	};
	55
	56	/* Slave interfaces on the L3 interconnect */
4a7cf90a KH	57	static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
4a7cf90a KH	58	&omap2430_mpu__l3_main,
02bfc030 PW	59	};
	60
	61	/* Master interfaces on the L3 interconnect */
4a7cf90a KH	62	static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
4a7cf90a KH	63	&omap2430_l3_main__l4_core,
02bfc030 PW	64	};
	65
	66	/* L3 */
4a7cf90a	67	static struct omap_hwmod omap2430_l3_main_hwmod = {
fa98347e	68	.name = "l3_main",
43b40992	69	.class = &l3_hwmod_class,
4a7cf90a KH	70	.masters = omap2430_l3_main_masters,
	71	.masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
	72	.slaves = omap2430_l3_main_slaves,
	73	.slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
2eb1875d KH	74	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2eb1875d KH	75	.flags = HWMOD_NO_IDLEST,
02bfc030 PW	76	};
	77
	78	static struct omap_hwmod omap2430_l4_wkup_hwmod;
046465b7 KH	79	static struct omap_hwmod omap2430_uart1_hwmod;
	80	static struct omap_hwmod omap2430_uart2_hwmod;
	81	static struct omap_hwmod omap2430_uart3_hwmod;
2004290f PW	82	static struct omap_hwmod omap2430_i2c1_hwmod;
	83	static struct omap_hwmod omap2430_i2c2_hwmod;
	84
	85	/* I2C IP block address space length (in bytes) */
	86	#define OMAP2_I2C_AS_LEN 128
	87
	88	/* L4 CORE -> I2C1 interface */
	89	static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
	90	{
	91	.pa_start = 0x48070000,
	92	.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
	93	.flags = ADDR_TYPE_RT,
	94	},
	95	};
	96
	97	static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
	98	.master = &omap2430_l4_core_hwmod,
	99	.slave = &omap2430_i2c1_hwmod,
	100	.clk = "i2c1_ick",
	101	.addr = omap2430_i2c1_addr_space,
	102	.addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
	103	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	104	};
	105
	106	/* L4 CORE -> I2C2 interface */
	107	static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
	108	{
	109	.pa_start = 0x48072000,
	110	.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
	111	.flags = ADDR_TYPE_RT,
	112	},
	113	};
	114
	115	static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
	116	.master = &omap2430_l4_core_hwmod,
	117	.slave = &omap2430_i2c2_hwmod,
	118	.clk = "i2c2_ick",
	119	.addr = omap2430_i2c2_addr_space,
	120	.addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
	121	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	122	};
02bfc030 PW	123
	124	/* L4_CORE -> L4_WKUP interface */
	125	static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
	126	.master = &omap2430_l4_core_hwmod,
	127	.slave = &omap2430_l4_wkup_hwmod,
	128	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	129	};
	130
046465b7 KH	131	/* L4 CORE -> UART1 interface */
	132	static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
	133	{
	134	.pa_start = OMAP2_UART1_BASE,
	135	.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
	136	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	137	},
	138	};
	139
	140	static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
	141	.master = &omap2430_l4_core_hwmod,
	142	.slave = &omap2430_uart1_hwmod,
	143	.clk = "uart1_ick",
	144	.addr = omap2430_uart1_addr_space,
	145	.addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
	146	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	147	};
	148
	149	/* L4 CORE -> UART2 interface */
	150	static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
	151	{
	152	.pa_start = OMAP2_UART2_BASE,
	153	.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
	154	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	155	},
	156	};
	157
	158	static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
	159	.master = &omap2430_l4_core_hwmod,
	160	.slave = &omap2430_uart2_hwmod,
	161	.clk = "uart2_ick",
	162	.addr = omap2430_uart2_addr_space,
	163	.addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
	164	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	165	};
	166
	167	/* L4 PER -> UART3 interface */
	168	static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
	169	{
	170	.pa_start = OMAP2_UART3_BASE,
	171	.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
	172	.flags = ADDR_MAP_ON_INIT \| ADDR_TYPE_RT,
	173	},
	174	};
	175
	176	static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
	177	.master = &omap2430_l4_core_hwmod,
	178	.slave = &omap2430_uart3_hwmod,
	179	.clk = "uart3_ick",
	180	.addr = omap2430_uart3_addr_space,
	181	.addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
	182	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	183	};
	184
02bfc030 PW	185	/* Slave interfaces on the L4_CORE interconnect */
02bfc030 PW	186	static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
4a7cf90a	187	&omap2430_l3_main__l4_core,
02bfc030 PW	188	};
	189
	190	/* Master interfaces on the L4_CORE interconnect */
	191	static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
	192	&omap2430_l4_core__l4_wkup,
	193	};
	194
	195	/* L4 CORE */
	196	static struct omap_hwmod omap2430_l4_core_hwmod = {
fa98347e	197	.name = "l4_core",
43b40992	198	.class = &l4_hwmod_class,
02bfc030 PW	199	.masters = omap2430_l4_core_masters,
	200	.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
	201	.slaves = omap2430_l4_core_slaves,
	202	.slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
2eb1875d KH	203	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2eb1875d KH	204	.flags = HWMOD_NO_IDLEST,
02bfc030 PW	205	};
	206
	207	/* Slave interfaces on the L4_WKUP interconnect */
	208	static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
	209	&omap2430_l4_core__l4_wkup,
046465b7 KH	210	&omap2_l4_core__uart1,
	211	&omap2_l4_core__uart2,
	212	&omap2_l4_core__uart3,
02bfc030 PW	213	};
	214
	215	/* Master interfaces on the L4_WKUP interconnect */
	216	static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
	217	};
	218
	219	/* L4 WKUP */
	220	static struct omap_hwmod omap2430_l4_wkup_hwmod = {
fa98347e	221	.name = "l4_wkup",
43b40992	222	.class = &l4_hwmod_class,
02bfc030 PW	223	.masters = omap2430_l4_wkup_masters,
	224	.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
	225	.slaves = omap2430_l4_wkup_slaves,
	226	.slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
2eb1875d KH	227	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2eb1875d KH	228	.flags = HWMOD_NO_IDLEST,
02bfc030 PW	229	};
	230
	231	/* Master interfaces on the MPU device */
	232	static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
4a7cf90a	233	&omap2430_mpu__l3_main,
02bfc030 PW	234	};
	235
	236	/* MPU */
	237	static struct omap_hwmod omap2430_mpu_hwmod = {
5c2c0296	238	.name = "mpu",
43b40992	239	.class = &mpu_hwmod_class,
50ebdac2	240	.main_clk = "mpu_ck",
02bfc030 PW	241	.masters = omap2430_mpu_masters,
	242	.masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
	243	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	244	};
	245
08072acf PW	246	/*
	247	* IVA2_1 interface data
	248	*/
	249
	250	/* IVA2 <- L3 interface */
	251	static struct omap_hwmod_ocp_if omap2430_l3__iva = {
	252	.master = &omap2430_l3_main_hwmod,
	253	.slave = &omap2430_iva_hwmod,
	254	.clk = "dsp_fck",
	255	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	256	};
	257
	258	static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
	259	&omap2430_l3__iva,
	260	};
	261
	262	/*
	263	* IVA2 (IVA2)
	264	*/
	265
	266	static struct omap_hwmod omap2430_iva_hwmod = {
	267	.name = "iva",
	268	.class = &iva_hwmod_class,
	269	.masters = omap2430_iva_masters,
	270	.masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
	271	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
	272	};
	273
165e2161 VC	274	/* l4_wkup -> wd_timer2 */
	275	static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
	276	{
	277	.pa_start = 0x49016000,
	278	.pa_end = 0x4901607f,
	279	.flags = ADDR_TYPE_RT
	280	},
	281	};
	282
	283	static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
	284	.master = &omap2430_l4_wkup_hwmod,
	285	.slave = &omap2430_wd_timer2_hwmod,
	286	.clk = "mpu_wdt_ick",
	287	.addr = omap2430_wd_timer2_addrs,
	288	.addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
	289	.user = OCP_USER_MPU \| OCP_USER_SDMA,
	290	};
	291
	292	/*
	293	* 'wd_timer' class
	294	* 32-bit watchdog upward counter that generates a pulse on the reset pin on
	295	* overflow condition
	296	*/
	297
	298	static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
	299	.rev_offs = 0x0,
	300	.sysc_offs = 0x0010,
	301	.syss_offs = 0x0014,
	302	.sysc_flags = (SYSC_HAS_EMUFREE \| SYSC_HAS_SOFTRESET \|
	303	SYSC_HAS_AUTOIDLE),
	304	.sysc_fields = &omap_hwmod_sysc_type1,
	305	};
	306
	307	static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
	308	.name = "wd_timer",
	309	.sysc = &omap2430_wd_timer_sysc,
	310	};
	311
	312	/* wd_timer2 */
	313	static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
	314	&omap2430_l4_wkup__wd_timer2,
	315	};
	316
	317	static struct omap_hwmod omap2430_wd_timer2_hwmod = {
	318	.name = "wd_timer2",
	319	.class = &omap2430_wd_timer_hwmod_class,
	320	.main_clk = "mpu_wdt_fck",
	321	.prcm = {
	322	.omap2 = {
	323	.prcm_reg_id = 1,
	324	.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
	325	.module_offs = WKUP_MOD,
	326	.idlest_reg_id = 1,
	327	.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
	328	},
	329	},
	330	.slaves = omap2430_wd_timer2_slaves,
	331	.slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
	332	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	333	};
	334
046465b7 KH	335	/* UART */
	336
	337	static struct omap_hwmod_class_sysconfig uart_sysc = {
	338	.rev_offs = 0x50,
	339	.sysc_offs = 0x54,
	340	.syss_offs = 0x58,
	341	.sysc_flags = (SYSC_HAS_SIDLEMODE \|
	342	SYSC_HAS_ENAWAKEUP \| SYSC_HAS_SOFTRESET \|
	343	SYSC_HAS_AUTOIDLE),
	344	.idlemodes = (SIDLE_FORCE \| SIDLE_NO \| SIDLE_SMART),
	345	.sysc_fields = &omap_hwmod_sysc_type1,
	346	};
	347
	348	static struct omap_hwmod_class uart_class = {
	349	.name = "uart",
	350	.sysc = &uart_sysc,
	351	};
	352
	353	/* UART1 */
	354
	355	static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
	356	{ .irq = INT_24XX_UART1_IRQ, },
	357	};
	358
	359	static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
	360	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
	361	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
	362	};
	363
	364	static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
	365	&omap2_l4_core__uart1,
	366	};
	367
	368	static struct omap_hwmod omap2430_uart1_hwmod = {
	369	.name = "uart1",
	370	.mpu_irqs = uart1_mpu_irqs,
	371	.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
	372	.sdma_reqs = uart1_sdma_reqs,
	373	.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
	374	.main_clk = "uart1_fck",
	375	.prcm = {
	376	.omap2 = {
	377	.module_offs = CORE_MOD,
	378	.prcm_reg_id = 1,
	379	.module_bit = OMAP24XX_EN_UART1_SHIFT,
	380	.idlest_reg_id = 1,
	381	.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
	382	},
	383	},
	384	.slaves = omap2430_uart1_slaves,
	385	.slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
	386	.class = &uart_class,
	387	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
	388	};
	389
	390	/* UART2 */
	391
	392	static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
	393	{ .irq = INT_24XX_UART2_IRQ, },
	394	};
	395
	396	static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
	397	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
	398	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
399	};
400
401	static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
402	&omap2_l4_core__uart2,
403	};
404
405	static struct omap_hwmod omap2430_uart2_hwmod = {
406	.name = "uart2",
407	.mpu_irqs = uart2_mpu_irqs,
408	.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
409	.sdma_reqs = uart2_sdma_reqs,
410	.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
411	.main_clk = "uart2_fck",
412	.prcm = {
413	.omap2 = {
414	.module_offs = CORE_MOD,
415	.prcm_reg_id = 1,
416	.module_bit = OMAP24XX_EN_UART2_SHIFT,
417	.idlest_reg_id = 1,
418	.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
419	},
420	},
421	.slaves = omap2430_uart2_slaves,
422	.slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
423	.class = &uart_class,
424	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
425	};
426
427	/* UART3 */
428
429	static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
430	{ .irq = INT_24XX_UART3_IRQ, },
431	};
432
433	static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
434	{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
435	{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
436	};
437
438	static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
439	&omap2_l4_core__uart3,
440	};
441
442	static struct omap_hwmod omap2430_uart3_hwmod = {
443	.name = "uart3",
444	.mpu_irqs = uart3_mpu_irqs,
445	.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
446	.sdma_reqs = uart3_sdma_reqs,
447	.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
448	.main_clk = "uart3_fck",
449	.prcm = {
450	.omap2 = {
451	.module_offs = CORE_MOD,
452	.prcm_reg_id = 2,
453	.module_bit = OMAP24XX_EN_UART3_SHIFT,
454	.idlest_reg_id = 2,
455	.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
456	},
457	},
458	.slaves = omap2430_uart3_slaves,
459	.slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
460	.class = &uart_class,
461	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
462	};
463
2004290f PW	464	/* I2C common */
	465	static struct omap_hwmod_class_sysconfig i2c_sysc = {
	466	.rev_offs = 0x00,
	467	.sysc_offs = 0x20,
	468	.syss_offs = 0x10,
	469	.sysc_flags = (SYSC_HAS_SOFTRESET \| SYSC_HAS_AUTOIDLE),
	470	.sysc_fields = &omap_hwmod_sysc_type1,
	471	};
	472
	473	static struct omap_hwmod_class i2c_class = {
	474	.name = "i2c",
	475	.sysc = &i2c_sysc,
	476	};
	477
	478	static struct omap_i2c_dev_attr i2c_dev_attr;
	479
	480	/* I2C1 */
	481
	482	static struct omap_i2c_dev_attr i2c1_dev_attr = {
	483	.fifo_depth = 8, /* bytes */
	484	};
	485
	486	static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
	487	{ .irq = INT_24XX_I2C1_IRQ, },
	488	};
	489
	490	static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
	491	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
	492	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
	493	};
	494
	495	static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
	496	&omap2430_l4_core__i2c1,
	497	};
	498
	499	static struct omap_hwmod omap2430_i2c1_hwmod = {
	500	.name = "i2c1",
	501	.mpu_irqs = i2c1_mpu_irqs,
	502	.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
	503	.sdma_reqs = i2c1_sdma_reqs,
	504	.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
	505	.main_clk = "i2chs1_fck",
	506	.prcm = {
	507	.omap2 = {
	508	/*
	509	* NOTE: The CM_FCLKEN* and CM_ICLKEN* for
	510	* I2CHS IP's do not follow the usual pattern.
	511	* prcm_reg_id alone cannot be used to program
	512	* the iclk and fclk. Needs to be handled using
	513	* additonal flags when clk handling is moved
	514	* to hwmod framework.
	515	*/
	516	.module_offs = CORE_MOD,
	517	.prcm_reg_id = 1,
	518	.module_bit = OMAP2430_EN_I2CHS1_SHIFT,
	519	.idlest_reg_id = 1,
	520	.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
	521	},
	522	},
	523	.slaves = omap2430_i2c1_slaves,
	524	.slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
	525	.class = &i2c_class,
	526	.dev_attr = &i2c1_dev_attr,
	527	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
528	};
529
530	/* I2C2 */
531
532	static struct omap_i2c_dev_attr i2c2_dev_attr = {
533	.fifo_depth = 8, /* bytes */
534	};
535
536	static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
537	{ .irq = INT_24XX_I2C2_IRQ, },
538	};
539
540	static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
541	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
542	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
543	};
544
545	static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
546	&omap2430_l4_core__i2c2,
547	};
548
549	static struct omap_hwmod omap2430_i2c2_hwmod = {
550	.name = "i2c2",
551	.mpu_irqs = i2c2_mpu_irqs,
552	.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
553	.sdma_reqs = i2c2_sdma_reqs,
554	.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
555	.main_clk = "i2chs2_fck",
556	.prcm = {
557	.omap2 = {
558	.module_offs = CORE_MOD,
559	.prcm_reg_id = 1,
560	.module_bit = OMAP2430_EN_I2CHS2_SHIFT,
561	.idlest_reg_id = 1,
562	.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
563	},
564	},
565	.slaves = omap2430_i2c2_slaves,
566	.slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
567	.class = &i2c_class,
568	.dev_attr = &i2c2_dev_attr,
569	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
570	};
571
02bfc030	572	static __initdata struct omap_hwmod *omap2430_hwmods[] = {
4a7cf90a	573	&omap2430_l3_main_hwmod,
02bfc030 PW	574	&omap2430_l4_core_hwmod,
	575	&omap2430_l4_wkup_hwmod,
	576	&omap2430_mpu_hwmod,
08072acf	577	&omap2430_iva_hwmod,
165e2161	578	&omap2430_wd_timer2_hwmod,
046465b7 KH	579	&omap2430_uart1_hwmod,
	580	&omap2430_uart2_hwmod,
	581	&omap2430_uart3_hwmod,
2004290f PW	582	&omap2430_i2c1_hwmod,
2004290f PW	583	&omap2430_i2c2_hwmod,
02bfc030 PW	584	NULL,
	585	};
	586
7359154e PW	587	int __init omap2430_hwmod_init(void)
	588	{
	589	return omap_hwmod_init(omap2430_hwmods);
	590	}