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Commit | Line | Data |
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02bfc030 | 1 | /* |
7359154e | 2 | * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
02bfc030 | 3 | * |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
02bfc030 PW |
5 | * Paul Walmsley |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX handle crossbar/shared link difference for L3? | |
7359154e | 12 | * XXX these should be marked initdata for multi-OMAP kernels |
02bfc030 | 13 | */ |
ce491cf8 | 14 | #include <plat/omap_hwmod.h> |
02bfc030 | 15 | #include <mach/irqs.h> |
ce491cf8 TL |
16 | #include <plat/cpu.h> |
17 | #include <plat/dma.h> | |
046465b7 | 18 | #include <plat/serial.h> |
2004290f | 19 | #include <plat/i2c.h> |
aeac0e44 | 20 | #include <plat/gpio.h> |
37801b3d | 21 | #include <plat/mcbsp.h> |
7f904c78 | 22 | #include <plat/mcspi.h> |
b6b58229 | 23 | #include <plat/dmtimer.h> |
6ab8946f | 24 | #include <plat/mmc.h> |
de56dbb6 | 25 | #include <plat/l3_2xxx.h> |
02bfc030 | 26 | |
43b40992 PW |
27 | #include "omap_hwmod_common_data.h" |
28 | ||
02bfc030 | 29 | #include "prm-regbits-24xx.h" |
165e2161 | 30 | #include "cm-regbits-24xx.h" |
ff2516fb | 31 | #include "wd_timer.h" |
02bfc030 | 32 | |
7359154e PW |
33 | /* |
34 | * OMAP2430 hardware module integration data | |
35 | * | |
36 | * ALl of the data in this section should be autogeneratable from the | |
37 | * TI hardware database or other technical documentation. Data that | |
38 | * is driver-specific or driver-kernel integration-specific belongs | |
39 | * elsewhere. | |
40 | */ | |
41 | ||
02bfc030 | 42 | static struct omap_hwmod omap2430_mpu_hwmod; |
08072acf | 43 | static struct omap_hwmod omap2430_iva_hwmod; |
4a7cf90a | 44 | static struct omap_hwmod omap2430_l3_main_hwmod; |
02bfc030 | 45 | static struct omap_hwmod omap2430_l4_core_hwmod; |
de56dbb6 SG |
46 | static struct omap_hwmod omap2430_dss_core_hwmod; |
47 | static struct omap_hwmod omap2430_dss_dispc_hwmod; | |
48 | static struct omap_hwmod omap2430_dss_rfbi_hwmod; | |
49 | static struct omap_hwmod omap2430_dss_venc_hwmod; | |
165e2161 | 50 | static struct omap_hwmod omap2430_wd_timer2_hwmod; |
aeac0e44 VC |
51 | static struct omap_hwmod omap2430_gpio1_hwmod; |
52 | static struct omap_hwmod omap2430_gpio2_hwmod; | |
53 | static struct omap_hwmod omap2430_gpio3_hwmod; | |
54 | static struct omap_hwmod omap2430_gpio4_hwmod; | |
55 | static struct omap_hwmod omap2430_gpio5_hwmod; | |
82cbd1ae | 56 | static struct omap_hwmod omap2430_dma_system_hwmod; |
37801b3d C |
57 | static struct omap_hwmod omap2430_mcbsp1_hwmod; |
58 | static struct omap_hwmod omap2430_mcbsp2_hwmod; | |
59 | static struct omap_hwmod omap2430_mcbsp3_hwmod; | |
60 | static struct omap_hwmod omap2430_mcbsp4_hwmod; | |
61 | static struct omap_hwmod omap2430_mcbsp5_hwmod; | |
7f904c78 C |
62 | static struct omap_hwmod omap2430_mcspi1_hwmod; |
63 | static struct omap_hwmod omap2430_mcspi2_hwmod; | |
64 | static struct omap_hwmod omap2430_mcspi3_hwmod; | |
bce06f37 PW |
65 | static struct omap_hwmod omap2430_mmc1_hwmod; |
66 | static struct omap_hwmod omap2430_mmc2_hwmod; | |
02bfc030 PW |
67 | |
68 | /* L3 -> L4_CORE interface */ | |
4a7cf90a KH |
69 | static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { |
70 | .master = &omap2430_l3_main_hwmod, | |
02bfc030 PW |
71 | .slave = &omap2430_l4_core_hwmod, |
72 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
73 | }; | |
74 | ||
75 | /* MPU -> L3 interface */ | |
4a7cf90a | 76 | static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { |
02bfc030 | 77 | .master = &omap2430_mpu_hwmod, |
4a7cf90a | 78 | .slave = &omap2430_l3_main_hwmod, |
02bfc030 PW |
79 | .user = OCP_USER_MPU, |
80 | }; | |
81 | ||
82 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
83 | static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { |
84 | &omap2430_mpu__l3_main, | |
02bfc030 PW |
85 | }; |
86 | ||
de56dbb6 SG |
87 | /* DSS -> l3 */ |
88 | static struct omap_hwmod_ocp_if omap2430_dss__l3 = { | |
89 | .master = &omap2430_dss_core_hwmod, | |
90 | .slave = &omap2430_l3_main_hwmod, | |
91 | .fw = { | |
92 | .omap2 = { | |
93 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, | |
94 | .flags = OMAP_FIREWALL_L3, | |
95 | } | |
96 | }, | |
97 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
98 | }; | |
99 | ||
02bfc030 | 100 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
101 | static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { |
102 | &omap2430_l3_main__l4_core, | |
02bfc030 PW |
103 | }; |
104 | ||
105 | /* L3 */ | |
4a7cf90a | 106 | static struct omap_hwmod omap2430_l3_main_hwmod = { |
fa98347e | 107 | .name = "l3_main", |
43b40992 | 108 | .class = &l3_hwmod_class, |
4a7cf90a KH |
109 | .masters = omap2430_l3_main_masters, |
110 | .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), | |
111 | .slaves = omap2430_l3_main_slaves, | |
112 | .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), | |
2eb1875d KH |
113 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
114 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
115 | }; |
116 | ||
117 | static struct omap_hwmod omap2430_l4_wkup_hwmod; | |
046465b7 KH |
118 | static struct omap_hwmod omap2430_uart1_hwmod; |
119 | static struct omap_hwmod omap2430_uart2_hwmod; | |
120 | static struct omap_hwmod omap2430_uart3_hwmod; | |
2004290f PW |
121 | static struct omap_hwmod omap2430_i2c1_hwmod; |
122 | static struct omap_hwmod omap2430_i2c2_hwmod; | |
123 | ||
44d02acf HH |
124 | static struct omap_hwmod omap2430_usbhsotg_hwmod; |
125 | ||
126 | /* l3_core -> usbhsotg interface */ | |
127 | static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { | |
128 | .master = &omap2430_usbhsotg_hwmod, | |
129 | .slave = &omap2430_l3_main_hwmod, | |
130 | .clk = "core_l3_ck", | |
131 | .user = OCP_USER_MPU, | |
132 | }; | |
133 | ||
2004290f | 134 | /* L4 CORE -> I2C1 interface */ |
2004290f PW |
135 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { |
136 | .master = &omap2430_l4_core_hwmod, | |
137 | .slave = &omap2430_i2c1_hwmod, | |
138 | .clk = "i2c1_ick", | |
ded11383 | 139 | .addr = omap2_i2c1_addr_space, |
2004290f PW |
140 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
141 | }; | |
142 | ||
143 | /* L4 CORE -> I2C2 interface */ | |
2004290f PW |
144 | static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { |
145 | .master = &omap2430_l4_core_hwmod, | |
146 | .slave = &omap2430_i2c2_hwmod, | |
147 | .clk = "i2c2_ick", | |
ded11383 | 148 | .addr = omap2_i2c2_addr_space, |
2004290f PW |
149 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
150 | }; | |
02bfc030 PW |
151 | |
152 | /* L4_CORE -> L4_WKUP interface */ | |
153 | static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { | |
154 | .master = &omap2430_l4_core_hwmod, | |
155 | .slave = &omap2430_l4_wkup_hwmod, | |
156 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
157 | }; | |
158 | ||
046465b7 | 159 | /* L4 CORE -> UART1 interface */ |
046465b7 KH |
160 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
161 | .master = &omap2430_l4_core_hwmod, | |
162 | .slave = &omap2430_uart1_hwmod, | |
163 | .clk = "uart1_ick", | |
ded11383 | 164 | .addr = omap2xxx_uart1_addr_space, |
046465b7 KH |
165 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
166 | }; | |
167 | ||
168 | /* L4 CORE -> UART2 interface */ | |
046465b7 KH |
169 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
170 | .master = &omap2430_l4_core_hwmod, | |
171 | .slave = &omap2430_uart2_hwmod, | |
172 | .clk = "uart2_ick", | |
ded11383 | 173 | .addr = omap2xxx_uart2_addr_space, |
046465b7 KH |
174 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
175 | }; | |
176 | ||
177 | /* L4 PER -> UART3 interface */ | |
046465b7 KH |
178 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
179 | .master = &omap2430_l4_core_hwmod, | |
180 | .slave = &omap2430_uart3_hwmod, | |
181 | .clk = "uart3_ick", | |
ded11383 | 182 | .addr = omap2xxx_uart3_addr_space, |
046465b7 KH |
183 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
184 | }; | |
185 | ||
44d02acf HH |
186 | /* |
187 | * usbhsotg interface data | |
188 | */ | |
189 | static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { | |
190 | { | |
191 | .pa_start = OMAP243X_HS_BASE, | |
192 | .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, | |
193 | .flags = ADDR_TYPE_RT | |
194 | }, | |
195 | }; | |
196 | ||
197 | /* l4_core ->usbhsotg interface */ | |
198 | static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { | |
199 | .master = &omap2430_l4_core_hwmod, | |
200 | .slave = &omap2430_usbhsotg_hwmod, | |
201 | .clk = "usb_l4_ick", | |
202 | .addr = omap2430_usbhsotg_addrs, | |
44d02acf HH |
203 | .user = OCP_USER_MPU, |
204 | }; | |
205 | ||
206 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { | |
207 | &omap2430_usbhsotg__l3, | |
208 | }; | |
209 | ||
210 | static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { | |
211 | &omap2430_l4_core__usbhsotg, | |
212 | }; | |
213 | ||
bce06f37 | 214 | /* L4 CORE -> MMC1 interface */ |
bce06f37 PW |
215 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { |
216 | .master = &omap2430_l4_core_hwmod, | |
217 | .slave = &omap2430_mmc1_hwmod, | |
218 | .clk = "mmchs1_ick", | |
219 | .addr = omap2430_mmc1_addr_space, | |
bce06f37 PW |
220 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
221 | }; | |
222 | ||
223 | /* L4 CORE -> MMC2 interface */ | |
bce06f37 PW |
224 | static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { |
225 | .master = &omap2430_l4_core_hwmod, | |
226 | .slave = &omap2430_mmc2_hwmod, | |
bce06f37 | 227 | .clk = "mmchs2_ick", |
78183f3f | 228 | .addr = omap2430_mmc2_addr_space, |
bce06f37 PW |
229 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
230 | }; | |
231 | ||
02bfc030 PW |
232 | /* Slave interfaces on the L4_CORE interconnect */ |
233 | static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { | |
4a7cf90a | 234 | &omap2430_l3_main__l4_core, |
02bfc030 PW |
235 | }; |
236 | ||
237 | /* Master interfaces on the L4_CORE interconnect */ | |
238 | static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { | |
239 | &omap2430_l4_core__l4_wkup, | |
bce06f37 PW |
240 | &omap2430_l4_core__mmc1, |
241 | &omap2430_l4_core__mmc2, | |
02bfc030 PW |
242 | }; |
243 | ||
244 | /* L4 CORE */ | |
245 | static struct omap_hwmod omap2430_l4_core_hwmod = { | |
fa98347e | 246 | .name = "l4_core", |
43b40992 | 247 | .class = &l4_hwmod_class, |
02bfc030 PW |
248 | .masters = omap2430_l4_core_masters, |
249 | .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), | |
250 | .slaves = omap2430_l4_core_slaves, | |
251 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), | |
2eb1875d KH |
252 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
253 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
254 | }; |
255 | ||
256 | /* Slave interfaces on the L4_WKUP interconnect */ | |
257 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { | |
258 | &omap2430_l4_core__l4_wkup, | |
046465b7 KH |
259 | &omap2_l4_core__uart1, |
260 | &omap2_l4_core__uart2, | |
261 | &omap2_l4_core__uart3, | |
02bfc030 PW |
262 | }; |
263 | ||
264 | /* Master interfaces on the L4_WKUP interconnect */ | |
265 | static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { | |
266 | }; | |
267 | ||
7f904c78 | 268 | /* l4 core -> mcspi1 interface */ |
7f904c78 C |
269 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { |
270 | .master = &omap2430_l4_core_hwmod, | |
271 | .slave = &omap2430_mcspi1_hwmod, | |
272 | .clk = "mcspi1_ick", | |
ded11383 | 273 | .addr = omap2_mcspi1_addr_space, |
7f904c78 C |
274 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
275 | }; | |
276 | ||
277 | /* l4 core -> mcspi2 interface */ | |
7f904c78 C |
278 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { |
279 | .master = &omap2430_l4_core_hwmod, | |
280 | .slave = &omap2430_mcspi2_hwmod, | |
281 | .clk = "mcspi2_ick", | |
ded11383 | 282 | .addr = omap2_mcspi2_addr_space, |
7f904c78 C |
283 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
284 | }; | |
285 | ||
286 | /* l4 core -> mcspi3 interface */ | |
7f904c78 C |
287 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { |
288 | .master = &omap2430_l4_core_hwmod, | |
289 | .slave = &omap2430_mcspi3_hwmod, | |
290 | .clk = "mcspi3_ick", | |
291 | .addr = omap2430_mcspi3_addr_space, | |
7f904c78 C |
292 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
293 | }; | |
294 | ||
02bfc030 PW |
295 | /* L4 WKUP */ |
296 | static struct omap_hwmod omap2430_l4_wkup_hwmod = { | |
fa98347e | 297 | .name = "l4_wkup", |
43b40992 | 298 | .class = &l4_hwmod_class, |
02bfc030 PW |
299 | .masters = omap2430_l4_wkup_masters, |
300 | .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), | |
301 | .slaves = omap2430_l4_wkup_slaves, | |
302 | .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), | |
2eb1875d KH |
303 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
304 | .flags = HWMOD_NO_IDLEST, | |
02bfc030 PW |
305 | }; |
306 | ||
307 | /* Master interfaces on the MPU device */ | |
308 | static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { | |
4a7cf90a | 309 | &omap2430_mpu__l3_main, |
02bfc030 PW |
310 | }; |
311 | ||
312 | /* MPU */ | |
313 | static struct omap_hwmod omap2430_mpu_hwmod = { | |
5c2c0296 | 314 | .name = "mpu", |
43b40992 | 315 | .class = &mpu_hwmod_class, |
50ebdac2 | 316 | .main_clk = "mpu_ck", |
02bfc030 PW |
317 | .masters = omap2430_mpu_masters, |
318 | .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), | |
319 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
320 | }; | |
321 | ||
08072acf PW |
322 | /* |
323 | * IVA2_1 interface data | |
324 | */ | |
325 | ||
326 | /* IVA2 <- L3 interface */ | |
327 | static struct omap_hwmod_ocp_if omap2430_l3__iva = { | |
328 | .master = &omap2430_l3_main_hwmod, | |
329 | .slave = &omap2430_iva_hwmod, | |
330 | .clk = "dsp_fck", | |
331 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
332 | }; | |
333 | ||
334 | static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { | |
335 | &omap2430_l3__iva, | |
336 | }; | |
337 | ||
338 | /* | |
339 | * IVA2 (IVA2) | |
340 | */ | |
341 | ||
342 | static struct omap_hwmod omap2430_iva_hwmod = { | |
343 | .name = "iva", | |
344 | .class = &iva_hwmod_class, | |
345 | .masters = omap2430_iva_masters, | |
346 | .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), | |
347 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
348 | }; | |
349 | ||
b6b58229 TG |
350 | /* Timer Common */ |
351 | static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { | |
352 | .rev_offs = 0x0000, | |
353 | .sysc_offs = 0x0010, | |
354 | .syss_offs = 0x0014, | |
355 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
356 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
357 | SYSC_HAS_AUTOIDLE), | |
358 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
359 | .sysc_fields = &omap_hwmod_sysc_type1, | |
360 | }; | |
361 | ||
362 | static struct omap_hwmod_class omap2430_timer_hwmod_class = { | |
363 | .name = "timer", | |
364 | .sysc = &omap2430_timer_sysc, | |
365 | .rev = OMAP_TIMER_IP_VERSION_1, | |
366 | }; | |
367 | ||
368 | /* timer1 */ | |
369 | static struct omap_hwmod omap2430_timer1_hwmod; | |
b6b58229 TG |
370 | |
371 | static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { | |
372 | { | |
373 | .pa_start = 0x49018000, | |
374 | .pa_end = 0x49018000 + SZ_1K - 1, | |
375 | .flags = ADDR_TYPE_RT | |
376 | }, | |
78183f3f | 377 | { } |
b6b58229 TG |
378 | }; |
379 | ||
380 | /* l4_wkup -> timer1 */ | |
381 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { | |
382 | .master = &omap2430_l4_wkup_hwmod, | |
383 | .slave = &omap2430_timer1_hwmod, | |
384 | .clk = "gpt1_ick", | |
385 | .addr = omap2430_timer1_addrs, | |
b6b58229 TG |
386 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
387 | }; | |
388 | ||
389 | /* timer1 slave port */ | |
390 | static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { | |
391 | &omap2430_l4_wkup__timer1, | |
392 | }; | |
393 | ||
394 | /* timer1 hwmod */ | |
395 | static struct omap_hwmod omap2430_timer1_hwmod = { | |
396 | .name = "timer1", | |
0d619a89 | 397 | .mpu_irqs = omap2_timer1_mpu_irqs, |
b6b58229 TG |
398 | .main_clk = "gpt1_fck", |
399 | .prcm = { | |
400 | .omap2 = { | |
401 | .prcm_reg_id = 1, | |
402 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, | |
403 | .module_offs = WKUP_MOD, | |
404 | .idlest_reg_id = 1, | |
405 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, | |
406 | }, | |
407 | }, | |
408 | .slaves = omap2430_timer1_slaves, | |
409 | .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), | |
410 | .class = &omap2430_timer_hwmod_class, | |
411 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
412 | }; | |
413 | ||
414 | /* timer2 */ | |
415 | static struct omap_hwmod omap2430_timer2_hwmod; | |
b6b58229 | 416 | |
b6b58229 TG |
417 | /* l4_core -> timer2 */ |
418 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { | |
419 | .master = &omap2430_l4_core_hwmod, | |
420 | .slave = &omap2430_timer2_hwmod, | |
421 | .clk = "gpt2_ick", | |
ded11383 | 422 | .addr = omap2xxx_timer2_addrs, |
b6b58229 TG |
423 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
424 | }; | |
425 | ||
426 | /* timer2 slave port */ | |
427 | static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { | |
428 | &omap2430_l4_core__timer2, | |
429 | }; | |
430 | ||
431 | /* timer2 hwmod */ | |
432 | static struct omap_hwmod omap2430_timer2_hwmod = { | |
433 | .name = "timer2", | |
0d619a89 | 434 | .mpu_irqs = omap2_timer2_mpu_irqs, |
b6b58229 TG |
435 | .main_clk = "gpt2_fck", |
436 | .prcm = { | |
437 | .omap2 = { | |
438 | .prcm_reg_id = 1, | |
439 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, | |
440 | .module_offs = CORE_MOD, | |
441 | .idlest_reg_id = 1, | |
442 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, | |
443 | }, | |
444 | }, | |
445 | .slaves = omap2430_timer2_slaves, | |
446 | .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), | |
447 | .class = &omap2430_timer_hwmod_class, | |
448 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
449 | }; | |
450 | ||
451 | /* timer3 */ | |
452 | static struct omap_hwmod omap2430_timer3_hwmod; | |
b6b58229 | 453 | |
b6b58229 TG |
454 | /* l4_core -> timer3 */ |
455 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { | |
456 | .master = &omap2430_l4_core_hwmod, | |
457 | .slave = &omap2430_timer3_hwmod, | |
458 | .clk = "gpt3_ick", | |
ded11383 | 459 | .addr = omap2xxx_timer3_addrs, |
b6b58229 TG |
460 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
461 | }; | |
462 | ||
463 | /* timer3 slave port */ | |
464 | static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { | |
465 | &omap2430_l4_core__timer3, | |
466 | }; | |
467 | ||
468 | /* timer3 hwmod */ | |
469 | static struct omap_hwmod omap2430_timer3_hwmod = { | |
470 | .name = "timer3", | |
0d619a89 | 471 | .mpu_irqs = omap2_timer3_mpu_irqs, |
b6b58229 TG |
472 | .main_clk = "gpt3_fck", |
473 | .prcm = { | |
474 | .omap2 = { | |
475 | .prcm_reg_id = 1, | |
476 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, | |
477 | .module_offs = CORE_MOD, | |
478 | .idlest_reg_id = 1, | |
479 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, | |
480 | }, | |
481 | }, | |
482 | .slaves = omap2430_timer3_slaves, | |
483 | .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), | |
484 | .class = &omap2430_timer_hwmod_class, | |
485 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
486 | }; | |
487 | ||
488 | /* timer4 */ | |
489 | static struct omap_hwmod omap2430_timer4_hwmod; | |
b6b58229 | 490 | |
b6b58229 TG |
491 | /* l4_core -> timer4 */ |
492 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { | |
493 | .master = &omap2430_l4_core_hwmod, | |
494 | .slave = &omap2430_timer4_hwmod, | |
495 | .clk = "gpt4_ick", | |
ded11383 | 496 | .addr = omap2xxx_timer4_addrs, |
b6b58229 TG |
497 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
498 | }; | |
499 | ||
500 | /* timer4 slave port */ | |
501 | static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { | |
502 | &omap2430_l4_core__timer4, | |
503 | }; | |
504 | ||
505 | /* timer4 hwmod */ | |
506 | static struct omap_hwmod omap2430_timer4_hwmod = { | |
507 | .name = "timer4", | |
0d619a89 | 508 | .mpu_irqs = omap2_timer4_mpu_irqs, |
b6b58229 TG |
509 | .main_clk = "gpt4_fck", |
510 | .prcm = { | |
511 | .omap2 = { | |
512 | .prcm_reg_id = 1, | |
513 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, | |
514 | .module_offs = CORE_MOD, | |
515 | .idlest_reg_id = 1, | |
516 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, | |
517 | }, | |
518 | }, | |
519 | .slaves = omap2430_timer4_slaves, | |
520 | .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), | |
521 | .class = &omap2430_timer_hwmod_class, | |
522 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
523 | }; | |
524 | ||
525 | /* timer5 */ | |
526 | static struct omap_hwmod omap2430_timer5_hwmod; | |
b6b58229 | 527 | |
b6b58229 TG |
528 | /* l4_core -> timer5 */ |
529 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { | |
530 | .master = &omap2430_l4_core_hwmod, | |
531 | .slave = &omap2430_timer5_hwmod, | |
532 | .clk = "gpt5_ick", | |
ded11383 | 533 | .addr = omap2xxx_timer5_addrs, |
b6b58229 TG |
534 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
535 | }; | |
536 | ||
537 | /* timer5 slave port */ | |
538 | static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { | |
539 | &omap2430_l4_core__timer5, | |
540 | }; | |
541 | ||
542 | /* timer5 hwmod */ | |
543 | static struct omap_hwmod omap2430_timer5_hwmod = { | |
544 | .name = "timer5", | |
0d619a89 | 545 | .mpu_irqs = omap2_timer5_mpu_irqs, |
b6b58229 TG |
546 | .main_clk = "gpt5_fck", |
547 | .prcm = { | |
548 | .omap2 = { | |
549 | .prcm_reg_id = 1, | |
550 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, | |
551 | .module_offs = CORE_MOD, | |
552 | .idlest_reg_id = 1, | |
553 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, | |
554 | }, | |
555 | }, | |
556 | .slaves = omap2430_timer5_slaves, | |
557 | .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), | |
558 | .class = &omap2430_timer_hwmod_class, | |
559 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
560 | }; | |
561 | ||
562 | /* timer6 */ | |
563 | static struct omap_hwmod omap2430_timer6_hwmod; | |
b6b58229 | 564 | |
b6b58229 TG |
565 | /* l4_core -> timer6 */ |
566 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { | |
567 | .master = &omap2430_l4_core_hwmod, | |
568 | .slave = &omap2430_timer6_hwmod, | |
569 | .clk = "gpt6_ick", | |
ded11383 | 570 | .addr = omap2xxx_timer6_addrs, |
b6b58229 TG |
571 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
572 | }; | |
573 | ||
574 | /* timer6 slave port */ | |
575 | static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { | |
576 | &omap2430_l4_core__timer6, | |
577 | }; | |
578 | ||
579 | /* timer6 hwmod */ | |
580 | static struct omap_hwmod omap2430_timer6_hwmod = { | |
581 | .name = "timer6", | |
0d619a89 | 582 | .mpu_irqs = omap2_timer6_mpu_irqs, |
b6b58229 TG |
583 | .main_clk = "gpt6_fck", |
584 | .prcm = { | |
585 | .omap2 = { | |
586 | .prcm_reg_id = 1, | |
587 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, | |
588 | .module_offs = CORE_MOD, | |
589 | .idlest_reg_id = 1, | |
590 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, | |
591 | }, | |
592 | }, | |
593 | .slaves = omap2430_timer6_slaves, | |
594 | .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), | |
595 | .class = &omap2430_timer_hwmod_class, | |
596 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
597 | }; | |
598 | ||
599 | /* timer7 */ | |
600 | static struct omap_hwmod omap2430_timer7_hwmod; | |
b6b58229 | 601 | |
b6b58229 TG |
602 | /* l4_core -> timer7 */ |
603 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { | |
604 | .master = &omap2430_l4_core_hwmod, | |
605 | .slave = &omap2430_timer7_hwmod, | |
606 | .clk = "gpt7_ick", | |
ded11383 | 607 | .addr = omap2xxx_timer7_addrs, |
b6b58229 TG |
608 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
609 | }; | |
610 | ||
611 | /* timer7 slave port */ | |
612 | static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { | |
613 | &omap2430_l4_core__timer7, | |
614 | }; | |
615 | ||
616 | /* timer7 hwmod */ | |
617 | static struct omap_hwmod omap2430_timer7_hwmod = { | |
618 | .name = "timer7", | |
0d619a89 | 619 | .mpu_irqs = omap2_timer7_mpu_irqs, |
b6b58229 TG |
620 | .main_clk = "gpt7_fck", |
621 | .prcm = { | |
622 | .omap2 = { | |
623 | .prcm_reg_id = 1, | |
624 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, | |
625 | .module_offs = CORE_MOD, | |
626 | .idlest_reg_id = 1, | |
627 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, | |
628 | }, | |
629 | }, | |
630 | .slaves = omap2430_timer7_slaves, | |
631 | .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), | |
632 | .class = &omap2430_timer_hwmod_class, | |
633 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
634 | }; | |
635 | ||
636 | /* timer8 */ | |
637 | static struct omap_hwmod omap2430_timer8_hwmod; | |
b6b58229 | 638 | |
b6b58229 TG |
639 | /* l4_core -> timer8 */ |
640 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { | |
641 | .master = &omap2430_l4_core_hwmod, | |
642 | .slave = &omap2430_timer8_hwmod, | |
643 | .clk = "gpt8_ick", | |
ded11383 | 644 | .addr = omap2xxx_timer8_addrs, |
b6b58229 TG |
645 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
646 | }; | |
647 | ||
648 | /* timer8 slave port */ | |
649 | static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { | |
650 | &omap2430_l4_core__timer8, | |
651 | }; | |
652 | ||
653 | /* timer8 hwmod */ | |
654 | static struct omap_hwmod omap2430_timer8_hwmod = { | |
655 | .name = "timer8", | |
0d619a89 | 656 | .mpu_irqs = omap2_timer8_mpu_irqs, |
b6b58229 TG |
657 | .main_clk = "gpt8_fck", |
658 | .prcm = { | |
659 | .omap2 = { | |
660 | .prcm_reg_id = 1, | |
661 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, | |
662 | .module_offs = CORE_MOD, | |
663 | .idlest_reg_id = 1, | |
664 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, | |
665 | }, | |
666 | }, | |
667 | .slaves = omap2430_timer8_slaves, | |
668 | .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), | |
669 | .class = &omap2430_timer_hwmod_class, | |
670 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
671 | }; | |
672 | ||
673 | /* timer9 */ | |
674 | static struct omap_hwmod omap2430_timer9_hwmod; | |
b6b58229 | 675 | |
b6b58229 TG |
676 | /* l4_core -> timer9 */ |
677 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { | |
678 | .master = &omap2430_l4_core_hwmod, | |
679 | .slave = &omap2430_timer9_hwmod, | |
680 | .clk = "gpt9_ick", | |
ded11383 | 681 | .addr = omap2xxx_timer9_addrs, |
b6b58229 TG |
682 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
683 | }; | |
684 | ||
685 | /* timer9 slave port */ | |
686 | static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { | |
687 | &omap2430_l4_core__timer9, | |
688 | }; | |
689 | ||
690 | /* timer9 hwmod */ | |
691 | static struct omap_hwmod omap2430_timer9_hwmod = { | |
692 | .name = "timer9", | |
0d619a89 | 693 | .mpu_irqs = omap2_timer9_mpu_irqs, |
b6b58229 TG |
694 | .main_clk = "gpt9_fck", |
695 | .prcm = { | |
696 | .omap2 = { | |
697 | .prcm_reg_id = 1, | |
698 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, | |
699 | .module_offs = CORE_MOD, | |
700 | .idlest_reg_id = 1, | |
701 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, | |
702 | }, | |
703 | }, | |
704 | .slaves = omap2430_timer9_slaves, | |
705 | .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), | |
706 | .class = &omap2430_timer_hwmod_class, | |
707 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
708 | }; | |
709 | ||
710 | /* timer10 */ | |
711 | static struct omap_hwmod omap2430_timer10_hwmod; | |
b6b58229 | 712 | |
b6b58229 TG |
713 | /* l4_core -> timer10 */ |
714 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { | |
715 | .master = &omap2430_l4_core_hwmod, | |
716 | .slave = &omap2430_timer10_hwmod, | |
717 | .clk = "gpt10_ick", | |
ded11383 | 718 | .addr = omap2_timer10_addrs, |
b6b58229 TG |
719 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
720 | }; | |
721 | ||
722 | /* timer10 slave port */ | |
723 | static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { | |
724 | &omap2430_l4_core__timer10, | |
725 | }; | |
726 | ||
727 | /* timer10 hwmod */ | |
728 | static struct omap_hwmod omap2430_timer10_hwmod = { | |
729 | .name = "timer10", | |
0d619a89 | 730 | .mpu_irqs = omap2_timer10_mpu_irqs, |
b6b58229 TG |
731 | .main_clk = "gpt10_fck", |
732 | .prcm = { | |
733 | .omap2 = { | |
734 | .prcm_reg_id = 1, | |
735 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, | |
736 | .module_offs = CORE_MOD, | |
737 | .idlest_reg_id = 1, | |
738 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, | |
739 | }, | |
740 | }, | |
741 | .slaves = omap2430_timer10_slaves, | |
742 | .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), | |
743 | .class = &omap2430_timer_hwmod_class, | |
744 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
745 | }; | |
746 | ||
747 | /* timer11 */ | |
748 | static struct omap_hwmod omap2430_timer11_hwmod; | |
b6b58229 | 749 | |
b6b58229 TG |
750 | /* l4_core -> timer11 */ |
751 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { | |
752 | .master = &omap2430_l4_core_hwmod, | |
753 | .slave = &omap2430_timer11_hwmod, | |
754 | .clk = "gpt11_ick", | |
ded11383 | 755 | .addr = omap2_timer11_addrs, |
b6b58229 TG |
756 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
757 | }; | |
758 | ||
759 | /* timer11 slave port */ | |
760 | static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { | |
761 | &omap2430_l4_core__timer11, | |
762 | }; | |
763 | ||
764 | /* timer11 hwmod */ | |
765 | static struct omap_hwmod omap2430_timer11_hwmod = { | |
766 | .name = "timer11", | |
0d619a89 | 767 | .mpu_irqs = omap2_timer11_mpu_irqs, |
b6b58229 TG |
768 | .main_clk = "gpt11_fck", |
769 | .prcm = { | |
770 | .omap2 = { | |
771 | .prcm_reg_id = 1, | |
772 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, | |
773 | .module_offs = CORE_MOD, | |
774 | .idlest_reg_id = 1, | |
775 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, | |
776 | }, | |
777 | }, | |
778 | .slaves = omap2430_timer11_slaves, | |
779 | .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), | |
780 | .class = &omap2430_timer_hwmod_class, | |
781 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
782 | }; | |
783 | ||
784 | /* timer12 */ | |
785 | static struct omap_hwmod omap2430_timer12_hwmod; | |
b6b58229 | 786 | |
b6b58229 TG |
787 | /* l4_core -> timer12 */ |
788 | static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { | |
789 | .master = &omap2430_l4_core_hwmod, | |
790 | .slave = &omap2430_timer12_hwmod, | |
791 | .clk = "gpt12_ick", | |
ded11383 | 792 | .addr = omap2xxx_timer12_addrs, |
b6b58229 TG |
793 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
794 | }; | |
795 | ||
796 | /* timer12 slave port */ | |
797 | static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { | |
798 | &omap2430_l4_core__timer12, | |
799 | }; | |
800 | ||
801 | /* timer12 hwmod */ | |
802 | static struct omap_hwmod omap2430_timer12_hwmod = { | |
803 | .name = "timer12", | |
0d619a89 | 804 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
b6b58229 TG |
805 | .main_clk = "gpt12_fck", |
806 | .prcm = { | |
807 | .omap2 = { | |
808 | .prcm_reg_id = 1, | |
809 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, | |
810 | .module_offs = CORE_MOD, | |
811 | .idlest_reg_id = 1, | |
812 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, | |
813 | }, | |
814 | }, | |
815 | .slaves = omap2430_timer12_slaves, | |
816 | .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), | |
817 | .class = &omap2430_timer_hwmod_class, | |
818 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
819 | }; | |
820 | ||
165e2161 VC |
821 | /* l4_wkup -> wd_timer2 */ |
822 | static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { | |
823 | { | |
824 | .pa_start = 0x49016000, | |
825 | .pa_end = 0x4901607f, | |
826 | .flags = ADDR_TYPE_RT | |
827 | }, | |
78183f3f | 828 | { } |
165e2161 VC |
829 | }; |
830 | ||
831 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { | |
832 | .master = &omap2430_l4_wkup_hwmod, | |
833 | .slave = &omap2430_wd_timer2_hwmod, | |
834 | .clk = "mpu_wdt_ick", | |
835 | .addr = omap2430_wd_timer2_addrs, | |
165e2161 VC |
836 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
837 | }; | |
838 | ||
839 | /* | |
840 | * 'wd_timer' class | |
841 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
842 | * overflow condition | |
843 | */ | |
844 | ||
845 | static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { | |
846 | .rev_offs = 0x0, | |
847 | .sysc_offs = 0x0010, | |
848 | .syss_offs = 0x0014, | |
849 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 850 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
165e2161 VC |
851 | .sysc_fields = &omap_hwmod_sysc_type1, |
852 | }; | |
853 | ||
854 | static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { | |
ff2516fb PW |
855 | .name = "wd_timer", |
856 | .sysc = &omap2430_wd_timer_sysc, | |
857 | .pre_shutdown = &omap2_wd_timer_disable | |
165e2161 VC |
858 | }; |
859 | ||
860 | /* wd_timer2 */ | |
861 | static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { | |
862 | &omap2430_l4_wkup__wd_timer2, | |
863 | }; | |
864 | ||
865 | static struct omap_hwmod omap2430_wd_timer2_hwmod = { | |
866 | .name = "wd_timer2", | |
867 | .class = &omap2430_wd_timer_hwmod_class, | |
868 | .main_clk = "mpu_wdt_fck", | |
869 | .prcm = { | |
870 | .omap2 = { | |
871 | .prcm_reg_id = 1, | |
872 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | |
873 | .module_offs = WKUP_MOD, | |
874 | .idlest_reg_id = 1, | |
875 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, | |
876 | }, | |
877 | }, | |
878 | .slaves = omap2430_wd_timer2_slaves, | |
879 | .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), | |
880 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
881 | }; | |
882 | ||
046465b7 KH |
883 | /* UART */ |
884 | ||
885 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
886 | .rev_offs = 0x50, | |
887 | .sysc_offs = 0x54, | |
888 | .syss_offs = 0x58, | |
889 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
890 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2d403fe0 | 891 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
046465b7 KH |
892 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
893 | .sysc_fields = &omap_hwmod_sysc_type1, | |
894 | }; | |
895 | ||
896 | static struct omap_hwmod_class uart_class = { | |
897 | .name = "uart", | |
898 | .sysc = &uart_sysc, | |
899 | }; | |
900 | ||
901 | /* UART1 */ | |
902 | ||
046465b7 KH |
903 | static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { |
904 | &omap2_l4_core__uart1, | |
905 | }; | |
906 | ||
907 | static struct omap_hwmod omap2430_uart1_hwmod = { | |
908 | .name = "uart1", | |
0d619a89 | 909 | .mpu_irqs = omap2_uart1_mpu_irqs, |
d826ebfa | 910 | .sdma_reqs = omap2_uart1_sdma_reqs, |
046465b7 KH |
911 | .main_clk = "uart1_fck", |
912 | .prcm = { | |
913 | .omap2 = { | |
914 | .module_offs = CORE_MOD, | |
915 | .prcm_reg_id = 1, | |
916 | .module_bit = OMAP24XX_EN_UART1_SHIFT, | |
917 | .idlest_reg_id = 1, | |
918 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, | |
919 | }, | |
920 | }, | |
921 | .slaves = omap2430_uart1_slaves, | |
922 | .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), | |
923 | .class = &uart_class, | |
924 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
925 | }; | |
926 | ||
927 | /* UART2 */ | |
928 | ||
046465b7 KH |
929 | static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { |
930 | &omap2_l4_core__uart2, | |
931 | }; | |
932 | ||
933 | static struct omap_hwmod omap2430_uart2_hwmod = { | |
934 | .name = "uart2", | |
0d619a89 | 935 | .mpu_irqs = omap2_uart2_mpu_irqs, |
d826ebfa | 936 | .sdma_reqs = omap2_uart2_sdma_reqs, |
046465b7 KH |
937 | .main_clk = "uart2_fck", |
938 | .prcm = { | |
939 | .omap2 = { | |
940 | .module_offs = CORE_MOD, | |
941 | .prcm_reg_id = 1, | |
942 | .module_bit = OMAP24XX_EN_UART2_SHIFT, | |
943 | .idlest_reg_id = 1, | |
944 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, | |
945 | }, | |
946 | }, | |
947 | .slaves = omap2430_uart2_slaves, | |
948 | .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), | |
949 | .class = &uart_class, | |
950 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
951 | }; | |
952 | ||
953 | /* UART3 */ | |
954 | ||
046465b7 KH |
955 | static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { |
956 | &omap2_l4_core__uart3, | |
957 | }; | |
958 | ||
959 | static struct omap_hwmod omap2430_uart3_hwmod = { | |
960 | .name = "uart3", | |
0d619a89 | 961 | .mpu_irqs = omap2_uart3_mpu_irqs, |
d826ebfa | 962 | .sdma_reqs = omap2_uart3_sdma_reqs, |
046465b7 KH |
963 | .main_clk = "uart3_fck", |
964 | .prcm = { | |
965 | .omap2 = { | |
966 | .module_offs = CORE_MOD, | |
967 | .prcm_reg_id = 2, | |
968 | .module_bit = OMAP24XX_EN_UART3_SHIFT, | |
969 | .idlest_reg_id = 2, | |
970 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, | |
971 | }, | |
972 | }, | |
973 | .slaves = omap2430_uart3_slaves, | |
974 | .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), | |
975 | .class = &uart_class, | |
976 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
977 | }; | |
978 | ||
de56dbb6 SG |
979 | /* |
980 | * 'dss' class | |
981 | * display sub-system | |
982 | */ | |
983 | ||
984 | static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { | |
985 | .rev_offs = 0x0000, | |
986 | .sysc_offs = 0x0010, | |
987 | .syss_offs = 0x0014, | |
988 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
989 | .sysc_fields = &omap_hwmod_sysc_type1, | |
990 | }; | |
991 | ||
992 | static struct omap_hwmod_class omap2430_dss_hwmod_class = { | |
993 | .name = "dss", | |
994 | .sysc = &omap2430_dss_sysc, | |
995 | }; | |
996 | ||
de56dbb6 SG |
997 | /* dss */ |
998 | /* dss master ports */ | |
999 | static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { | |
1000 | &omap2430_dss__l3, | |
1001 | }; | |
1002 | ||
de56dbb6 SG |
1003 | /* l4_core -> dss */ |
1004 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { | |
1005 | .master = &omap2430_l4_core_hwmod, | |
1006 | .slave = &omap2430_dss_core_hwmod, | |
1007 | .clk = "dss_ick", | |
ded11383 | 1008 | .addr = omap2_dss_addrs, |
de56dbb6 SG |
1009 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1010 | }; | |
1011 | ||
1012 | /* dss slave ports */ | |
1013 | static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { | |
1014 | &omap2430_l4_core__dss, | |
1015 | }; | |
1016 | ||
1017 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
1018 | { .role = "tv_clk", .clk = "dss_54m_fck" }, | |
1019 | { .role = "sys_clk", .clk = "dss2_fck" }, | |
1020 | }; | |
1021 | ||
1022 | static struct omap_hwmod omap2430_dss_core_hwmod = { | |
1023 | .name = "dss_core", | |
1024 | .class = &omap2430_dss_hwmod_class, | |
1025 | .main_clk = "dss1_fck", /* instead of dss_fck */ | |
d826ebfa | 1026 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
de56dbb6 SG |
1027 | .prcm = { |
1028 | .omap2 = { | |
1029 | .prcm_reg_id = 1, | |
1030 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1031 | .module_offs = CORE_MOD, | |
1032 | .idlest_reg_id = 1, | |
1033 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
1034 | }, | |
1035 | }, | |
1036 | .opt_clks = dss_opt_clks, | |
1037 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
1038 | .slaves = omap2430_dss_slaves, | |
1039 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), | |
1040 | .masters = omap2430_dss_masters, | |
1041 | .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), | |
1042 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1043 | .flags = HWMOD_NO_IDLEST, | |
1044 | }; | |
1045 | ||
1046 | /* | |
1047 | * 'dispc' class | |
1048 | * display controller | |
1049 | */ | |
1050 | ||
1051 | static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { | |
1052 | .rev_offs = 0x0000, | |
1053 | .sysc_offs = 0x0010, | |
1054 | .syss_offs = 0x0014, | |
1055 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | | |
1056 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1057 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1058 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1059 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1060 | }; | |
1061 | ||
1062 | static struct omap_hwmod_class omap2430_dispc_hwmod_class = { | |
1063 | .name = "dispc", | |
1064 | .sysc = &omap2430_dispc_sysc, | |
1065 | }; | |
1066 | ||
de56dbb6 SG |
1067 | /* l4_core -> dss_dispc */ |
1068 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { | |
1069 | .master = &omap2430_l4_core_hwmod, | |
1070 | .slave = &omap2430_dss_dispc_hwmod, | |
1071 | .clk = "dss_ick", | |
ded11383 | 1072 | .addr = omap2_dss_dispc_addrs, |
de56dbb6 SG |
1073 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1074 | }; | |
1075 | ||
1076 | /* dss_dispc slave ports */ | |
1077 | static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { | |
1078 | &omap2430_l4_core__dss_dispc, | |
1079 | }; | |
1080 | ||
1081 | static struct omap_hwmod omap2430_dss_dispc_hwmod = { | |
1082 | .name = "dss_dispc", | |
1083 | .class = &omap2430_dispc_hwmod_class, | |
0d619a89 | 1084 | .mpu_irqs = omap2_dispc_irqs, |
de56dbb6 SG |
1085 | .main_clk = "dss1_fck", |
1086 | .prcm = { | |
1087 | .omap2 = { | |
1088 | .prcm_reg_id = 1, | |
1089 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1090 | .module_offs = CORE_MOD, | |
1091 | .idlest_reg_id = 1, | |
1092 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, | |
1093 | }, | |
1094 | }, | |
1095 | .slaves = omap2430_dss_dispc_slaves, | |
1096 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), | |
1097 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1098 | .flags = HWMOD_NO_IDLEST, | |
1099 | }; | |
1100 | ||
1101 | /* | |
1102 | * 'rfbi' class | |
1103 | * remote frame buffer interface | |
1104 | */ | |
1105 | ||
1106 | static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { | |
1107 | .rev_offs = 0x0000, | |
1108 | .sysc_offs = 0x0010, | |
1109 | .syss_offs = 0x0014, | |
1110 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1111 | SYSC_HAS_AUTOIDLE), | |
1112 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1113 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1114 | }; | |
1115 | ||
1116 | static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { | |
1117 | .name = "rfbi", | |
1118 | .sysc = &omap2430_rfbi_sysc, | |
1119 | }; | |
1120 | ||
de56dbb6 SG |
1121 | /* l4_core -> dss_rfbi */ |
1122 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { | |
1123 | .master = &omap2430_l4_core_hwmod, | |
1124 | .slave = &omap2430_dss_rfbi_hwmod, | |
1125 | .clk = "dss_ick", | |
ded11383 | 1126 | .addr = omap2_dss_rfbi_addrs, |
de56dbb6 SG |
1127 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1128 | }; | |
1129 | ||
1130 | /* dss_rfbi slave ports */ | |
1131 | static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { | |
1132 | &omap2430_l4_core__dss_rfbi, | |
1133 | }; | |
1134 | ||
1135 | static struct omap_hwmod omap2430_dss_rfbi_hwmod = { | |
1136 | .name = "dss_rfbi", | |
1137 | .class = &omap2430_rfbi_hwmod_class, | |
1138 | .main_clk = "dss1_fck", | |
1139 | .prcm = { | |
1140 | .omap2 = { | |
1141 | .prcm_reg_id = 1, | |
1142 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1143 | .module_offs = CORE_MOD, | |
1144 | }, | |
1145 | }, | |
1146 | .slaves = omap2430_dss_rfbi_slaves, | |
1147 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), | |
1148 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1149 | .flags = HWMOD_NO_IDLEST, | |
1150 | }; | |
1151 | ||
1152 | /* | |
1153 | * 'venc' class | |
1154 | * video encoder | |
1155 | */ | |
1156 | ||
1157 | static struct omap_hwmod_class omap2430_venc_hwmod_class = { | |
1158 | .name = "venc", | |
1159 | }; | |
1160 | ||
de56dbb6 SG |
1161 | /* l4_core -> dss_venc */ |
1162 | static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { | |
1163 | .master = &omap2430_l4_core_hwmod, | |
1164 | .slave = &omap2430_dss_venc_hwmod, | |
1165 | .clk = "dss_54m_fck", | |
ded11383 | 1166 | .addr = omap2_dss_venc_addrs, |
c39bee8a | 1167 | .flags = OCPIF_SWSUP_IDLE, |
de56dbb6 SG |
1168 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1169 | }; | |
1170 | ||
1171 | /* dss_venc slave ports */ | |
1172 | static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { | |
1173 | &omap2430_l4_core__dss_venc, | |
1174 | }; | |
1175 | ||
1176 | static struct omap_hwmod omap2430_dss_venc_hwmod = { | |
1177 | .name = "dss_venc", | |
1178 | .class = &omap2430_venc_hwmod_class, | |
1179 | .main_clk = "dss1_fck", | |
1180 | .prcm = { | |
1181 | .omap2 = { | |
1182 | .prcm_reg_id = 1, | |
1183 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, | |
1184 | .module_offs = CORE_MOD, | |
1185 | }, | |
1186 | }, | |
1187 | .slaves = omap2430_dss_venc_slaves, | |
1188 | .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), | |
1189 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1190 | .flags = HWMOD_NO_IDLEST, | |
1191 | }; | |
1192 | ||
2004290f PW |
1193 | /* I2C common */ |
1194 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
1195 | .rev_offs = 0x00, | |
1196 | .sysc_offs = 0x20, | |
1197 | .syss_offs = 0x10, | |
2d403fe0 PW |
1198 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1199 | SYSS_HAS_RESET_STATUS), | |
2004290f PW |
1200 | .sysc_fields = &omap_hwmod_sysc_type1, |
1201 | }; | |
1202 | ||
1203 | static struct omap_hwmod_class i2c_class = { | |
1204 | .name = "i2c", | |
1205 | .sysc = &i2c_sysc, | |
1206 | }; | |
1207 | ||
50ebb777 | 1208 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
2004290f PW |
1209 | .fifo_depth = 8, /* bytes */ |
1210 | }; | |
1211 | ||
50ebb777 BC |
1212 | /* I2C1 */ |
1213 | ||
2004290f PW |
1214 | static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { |
1215 | &omap2430_l4_core__i2c1, | |
1216 | }; | |
1217 | ||
1218 | static struct omap_hwmod omap2430_i2c1_hwmod = { | |
1219 | .name = "i2c1", | |
0d619a89 | 1220 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
d826ebfa | 1221 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
2004290f PW |
1222 | .main_clk = "i2chs1_fck", |
1223 | .prcm = { | |
1224 | .omap2 = { | |
1225 | /* | |
1226 | * NOTE: The CM_FCLKEN* and CM_ICLKEN* for | |
1227 | * I2CHS IP's do not follow the usual pattern. | |
1228 | * prcm_reg_id alone cannot be used to program | |
1229 | * the iclk and fclk. Needs to be handled using | |
25985edc | 1230 | * additional flags when clk handling is moved |
2004290f PW |
1231 | * to hwmod framework. |
1232 | */ | |
1233 | .module_offs = CORE_MOD, | |
1234 | .prcm_reg_id = 1, | |
1235 | .module_bit = OMAP2430_EN_I2CHS1_SHIFT, | |
1236 | .idlest_reg_id = 1, | |
1237 | .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, | |
1238 | }, | |
1239 | }, | |
1240 | .slaves = omap2430_i2c1_slaves, | |
1241 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), | |
1242 | .class = &i2c_class, | |
50ebb777 | 1243 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
1244 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1245 | }; | |
1246 | ||
1247 | /* I2C2 */ | |
1248 | ||
2004290f PW |
1249 | static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { |
1250 | &omap2430_l4_core__i2c2, | |
1251 | }; | |
1252 | ||
1253 | static struct omap_hwmod omap2430_i2c2_hwmod = { | |
1254 | .name = "i2c2", | |
0d619a89 | 1255 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
d826ebfa | 1256 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
2004290f PW |
1257 | .main_clk = "i2chs2_fck", |
1258 | .prcm = { | |
1259 | .omap2 = { | |
1260 | .module_offs = CORE_MOD, | |
1261 | .prcm_reg_id = 1, | |
1262 | .module_bit = OMAP2430_EN_I2CHS2_SHIFT, | |
1263 | .idlest_reg_id = 1, | |
1264 | .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, | |
1265 | }, | |
1266 | }, | |
1267 | .slaves = omap2430_i2c2_slaves, | |
1268 | .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), | |
1269 | .class = &i2c_class, | |
50ebb777 | 1270 | .dev_attr = &i2c_dev_attr, |
2004290f PW |
1271 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
1272 | }; | |
1273 | ||
aeac0e44 VC |
1274 | /* l4_wkup -> gpio1 */ |
1275 | static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { | |
1276 | { | |
1277 | .pa_start = 0x4900C000, | |
1278 | .pa_end = 0x4900C1ff, | |
1279 | .flags = ADDR_TYPE_RT | |
1280 | }, | |
78183f3f | 1281 | { } |
aeac0e44 VC |
1282 | }; |
1283 | ||
1284 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { | |
1285 | .master = &omap2430_l4_wkup_hwmod, | |
1286 | .slave = &omap2430_gpio1_hwmod, | |
1287 | .clk = "gpios_ick", | |
1288 | .addr = omap2430_gpio1_addr_space, | |
aeac0e44 VC |
1289 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1290 | }; | |
1291 | ||
1292 | /* l4_wkup -> gpio2 */ | |
1293 | static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { | |
1294 | { | |
1295 | .pa_start = 0x4900E000, | |
1296 | .pa_end = 0x4900E1ff, | |
1297 | .flags = ADDR_TYPE_RT | |
1298 | }, | |
78183f3f | 1299 | { } |
aeac0e44 VC |
1300 | }; |
1301 | ||
1302 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { | |
1303 | .master = &omap2430_l4_wkup_hwmod, | |
1304 | .slave = &omap2430_gpio2_hwmod, | |
1305 | .clk = "gpios_ick", | |
1306 | .addr = omap2430_gpio2_addr_space, | |
aeac0e44 VC |
1307 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1308 | }; | |
1309 | ||
1310 | /* l4_wkup -> gpio3 */ | |
1311 | static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { | |
1312 | { | |
1313 | .pa_start = 0x49010000, | |
1314 | .pa_end = 0x490101ff, | |
1315 | .flags = ADDR_TYPE_RT | |
1316 | }, | |
78183f3f | 1317 | { } |
aeac0e44 VC |
1318 | }; |
1319 | ||
1320 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { | |
1321 | .master = &omap2430_l4_wkup_hwmod, | |
1322 | .slave = &omap2430_gpio3_hwmod, | |
1323 | .clk = "gpios_ick", | |
1324 | .addr = omap2430_gpio3_addr_space, | |
aeac0e44 VC |
1325 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1326 | }; | |
1327 | ||
1328 | /* l4_wkup -> gpio4 */ | |
1329 | static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { | |
1330 | { | |
1331 | .pa_start = 0x49012000, | |
1332 | .pa_end = 0x490121ff, | |
1333 | .flags = ADDR_TYPE_RT | |
1334 | }, | |
78183f3f | 1335 | { } |
aeac0e44 VC |
1336 | }; |
1337 | ||
1338 | static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { | |
1339 | .master = &omap2430_l4_wkup_hwmod, | |
1340 | .slave = &omap2430_gpio4_hwmod, | |
1341 | .clk = "gpios_ick", | |
1342 | .addr = omap2430_gpio4_addr_space, | |
aeac0e44 VC |
1343 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1344 | }; | |
1345 | ||
1346 | /* l4_core -> gpio5 */ | |
1347 | static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { | |
1348 | { | |
1349 | .pa_start = 0x480B6000, | |
1350 | .pa_end = 0x480B61ff, | |
1351 | .flags = ADDR_TYPE_RT | |
1352 | }, | |
78183f3f | 1353 | { } |
aeac0e44 VC |
1354 | }; |
1355 | ||
1356 | static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { | |
1357 | .master = &omap2430_l4_core_hwmod, | |
1358 | .slave = &omap2430_gpio5_hwmod, | |
1359 | .clk = "gpio5_ick", | |
1360 | .addr = omap2430_gpio5_addr_space, | |
aeac0e44 VC |
1361 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1362 | }; | |
1363 | ||
1364 | /* gpio dev_attr */ | |
1365 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1366 | .bank_width = 32, | |
1367 | .dbck_flag = false, | |
1368 | }; | |
1369 | ||
1370 | static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { | |
1371 | .rev_offs = 0x0000, | |
1372 | .sysc_offs = 0x0010, | |
1373 | .syss_offs = 0x0014, | |
1374 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
2d403fe0 PW |
1375 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
1376 | SYSS_HAS_RESET_STATUS), | |
aeac0e44 VC |
1377 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
1378 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1379 | }; | |
1380 | ||
1381 | /* | |
1382 | * 'gpio' class | |
1383 | * general purpose io module | |
1384 | */ | |
1385 | static struct omap_hwmod_class omap243x_gpio_hwmod_class = { | |
1386 | .name = "gpio", | |
1387 | .sysc = &omap243x_gpio_sysc, | |
1388 | .rev = 0, | |
1389 | }; | |
1390 | ||
1391 | /* gpio1 */ | |
aeac0e44 VC |
1392 | static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { |
1393 | &omap2430_l4_wkup__gpio1, | |
1394 | }; | |
1395 | ||
1396 | static struct omap_hwmod omap2430_gpio1_hwmod = { | |
1397 | .name = "gpio1", | |
f95440ca | 1398 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1399 | .mpu_irqs = omap2_gpio1_irqs, |
aeac0e44 VC |
1400 | .main_clk = "gpios_fck", |
1401 | .prcm = { | |
1402 | .omap2 = { | |
1403 | .prcm_reg_id = 1, | |
1404 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1405 | .module_offs = WKUP_MOD, | |
1406 | .idlest_reg_id = 1, | |
1407 | .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1408 | }, | |
1409 | }, | |
1410 | .slaves = omap2430_gpio1_slaves, | |
1411 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), | |
1412 | .class = &omap243x_gpio_hwmod_class, | |
1413 | .dev_attr = &gpio_dev_attr, | |
1414 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1415 | }; | |
1416 | ||
1417 | /* gpio2 */ | |
aeac0e44 VC |
1418 | static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { |
1419 | &omap2430_l4_wkup__gpio2, | |
1420 | }; | |
1421 | ||
1422 | static struct omap_hwmod omap2430_gpio2_hwmod = { | |
1423 | .name = "gpio2", | |
f95440ca | 1424 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1425 | .mpu_irqs = omap2_gpio2_irqs, |
aeac0e44 VC |
1426 | .main_clk = "gpios_fck", |
1427 | .prcm = { | |
1428 | .omap2 = { | |
1429 | .prcm_reg_id = 1, | |
1430 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1431 | .module_offs = WKUP_MOD, | |
1432 | .idlest_reg_id = 1, | |
1433 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1434 | }, | |
1435 | }, | |
1436 | .slaves = omap2430_gpio2_slaves, | |
1437 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), | |
1438 | .class = &omap243x_gpio_hwmod_class, | |
1439 | .dev_attr = &gpio_dev_attr, | |
1440 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1441 | }; | |
1442 | ||
1443 | /* gpio3 */ | |
aeac0e44 VC |
1444 | static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { |
1445 | &omap2430_l4_wkup__gpio3, | |
1446 | }; | |
1447 | ||
1448 | static struct omap_hwmod omap2430_gpio3_hwmod = { | |
1449 | .name = "gpio3", | |
f95440ca | 1450 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1451 | .mpu_irqs = omap2_gpio3_irqs, |
aeac0e44 VC |
1452 | .main_clk = "gpios_fck", |
1453 | .prcm = { | |
1454 | .omap2 = { | |
1455 | .prcm_reg_id = 1, | |
1456 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1457 | .module_offs = WKUP_MOD, | |
1458 | .idlest_reg_id = 1, | |
1459 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1460 | }, | |
1461 | }, | |
1462 | .slaves = omap2430_gpio3_slaves, | |
1463 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), | |
1464 | .class = &omap243x_gpio_hwmod_class, | |
1465 | .dev_attr = &gpio_dev_attr, | |
1466 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1467 | }; | |
1468 | ||
1469 | /* gpio4 */ | |
aeac0e44 VC |
1470 | static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { |
1471 | &omap2430_l4_wkup__gpio4, | |
1472 | }; | |
1473 | ||
1474 | static struct omap_hwmod omap2430_gpio4_hwmod = { | |
1475 | .name = "gpio4", | |
f95440ca | 1476 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
0d619a89 | 1477 | .mpu_irqs = omap2_gpio4_irqs, |
aeac0e44 VC |
1478 | .main_clk = "gpios_fck", |
1479 | .prcm = { | |
1480 | .omap2 = { | |
1481 | .prcm_reg_id = 1, | |
1482 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, | |
1483 | .module_offs = WKUP_MOD, | |
1484 | .idlest_reg_id = 1, | |
1485 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, | |
1486 | }, | |
1487 | }, | |
1488 | .slaves = omap2430_gpio4_slaves, | |
1489 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), | |
1490 | .class = &omap243x_gpio_hwmod_class, | |
1491 | .dev_attr = &gpio_dev_attr, | |
1492 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1493 | }; | |
1494 | ||
1495 | /* gpio5 */ | |
1496 | static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { | |
1497 | { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ | |
212738a4 | 1498 | { .irq = -1 } |
aeac0e44 VC |
1499 | }; |
1500 | ||
1501 | static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { | |
1502 | &omap2430_l4_core__gpio5, | |
1503 | }; | |
1504 | ||
1505 | static struct omap_hwmod omap2430_gpio5_hwmod = { | |
1506 | .name = "gpio5", | |
f95440ca | 1507 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
aeac0e44 | 1508 | .mpu_irqs = omap243x_gpio5_irqs, |
aeac0e44 VC |
1509 | .main_clk = "gpio5_fck", |
1510 | .prcm = { | |
1511 | .omap2 = { | |
1512 | .prcm_reg_id = 2, | |
1513 | .module_bit = OMAP2430_EN_GPIO5_SHIFT, | |
1514 | .module_offs = CORE_MOD, | |
1515 | .idlest_reg_id = 2, | |
1516 | .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, | |
1517 | }, | |
1518 | }, | |
1519 | .slaves = omap2430_gpio5_slaves, | |
1520 | .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), | |
1521 | .class = &omap243x_gpio_hwmod_class, | |
1522 | .dev_attr = &gpio_dev_attr, | |
1523 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1524 | }; | |
1525 | ||
82cbd1ae MK |
1526 | /* dma_system */ |
1527 | static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { | |
1528 | .rev_offs = 0x0000, | |
1529 | .sysc_offs = 0x002c, | |
1530 | .syss_offs = 0x0028, | |
1531 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | | |
1532 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | | |
2d403fe0 | 1533 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
82cbd1ae MK |
1534 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
1535 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1536 | }; | |
1537 | ||
1538 | static struct omap_hwmod_class omap2430_dma_hwmod_class = { | |
1539 | .name = "dma", | |
1540 | .sysc = &omap2430_dma_sysc, | |
1541 | }; | |
1542 | ||
1543 | /* dma attributes */ | |
1544 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1545 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1546 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1547 | .lch_count = 32, | |
1548 | }; | |
1549 | ||
82cbd1ae MK |
1550 | /* dma_system -> L3 */ |
1551 | static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { | |
1552 | .master = &omap2430_dma_system_hwmod, | |
1553 | .slave = &omap2430_l3_main_hwmod, | |
1554 | .clk = "core_l3_ck", | |
1555 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1556 | }; | |
1557 | ||
1558 | /* dma_system master ports */ | |
1559 | static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { | |
1560 | &omap2430_dma_system__l3, | |
1561 | }; | |
1562 | ||
1563 | /* l4_core -> dma_system */ | |
1564 | static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { | |
1565 | .master = &omap2430_l4_core_hwmod, | |
1566 | .slave = &omap2430_dma_system_hwmod, | |
1567 | .clk = "sdma_ick", | |
ded11383 | 1568 | .addr = omap2_dma_system_addrs, |
82cbd1ae MK |
1569 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1570 | }; | |
1571 | ||
1572 | /* dma_system slave ports */ | |
1573 | static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { | |
1574 | &omap2430_l4_core__dma_system, | |
1575 | }; | |
1576 | ||
1577 | static struct omap_hwmod omap2430_dma_system_hwmod = { | |
1578 | .name = "dma", | |
1579 | .class = &omap2430_dma_hwmod_class, | |
0d619a89 | 1580 | .mpu_irqs = omap2_dma_system_irqs, |
82cbd1ae MK |
1581 | .main_clk = "core_l3_ck", |
1582 | .slaves = omap2430_dma_system_slaves, | |
1583 | .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), | |
1584 | .masters = omap2430_dma_system_masters, | |
1585 | .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), | |
1586 | .dev_attr = &dma_dev_attr, | |
1587 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1588 | .flags = HWMOD_NO_IDLEST, | |
1589 | }; | |
1590 | ||
fca1ab55 ORL |
1591 | /* |
1592 | * 'mailbox' class | |
1593 | * mailbox module allowing communication between the on-chip processors | |
1594 | * using a queued mailbox-interrupt mechanism. | |
1595 | */ | |
1596 | ||
1597 | static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = { | |
1598 | .rev_offs = 0x000, | |
1599 | .sysc_offs = 0x010, | |
1600 | .syss_offs = 0x014, | |
1601 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1602 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1603 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1604 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1605 | }; | |
1606 | ||
1607 | static struct omap_hwmod_class omap2430_mailbox_hwmod_class = { | |
1608 | .name = "mailbox", | |
1609 | .sysc = &omap2430_mailbox_sysc, | |
1610 | }; | |
1611 | ||
1612 | /* mailbox */ | |
1613 | static struct omap_hwmod omap2430_mailbox_hwmod; | |
1614 | static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { | |
1615 | { .irq = 26 }, | |
212738a4 | 1616 | { .irq = -1 } |
fca1ab55 ORL |
1617 | }; |
1618 | ||
fca1ab55 ORL |
1619 | /* l4_core -> mailbox */ |
1620 | static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { | |
1621 | .master = &omap2430_l4_core_hwmod, | |
1622 | .slave = &omap2430_mailbox_hwmod, | |
ded11383 | 1623 | .addr = omap2_mailbox_addrs, |
fca1ab55 ORL |
1624 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1625 | }; | |
1626 | ||
1627 | /* mailbox slave ports */ | |
1628 | static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { | |
1629 | &omap2430_l4_core__mailbox, | |
1630 | }; | |
1631 | ||
1632 | static struct omap_hwmod omap2430_mailbox_hwmod = { | |
1633 | .name = "mailbox", | |
1634 | .class = &omap2430_mailbox_hwmod_class, | |
1635 | .mpu_irqs = omap2430_mailbox_irqs, | |
fca1ab55 ORL |
1636 | .main_clk = "mailboxes_ick", |
1637 | .prcm = { | |
1638 | .omap2 = { | |
1639 | .prcm_reg_id = 1, | |
1640 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | |
1641 | .module_offs = CORE_MOD, | |
1642 | .idlest_reg_id = 1, | |
1643 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, | |
1644 | }, | |
1645 | }, | |
1646 | .slaves = omap2430_mailbox_slaves, | |
1647 | .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), | |
1648 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1649 | }; | |
1650 | ||
7f904c78 C |
1651 | /* |
1652 | * 'mcspi' class | |
1653 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1654 | * bus | |
1655 | */ | |
1656 | ||
1657 | static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { | |
1658 | .rev_offs = 0x0000, | |
1659 | .sysc_offs = 0x0010, | |
1660 | .syss_offs = 0x0014, | |
1661 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1662 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1663 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1664 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1665 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1666 | }; | |
1667 | ||
1668 | static struct omap_hwmod_class omap2430_mcspi_class = { | |
1669 | .name = "mcspi", | |
1670 | .sysc = &omap2430_mcspi_sysc, | |
1671 | .rev = OMAP2_MCSPI_REV, | |
1672 | }; | |
1673 | ||
1674 | /* mcspi1 */ | |
7f904c78 C |
1675 | static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { |
1676 | &omap2430_l4_core__mcspi1, | |
1677 | }; | |
1678 | ||
1679 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1680 | .num_chipselect = 4, | |
1681 | }; | |
1682 | ||
1683 | static struct omap_hwmod omap2430_mcspi1_hwmod = { | |
1684 | .name = "mcspi1_hwmod", | |
0d619a89 | 1685 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
d826ebfa | 1686 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
7f904c78 C |
1687 | .main_clk = "mcspi1_fck", |
1688 | .prcm = { | |
1689 | .omap2 = { | |
1690 | .module_offs = CORE_MOD, | |
1691 | .prcm_reg_id = 1, | |
1692 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, | |
1693 | .idlest_reg_id = 1, | |
1694 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, | |
1695 | }, | |
1696 | }, | |
1697 | .slaves = omap2430_mcspi1_slaves, | |
1698 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), | |
1699 | .class = &omap2430_mcspi_class, | |
1700 | .dev_attr = &omap_mcspi1_dev_attr, | |
1701 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1702 | }; | |
1703 | ||
1704 | /* mcspi2 */ | |
7f904c78 C |
1705 | static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { |
1706 | &omap2430_l4_core__mcspi2, | |
1707 | }; | |
1708 | ||
1709 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1710 | .num_chipselect = 2, | |
1711 | }; | |
1712 | ||
1713 | static struct omap_hwmod omap2430_mcspi2_hwmod = { | |
1714 | .name = "mcspi2_hwmod", | |
0d619a89 | 1715 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
d826ebfa | 1716 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
7f904c78 C |
1717 | .main_clk = "mcspi2_fck", |
1718 | .prcm = { | |
1719 | .omap2 = { | |
1720 | .module_offs = CORE_MOD, | |
1721 | .prcm_reg_id = 1, | |
1722 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, | |
1723 | .idlest_reg_id = 1, | |
1724 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, | |
1725 | }, | |
1726 | }, | |
1727 | .slaves = omap2430_mcspi2_slaves, | |
1728 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), | |
1729 | .class = &omap2430_mcspi_class, | |
1730 | .dev_attr = &omap_mcspi2_dev_attr, | |
1731 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1732 | }; | |
1733 | ||
1734 | /* mcspi3 */ | |
1735 | static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { | |
1736 | { .irq = 91 }, | |
212738a4 | 1737 | { .irq = -1 } |
7f904c78 C |
1738 | }; |
1739 | ||
1740 | static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { | |
1741 | { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ | |
1742 | { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ | |
1743 | { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ | |
1744 | { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ | |
bc614958 | 1745 | { .dma_req = -1 } |
7f904c78 C |
1746 | }; |
1747 | ||
1748 | static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { | |
1749 | &omap2430_l4_core__mcspi3, | |
1750 | }; | |
1751 | ||
1752 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
1753 | .num_chipselect = 2, | |
1754 | }; | |
1755 | ||
1756 | static struct omap_hwmod omap2430_mcspi3_hwmod = { | |
1757 | .name = "mcspi3_hwmod", | |
1758 | .mpu_irqs = omap2430_mcspi3_mpu_irqs, | |
7f904c78 | 1759 | .sdma_reqs = omap2430_mcspi3_sdma_reqs, |
7f904c78 C |
1760 | .main_clk = "mcspi3_fck", |
1761 | .prcm = { | |
1762 | .omap2 = { | |
1763 | .module_offs = CORE_MOD, | |
1764 | .prcm_reg_id = 2, | |
1765 | .module_bit = OMAP2430_EN_MCSPI3_SHIFT, | |
1766 | .idlest_reg_id = 2, | |
1767 | .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, | |
1768 | }, | |
1769 | }, | |
1770 | .slaves = omap2430_mcspi3_slaves, | |
1771 | .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), | |
1772 | .class = &omap2430_mcspi_class, | |
1773 | .dev_attr = &omap_mcspi3_dev_attr, | |
1774 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1775 | }; | |
1776 | ||
44d02acf HH |
1777 | /* |
1778 | * usbhsotg | |
1779 | */ | |
1780 | static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { | |
1781 | .rev_offs = 0x0400, | |
1782 | .sysc_offs = 0x0404, | |
1783 | .syss_offs = 0x0408, | |
1784 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1785 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1786 | SYSC_HAS_AUTOIDLE), | |
1787 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1788 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1789 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1790 | }; | |
1791 | ||
1792 | static struct omap_hwmod_class usbotg_class = { | |
1793 | .name = "usbotg", | |
1794 | .sysc = &omap2430_usbhsotg_sysc, | |
1795 | }; | |
1796 | ||
1797 | /* usb_otg_hs */ | |
1798 | static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { | |
1799 | ||
1800 | { .name = "mc", .irq = 92 }, | |
1801 | { .name = "dma", .irq = 93 }, | |
212738a4 | 1802 | { .irq = -1 } |
44d02acf HH |
1803 | }; |
1804 | ||
1805 | static struct omap_hwmod omap2430_usbhsotg_hwmod = { | |
1806 | .name = "usb_otg_hs", | |
1807 | .mpu_irqs = omap2430_usbhsotg_mpu_irqs, | |
44d02acf HH |
1808 | .main_clk = "usbhs_ick", |
1809 | .prcm = { | |
1810 | .omap2 = { | |
1811 | .prcm_reg_id = 1, | |
1812 | .module_bit = OMAP2430_EN_USBHS_MASK, | |
1813 | .module_offs = CORE_MOD, | |
1814 | .idlest_reg_id = 1, | |
1815 | .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, | |
1816 | }, | |
1817 | }, | |
1818 | .masters = omap2430_usbhsotg_masters, | |
1819 | .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), | |
1820 | .slaves = omap2430_usbhsotg_slaves, | |
1821 | .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), | |
1822 | .class = &usbotg_class, | |
1823 | /* | |
1824 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1825 | * broken when autoidle is enabled | |
1826 | * workaround is to disable the autoidle bit at module level. | |
1827 | */ | |
1828 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1829 | | HWMOD_SWSUP_MSTANDBY, | |
1830 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) | |
1831 | }; | |
1832 | ||
37801b3d C |
1833 | /* |
1834 | * 'mcbsp' class | |
1835 | * multi channel buffered serial port controller | |
1836 | */ | |
1837 | ||
1838 | static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { | |
1839 | .rev_offs = 0x007C, | |
1840 | .sysc_offs = 0x008C, | |
1841 | .sysc_flags = (SYSC_HAS_SOFTRESET), | |
1842 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1843 | }; | |
1844 | ||
1845 | static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |
1846 | .name = "mcbsp", | |
1847 | .sysc = &omap2430_mcbsp_sysc, | |
1848 | .rev = MCBSP_CONFIG_TYPE2, | |
1849 | }; | |
04aa67de | 1850 | |
37801b3d C |
1851 | /* mcbsp1 */ |
1852 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | |
1853 | { .name = "tx", .irq = 59 }, | |
1854 | { .name = "rx", .irq = 60 }, | |
1855 | { .name = "ovr", .irq = 61 }, | |
1856 | { .name = "common", .irq = 64 }, | |
212738a4 | 1857 | { .irq = -1 } |
37801b3d C |
1858 | }; |
1859 | ||
37801b3d C |
1860 | /* l4_core -> mcbsp1 */ |
1861 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { | |
1862 | .master = &omap2430_l4_core_hwmod, | |
1863 | .slave = &omap2430_mcbsp1_hwmod, | |
1864 | .clk = "mcbsp1_ick", | |
ded11383 | 1865 | .addr = omap2_mcbsp1_addrs, |
37801b3d C |
1866 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1867 | }; | |
1868 | ||
1869 | /* mcbsp1 slave ports */ | |
1870 | static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { | |
1871 | &omap2430_l4_core__mcbsp1, | |
1872 | }; | |
1873 | ||
1874 | static struct omap_hwmod omap2430_mcbsp1_hwmod = { | |
1875 | .name = "mcbsp1", | |
1876 | .class = &omap2430_mcbsp_hwmod_class, | |
1877 | .mpu_irqs = omap2430_mcbsp1_irqs, | |
d826ebfa | 1878 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
37801b3d C |
1879 | .main_clk = "mcbsp1_fck", |
1880 | .prcm = { | |
1881 | .omap2 = { | |
1882 | .prcm_reg_id = 1, | |
1883 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, | |
1884 | .module_offs = CORE_MOD, | |
1885 | .idlest_reg_id = 1, | |
1886 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | |
1887 | }, | |
1888 | }, | |
1889 | .slaves = omap2430_mcbsp1_slaves, | |
1890 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), | |
1891 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1892 | }; | |
1893 | ||
1894 | /* mcbsp2 */ | |
1895 | static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { | |
1896 | { .name = "tx", .irq = 62 }, | |
1897 | { .name = "rx", .irq = 63 }, | |
1898 | { .name = "common", .irq = 16 }, | |
212738a4 | 1899 | { .irq = -1 } |
37801b3d C |
1900 | }; |
1901 | ||
37801b3d C |
1902 | /* l4_core -> mcbsp2 */ |
1903 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { | |
1904 | .master = &omap2430_l4_core_hwmod, | |
1905 | .slave = &omap2430_mcbsp2_hwmod, | |
1906 | .clk = "mcbsp2_ick", | |
ded11383 | 1907 | .addr = omap2xxx_mcbsp2_addrs, |
37801b3d C |
1908 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1909 | }; | |
1910 | ||
1911 | /* mcbsp2 slave ports */ | |
1912 | static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { | |
1913 | &omap2430_l4_core__mcbsp2, | |
1914 | }; | |
1915 | ||
1916 | static struct omap_hwmod omap2430_mcbsp2_hwmod = { | |
1917 | .name = "mcbsp2", | |
1918 | .class = &omap2430_mcbsp_hwmod_class, | |
1919 | .mpu_irqs = omap2430_mcbsp2_irqs, | |
d826ebfa | 1920 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
37801b3d C |
1921 | .main_clk = "mcbsp2_fck", |
1922 | .prcm = { | |
1923 | .omap2 = { | |
1924 | .prcm_reg_id = 1, | |
1925 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, | |
1926 | .module_offs = CORE_MOD, | |
1927 | .idlest_reg_id = 1, | |
1928 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | |
1929 | }, | |
1930 | }, | |
1931 | .slaves = omap2430_mcbsp2_slaves, | |
1932 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), | |
1933 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1934 | }; | |
1935 | ||
1936 | /* mcbsp3 */ | |
1937 | static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { | |
1938 | { .name = "tx", .irq = 89 }, | |
1939 | { .name = "rx", .irq = 90 }, | |
1940 | { .name = "common", .irq = 17 }, | |
212738a4 | 1941 | { .irq = -1 } |
37801b3d C |
1942 | }; |
1943 | ||
37801b3d C |
1944 | static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { |
1945 | { | |
1946 | .name = "mpu", | |
1947 | .pa_start = 0x4808C000, | |
1948 | .pa_end = 0x4808C0ff, | |
1949 | .flags = ADDR_TYPE_RT | |
1950 | }, | |
78183f3f | 1951 | { } |
37801b3d | 1952 | }; |
04aa67de | 1953 | |
37801b3d C |
1954 | /* l4_core -> mcbsp3 */ |
1955 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { | |
1956 | .master = &omap2430_l4_core_hwmod, | |
1957 | .slave = &omap2430_mcbsp3_hwmod, | |
1958 | .clk = "mcbsp3_ick", | |
1959 | .addr = omap2430_mcbsp3_addrs, | |
37801b3d C |
1960 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
1961 | }; | |
1962 | ||
1963 | /* mcbsp3 slave ports */ | |
1964 | static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { | |
1965 | &omap2430_l4_core__mcbsp3, | |
1966 | }; | |
1967 | ||
1968 | static struct omap_hwmod omap2430_mcbsp3_hwmod = { | |
1969 | .name = "mcbsp3", | |
1970 | .class = &omap2430_mcbsp_hwmod_class, | |
1971 | .mpu_irqs = omap2430_mcbsp3_irqs, | |
d826ebfa | 1972 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, |
37801b3d C |
1973 | .main_clk = "mcbsp3_fck", |
1974 | .prcm = { | |
1975 | .omap2 = { | |
1976 | .prcm_reg_id = 1, | |
1977 | .module_bit = OMAP2430_EN_MCBSP3_SHIFT, | |
1978 | .module_offs = CORE_MOD, | |
1979 | .idlest_reg_id = 2, | |
1980 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | |
1981 | }, | |
1982 | }, | |
1983 | .slaves = omap2430_mcbsp3_slaves, | |
1984 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), | |
1985 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
1986 | }; | |
1987 | ||
1988 | /* mcbsp4 */ | |
1989 | static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { | |
1990 | { .name = "tx", .irq = 54 }, | |
1991 | { .name = "rx", .irq = 55 }, | |
1992 | { .name = "common", .irq = 18 }, | |
212738a4 | 1993 | { .irq = -1 } |
37801b3d C |
1994 | }; |
1995 | ||
1996 | static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { | |
1997 | { .name = "rx", .dma_req = 20 }, | |
1998 | { .name = "tx", .dma_req = 19 }, | |
bc614958 | 1999 | { .dma_req = -1 } |
37801b3d C |
2000 | }; |
2001 | ||
2002 | static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { | |
2003 | { | |
2004 | .name = "mpu", | |
2005 | .pa_start = 0x4808E000, | |
2006 | .pa_end = 0x4808E0ff, | |
2007 | .flags = ADDR_TYPE_RT | |
2008 | }, | |
78183f3f | 2009 | { } |
37801b3d C |
2010 | }; |
2011 | ||
2012 | /* l4_core -> mcbsp4 */ | |
2013 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { | |
2014 | .master = &omap2430_l4_core_hwmod, | |
2015 | .slave = &omap2430_mcbsp4_hwmod, | |
2016 | .clk = "mcbsp4_ick", | |
2017 | .addr = omap2430_mcbsp4_addrs, | |
37801b3d C |
2018 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2019 | }; | |
2020 | ||
2021 | /* mcbsp4 slave ports */ | |
2022 | static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { | |
2023 | &omap2430_l4_core__mcbsp4, | |
2024 | }; | |
2025 | ||
2026 | static struct omap_hwmod omap2430_mcbsp4_hwmod = { | |
2027 | .name = "mcbsp4", | |
2028 | .class = &omap2430_mcbsp_hwmod_class, | |
2029 | .mpu_irqs = omap2430_mcbsp4_irqs, | |
37801b3d | 2030 | .sdma_reqs = omap2430_mcbsp4_sdma_chs, |
37801b3d C |
2031 | .main_clk = "mcbsp4_fck", |
2032 | .prcm = { | |
2033 | .omap2 = { | |
2034 | .prcm_reg_id = 1, | |
2035 | .module_bit = OMAP2430_EN_MCBSP4_SHIFT, | |
2036 | .module_offs = CORE_MOD, | |
2037 | .idlest_reg_id = 2, | |
2038 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | |
2039 | }, | |
2040 | }, | |
2041 | .slaves = omap2430_mcbsp4_slaves, | |
2042 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), | |
2043 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
2044 | }; | |
2045 | ||
2046 | /* mcbsp5 */ | |
2047 | static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { | |
2048 | { .name = "tx", .irq = 81 }, | |
2049 | { .name = "rx", .irq = 82 }, | |
2050 | { .name = "common", .irq = 19 }, | |
212738a4 | 2051 | { .irq = -1 } |
37801b3d C |
2052 | }; |
2053 | ||
2054 | static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { | |
2055 | { .name = "rx", .dma_req = 22 }, | |
2056 | { .name = "tx", .dma_req = 21 }, | |
bc614958 | 2057 | { .dma_req = -1 } |
37801b3d C |
2058 | }; |
2059 | ||
2060 | static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { | |
2061 | { | |
2062 | .name = "mpu", | |
2063 | .pa_start = 0x48096000, | |
2064 | .pa_end = 0x480960ff, | |
2065 | .flags = ADDR_TYPE_RT | |
2066 | }, | |
78183f3f | 2067 | { } |
37801b3d C |
2068 | }; |
2069 | ||
2070 | /* l4_core -> mcbsp5 */ | |
2071 | static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { | |
2072 | .master = &omap2430_l4_core_hwmod, | |
2073 | .slave = &omap2430_mcbsp5_hwmod, | |
2074 | .clk = "mcbsp5_ick", | |
2075 | .addr = omap2430_mcbsp5_addrs, | |
37801b3d C |
2076 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2077 | }; | |
2078 | ||
2079 | /* mcbsp5 slave ports */ | |
2080 | static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { | |
2081 | &omap2430_l4_core__mcbsp5, | |
2082 | }; | |
2083 | ||
2084 | static struct omap_hwmod omap2430_mcbsp5_hwmod = { | |
2085 | .name = "mcbsp5", | |
2086 | .class = &omap2430_mcbsp_hwmod_class, | |
2087 | .mpu_irqs = omap2430_mcbsp5_irqs, | |
37801b3d | 2088 | .sdma_reqs = omap2430_mcbsp5_sdma_chs, |
37801b3d C |
2089 | .main_clk = "mcbsp5_fck", |
2090 | .prcm = { | |
2091 | .omap2 = { | |
2092 | .prcm_reg_id = 1, | |
2093 | .module_bit = OMAP2430_EN_MCBSP5_SHIFT, | |
2094 | .module_offs = CORE_MOD, | |
2095 | .idlest_reg_id = 2, | |
2096 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | |
2097 | }, | |
2098 | }, | |
2099 | .slaves = omap2430_mcbsp5_slaves, | |
2100 | .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), | |
2101 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
2102 | }; | |
04aa67de | 2103 | |
bce06f37 | 2104 | /* MMC/SD/SDIO common */ |
04aa67de | 2105 | |
bce06f37 PW |
2106 | static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
2107 | .rev_offs = 0x1fc, | |
2108 | .sysc_offs = 0x10, | |
2109 | .syss_offs = 0x14, | |
2110 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2111 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2112 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
2113 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2114 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2115 | }; | |
2116 | ||
2117 | static struct omap_hwmod_class omap2430_mmc_class = { | |
2118 | .name = "mmc", | |
2119 | .sysc = &omap2430_mmc_sysc, | |
2120 | }; | |
2121 | ||
2122 | /* MMC/SD/SDIO1 */ | |
2123 | ||
2124 | static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { | |
2125 | { .irq = 83 }, | |
212738a4 | 2126 | { .irq = -1 } |
bce06f37 PW |
2127 | }; |
2128 | ||
2129 | static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { | |
2130 | { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ | |
2131 | { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ | |
bc614958 | 2132 | { .dma_req = -1 } |
bce06f37 PW |
2133 | }; |
2134 | ||
2135 | static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { | |
2136 | { .role = "dbck", .clk = "mmchsdb1_fck" }, | |
2137 | }; | |
2138 | ||
2139 | static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { | |
2140 | &omap2430_l4_core__mmc1, | |
2141 | }; | |
2142 | ||
6ab8946f KK |
2143 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
2144 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
2145 | }; | |
2146 | ||
bce06f37 PW |
2147 | static struct omap_hwmod omap2430_mmc1_hwmod = { |
2148 | .name = "mmc1", | |
2149 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
2150 | .mpu_irqs = omap2430_mmc1_mpu_irqs, | |
bce06f37 | 2151 | .sdma_reqs = omap2430_mmc1_sdma_reqs, |
bce06f37 PW |
2152 | .opt_clks = omap2430_mmc1_opt_clks, |
2153 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), | |
2154 | .main_clk = "mmchs1_fck", | |
2155 | .prcm = { | |
2156 | .omap2 = { | |
2157 | .module_offs = CORE_MOD, | |
2158 | .prcm_reg_id = 2, | |
2159 | .module_bit = OMAP2430_EN_MMCHS1_SHIFT, | |
2160 | .idlest_reg_id = 2, | |
2161 | .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, | |
2162 | }, | |
2163 | }, | |
6ab8946f | 2164 | .dev_attr = &mmc1_dev_attr, |
bce06f37 PW |
2165 | .slaves = omap2430_mmc1_slaves, |
2166 | .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), | |
2167 | .class = &omap2430_mmc_class, | |
2168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
2169 | }; | |
2170 | ||
2171 | /* MMC/SD/SDIO2 */ | |
2172 | ||
2173 | static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { | |
2174 | { .irq = 86 }, | |
212738a4 | 2175 | { .irq = -1 } |
bce06f37 PW |
2176 | }; |
2177 | ||
2178 | static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { | |
2179 | { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ | |
2180 | { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ | |
bc614958 | 2181 | { .dma_req = -1 } |
bce06f37 PW |
2182 | }; |
2183 | ||
2184 | static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { | |
2185 | { .role = "dbck", .clk = "mmchsdb2_fck" }, | |
2186 | }; | |
2187 | ||
2188 | static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { | |
2189 | &omap2430_l4_core__mmc2, | |
2190 | }; | |
04aa67de | 2191 | |
bce06f37 PW |
2192 | static struct omap_hwmod omap2430_mmc2_hwmod = { |
2193 | .name = "mmc2", | |
2194 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
2195 | .mpu_irqs = omap2430_mmc2_mpu_irqs, | |
bce06f37 | 2196 | .sdma_reqs = omap2430_mmc2_sdma_reqs, |
bce06f37 PW |
2197 | .opt_clks = omap2430_mmc2_opt_clks, |
2198 | .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), | |
2199 | .main_clk = "mmchs2_fck", | |
2200 | .prcm = { | |
2201 | .omap2 = { | |
2202 | .module_offs = CORE_MOD, | |
2203 | .prcm_reg_id = 2, | |
2204 | .module_bit = OMAP2430_EN_MMCHS2_SHIFT, | |
2205 | .idlest_reg_id = 2, | |
2206 | .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, | |
2207 | }, | |
2208 | }, | |
2209 | .slaves = omap2430_mmc2_slaves, | |
2210 | .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), | |
2211 | .class = &omap2430_mmc_class, | |
2212 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | |
2213 | }; | |
04aa67de | 2214 | |
02bfc030 | 2215 | static __initdata struct omap_hwmod *omap2430_hwmods[] = { |
4a7cf90a | 2216 | &omap2430_l3_main_hwmod, |
02bfc030 PW |
2217 | &omap2430_l4_core_hwmod, |
2218 | &omap2430_l4_wkup_hwmod, | |
2219 | &omap2430_mpu_hwmod, | |
08072acf | 2220 | &omap2430_iva_hwmod, |
b6b58229 TG |
2221 | |
2222 | &omap2430_timer1_hwmod, | |
2223 | &omap2430_timer2_hwmod, | |
2224 | &omap2430_timer3_hwmod, | |
2225 | &omap2430_timer4_hwmod, | |
2226 | &omap2430_timer5_hwmod, | |
2227 | &omap2430_timer6_hwmod, | |
2228 | &omap2430_timer7_hwmod, | |
2229 | &omap2430_timer8_hwmod, | |
2230 | &omap2430_timer9_hwmod, | |
2231 | &omap2430_timer10_hwmod, | |
2232 | &omap2430_timer11_hwmod, | |
2233 | &omap2430_timer12_hwmod, | |
2234 | ||
165e2161 | 2235 | &omap2430_wd_timer2_hwmod, |
046465b7 KH |
2236 | &omap2430_uart1_hwmod, |
2237 | &omap2430_uart2_hwmod, | |
2238 | &omap2430_uart3_hwmod, | |
de56dbb6 SG |
2239 | /* dss class */ |
2240 | &omap2430_dss_core_hwmod, | |
2241 | &omap2430_dss_dispc_hwmod, | |
2242 | &omap2430_dss_rfbi_hwmod, | |
2243 | &omap2430_dss_venc_hwmod, | |
2244 | /* i2c class */ | |
2004290f PW |
2245 | &omap2430_i2c1_hwmod, |
2246 | &omap2430_i2c2_hwmod, | |
bce06f37 PW |
2247 | &omap2430_mmc1_hwmod, |
2248 | &omap2430_mmc2_hwmod, | |
aeac0e44 VC |
2249 | |
2250 | /* gpio class */ | |
2251 | &omap2430_gpio1_hwmod, | |
2252 | &omap2430_gpio2_hwmod, | |
2253 | &omap2430_gpio3_hwmod, | |
2254 | &omap2430_gpio4_hwmod, | |
2255 | &omap2430_gpio5_hwmod, | |
82cbd1ae MK |
2256 | |
2257 | /* dma_system class*/ | |
2258 | &omap2430_dma_system_hwmod, | |
7f904c78 | 2259 | |
37801b3d C |
2260 | /* mcbsp class */ |
2261 | &omap2430_mcbsp1_hwmod, | |
2262 | &omap2430_mcbsp2_hwmod, | |
2263 | &omap2430_mcbsp3_hwmod, | |
2264 | &omap2430_mcbsp4_hwmod, | |
2265 | &omap2430_mcbsp5_hwmod, | |
2266 | ||
fca1ab55 ORL |
2267 | /* mailbox class */ |
2268 | &omap2430_mailbox_hwmod, | |
2269 | ||
7f904c78 C |
2270 | /* mcspi class */ |
2271 | &omap2430_mcspi1_hwmod, | |
2272 | &omap2430_mcspi2_hwmod, | |
2273 | &omap2430_mcspi3_hwmod, | |
04aa67de | 2274 | |
44d02acf HH |
2275 | /* usbotg class*/ |
2276 | &omap2430_usbhsotg_hwmod, | |
04aa67de | 2277 | |
02bfc030 PW |
2278 | NULL, |
2279 | }; | |
2280 | ||
7359154e PW |
2281 | int __init omap2430_hwmod_init(void) |
2282 | { | |
550c8092 | 2283 | return omap_hwmod_register(omap2430_hwmods); |
7359154e | 2284 | } |