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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
b86aeafc | 17 | #include <linux/power/smartreflex.h> |
4b25408f | 18 | #include <linux/platform_data/gpio-omap.h> |
b86aeafc | 19 | |
7359154e | 20 | #include <plat/omap_hwmod.h> |
7359154e | 21 | #include <plat/dma.h> |
046465b7 | 22 | #include <plat/serial.h> |
e04d9e1e | 23 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
24 | #include <plat/l4_3xxx.h> |
25 | #include <plat/i2c.h> | |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
5486474c | 30 | #include <plat/iommu.h> |
7359154e | 31 | |
7d7e1eba TL |
32 | #include <mach/am35xx.h> |
33 | ||
dbc04161 | 34 | #include "soc.h" |
43b40992 | 35 | #include "omap_hwmod_common_data.h" |
7359154e | 36 | #include "prm-regbits-34xx.h" |
6b667f88 | 37 | #include "cm-regbits-34xx.h" |
ff2516fb | 38 | #include "wd_timer.h" |
7359154e PW |
39 | |
40 | /* | |
41 | * OMAP3xxx hardware module integration data | |
42 | * | |
844a3b63 | 43 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
44 | * TI hardware database or other technical documentation. Data that |
45 | * is driver-specific or driver-kernel integration-specific belongs | |
46 | * elsewhere. | |
47 | */ | |
48 | ||
844a3b63 PW |
49 | /* |
50 | * IP blocks | |
51 | */ | |
7359154e | 52 | |
844a3b63 | 53 | /* L3 */ |
4bb194dc | 54 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
7d7e1eba TL |
55 | { .irq = 9 + OMAP_INTC_START, }, |
56 | { .irq = 10 + OMAP_INTC_START, }, | |
57 | { .irq = -1 }, | |
4bb194dc | 58 | }; |
59 | ||
4a7cf90a | 60 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 61 | .name = "l3_main", |
43b40992 | 62 | .class = &l3_hwmod_class, |
0d619a89 | 63 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 64 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
65 | }; |
66 | ||
844a3b63 PW |
67 | /* L4 CORE */ |
68 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
69 | .name = "l4_core", | |
70 | .class = &l4_hwmod_class, | |
71 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 72 | }; |
7359154e | 73 | |
844a3b63 PW |
74 | /* L4 PER */ |
75 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
76 | .name = "l4_per", | |
77 | .class = &l4_hwmod_class, | |
78 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 79 | }; |
844a3b63 PW |
80 | |
81 | /* L4 WKUP */ | |
82 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
83 | .name = "l4_wkup", | |
84 | .class = &l4_hwmod_class, | |
85 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
86 | }; |
87 | ||
844a3b63 PW |
88 | /* L4 SEC */ |
89 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
90 | .name = "l4_sec", | |
91 | .class = &l4_hwmod_class, | |
92 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
93 | }; |
94 | ||
844a3b63 PW |
95 | /* MPU */ |
96 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
97 | .name = "mpu", | |
98 | .class = &mpu_hwmod_class, | |
99 | .main_clk = "arm_fck", | |
b163605e PW |
100 | }; |
101 | ||
844a3b63 | 102 | /* IVA2 (IVA2) */ |
f42c5496 | 103 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
ed733619 TK |
104 | { .name = "logic", .rst_shift = 0, .st_shift = 8 }, |
105 | { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, | |
106 | { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, | |
f42c5496 PW |
107 | }; |
108 | ||
844a3b63 PW |
109 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
110 | .name = "iva", | |
111 | .class = &iva_hwmod_class, | |
f42c5496 PW |
112 | .clkdm_name = "iva2_clkdm", |
113 | .rst_lines = omap3xxx_iva_resets, | |
114 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
115 | .main_clk = "iva2_ck", | |
ed733619 TK |
116 | .prcm = { |
117 | .omap2 = { | |
118 | .module_offs = OMAP3430_IVA2_MOD, | |
119 | .prcm_reg_id = 1, | |
120 | .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
121 | .idlest_reg_id = 1, | |
122 | .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, | |
123 | } | |
124 | }, | |
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125 | }; |
126 | ||
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127 | /* timer class */ |
128 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
129 | .rev_offs = 0x0000, | |
130 | .sysc_offs = 0x0010, | |
131 | .syss_offs = 0x0014, | |
132 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
133 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
134 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
135 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
136 | .sysc_fields = &omap_hwmod_sysc_type1, | |
b163605e PW |
137 | }; |
138 | ||
844a3b63 PW |
139 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
140 | .name = "timer", | |
141 | .sysc = &omap3xxx_timer_1ms_sysc, | |
b163605e PW |
142 | }; |
143 | ||
844a3b63 PW |
144 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
145 | .rev_offs = 0x0000, | |
146 | .sysc_offs = 0x0010, | |
147 | .syss_offs = 0x0014, | |
148 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
149 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
150 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
151 | .sysc_fields = &omap_hwmod_sysc_type1, | |
b163605e PW |
152 | }; |
153 | ||
844a3b63 PW |
154 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
155 | .name = "timer", | |
156 | .sysc = &omap3xxx_timer_sysc, | |
046465b7 KH |
157 | }; |
158 | ||
844a3b63 PW |
159 | /* secure timers dev attribute */ |
160 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
139486fa | 161 | .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, |
046465b7 KH |
162 | }; |
163 | ||
844a3b63 PW |
164 | /* always-on timers dev attribute */ |
165 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
166 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
167 | }; |
168 | ||
844a3b63 PW |
169 | /* pwm timers dev attribute */ |
170 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
171 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
172 | }; |
173 | ||
844a3b63 PW |
174 | /* timer1 */ |
175 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
176 | .name = "timer1", | |
177 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
178 | .main_clk = "gpt1_fck", | |
179 | .prcm = { | |
180 | .omap2 = { | |
181 | .prcm_reg_id = 1, | |
182 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
183 | .module_offs = WKUP_MOD, | |
184 | .idlest_reg_id = 1, | |
185 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
186 | }, | |
046465b7 | 187 | }, |
844a3b63 PW |
188 | .dev_attr = &capability_alwon_dev_attr, |
189 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
190 | }; |
191 | ||
844a3b63 PW |
192 | /* timer2 */ |
193 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
194 | .name = "timer2", | |
195 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
196 | .main_clk = "gpt2_fck", | |
197 | .prcm = { | |
198 | .omap2 = { | |
199 | .prcm_reg_id = 1, | |
200 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
201 | .module_offs = OMAP3430_PER_MOD, | |
202 | .idlest_reg_id = 1, | |
203 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
204 | }, | |
205 | }, | |
844a3b63 | 206 | .class = &omap3xxx_timer_1ms_hwmod_class, |
046465b7 KH |
207 | }; |
208 | ||
844a3b63 PW |
209 | /* timer3 */ |
210 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
211 | .name = "timer3", | |
212 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
213 | .main_clk = "gpt3_fck", | |
214 | .prcm = { | |
215 | .omap2 = { | |
216 | .prcm_reg_id = 1, | |
217 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
218 | .module_offs = OMAP3430_PER_MOD, | |
219 | .idlest_reg_id = 1, | |
220 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
221 | }, | |
222 | }, | |
844a3b63 | 223 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
224 | }; |
225 | ||
844a3b63 PW |
226 | /* timer4 */ |
227 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
228 | .name = "timer4", | |
229 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
230 | .main_clk = "gpt4_fck", | |
231 | .prcm = { | |
232 | .omap2 = { | |
233 | .prcm_reg_id = 1, | |
234 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
235 | .module_offs = OMAP3430_PER_MOD, | |
236 | .idlest_reg_id = 1, | |
237 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
238 | }, | |
239 | }, | |
844a3b63 | 240 | .class = &omap3xxx_timer_hwmod_class, |
046465b7 KH |
241 | }; |
242 | ||
844a3b63 PW |
243 | /* timer5 */ |
244 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
245 | .name = "timer5", | |
246 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
247 | .main_clk = "gpt5_fck", | |
248 | .prcm = { | |
249 | .omap2 = { | |
250 | .prcm_reg_id = 1, | |
251 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
252 | .module_offs = OMAP3430_PER_MOD, | |
253 | .idlest_reg_id = 1, | |
254 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
255 | }, | |
4bf90f65 | 256 | }, |
844a3b63 | 257 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
258 | }; |
259 | ||
844a3b63 PW |
260 | /* timer6 */ |
261 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
262 | .name = "timer6", | |
263 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
264 | .main_clk = "gpt6_fck", | |
265 | .prcm = { | |
266 | .omap2 = { | |
267 | .prcm_reg_id = 1, | |
268 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
269 | .module_offs = OMAP3430_PER_MOD, | |
270 | .idlest_reg_id = 1, | |
271 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
272 | }, | |
273 | }, | |
844a3b63 | 274 | .class = &omap3xxx_timer_hwmod_class, |
4bf90f65 KM |
275 | }; |
276 | ||
844a3b63 PW |
277 | /* timer7 */ |
278 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
279 | .name = "timer7", | |
280 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
281 | .main_clk = "gpt7_fck", | |
282 | .prcm = { | |
4fe20e97 | 283 | .omap2 = { |
844a3b63 PW |
284 | .prcm_reg_id = 1, |
285 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
286 | .module_offs = OMAP3430_PER_MOD, | |
287 | .idlest_reg_id = 1, | |
288 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
289 | }, | |
4fe20e97 | 290 | }, |
844a3b63 | 291 | .class = &omap3xxx_timer_hwmod_class, |
4fe20e97 RN |
292 | }; |
293 | ||
844a3b63 PW |
294 | /* timer8 */ |
295 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
296 | .name = "timer8", | |
297 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
298 | .main_clk = "gpt8_fck", | |
299 | .prcm = { | |
4fe20e97 | 300 | .omap2 = { |
844a3b63 PW |
301 | .prcm_reg_id = 1, |
302 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
303 | .module_offs = OMAP3430_PER_MOD, | |
304 | .idlest_reg_id = 1, | |
305 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
306 | }, | |
4fe20e97 | 307 | }, |
844a3b63 PW |
308 | .dev_attr = &capability_pwm_dev_attr, |
309 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
310 | }; |
311 | ||
844a3b63 PW |
312 | /* timer9 */ |
313 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
314 | .name = "timer9", | |
315 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
316 | .main_clk = "gpt9_fck", | |
317 | .prcm = { | |
318 | .omap2 = { | |
319 | .prcm_reg_id = 1, | |
320 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
321 | .module_offs = OMAP3430_PER_MOD, | |
322 | .idlest_reg_id = 1, | |
323 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
324 | }, | |
4fe20e97 | 325 | }, |
844a3b63 PW |
326 | .dev_attr = &capability_pwm_dev_attr, |
327 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
328 | }; |
329 | ||
844a3b63 PW |
330 | /* timer10 */ |
331 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
332 | .name = "timer10", | |
333 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
334 | .main_clk = "gpt10_fck", | |
335 | .prcm = { | |
4fe20e97 | 336 | .omap2 = { |
844a3b63 PW |
337 | .prcm_reg_id = 1, |
338 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
339 | .module_offs = CORE_MOD, | |
340 | .idlest_reg_id = 1, | |
341 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
342 | }, | |
4fe20e97 | 343 | }, |
844a3b63 PW |
344 | .dev_attr = &capability_pwm_dev_attr, |
345 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
346 | }; |
347 | ||
844a3b63 PW |
348 | /* timer11 */ |
349 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
350 | .name = "timer11", | |
351 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
352 | .main_clk = "gpt11_fck", | |
353 | .prcm = { | |
354 | .omap2 = { | |
355 | .prcm_reg_id = 1, | |
356 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
357 | .module_offs = CORE_MOD, | |
358 | .idlest_reg_id = 1, | |
359 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
360 | }, | |
361 | }, | |
362 | .dev_attr = &capability_pwm_dev_attr, | |
363 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
364 | }; |
365 | ||
844a3b63 PW |
366 | /* timer12 */ |
367 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
7d7e1eba TL |
368 | { .irq = 95 + OMAP_INTC_START, }, |
369 | { .irq = -1 }, | |
d62bc78a NM |
370 | }; |
371 | ||
844a3b63 PW |
372 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
373 | .name = "timer12", | |
374 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
375 | .main_clk = "gpt12_fck", | |
376 | .prcm = { | |
377 | .omap2 = { | |
378 | .prcm_reg_id = 1, | |
379 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
380 | .module_offs = WKUP_MOD, | |
381 | .idlest_reg_id = 1, | |
382 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
383 | }, | |
d3442726 | 384 | }, |
844a3b63 PW |
385 | .dev_attr = &capability_secure_dev_attr, |
386 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
387 | }; |
388 | ||
844a3b63 PW |
389 | /* |
390 | * 'wd_timer' class | |
391 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
392 | * overflow condition | |
393 | */ | |
394 | ||
395 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
396 | .rev_offs = 0x0000, | |
397 | .sysc_offs = 0x0010, | |
398 | .syss_offs = 0x0014, | |
399 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
400 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
401 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
402 | SYSS_HAS_RESET_STATUS), | |
403 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
404 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
405 | }; |
406 | ||
844a3b63 PW |
407 | /* I2C common */ |
408 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
409 | .rev_offs = 0x00, | |
410 | .sysc_offs = 0x20, | |
411 | .syss_offs = 0x10, | |
412 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
413 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
414 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
415 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
416 | .clockact = CLOCKACT_TEST_ICLK, | |
417 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
418 | }; |
419 | ||
844a3b63 PW |
420 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
421 | .name = "wd_timer", | |
422 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
423 | .pre_shutdown = &omap2_wd_timer_disable, |
424 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
425 | }; |
426 | ||
844a3b63 PW |
427 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
428 | .name = "wd_timer2", | |
429 | .class = &omap3xxx_wd_timer_hwmod_class, | |
430 | .main_clk = "wdt2_fck", | |
431 | .prcm = { | |
432 | .omap2 = { | |
433 | .prcm_reg_id = 1, | |
434 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
435 | .module_offs = WKUP_MOD, | |
436 | .idlest_reg_id = 1, | |
437 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
438 | }, | |
439 | }, | |
440 | /* | |
441 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
442 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
443 | */ | |
444 | .flags = HWMOD_SWSUP_SIDLE, | |
445 | }; | |
870ea2b8 | 446 | |
844a3b63 PW |
447 | /* UART1 */ |
448 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
449 | .name = "uart1", | |
450 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
451 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
452 | .main_clk = "uart1_fck", | |
453 | .prcm = { | |
454 | .omap2 = { | |
455 | .module_offs = CORE_MOD, | |
456 | .prcm_reg_id = 1, | |
457 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
458 | .idlest_reg_id = 1, | |
459 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
460 | }, | |
870ea2b8 | 461 | }, |
844a3b63 | 462 | .class = &omap2_uart_class, |
870ea2b8 HH |
463 | }; |
464 | ||
844a3b63 PW |
465 | /* UART2 */ |
466 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
467 | .name = "uart2", | |
468 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
469 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
470 | .main_clk = "uart2_fck", | |
471 | .prcm = { | |
472 | .omap2 = { | |
473 | .module_offs = CORE_MOD, | |
474 | .prcm_reg_id = 1, | |
475 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
476 | .idlest_reg_id = 1, | |
477 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
478 | }, | |
479 | }, | |
480 | .class = &omap2_uart_class, | |
870ea2b8 HH |
481 | }; |
482 | ||
844a3b63 PW |
483 | /* UART3 */ |
484 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
485 | .name = "uart3", | |
486 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
487 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
488 | .main_clk = "uart3_fck", | |
489 | .prcm = { | |
490 | .omap2 = { | |
491 | .module_offs = OMAP3430_PER_MOD, | |
492 | .prcm_reg_id = 1, | |
493 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
494 | .idlest_reg_id = 1, | |
495 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
496 | }, | |
273ff8c3 | 497 | }, |
844a3b63 | 498 | .class = &omap2_uart_class, |
273ff8c3 HH |
499 | }; |
500 | ||
844a3b63 PW |
501 | /* UART4 */ |
502 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
7d7e1eba TL |
503 | { .irq = 80 + OMAP_INTC_START, }, |
504 | { .irq = -1 }, | |
273ff8c3 HH |
505 | }; |
506 | ||
844a3b63 PW |
507 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
508 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
509 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
510 | { .dma_req = -1 } | |
7359154e PW |
511 | }; |
512 | ||
844a3b63 PW |
513 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
514 | .name = "uart4", | |
515 | .mpu_irqs = uart4_mpu_irqs, | |
516 | .sdma_reqs = uart4_sdma_reqs, | |
517 | .main_clk = "uart4_fck", | |
518 | .prcm = { | |
519 | .omap2 = { | |
520 | .module_offs = OMAP3430_PER_MOD, | |
521 | .prcm_reg_id = 1, | |
522 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
523 | .idlest_reg_id = 1, | |
524 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
525 | }, | |
526 | }, | |
527 | .class = &omap2_uart_class, | |
7359154e PW |
528 | }; |
529 | ||
844a3b63 | 530 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
7d7e1eba TL |
531 | { .irq = 84 + OMAP_INTC_START, }, |
532 | { .irq = -1 }, | |
43085705 PW |
533 | }; |
534 | ||
844a3b63 PW |
535 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
536 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
537 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
bf765237 | 538 | { .dma_req = -1 } |
7359154e PW |
539 | }; |
540 | ||
82ee620d PW |
541 | /* |
542 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | |
543 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | |
544 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | |
545 | * should not be needed. The functional clock structure of the AM35xx | |
546 | * UART4 is extremely unclear and opaque; it is unclear what the role | |
547 | * of uart1/2_fck is for the UART4. Any clarification from either | |
548 | * empirical testing or the AM3505/3517 hardware designers would be | |
549 | * most welcome. | |
550 | */ | |
551 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | |
552 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | |
553 | }; | |
554 | ||
844a3b63 PW |
555 | static struct omap_hwmod am35xx_uart4_hwmod = { |
556 | .name = "uart4", | |
557 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
558 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
559 | .main_clk = "uart4_fck", | |
560 | .prcm = { | |
561 | .omap2 = { | |
562 | .module_offs = CORE_MOD, | |
563 | .prcm_reg_id = 1, | |
bf765237 | 564 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 565 | .idlest_reg_id = 1, |
bf765237 | 566 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
567 | }, |
568 | }, | |
82ee620d PW |
569 | .opt_clks = am35xx_uart4_opt_clks, |
570 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | |
571 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
844a3b63 PW |
572 | .class = &omap2_uart_class, |
573 | }; | |
574 | ||
575 | static struct omap_hwmod_class i2c_class = { | |
576 | .name = "i2c", | |
577 | .sysc = &i2c_sysc, | |
578 | .rev = OMAP_I2C_IP_VERSION_1, | |
579 | .reset = &omap_i2c_reset, | |
580 | }; | |
581 | ||
582 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
583 | { .name = "dispc", .dma_req = 5 }, | |
584 | { .name = "dsi1", .dma_req = 74 }, | |
585 | { .dma_req = -1 } | |
43085705 PW |
586 | }; |
587 | ||
844a3b63 PW |
588 | /* dss */ |
589 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
590 | /* | |
591 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
592 | * driver does not use these clocks. | |
593 | */ | |
594 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
595 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
596 | /* required only on OMAP3430 */ | |
597 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
598 | }; |
599 | ||
844a3b63 PW |
600 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
601 | .name = "dss_core", | |
602 | .class = &omap2_dss_hwmod_class, | |
603 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
604 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
605 | .prcm = { | |
606 | .omap2 = { | |
607 | .prcm_reg_id = 1, | |
608 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
609 | .module_offs = OMAP3430_DSS_MOD, | |
610 | .idlest_reg_id = 1, | |
611 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
612 | }, | |
613 | }, | |
614 | .opt_clks = dss_opt_clks, | |
615 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
616 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
617 | }; | |
540064bf | 618 | |
844a3b63 PW |
619 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
620 | .name = "dss_core", | |
621 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
622 | .class = &omap2_dss_hwmod_class, | |
623 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
624 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
625 | .prcm = { | |
626 | .omap2 = { | |
627 | .prcm_reg_id = 1, | |
628 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
629 | .module_offs = OMAP3430_DSS_MOD, | |
630 | .idlest_reg_id = 1, | |
631 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
632 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
633 | }, | |
634 | }, | |
635 | .opt_clks = dss_opt_clks, | |
636 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
637 | }; |
638 | ||
540064bf | 639 | /* |
844a3b63 PW |
640 | * 'dispc' class |
641 | * display controller | |
540064bf KH |
642 | */ |
643 | ||
844a3b63 | 644 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
645 | .rev_offs = 0x0000, |
646 | .sysc_offs = 0x0010, | |
647 | .syss_offs = 0x0014, | |
844a3b63 PW |
648 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
649 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
650 | SYSC_HAS_ENAWAKEUP), | |
651 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
652 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 653 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
654 | }; |
655 | ||
844a3b63 PW |
656 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
657 | .name = "dispc", | |
658 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
659 | }; |
660 | ||
844a3b63 PW |
661 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
662 | .name = "dss_dispc", | |
663 | .class = &omap3_dispc_hwmod_class, | |
664 | .mpu_irqs = omap2_dispc_irqs, | |
665 | .main_clk = "dss1_alwon_fck", | |
666 | .prcm = { | |
667 | .omap2 = { | |
668 | .prcm_reg_id = 1, | |
669 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
670 | .module_offs = OMAP3430_DSS_MOD, | |
671 | }, | |
672 | }, | |
673 | .flags = HWMOD_NO_IDLEST, | |
674 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
675 | }; |
676 | ||
844a3b63 PW |
677 | /* |
678 | * 'dsi' class | |
679 | * display serial interface controller | |
680 | */ | |
4fe20e97 | 681 | |
844a3b63 PW |
682 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
683 | .name = "dsi", | |
c345c8b0 TKD |
684 | }; |
685 | ||
844a3b63 | 686 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
7d7e1eba TL |
687 | { .irq = 25 + OMAP_INTC_START, }, |
688 | { .irq = -1 }, | |
c345c8b0 TKD |
689 | }; |
690 | ||
844a3b63 PW |
691 | /* dss_dsi1 */ |
692 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
693 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
694 | }; |
695 | ||
844a3b63 PW |
696 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
697 | .name = "dss_dsi1", | |
698 | .class = &omap3xxx_dsi_hwmod_class, | |
699 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
700 | .main_clk = "dss1_alwon_fck", | |
701 | .prcm = { | |
702 | .omap2 = { | |
703 | .prcm_reg_id = 1, | |
704 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
705 | .module_offs = OMAP3430_DSS_MOD, | |
706 | }, | |
ce722d26 | 707 | }, |
844a3b63 PW |
708 | .opt_clks = dss_dsi1_opt_clks, |
709 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
710 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
711 | }; |
712 | ||
844a3b63 PW |
713 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
714 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
715 | }; |
716 | ||
844a3b63 PW |
717 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
718 | .name = "dss_rfbi", | |
719 | .class = &omap2_rfbi_hwmod_class, | |
720 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
721 | .prcm = { |
722 | .omap2 = { | |
723 | .prcm_reg_id = 1, | |
844a3b63 PW |
724 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
725 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
726 | }, |
727 | }, | |
844a3b63 PW |
728 | .opt_clks = dss_rfbi_opt_clks, |
729 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
730 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
731 | }; |
732 | ||
844a3b63 PW |
733 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
734 | /* required only on OMAP3430 */ | |
735 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
736 | }; |
737 | ||
844a3b63 PW |
738 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
739 | .name = "dss_venc", | |
740 | .class = &omap2_venc_hwmod_class, | |
741 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
742 | .prcm = { |
743 | .omap2 = { | |
046465b7 | 744 | .prcm_reg_id = 1, |
844a3b63 PW |
745 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
746 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
747 | }, |
748 | }, | |
844a3b63 PW |
749 | .opt_clks = dss_venc_opt_clks, |
750 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
751 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
752 | }; |
753 | ||
844a3b63 PW |
754 | /* I2C1 */ |
755 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
756 | .fifo_depth = 8, /* bytes */ | |
757 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
758 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
759 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
760 | }; |
761 | ||
844a3b63 PW |
762 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
763 | .name = "i2c1", | |
764 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
765 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
766 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
767 | .main_clk = "i2c1_fck", | |
046465b7 KH |
768 | .prcm = { |
769 | .omap2 = { | |
844a3b63 | 770 | .module_offs = CORE_MOD, |
046465b7 | 771 | .prcm_reg_id = 1, |
844a3b63 | 772 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 773 | .idlest_reg_id = 1, |
844a3b63 | 774 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
775 | }, |
776 | }, | |
844a3b63 PW |
777 | .class = &i2c_class, |
778 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
779 | }; |
780 | ||
844a3b63 PW |
781 | /* I2C2 */ |
782 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
783 | .fifo_depth = 8, /* bytes */ | |
784 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
785 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
786 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
787 | }; |
788 | ||
844a3b63 PW |
789 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
790 | .name = "i2c2", | |
791 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
792 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
793 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
794 | .main_clk = "i2c2_fck", | |
046465b7 KH |
795 | .prcm = { |
796 | .omap2 = { | |
844a3b63 | 797 | .module_offs = CORE_MOD, |
046465b7 | 798 | .prcm_reg_id = 1, |
844a3b63 | 799 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 800 | .idlest_reg_id = 1, |
844a3b63 | 801 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
802 | }, |
803 | }, | |
844a3b63 PW |
804 | .class = &i2c_class, |
805 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
806 | }; |
807 | ||
844a3b63 PW |
808 | /* I2C3 */ |
809 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
810 | .fifo_depth = 64, /* bytes */ | |
811 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
812 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
813 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
814 | }; | |
046465b7 | 815 | |
844a3b63 | 816 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
7d7e1eba TL |
817 | { .irq = 61 + OMAP_INTC_START, }, |
818 | { .irq = -1 }, | |
046465b7 KH |
819 | }; |
820 | ||
844a3b63 PW |
821 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
822 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
823 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
824 | { .dma_req = -1 } | |
046465b7 KH |
825 | }; |
826 | ||
844a3b63 PW |
827 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
828 | .name = "i2c3", | |
829 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
830 | .mpu_irqs = i2c3_mpu_irqs, | |
831 | .sdma_reqs = i2c3_sdma_reqs, | |
832 | .main_clk = "i2c3_fck", | |
046465b7 KH |
833 | .prcm = { |
834 | .omap2 = { | |
844a3b63 | 835 | .module_offs = CORE_MOD, |
046465b7 | 836 | .prcm_reg_id = 1, |
844a3b63 | 837 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 838 | .idlest_reg_id = 1, |
844a3b63 | 839 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
840 | }, |
841 | }, | |
844a3b63 PW |
842 | .class = &i2c_class, |
843 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
844 | }; |
845 | ||
844a3b63 PW |
846 | /* |
847 | * 'gpio' class | |
848 | * general purpose io module | |
849 | */ | |
4fe20e97 | 850 | |
844a3b63 PW |
851 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
852 | .rev_offs = 0x0000, | |
853 | .sysc_offs = 0x0010, | |
854 | .syss_offs = 0x0014, | |
855 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
856 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
857 | SYSS_HAS_RESET_STATUS), | |
858 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
859 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
860 | }; |
861 | ||
844a3b63 PW |
862 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
863 | .name = "gpio", | |
864 | .sysc = &omap3xxx_gpio_sysc, | |
865 | .rev = 1, | |
4fe20e97 RN |
866 | }; |
867 | ||
844a3b63 PW |
868 | /* gpio_dev_attr */ |
869 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
870 | .bank_width = 32, | |
871 | .dbck_flag = true, | |
872 | }; | |
873 | ||
874 | /* gpio1 */ | |
875 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
876 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
877 | }; | |
878 | ||
879 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
880 | .name = "gpio1", | |
881 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
882 | .mpu_irqs = omap2_gpio1_irqs, | |
883 | .main_clk = "gpio1_ick", | |
884 | .opt_clks = gpio1_opt_clks, | |
885 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
886 | .prcm = { |
887 | .omap2 = { | |
4fe20e97 | 888 | .prcm_reg_id = 1, |
844a3b63 PW |
889 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
890 | .module_offs = WKUP_MOD, | |
4fe20e97 | 891 | .idlest_reg_id = 1, |
844a3b63 | 892 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
893 | }, |
894 | }, | |
844a3b63 PW |
895 | .class = &omap3xxx_gpio_hwmod_class, |
896 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
897 | }; |
898 | ||
844a3b63 PW |
899 | /* gpio2 */ |
900 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
901 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
902 | }; |
903 | ||
844a3b63 PW |
904 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
905 | .name = "gpio2", | |
906 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
907 | .mpu_irqs = omap2_gpio2_irqs, | |
908 | .main_clk = "gpio2_ick", | |
909 | .opt_clks = gpio2_opt_clks, | |
910 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
911 | .prcm = { |
912 | .omap2 = { | |
4fe20e97 | 913 | .prcm_reg_id = 1, |
844a3b63 | 914 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 915 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 916 | .idlest_reg_id = 1, |
844a3b63 | 917 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
918 | }, |
919 | }, | |
844a3b63 PW |
920 | .class = &omap3xxx_gpio_hwmod_class, |
921 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
922 | }; |
923 | ||
844a3b63 PW |
924 | /* gpio3 */ |
925 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
926 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
927 | }; |
928 | ||
844a3b63 PW |
929 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
930 | .name = "gpio3", | |
931 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
932 | .mpu_irqs = omap2_gpio3_irqs, | |
933 | .main_clk = "gpio3_ick", | |
934 | .opt_clks = gpio3_opt_clks, | |
935 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
936 | .prcm = { |
937 | .omap2 = { | |
4fe20e97 | 938 | .prcm_reg_id = 1, |
844a3b63 | 939 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 940 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 941 | .idlest_reg_id = 1, |
844a3b63 | 942 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
943 | }, |
944 | }, | |
844a3b63 PW |
945 | .class = &omap3xxx_gpio_hwmod_class, |
946 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
947 | }; |
948 | ||
844a3b63 PW |
949 | /* gpio4 */ |
950 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
951 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
952 | }; |
953 | ||
844a3b63 PW |
954 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
955 | .name = "gpio4", | |
956 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
957 | .mpu_irqs = omap2_gpio4_irqs, | |
958 | .main_clk = "gpio4_ick", | |
959 | .opt_clks = gpio4_opt_clks, | |
960 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
961 | .prcm = { |
962 | .omap2 = { | |
963 | .prcm_reg_id = 1, | |
844a3b63 | 964 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
965 | .module_offs = OMAP3430_PER_MOD, |
966 | .idlest_reg_id = 1, | |
844a3b63 | 967 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 968 | }, |
70034d38 | 969 | }, |
844a3b63 PW |
970 | .class = &omap3xxx_gpio_hwmod_class, |
971 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
972 | }; |
973 | ||
844a3b63 PW |
974 | /* gpio5 */ |
975 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
7d7e1eba TL |
976 | { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ |
977 | { .irq = -1 }, | |
844a3b63 | 978 | }; |
70034d38 | 979 | |
844a3b63 PW |
980 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
981 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
982 | }; |
983 | ||
844a3b63 PW |
984 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
985 | .name = "gpio5", | |
986 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
987 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
988 | .main_clk = "gpio5_ick", | |
989 | .opt_clks = gpio5_opt_clks, | |
990 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
991 | .prcm = { |
992 | .omap2 = { | |
993 | .prcm_reg_id = 1, | |
844a3b63 PW |
994 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
995 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 996 | .idlest_reg_id = 1, |
844a3b63 | 997 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 998 | }, |
70034d38 | 999 | }, |
844a3b63 PW |
1000 | .class = &omap3xxx_gpio_hwmod_class, |
1001 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
1002 | }; |
1003 | ||
844a3b63 PW |
1004 | /* gpio6 */ |
1005 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
7d7e1eba TL |
1006 | { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ |
1007 | { .irq = -1 }, | |
844a3b63 | 1008 | }; |
70034d38 | 1009 | |
844a3b63 PW |
1010 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
1011 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
1012 | }; |
1013 | ||
844a3b63 PW |
1014 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
1015 | .name = "gpio6", | |
1016 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
1017 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1018 | .main_clk = "gpio6_ick", | |
1019 | .opt_clks = gpio6_opt_clks, | |
1020 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1021 | .prcm = { |
1022 | .omap2 = { | |
1023 | .prcm_reg_id = 1, | |
844a3b63 PW |
1024 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1025 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1026 | .idlest_reg_id = 1, |
844a3b63 | 1027 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1028 | }, |
1029 | }, | |
844a3b63 PW |
1030 | .class = &omap3xxx_gpio_hwmod_class, |
1031 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1032 | }; |
1033 | ||
844a3b63 PW |
1034 | /* dma attributes */ |
1035 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1036 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1037 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1038 | .lch_count = 32, | |
ce722d26 TG |
1039 | }; |
1040 | ||
844a3b63 PW |
1041 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1042 | .rev_offs = 0x0000, | |
1043 | .sysc_offs = 0x002c, | |
1044 | .syss_offs = 0x0028, | |
1045 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1046 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1047 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1048 | SYSS_HAS_RESET_STATUS), | |
1049 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1050 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1051 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1052 | }; |
1053 | ||
844a3b63 PW |
1054 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1055 | .name = "dma", | |
1056 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1057 | }; |
1058 | ||
844a3b63 PW |
1059 | /* dma_system */ |
1060 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1061 | .name = "dma", | |
1062 | .class = &omap3xxx_dma_hwmod_class, | |
1063 | .mpu_irqs = omap2_dma_system_irqs, | |
1064 | .main_clk = "core_l3_ick", | |
1065 | .prcm = { | |
ce722d26 | 1066 | .omap2 = { |
844a3b63 PW |
1067 | .module_offs = CORE_MOD, |
1068 | .prcm_reg_id = 1, | |
1069 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1070 | .idlest_reg_id = 1, | |
1071 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1072 | }, |
1073 | }, | |
844a3b63 PW |
1074 | .dev_attr = &dma_dev_attr, |
1075 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1076 | }; |
1077 | ||
844a3b63 PW |
1078 | /* |
1079 | * 'mcbsp' class | |
1080 | * multi channel buffered serial port controller | |
1081 | */ | |
1082 | ||
1083 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1084 | .sysc_offs = 0x008c, | |
1085 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1086 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1087 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1088 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1089 | .clockact = 0x2, | |
70034d38 VC |
1090 | }; |
1091 | ||
844a3b63 PW |
1092 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1093 | .name = "mcbsp", | |
1094 | .sysc = &omap3xxx_mcbsp_sysc, | |
1095 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1096 | }; |
1097 | ||
7039154b PU |
1098 | /* McBSP functional clock mapping */ |
1099 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | |
1100 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1101 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | |
1102 | }; | |
1103 | ||
1104 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | |
1105 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | |
1106 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | |
1107 | }; | |
1108 | ||
844a3b63 PW |
1109 | /* mcbsp1 */ |
1110 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
7d7e1eba TL |
1111 | { .name = "common", .irq = 16 + OMAP_INTC_START, }, |
1112 | { .name = "tx", .irq = 59 + OMAP_INTC_START, }, | |
1113 | { .name = "rx", .irq = 60 + OMAP_INTC_START, }, | |
1114 | { .irq = -1 }, | |
844a3b63 | 1115 | }; |
6b667f88 | 1116 | |
844a3b63 PW |
1117 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1118 | .name = "mcbsp1", | |
1119 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1120 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1121 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1122 | .main_clk = "mcbsp1_fck", | |
1123 | .prcm = { | |
1124 | .omap2 = { | |
1125 | .prcm_reg_id = 1, | |
1126 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1127 | .module_offs = CORE_MOD, | |
1128 | .idlest_reg_id = 1, | |
1129 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1130 | }, | |
1131 | }, | |
7039154b PU |
1132 | .opt_clks = mcbsp15_opt_clks, |
1133 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1134 | }; |
1135 | ||
844a3b63 PW |
1136 | /* mcbsp2 */ |
1137 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
7d7e1eba TL |
1138 | { .name = "common", .irq = 17 + OMAP_INTC_START, }, |
1139 | { .name = "tx", .irq = 62 + OMAP_INTC_START, }, | |
1140 | { .name = "rx", .irq = 63 + OMAP_INTC_START, }, | |
1141 | { .irq = -1 }, | |
70034d38 VC |
1142 | }; |
1143 | ||
844a3b63 PW |
1144 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1145 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1146 | }; |
1147 | ||
844a3b63 PW |
1148 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1149 | .name = "mcbsp2", | |
1150 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1151 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1152 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1153 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1154 | .prcm = { |
1155 | .omap2 = { | |
1156 | .prcm_reg_id = 1, | |
844a3b63 PW |
1157 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1158 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1159 | .idlest_reg_id = 1, |
844a3b63 | 1160 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1161 | }, |
1162 | }, | |
7039154b PU |
1163 | .opt_clks = mcbsp234_opt_clks, |
1164 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1165 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1166 | }; |
1167 | ||
844a3b63 PW |
1168 | /* mcbsp3 */ |
1169 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
7d7e1eba TL |
1170 | { .name = "common", .irq = 22 + OMAP_INTC_START, }, |
1171 | { .name = "tx", .irq = 89 + OMAP_INTC_START, }, | |
1172 | { .name = "rx", .irq = 90 + OMAP_INTC_START, }, | |
1173 | { .irq = -1 }, | |
844a3b63 PW |
1174 | }; |
1175 | ||
1176 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1177 | .sidetone = "mcbsp3_sidetone", | |
1178 | }; | |
1179 | ||
1180 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1181 | .name = "mcbsp3", | |
1182 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1183 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1184 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1185 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1186 | .prcm = { |
1187 | .omap2 = { | |
1188 | .prcm_reg_id = 1, | |
844a3b63 PW |
1189 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1190 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1191 | .idlest_reg_id = 1, |
844a3b63 | 1192 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1193 | }, |
1194 | }, | |
7039154b PU |
1195 | .opt_clks = mcbsp234_opt_clks, |
1196 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
844a3b63 | 1197 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1198 | }; |
1199 | ||
844a3b63 PW |
1200 | /* mcbsp4 */ |
1201 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
7d7e1eba TL |
1202 | { .name = "common", .irq = 23 + OMAP_INTC_START, }, |
1203 | { .name = "tx", .irq = 54 + OMAP_INTC_START, }, | |
1204 | { .name = "rx", .irq = 55 + OMAP_INTC_START, }, | |
1205 | { .irq = -1 }, | |
844a3b63 PW |
1206 | }; |
1207 | ||
1208 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1209 | { .name = "rx", .dma_req = 20 }, | |
1210 | { .name = "tx", .dma_req = 19 }, | |
1211 | { .dma_req = -1 } | |
1212 | }; | |
1213 | ||
1214 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1215 | .name = "mcbsp4", | |
1216 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1217 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1218 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1219 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1220 | .prcm = { |
1221 | .omap2 = { | |
1222 | .prcm_reg_id = 1, | |
844a3b63 PW |
1223 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1224 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1225 | .idlest_reg_id = 1, |
844a3b63 | 1226 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1227 | }, |
1228 | }, | |
7039154b PU |
1229 | .opt_clks = mcbsp234_opt_clks, |
1230 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | |
046465b7 KH |
1231 | }; |
1232 | ||
844a3b63 PW |
1233 | /* mcbsp5 */ |
1234 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
7d7e1eba TL |
1235 | { .name = "common", .irq = 27 + OMAP_INTC_START, }, |
1236 | { .name = "tx", .irq = 81 + OMAP_INTC_START, }, | |
1237 | { .name = "rx", .irq = 82 + OMAP_INTC_START, }, | |
1238 | { .irq = -1 }, | |
844a3b63 PW |
1239 | }; |
1240 | ||
1241 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1242 | { .name = "rx", .dma_req = 22 }, | |
1243 | { .name = "tx", .dma_req = 21 }, | |
1244 | { .dma_req = -1 } | |
1245 | }; | |
1246 | ||
1247 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1248 | .name = "mcbsp5", | |
1249 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1250 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1251 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1252 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1253 | .prcm = { |
1254 | .omap2 = { | |
046465b7 | 1255 | .prcm_reg_id = 1, |
844a3b63 PW |
1256 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1257 | .module_offs = CORE_MOD, | |
70034d38 | 1258 | .idlest_reg_id = 1, |
844a3b63 | 1259 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1260 | }, |
1261 | }, | |
7039154b PU |
1262 | .opt_clks = mcbsp15_opt_clks, |
1263 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | |
70034d38 VC |
1264 | }; |
1265 | ||
844a3b63 PW |
1266 | /* 'mcbsp sidetone' class */ |
1267 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1268 | .sysc_offs = 0x0010, | |
1269 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1270 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1271 | }; | |
046465b7 | 1272 | |
844a3b63 PW |
1273 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1274 | .name = "mcbsp_sidetone", | |
1275 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1276 | }; |
1277 | ||
844a3b63 PW |
1278 | /* mcbsp2_sidetone */ |
1279 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
7d7e1eba TL |
1280 | { .name = "irq", .irq = 4 + OMAP_INTC_START, }, |
1281 | { .irq = -1 }, | |
70034d38 VC |
1282 | }; |
1283 | ||
844a3b63 PW |
1284 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1285 | .name = "mcbsp2_sidetone", | |
1286 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1287 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1288 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1289 | .prcm = { |
1290 | .omap2 = { | |
046465b7 | 1291 | .prcm_reg_id = 1, |
844a3b63 PW |
1292 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1293 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1294 | .idlest_reg_id = 1, |
844a3b63 | 1295 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1296 | }, |
1297 | }, | |
4bf90f65 KM |
1298 | }; |
1299 | ||
844a3b63 PW |
1300 | /* mcbsp3_sidetone */ |
1301 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
7d7e1eba TL |
1302 | { .name = "irq", .irq = 5 + OMAP_INTC_START, }, |
1303 | { .irq = -1 }, | |
4bf90f65 KM |
1304 | }; |
1305 | ||
844a3b63 PW |
1306 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1307 | .name = "mcbsp3_sidetone", | |
1308 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1309 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1310 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1311 | .prcm = { |
4bf90f65 | 1312 | .omap2 = { |
4bf90f65 | 1313 | .prcm_reg_id = 1, |
844a3b63 PW |
1314 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1315 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1316 | .idlest_reg_id = 1, |
844a3b63 | 1317 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1318 | }, |
1319 | }, | |
4bf90f65 KM |
1320 | }; |
1321 | ||
844a3b63 PW |
1322 | /* SR common */ |
1323 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1324 | .clkact_shift = 20, | |
1325 | }; | |
4bf90f65 | 1326 | |
844a3b63 PW |
1327 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1328 | .sysc_offs = 0x24, | |
1329 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1330 | .clockact = CLOCKACT_TEST_ICLK, | |
1331 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1332 | }; |
1333 | ||
844a3b63 PW |
1334 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1335 | .name = "smartreflex", | |
1336 | .sysc = &omap34xx_sr_sysc, | |
1337 | .rev = 1, | |
e04d9e1e SG |
1338 | }; |
1339 | ||
844a3b63 PW |
1340 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1341 | .sidle_shift = 24, | |
1342 | .enwkup_shift = 26, | |
1343 | }; | |
e04d9e1e | 1344 | |
844a3b63 PW |
1345 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1346 | .sysc_offs = 0x38, | |
1347 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1348 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1349 | SYSC_NO_CACHE), | |
1350 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1351 | }; | |
1352 | ||
1353 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1354 | .name = "smartreflex", | |
1355 | .sysc = &omap36xx_sr_sysc, | |
1356 | .rev = 2, | |
1357 | }; | |
1358 | ||
1359 | /* SR1 */ | |
1360 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1361 | .sensor_voltdm_name = "mpu_iva", | |
1362 | }; | |
1363 | ||
1364 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
7d7e1eba TL |
1365 | { .irq = 18 + OMAP_INTC_START, }, |
1366 | { .irq = -1 }, | |
844a3b63 PW |
1367 | }; |
1368 | ||
1369 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1fcd3069 | 1370 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1371 | .class = &omap34xx_smartreflex_hwmod_class, |
1372 | .main_clk = "sr1_fck", | |
1373 | .prcm = { | |
e04d9e1e | 1374 | .omap2 = { |
844a3b63 PW |
1375 | .prcm_reg_id = 1, |
1376 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1377 | .module_offs = WKUP_MOD, | |
1378 | .idlest_reg_id = 1, | |
1379 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1380 | }, | |
e04d9e1e | 1381 | }, |
844a3b63 PW |
1382 | .dev_attr = &sr1_dev_attr, |
1383 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1384 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1385 | }; |
1386 | ||
844a3b63 | 1387 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1fcd3069 | 1388 | .name = "smartreflex_mpu_iva", |
844a3b63 PW |
1389 | .class = &omap36xx_smartreflex_hwmod_class, |
1390 | .main_clk = "sr1_fck", | |
1391 | .prcm = { | |
e04d9e1e | 1392 | .omap2 = { |
844a3b63 PW |
1393 | .prcm_reg_id = 1, |
1394 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1395 | .module_offs = WKUP_MOD, | |
1396 | .idlest_reg_id = 1, | |
1397 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1398 | }, | |
e04d9e1e | 1399 | }, |
844a3b63 PW |
1400 | .dev_attr = &sr1_dev_attr, |
1401 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1402 | }; |
1403 | ||
844a3b63 PW |
1404 | /* SR2 */ |
1405 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1406 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1407 | }; |
1408 | ||
844a3b63 | 1409 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
7d7e1eba TL |
1410 | { .irq = 19 + OMAP_INTC_START, }, |
1411 | { .irq = -1 }, | |
844a3b63 PW |
1412 | }; |
1413 | ||
1414 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1fcd3069 | 1415 | .name = "smartreflex_core", |
844a3b63 PW |
1416 | .class = &omap34xx_smartreflex_hwmod_class, |
1417 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1418 | .prcm = { |
1419 | .omap2 = { | |
1420 | .prcm_reg_id = 1, | |
844a3b63 PW |
1421 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1422 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1423 | .idlest_reg_id = 1, |
844a3b63 | 1424 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1425 | }, |
1426 | }, | |
844a3b63 PW |
1427 | .dev_attr = &sr2_dev_attr, |
1428 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1429 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1430 | }; |
1431 | ||
844a3b63 | 1432 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1fcd3069 | 1433 | .name = "smartreflex_core", |
844a3b63 PW |
1434 | .class = &omap36xx_smartreflex_hwmod_class, |
1435 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1436 | .prcm = { |
1437 | .omap2 = { | |
1438 | .prcm_reg_id = 1, | |
844a3b63 PW |
1439 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1440 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1441 | .idlest_reg_id = 1, |
844a3b63 | 1442 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1443 | }, |
1444 | }, | |
844a3b63 PW |
1445 | .dev_attr = &sr2_dev_attr, |
1446 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1447 | }; |
1448 | ||
1ac6d46e | 1449 | /* |
844a3b63 PW |
1450 | * 'mailbox' class |
1451 | * mailbox module allowing communication between the on-chip processors | |
1452 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1453 | */ |
1454 | ||
844a3b63 PW |
1455 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1456 | .rev_offs = 0x000, | |
1457 | .sysc_offs = 0x010, | |
1458 | .syss_offs = 0x014, | |
1459 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1460 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1461 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1462 | .sysc_fields = &omap_hwmod_sysc_type1, |
1463 | }; | |
1464 | ||
844a3b63 PW |
1465 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1466 | .name = "mailbox", | |
1467 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1468 | }; |
1469 | ||
844a3b63 | 1470 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
7d7e1eba TL |
1471 | { .irq = 26 + OMAP_INTC_START, }, |
1472 | { .irq = -1 }, | |
e04d9e1e SG |
1473 | }; |
1474 | ||
844a3b63 PW |
1475 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1476 | .name = "mailbox", | |
1477 | .class = &omap3xxx_mailbox_hwmod_class, | |
1478 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1479 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1480 | .prcm = { |
1481 | .omap2 = { | |
1482 | .prcm_reg_id = 1, | |
844a3b63 PW |
1483 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1484 | .module_offs = CORE_MOD, | |
1485 | .idlest_reg_id = 1, | |
1486 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1487 | }, |
1488 | }, | |
e04d9e1e SG |
1489 | }; |
1490 | ||
1491 | /* | |
844a3b63 PW |
1492 | * 'mcspi' class |
1493 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1494 | * bus | |
e04d9e1e SG |
1495 | */ |
1496 | ||
844a3b63 PW |
1497 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1498 | .rev_offs = 0x0000, | |
1499 | .sysc_offs = 0x0010, | |
1500 | .syss_offs = 0x0014, | |
1501 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1502 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1503 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1504 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1505 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1506 | }; |
1507 | ||
844a3b63 PW |
1508 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1509 | .name = "mcspi", | |
1510 | .sysc = &omap34xx_mcspi_sysc, | |
1511 | .rev = OMAP3_MCSPI_REV, | |
affe360d AT |
1512 | }; |
1513 | ||
844a3b63 PW |
1514 | /* mcspi1 */ |
1515 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1516 | .num_chipselect = 4, | |
e04d9e1e SG |
1517 | }; |
1518 | ||
844a3b63 PW |
1519 | static struct omap_hwmod omap34xx_mcspi1 = { |
1520 | .name = "mcspi1", | |
1521 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1522 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1523 | .main_clk = "mcspi1_fck", | |
1524 | .prcm = { | |
e04d9e1e | 1525 | .omap2 = { |
844a3b63 PW |
1526 | .module_offs = CORE_MOD, |
1527 | .prcm_reg_id = 1, | |
1528 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1529 | .idlest_reg_id = 1, | |
1530 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1531 | }, | |
e04d9e1e | 1532 | }, |
844a3b63 PW |
1533 | .class = &omap34xx_mcspi_class, |
1534 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1535 | }; |
1536 | ||
844a3b63 PW |
1537 | /* mcspi2 */ |
1538 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1539 | .num_chipselect = 2, | |
6c3d7e34 TV |
1540 | }; |
1541 | ||
844a3b63 PW |
1542 | static struct omap_hwmod omap34xx_mcspi2 = { |
1543 | .name = "mcspi2", | |
1544 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1545 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1546 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1547 | .prcm = { |
1548 | .omap2 = { | |
844a3b63 | 1549 | .module_offs = CORE_MOD, |
e04d9e1e | 1550 | .prcm_reg_id = 1, |
844a3b63 PW |
1551 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1552 | .idlest_reg_id = 1, | |
1553 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1554 | }, |
1555 | }, | |
844a3b63 PW |
1556 | .class = &omap34xx_mcspi_class, |
1557 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1558 | }; |
1559 | ||
844a3b63 PW |
1560 | /* mcspi3 */ |
1561 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
7d7e1eba TL |
1562 | { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ |
1563 | { .irq = -1 }, | |
844a3b63 PW |
1564 | }; |
1565 | ||
1566 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1567 | { .name = "tx0", .dma_req = 15 }, | |
1568 | { .name = "rx0", .dma_req = 16 }, | |
1569 | { .name = "tx1", .dma_req = 23 }, | |
1570 | { .name = "rx1", .dma_req = 24 }, | |
1571 | { .dma_req = -1 } | |
e04d9e1e SG |
1572 | }; |
1573 | ||
844a3b63 PW |
1574 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1575 | .num_chipselect = 2, | |
6c3d7e34 TV |
1576 | }; |
1577 | ||
844a3b63 PW |
1578 | static struct omap_hwmod omap34xx_mcspi3 = { |
1579 | .name = "mcspi3", | |
1580 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1581 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1582 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1583 | .prcm = { |
1584 | .omap2 = { | |
844a3b63 | 1585 | .module_offs = CORE_MOD, |
e04d9e1e | 1586 | .prcm_reg_id = 1, |
844a3b63 PW |
1587 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1588 | .idlest_reg_id = 1, | |
1589 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1590 | }, |
1591 | }, | |
844a3b63 PW |
1592 | .class = &omap34xx_mcspi_class, |
1593 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1594 | }; |
1595 | ||
844a3b63 PW |
1596 | /* mcspi4 */ |
1597 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
7d7e1eba TL |
1598 | { .name = "irq", .irq = 48 + OMAP_INTC_START, }, |
1599 | { .irq = -1 }, | |
e04d9e1e SG |
1600 | }; |
1601 | ||
844a3b63 PW |
1602 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1603 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1604 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1605 | { .dma_req = -1 } | |
6c3d7e34 TV |
1606 | }; |
1607 | ||
844a3b63 PW |
1608 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1609 | .num_chipselect = 1, | |
1610 | }; | |
1611 | ||
1612 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1613 | .name = "mcspi4", | |
1614 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1615 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1616 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1617 | .prcm = { |
1618 | .omap2 = { | |
844a3b63 | 1619 | .module_offs = CORE_MOD, |
e04d9e1e | 1620 | .prcm_reg_id = 1, |
844a3b63 PW |
1621 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1622 | .idlest_reg_id = 1, | |
1623 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1624 | }, |
1625 | }, | |
844a3b63 PW |
1626 | .class = &omap34xx_mcspi_class, |
1627 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1628 | }; |
1629 | ||
844a3b63 PW |
1630 | /* usbhsotg */ |
1631 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1632 | .rev_offs = 0x0400, | |
1633 | .sysc_offs = 0x0404, | |
1634 | .syss_offs = 0x0408, | |
1635 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1636 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1637 | SYSC_HAS_AUTOIDLE), | |
1638 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1639 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1640 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1641 | }; | |
4fe20e97 | 1642 | |
844a3b63 PW |
1643 | static struct omap_hwmod_class usbotg_class = { |
1644 | .name = "usbotg", | |
1645 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1646 | }; |
1647 | ||
844a3b63 PW |
1648 | /* usb_otg_hs */ |
1649 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1650 | ||
7d7e1eba TL |
1651 | { .name = "mc", .irq = 92 + OMAP_INTC_START, }, |
1652 | { .name = "dma", .irq = 93 + OMAP_INTC_START, }, | |
1653 | { .irq = -1 }, | |
844a3b63 PW |
1654 | }; |
1655 | ||
1656 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1657 | .name = "usb_otg_hs", | |
1658 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1659 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1660 | .prcm = { |
1661 | .omap2 = { | |
4fe20e97 | 1662 | .prcm_reg_id = 1, |
844a3b63 PW |
1663 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1664 | .module_offs = CORE_MOD, | |
4fe20e97 | 1665 | .idlest_reg_id = 1, |
844a3b63 PW |
1666 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1667 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1668 | }, |
1669 | }, | |
844a3b63 PW |
1670 | .class = &usbotg_class, |
1671 | ||
1672 | /* | |
1673 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1674 | * broken when autoidle is enabled | |
1675 | * workaround is to disable the autoidle bit at module level. | |
1676 | */ | |
1677 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1678 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1679 | }; |
1680 | ||
844a3b63 PW |
1681 | /* usb_otg_hs */ |
1682 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
7d7e1eba TL |
1683 | { .name = "mc", .irq = 71 + OMAP_INTC_START, }, |
1684 | { .irq = -1 }, | |
4fe20e97 RN |
1685 | }; |
1686 | ||
844a3b63 PW |
1687 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1688 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1689 | }; |
1690 | ||
1691 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1692 | .name = "am35x_otg_hs", | |
1693 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1694 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1695 | .class = &am35xx_usbotg_class, |
89ea2583 | 1696 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1697 | }; |
1698 | ||
844a3b63 PW |
1699 | /* MMC/SD/SDIO common */ |
1700 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1701 | .rev_offs = 0x1fc, | |
1702 | .sysc_offs = 0x10, | |
1703 | .syss_offs = 0x14, | |
1704 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1705 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1706 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1707 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1708 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1709 | }; | |
4fe20e97 | 1710 | |
844a3b63 PW |
1711 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1712 | .name = "mmc", | |
1713 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1714 | }; |
1715 | ||
844a3b63 PW |
1716 | /* MMC/SD/SDIO1 */ |
1717 | ||
1718 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
7d7e1eba TL |
1719 | { .irq = 83 + OMAP_INTC_START, }, |
1720 | { .irq = -1 }, | |
4fe20e97 RN |
1721 | }; |
1722 | ||
844a3b63 PW |
1723 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1724 | { .name = "tx", .dma_req = 61, }, | |
1725 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1726 | { .dma_req = -1 } |
4fe20e97 RN |
1727 | }; |
1728 | ||
844a3b63 PW |
1729 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1730 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1731 | }; | |
1732 | ||
1733 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1734 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1735 | }; | |
1736 | ||
1737 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1738 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1739 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1740 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1741 | }; | |
1742 | ||
1743 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1744 | .name = "mmc1", | |
1745 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1746 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1747 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1748 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1749 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1750 | .prcm = { |
1751 | .omap2 = { | |
1752 | .module_offs = CORE_MOD, | |
1753 | .prcm_reg_id = 1, | |
844a3b63 | 1754 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1755 | .idlest_reg_id = 1, |
844a3b63 | 1756 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1757 | }, |
1758 | }, | |
844a3b63 PW |
1759 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1760 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1761 | }; |
1762 | ||
844a3b63 PW |
1763 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1764 | .name = "mmc1", | |
1765 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1766 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1767 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1768 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1769 | .main_clk = "mmchs1_fck", | |
1770 | .prcm = { | |
1771 | .omap2 = { | |
1772 | .module_offs = CORE_MOD, | |
1773 | .prcm_reg_id = 1, | |
1774 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1775 | .idlest_reg_id = 1, | |
1776 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1777 | }, | |
70034d38 | 1778 | }, |
844a3b63 PW |
1779 | .dev_attr = &mmc1_dev_attr, |
1780 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1781 | }; |
1782 | ||
844a3b63 | 1783 | /* MMC/SD/SDIO2 */ |
70034d38 | 1784 | |
844a3b63 | 1785 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
7d7e1eba TL |
1786 | { .irq = 86 + OMAP_INTC_START, }, |
1787 | { .irq = -1 }, | |
70034d38 VC |
1788 | }; |
1789 | ||
844a3b63 PW |
1790 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1791 | { .name = "tx", .dma_req = 47, }, | |
1792 | { .name = "rx", .dma_req = 48, }, | |
1793 | { .dma_req = -1 } | |
70034d38 VC |
1794 | }; |
1795 | ||
844a3b63 PW |
1796 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1797 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1798 | }; |
1799 | ||
844a3b63 PW |
1800 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1801 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1802 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1803 | }; |
1804 | ||
844a3b63 PW |
1805 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1806 | .name = "mmc2", | |
1807 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1808 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1809 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1810 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1811 | .main_clk = "mmchs2_fck", | |
1812 | .prcm = { | |
1813 | .omap2 = { | |
1814 | .module_offs = CORE_MOD, | |
1815 | .prcm_reg_id = 1, | |
1816 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1817 | .idlest_reg_id = 1, | |
1818 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1819 | }, | |
70034d38 | 1820 | }, |
844a3b63 PW |
1821 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1822 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1823 | }; |
1824 | ||
844a3b63 PW |
1825 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1826 | .name = "mmc2", | |
1827 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1828 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1829 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1830 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1831 | .main_clk = "mmchs2_fck", | |
1832 | .prcm = { | |
1833 | .omap2 = { | |
1834 | .module_offs = CORE_MOD, | |
1835 | .prcm_reg_id = 1, | |
1836 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1837 | .idlest_reg_id = 1, | |
1838 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1839 | }, | |
1840 | }, | |
1841 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1842 | }; |
1843 | ||
844a3b63 PW |
1844 | /* MMC/SD/SDIO3 */ |
1845 | ||
1846 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
7d7e1eba TL |
1847 | { .irq = 94 + OMAP_INTC_START, }, |
1848 | { .irq = -1 }, | |
70034d38 VC |
1849 | }; |
1850 | ||
844a3b63 PW |
1851 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1852 | { .name = "tx", .dma_req = 77, }, | |
1853 | { .name = "rx", .dma_req = 78, }, | |
1854 | { .dma_req = -1 } | |
70034d38 VC |
1855 | }; |
1856 | ||
844a3b63 PW |
1857 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1858 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1859 | }; |
1860 | ||
844a3b63 PW |
1861 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1862 | .name = "mmc3", | |
1863 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1864 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1865 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1866 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1867 | .main_clk = "mmchs3_fck", | |
1868 | .prcm = { | |
1869 | .omap2 = { | |
1870 | .prcm_reg_id = 1, | |
1871 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1872 | .idlest_reg_id = 1, | |
1873 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1874 | }, | |
1875 | }, | |
1876 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1877 | }; |
1878 | ||
1879 | /* | |
844a3b63 PW |
1880 | * 'usb_host_hs' class |
1881 | * high-speed multi-port usb host controller | |
70034d38 VC |
1882 | */ |
1883 | ||
844a3b63 | 1884 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1885 | .rev_offs = 0x0000, |
1886 | .sysc_offs = 0x0010, | |
1887 | .syss_offs = 0x0014, | |
844a3b63 PW |
1888 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1889 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1890 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1891 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1892 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1893 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1894 | }; |
1895 | ||
844a3b63 PW |
1896 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1897 | .name = "usb_host_hs", | |
1898 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1899 | }; |
1900 | ||
844a3b63 PW |
1901 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1902 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1903 | }; |
1904 | ||
844a3b63 | 1905 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
7d7e1eba TL |
1906 | { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, |
1907 | { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, | |
1908 | { .irq = -1 }, | |
70034d38 VC |
1909 | }; |
1910 | ||
844a3b63 PW |
1911 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1912 | .name = "usb_host_hs", | |
1913 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1914 | .clkdm_name = "l3_init_clkdm", | |
1915 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1916 | .main_clk = "usbhost_48m_fck", | |
1917 | .prcm = { | |
70034d38 | 1918 | .omap2 = { |
844a3b63 | 1919 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1920 | .prcm_reg_id = 1, |
844a3b63 | 1921 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1922 | .idlest_reg_id = 1, |
844a3b63 PW |
1923 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1924 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1925 | }, |
1926 | }, | |
844a3b63 PW |
1927 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1928 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1929 | |
844a3b63 PW |
1930 | /* |
1931 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1932 | * id: i660 | |
1933 | * | |
1934 | * Description: | |
1935 | * In the following configuration : | |
1936 | * - USBHOST module is set to smart-idle mode | |
1937 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1938 | * happens when the system is going to a low power mode : all ports | |
1939 | * have been suspended, the master part of the USBHOST module has | |
1940 | * entered the standby state, and SW has cut the functional clocks) | |
1941 | * - an USBHOST interrupt occurs before the module is able to answer | |
1942 | * idle_ack, typically a remote wakeup IRQ. | |
1943 | * Then the USB HOST module will enter a deadlock situation where it | |
1944 | * is no more accessible nor functional. | |
1945 | * | |
1946 | * Workaround: | |
1947 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1948 | */ | |
1949 | ||
1950 | /* | |
1951 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1952 | * Id: i571 | |
1953 | * | |
1954 | * Description: | |
1955 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1956 | * ready to enter the standby state (i.e. all ports are suspended and | |
1957 | * all attached devices are in suspend mode), then it can wrongly assert | |
1958 | * the Mstandby signal too early while there are still some residual OCP | |
1959 | * transactions ongoing. If this condition occurs, the internal state | |
1960 | * machine may go to an undefined state and the USB link may be stuck | |
1961 | * upon the next resume. | |
1962 | * | |
1963 | * Workaround: | |
1964 | * Don't use smart standby; use only force standby, | |
1965 | * hence HWMOD_SWSUP_MSTANDBY | |
1966 | */ | |
1967 | ||
1968 | /* | |
1969 | * During system boot; If the hwmod framework resets the module | |
1970 | * the module will have smart idle settings; which can lead to deadlock | |
1971 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1972 | * Use HWMOD_INIT_NO_RESET. | |
1973 | */ | |
70034d38 | 1974 | |
844a3b63 PW |
1975 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1976 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1977 | }; |
1978 | ||
844a3b63 PW |
1979 | /* |
1980 | * 'usb_tll_hs' class | |
1981 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1982 | */ | |
1983 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1984 | .rev_offs = 0x0000, | |
1985 | .sysc_offs = 0x0010, | |
1986 | .syss_offs = 0x0014, | |
1987 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1988 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1989 | SYSC_HAS_AUTOIDLE), | |
1990 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1991 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1992 | }; |
1993 | ||
844a3b63 PW |
1994 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1995 | .name = "usb_tll_hs", | |
1996 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1997 | }; |
1998 | ||
844a3b63 | 1999 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
7d7e1eba TL |
2000 | { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, |
2001 | { .irq = -1 }, | |
70034d38 VC |
2002 | }; |
2003 | ||
844a3b63 PW |
2004 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
2005 | .name = "usb_tll_hs", | |
2006 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
2007 | .clkdm_name = "l3_init_clkdm", | |
2008 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
2009 | .main_clk = "usbtll_fck", | |
2010 | .prcm = { | |
70034d38 | 2011 | .omap2 = { |
844a3b63 PW |
2012 | .module_offs = CORE_MOD, |
2013 | .prcm_reg_id = 3, | |
2014 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
2015 | .idlest_reg_id = 3, | |
2016 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
2017 | }, |
2018 | }, | |
70034d38 VC |
2019 | }; |
2020 | ||
45a4bb06 PW |
2021 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
2022 | .name = "hdq1w", | |
2023 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
2024 | .main_clk = "hdq_fck", | |
2025 | .prcm = { | |
2026 | .omap2 = { | |
2027 | .module_offs = CORE_MOD, | |
2028 | .prcm_reg_id = 1, | |
2029 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
2030 | .idlest_reg_id = 1, | |
2031 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
2032 | }, | |
2033 | }, | |
2034 | .class = &omap2_hdq1w_class, | |
2035 | }; | |
2036 | ||
8f993a01 TK |
2037 | /* SAD2D */ |
2038 | static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { | |
2039 | { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, | |
2040 | { .name = "rst_modem_sw", .rst_shift = 1 }, | |
2041 | }; | |
2042 | ||
2043 | static struct omap_hwmod_class omap3xxx_sad2d_class = { | |
2044 | .name = "sad2d", | |
2045 | }; | |
2046 | ||
2047 | static struct omap_hwmod omap3xxx_sad2d_hwmod = { | |
2048 | .name = "sad2d", | |
2049 | .rst_lines = omap3xxx_sad2d_resets, | |
2050 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), | |
2051 | .main_clk = "sad2d_ick", | |
2052 | .prcm = { | |
2053 | .omap2 = { | |
2054 | .module_offs = CORE_MOD, | |
2055 | .prcm_reg_id = 1, | |
2056 | .module_bit = OMAP3430_EN_SAD2D_SHIFT, | |
2057 | .idlest_reg_id = 1, | |
2058 | .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, | |
2059 | }, | |
2060 | }, | |
2061 | .class = &omap3xxx_sad2d_class, | |
2062 | }; | |
2063 | ||
c8d82ff6 VH |
2064 | /* |
2065 | * '32K sync counter' class | |
2066 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2067 | */ | |
2068 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2069 | .rev_offs = 0x0000, | |
2070 | .sysc_offs = 0x0004, | |
2071 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2072 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2073 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2074 | }; | |
2075 | ||
2076 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2077 | .name = "counter", | |
2078 | .sysc = &omap3xxx_counter_sysc, | |
2079 | }; | |
2080 | ||
2081 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2082 | .name = "counter_32k", | |
2083 | .class = &omap3xxx_counter_hwmod_class, | |
2084 | .clkdm_name = "wkup_clkdm", | |
2085 | .flags = HWMOD_SWSUP_SIDLE, | |
2086 | .main_clk = "wkup_32k_fck", | |
2087 | .prcm = { | |
2088 | .omap2 = { | |
2089 | .module_offs = WKUP_MOD, | |
2090 | .prcm_reg_id = 1, | |
2091 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2092 | .idlest_reg_id = 1, | |
2093 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2094 | }, | |
2095 | }, | |
2096 | }; | |
2097 | ||
844a3b63 PW |
2098 | /* |
2099 | * interfaces | |
2100 | */ | |
2101 | ||
2102 | /* L3 -> L4_CORE interface */ | |
2103 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2104 | .master = &omap3xxx_l3_main_hwmod, | |
2105 | .slave = &omap3xxx_l4_core_hwmod, | |
2106 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2107 | }; |
2108 | ||
844a3b63 PW |
2109 | /* L3 -> L4_PER interface */ |
2110 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2111 | .master = &omap3xxx_l3_main_hwmod, | |
2112 | .slave = &omap3xxx_l4_per_hwmod, | |
2113 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2114 | }; |
2115 | ||
844a3b63 PW |
2116 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2117 | { | |
2118 | .pa_start = 0x68000000, | |
2119 | .pa_end = 0x6800ffff, | |
2120 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2121 | }, |
844a3b63 | 2122 | { } |
70034d38 VC |
2123 | }; |
2124 | ||
844a3b63 PW |
2125 | /* MPU -> L3 interface */ |
2126 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2127 | .master = &omap3xxx_mpu_hwmod, | |
2128 | .slave = &omap3xxx_l3_main_hwmod, | |
2129 | .addr = omap3xxx_l3_main_addrs, | |
2130 | .user = OCP_USER_MPU, | |
70034d38 VC |
2131 | }; |
2132 | ||
844a3b63 PW |
2133 | /* DSS -> l3 */ |
2134 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2135 | .master = &omap3430es1_dss_core_hwmod, | |
2136 | .slave = &omap3xxx_l3_main_hwmod, | |
2137 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2138 | }; |
2139 | ||
844a3b63 PW |
2140 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2141 | .master = &omap3xxx_dss_core_hwmod, | |
2142 | .slave = &omap3xxx_l3_main_hwmod, | |
2143 | .fw = { | |
70034d38 | 2144 | .omap2 = { |
844a3b63 PW |
2145 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2146 | .flags = OMAP_FIREWALL_L3, | |
2147 | } | |
70034d38 | 2148 | }, |
844a3b63 | 2149 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2150 | }; |
2151 | ||
844a3b63 PW |
2152 | /* l3_core -> usbhsotg interface */ |
2153 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2154 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2155 | .slave = &omap3xxx_l3_main_hwmod, |
2156 | .clk = "core_l3_ick", | |
844a3b63 | 2157 | .user = OCP_USER_MPU, |
01438ab6 MK |
2158 | }; |
2159 | ||
844a3b63 PW |
2160 | /* l3_core -> am35xx_usbhsotg interface */ |
2161 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2162 | .master = &am35xx_usbhsotg_hwmod, | |
2163 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2164 | .clk = "hsotgusb_ick", |
844a3b63 | 2165 | .user = OCP_USER_MPU, |
01438ab6 | 2166 | }; |
89ea2583 | 2167 | |
8f993a01 TK |
2168 | /* l3_core -> sad2d interface */ |
2169 | static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { | |
2170 | .master = &omap3xxx_sad2d_hwmod, | |
2171 | .slave = &omap3xxx_l3_main_hwmod, | |
2172 | .clk = "core_l3_ick", | |
2173 | .user = OCP_USER_MPU, | |
2174 | }; | |
2175 | ||
844a3b63 PW |
2176 | /* L4_CORE -> L4_WKUP interface */ |
2177 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2178 | .master = &omap3xxx_l4_core_hwmod, | |
2179 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2180 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2181 | }; |
2182 | ||
844a3b63 PW |
2183 | /* L4 CORE -> MMC1 interface */ |
2184 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2185 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2186 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2187 | .clk = "mmchs1_ick", | |
2188 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2189 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2190 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2191 | }; |
2192 | ||
844a3b63 PW |
2193 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2194 | .master = &omap3xxx_l4_core_hwmod, | |
2195 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2196 | .clk = "mmchs1_ick", | |
2197 | .addr = omap2430_mmc1_addr_space, | |
2198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2199 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2200 | }; |
2201 | ||
844a3b63 PW |
2202 | /* L4 CORE -> MMC2 interface */ |
2203 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2204 | .master = &omap3xxx_l4_core_hwmod, | |
2205 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2206 | .clk = "mmchs2_ick", | |
2207 | .addr = omap2430_mmc2_addr_space, | |
2208 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2209 | .flags = OMAP_FIREWALL_L4 | |
2210 | }; | |
70034d38 | 2211 | |
844a3b63 PW |
2212 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2213 | .master = &omap3xxx_l4_core_hwmod, | |
2214 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2215 | .clk = "mmchs2_ick", | |
2216 | .addr = omap2430_mmc2_addr_space, | |
2217 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2218 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2219 | }; |
2220 | ||
844a3b63 PW |
2221 | /* L4 CORE -> MMC3 interface */ |
2222 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2223 | { | |
2224 | .pa_start = 0x480ad000, | |
2225 | .pa_end = 0x480ad1ff, | |
2226 | .flags = ADDR_TYPE_RT, | |
2227 | }, | |
2228 | { } | |
70034d38 VC |
2229 | }; |
2230 | ||
844a3b63 PW |
2231 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2232 | .master = &omap3xxx_l4_core_hwmod, | |
2233 | .slave = &omap3xxx_mmc3_hwmod, | |
2234 | .clk = "mmchs3_ick", | |
2235 | .addr = omap3xxx_mmc3_addr_space, | |
2236 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2237 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2238 | }; |
2239 | ||
844a3b63 PW |
2240 | /* L4 CORE -> UART1 interface */ |
2241 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2242 | { |
844a3b63 PW |
2243 | .pa_start = OMAP3_UART1_BASE, |
2244 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2245 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2246 | }, |
78183f3f | 2247 | { } |
70034d38 VC |
2248 | }; |
2249 | ||
844a3b63 | 2250 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2251 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2252 | .slave = &omap3xxx_uart1_hwmod, |
2253 | .clk = "uart1_ick", | |
2254 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2255 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2256 | }; |
2257 | ||
844a3b63 PW |
2258 | /* L4 CORE -> UART2 interface */ |
2259 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2260 | { | |
2261 | .pa_start = OMAP3_UART2_BASE, | |
2262 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2263 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2264 | }, |
844a3b63 | 2265 | { } |
70034d38 VC |
2266 | }; |
2267 | ||
844a3b63 PW |
2268 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2269 | .master = &omap3xxx_l4_core_hwmod, | |
2270 | .slave = &omap3xxx_uart2_hwmod, | |
2271 | .clk = "uart2_ick", | |
2272 | .addr = omap3xxx_uart2_addr_space, | |
2273 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2274 | }; |
2275 | ||
844a3b63 PW |
2276 | /* L4 PER -> UART3 interface */ |
2277 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2278 | { |
844a3b63 PW |
2279 | .pa_start = OMAP3_UART3_BASE, |
2280 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2281 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2282 | }, |
78183f3f | 2283 | { } |
70034d38 VC |
2284 | }; |
2285 | ||
844a3b63 | 2286 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2287 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2288 | .slave = &omap3xxx_uart3_hwmod, |
2289 | .clk = "uart3_ick", | |
2290 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2291 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2292 | }; |
2293 | ||
844a3b63 PW |
2294 | /* L4 PER -> UART4 interface */ |
2295 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2296 | { | |
2297 | .pa_start = OMAP3_UART4_BASE, | |
2298 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2299 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2300 | }, |
844a3b63 | 2301 | { } |
70034d38 VC |
2302 | }; |
2303 | ||
844a3b63 PW |
2304 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2305 | .master = &omap3xxx_l4_per_hwmod, | |
2306 | .slave = &omap36xx_uart4_hwmod, | |
2307 | .clk = "uart4_ick", | |
2308 | .addr = omap36xx_uart4_addr_space, | |
2309 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2310 | }; |
2311 | ||
844a3b63 PW |
2312 | /* AM35xx: L4 CORE -> UART4 interface */ |
2313 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2314 | { |
844a3b63 PW |
2315 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2316 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2317 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2318 | }, |
bf765237 | 2319 | { } |
70034d38 VC |
2320 | }; |
2321 | ||
844a3b63 PW |
2322 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2323 | .master = &omap3xxx_l4_core_hwmod, | |
2324 | .slave = &am35xx_uart4_hwmod, | |
2325 | .clk = "uart4_ick", | |
2326 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2327 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2328 | }; | |
2329 | ||
844a3b63 PW |
2330 | /* L4 CORE -> I2C1 interface */ |
2331 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2332 | .master = &omap3xxx_l4_core_hwmod, | |
2333 | .slave = &omap3xxx_i2c1_hwmod, | |
2334 | .clk = "i2c1_ick", | |
2335 | .addr = omap2_i2c1_addr_space, | |
2336 | .fw = { | |
2337 | .omap2 = { | |
2338 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2339 | .l4_prot_group = 7, | |
2340 | .flags = OMAP_FIREWALL_L4, | |
2341 | } | |
2342 | }, | |
2343 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2344 | }; |
2345 | ||
844a3b63 PW |
2346 | /* L4 CORE -> I2C2 interface */ |
2347 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2348 | .master = &omap3xxx_l4_core_hwmod, | |
2349 | .slave = &omap3xxx_i2c2_hwmod, | |
2350 | .clk = "i2c2_ick", | |
2351 | .addr = omap2_i2c2_addr_space, | |
2352 | .fw = { | |
70034d38 | 2353 | .omap2 = { |
844a3b63 PW |
2354 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2355 | .l4_prot_group = 7, | |
2356 | .flags = OMAP_FIREWALL_L4, | |
2357 | } | |
70034d38 | 2358 | }, |
844a3b63 | 2359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2360 | }; |
2361 | ||
844a3b63 PW |
2362 | /* L4 CORE -> I2C3 interface */ |
2363 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2364 | { | |
2365 | .pa_start = 0x48060000, | |
2366 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2367 | .flags = ADDR_TYPE_RT, | |
2368 | }, | |
2369 | { } | |
70034d38 VC |
2370 | }; |
2371 | ||
844a3b63 PW |
2372 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2373 | .master = &omap3xxx_l4_core_hwmod, | |
2374 | .slave = &omap3xxx_i2c3_hwmod, | |
2375 | .clk = "i2c3_ick", | |
2376 | .addr = omap3xxx_i2c3_addr_space, | |
2377 | .fw = { | |
2378 | .omap2 = { | |
2379 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2380 | .l4_prot_group = 7, | |
2381 | .flags = OMAP_FIREWALL_L4, | |
2382 | } | |
2383 | }, | |
2384 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2385 | }; |
2386 | ||
844a3b63 PW |
2387 | /* L4 CORE -> SR1 interface */ |
2388 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2389 | { |
844a3b63 PW |
2390 | .pa_start = OMAP34XX_SR1_BASE, |
2391 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2392 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2393 | }, |
78183f3f | 2394 | { } |
70034d38 VC |
2395 | }; |
2396 | ||
844a3b63 PW |
2397 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2398 | .master = &omap3xxx_l4_core_hwmod, | |
2399 | .slave = &omap34xx_sr1_hwmod, | |
2400 | .clk = "sr_l4_ick", | |
2401 | .addr = omap3_sr1_addr_space, | |
2402 | .user = OCP_USER_MPU, | |
70034d38 VC |
2403 | }; |
2404 | ||
844a3b63 PW |
2405 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2406 | .master = &omap3xxx_l4_core_hwmod, | |
2407 | .slave = &omap36xx_sr1_hwmod, | |
2408 | .clk = "sr_l4_ick", | |
2409 | .addr = omap3_sr1_addr_space, | |
2410 | .user = OCP_USER_MPU, | |
2411 | }; | |
2412 | ||
2413 | /* L4 CORE -> SR1 interface */ | |
2414 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2415 | { | |
2416 | .pa_start = OMAP34XX_SR2_BASE, | |
2417 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2418 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2419 | }, |
844a3b63 | 2420 | { } |
70034d38 VC |
2421 | }; |
2422 | ||
844a3b63 PW |
2423 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2424 | .master = &omap3xxx_l4_core_hwmod, | |
2425 | .slave = &omap34xx_sr2_hwmod, | |
2426 | .clk = "sr_l4_ick", | |
2427 | .addr = omap3_sr2_addr_space, | |
2428 | .user = OCP_USER_MPU, | |
70034d38 VC |
2429 | }; |
2430 | ||
844a3b63 PW |
2431 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2432 | .master = &omap3xxx_l4_core_hwmod, | |
2433 | .slave = &omap36xx_sr2_hwmod, | |
2434 | .clk = "sr_l4_ick", | |
2435 | .addr = omap3_sr2_addr_space, | |
2436 | .user = OCP_USER_MPU, | |
70034d38 VC |
2437 | }; |
2438 | ||
844a3b63 | 2439 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2440 | { |
844a3b63 PW |
2441 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2442 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2443 | .flags = ADDR_TYPE_RT |
2444 | }, | |
78183f3f | 2445 | { } |
70034d38 VC |
2446 | }; |
2447 | ||
844a3b63 PW |
2448 | /* l4_core -> usbhsotg */ |
2449 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2450 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2451 | .slave = &omap3xxx_usbhsotg_hwmod, |
2452 | .clk = "l4_ick", | |
2453 | .addr = omap3xxx_usbhsotg_addrs, | |
2454 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2455 | }; |
2456 | ||
844a3b63 PW |
2457 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2458 | { | |
2459 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2460 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2461 | .flags = ADDR_TYPE_RT | |
70034d38 | 2462 | }, |
844a3b63 | 2463 | { } |
70034d38 VC |
2464 | }; |
2465 | ||
844a3b63 PW |
2466 | /* l4_core -> usbhsotg */ |
2467 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2468 | .master = &omap3xxx_l4_core_hwmod, | |
2469 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2470 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2471 | .addr = am35xx_usbhsotg_addrs, |
2472 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2473 | }; |
2474 | ||
844a3b63 PW |
2475 | /* L4_WKUP -> L4_SEC interface */ |
2476 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2477 | .master = &omap3xxx_l4_wkup_hwmod, | |
2478 | .slave = &omap3xxx_l4_sec_hwmod, | |
2479 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2480 | }; |
2481 | ||
844a3b63 PW |
2482 | /* IVA2 <- L3 interface */ |
2483 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2484 | .master = &omap3xxx_l3_main_hwmod, | |
2485 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2486 | .clk = "core_l3_ick", |
844a3b63 | 2487 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2488 | }; |
2489 | ||
844a3b63 | 2490 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2491 | { |
844a3b63 PW |
2492 | .pa_start = 0x48318000, |
2493 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2494 | .flags = ADDR_TYPE_RT |
2495 | }, | |
78183f3f | 2496 | { } |
01438ab6 MK |
2497 | }; |
2498 | ||
844a3b63 PW |
2499 | /* l4_wkup -> timer1 */ |
2500 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2501 | .master = &omap3xxx_l4_wkup_hwmod, | |
2502 | .slave = &omap3xxx_timer1_hwmod, | |
2503 | .clk = "gpt1_ick", | |
2504 | .addr = omap3xxx_timer1_addrs, | |
2505 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2506 | }; |
2507 | ||
844a3b63 PW |
2508 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2509 | { | |
2510 | .pa_start = 0x49032000, | |
2511 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2512 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2513 | }, |
844a3b63 | 2514 | { } |
01438ab6 MK |
2515 | }; |
2516 | ||
844a3b63 PW |
2517 | /* l4_per -> timer2 */ |
2518 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2519 | .master = &omap3xxx_l4_per_hwmod, | |
2520 | .slave = &omap3xxx_timer2_hwmod, | |
2521 | .clk = "gpt2_ick", | |
2522 | .addr = omap3xxx_timer2_addrs, | |
2523 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2524 | }; |
2525 | ||
844a3b63 | 2526 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2527 | { |
844a3b63 PW |
2528 | .pa_start = 0x49034000, |
2529 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2530 | .flags = ADDR_TYPE_RT |
2531 | }, | |
78183f3f | 2532 | { } |
01438ab6 MK |
2533 | }; |
2534 | ||
844a3b63 PW |
2535 | /* l4_per -> timer3 */ |
2536 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2537 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2538 | .slave = &omap3xxx_timer3_hwmod, |
2539 | .clk = "gpt3_ick", | |
2540 | .addr = omap3xxx_timer3_addrs, | |
2541 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2542 | }; |
2543 | ||
844a3b63 PW |
2544 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2545 | { | |
2546 | .pa_start = 0x49036000, | |
2547 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2548 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2549 | }, |
844a3b63 | 2550 | { } |
01438ab6 MK |
2551 | }; |
2552 | ||
844a3b63 PW |
2553 | /* l4_per -> timer4 */ |
2554 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2555 | .master = &omap3xxx_l4_per_hwmod, | |
2556 | .slave = &omap3xxx_timer4_hwmod, | |
2557 | .clk = "gpt4_ick", | |
2558 | .addr = omap3xxx_timer4_addrs, | |
2559 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2560 | }; |
2561 | ||
844a3b63 PW |
2562 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2563 | { | |
2564 | .pa_start = 0x49038000, | |
2565 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2566 | .flags = ADDR_TYPE_RT | |
2567 | }, | |
2568 | { } | |
d3442726 TG |
2569 | }; |
2570 | ||
844a3b63 PW |
2571 | /* l4_per -> timer5 */ |
2572 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2573 | .master = &omap3xxx_l4_per_hwmod, | |
2574 | .slave = &omap3xxx_timer5_hwmod, | |
2575 | .clk = "gpt5_ick", | |
2576 | .addr = omap3xxx_timer5_addrs, | |
2577 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2578 | }; |
2579 | ||
844a3b63 PW |
2580 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2581 | { | |
2582 | .pa_start = 0x4903A000, | |
2583 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2584 | .flags = ADDR_TYPE_RT | |
2585 | }, | |
2586 | { } | |
cea6b942 SG |
2587 | }; |
2588 | ||
844a3b63 PW |
2589 | /* l4_per -> timer6 */ |
2590 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2591 | .master = &omap3xxx_l4_per_hwmod, | |
2592 | .slave = &omap3xxx_timer6_hwmod, | |
2593 | .clk = "gpt6_ick", | |
2594 | .addr = omap3xxx_timer6_addrs, | |
2595 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2596 | }; |
2597 | ||
844a3b63 PW |
2598 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2599 | { | |
2600 | .pa_start = 0x4903C000, | |
2601 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2602 | .flags = ADDR_TYPE_RT | |
d3442726 | 2603 | }, |
844a3b63 | 2604 | { } |
d3442726 TG |
2605 | }; |
2606 | ||
844a3b63 PW |
2607 | /* l4_per -> timer7 */ |
2608 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2609 | .master = &omap3xxx_l4_per_hwmod, | |
2610 | .slave = &omap3xxx_timer7_hwmod, | |
2611 | .clk = "gpt7_ick", | |
2612 | .addr = omap3xxx_timer7_addrs, | |
2613 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2614 | }; |
2615 | ||
844a3b63 PW |
2616 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2617 | { | |
2618 | .pa_start = 0x4903E000, | |
2619 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2620 | .flags = ADDR_TYPE_RT | |
d3442726 | 2621 | }, |
844a3b63 | 2622 | { } |
d3442726 TG |
2623 | }; |
2624 | ||
844a3b63 PW |
2625 | /* l4_per -> timer8 */ |
2626 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2627 | .master = &omap3xxx_l4_per_hwmod, | |
2628 | .slave = &omap3xxx_timer8_hwmod, | |
2629 | .clk = "gpt8_ick", | |
2630 | .addr = omap3xxx_timer8_addrs, | |
2631 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2632 | }; |
2633 | ||
844a3b63 PW |
2634 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2635 | { | |
2636 | .pa_start = 0x49040000, | |
2637 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2638 | .flags = ADDR_TYPE_RT | |
2639 | }, | |
2640 | { } | |
2641 | }; | |
0f9dfdd3 | 2642 | |
844a3b63 PW |
2643 | /* l4_per -> timer9 */ |
2644 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2645 | .master = &omap3xxx_l4_per_hwmod, | |
2646 | .slave = &omap3xxx_timer9_hwmod, | |
2647 | .clk = "gpt9_ick", | |
2648 | .addr = omap3xxx_timer9_addrs, | |
2649 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2650 | }; |
2651 | ||
844a3b63 PW |
2652 | /* l4_core -> timer10 */ |
2653 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2654 | .master = &omap3xxx_l4_core_hwmod, | |
2655 | .slave = &omap3xxx_timer10_hwmod, | |
2656 | .clk = "gpt10_ick", | |
2657 | .addr = omap2_timer10_addrs, | |
2658 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2659 | }; |
2660 | ||
844a3b63 PW |
2661 | /* l4_core -> timer11 */ |
2662 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2663 | .master = &omap3xxx_l4_core_hwmod, | |
2664 | .slave = &omap3xxx_timer11_hwmod, | |
2665 | .clk = "gpt11_ick", | |
2666 | .addr = omap2_timer11_addrs, | |
2667 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2668 | }; |
2669 | ||
844a3b63 | 2670 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2671 | { |
844a3b63 PW |
2672 | .pa_start = 0x48304000, |
2673 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2674 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2675 | }, |
78183f3f | 2676 | { } |
0f9dfdd3 FC |
2677 | }; |
2678 | ||
844a3b63 PW |
2679 | /* l4_core -> timer12 */ |
2680 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2681 | .master = &omap3xxx_l4_sec_hwmod, | |
2682 | .slave = &omap3xxx_timer12_hwmod, | |
2683 | .clk = "gpt12_ick", | |
2684 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2685 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2686 | }; | |
2687 | ||
844a3b63 PW |
2688 | /* l4_wkup -> wd_timer2 */ |
2689 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2690 | { | |
2691 | .pa_start = 0x48314000, | |
2692 | .pa_end = 0x4831407f, | |
2693 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2694 | }, |
844a3b63 | 2695 | { } |
0f9dfdd3 FC |
2696 | }; |
2697 | ||
844a3b63 PW |
2698 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2699 | .master = &omap3xxx_l4_wkup_hwmod, | |
2700 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2701 | .clk = "wdt2_ick", | |
2702 | .addr = omap3xxx_wd_timer2_addrs, | |
2703 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2704 | }; | |
2705 | ||
2706 | /* l4_core -> dss */ | |
2707 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2708 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2709 | .slave = &omap3430es1_dss_core_hwmod, |
2710 | .clk = "dss_ick", | |
2711 | .addr = omap2_dss_addrs, | |
2712 | .fw = { | |
2713 | .omap2 = { | |
2714 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2715 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2716 | .flags = OMAP_FIREWALL_L4, | |
2717 | } | |
2718 | }, | |
0f616a4e C |
2719 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2720 | }; | |
2721 | ||
844a3b63 | 2722 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2723 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2724 | .slave = &omap3xxx_dss_core_hwmod, |
2725 | .clk = "dss_ick", | |
2726 | .addr = omap2_dss_addrs, | |
2727 | .fw = { | |
2728 | .omap2 = { | |
2729 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2730 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2731 | .flags = OMAP_FIREWALL_L4, | |
2732 | } | |
2733 | }, | |
0f616a4e C |
2734 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2735 | }; | |
2736 | ||
844a3b63 PW |
2737 | /* l4_core -> dss_dispc */ |
2738 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2739 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2740 | .slave = &omap3xxx_dss_dispc_hwmod, |
2741 | .clk = "dss_ick", | |
2742 | .addr = omap2_dss_dispc_addrs, | |
2743 | .fw = { | |
2744 | .omap2 = { | |
2745 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2746 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2747 | .flags = OMAP_FIREWALL_L4, | |
2748 | } | |
2749 | }, | |
0f616a4e C |
2750 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2751 | }; | |
2752 | ||
844a3b63 | 2753 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2754 | { |
844a3b63 PW |
2755 | .pa_start = 0x4804FC00, |
2756 | .pa_end = 0x4804FFFF, | |
2757 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2758 | }, |
78183f3f | 2759 | { } |
0f616a4e C |
2760 | }; |
2761 | ||
844a3b63 PW |
2762 | /* l4_core -> dss_dsi1 */ |
2763 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2764 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2765 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2766 | .clk = "dss_ick", | |
2767 | .addr = omap3xxx_dss_dsi1_addrs, | |
2768 | .fw = { | |
2769 | .omap2 = { | |
2770 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2771 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2772 | .flags = OMAP_FIREWALL_L4, | |
2773 | } | |
2774 | }, | |
0f616a4e C |
2775 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2776 | }; | |
2777 | ||
844a3b63 PW |
2778 | /* l4_core -> dss_rfbi */ |
2779 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2780 | .master = &omap3xxx_l4_core_hwmod, | |
2781 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2782 | .clk = "dss_ick", | |
2783 | .addr = omap2_dss_rfbi_addrs, | |
2784 | .fw = { | |
0f616a4e | 2785 | .omap2 = { |
844a3b63 PW |
2786 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2787 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2788 | .flags = OMAP_FIREWALL_L4, | |
2789 | } | |
0f616a4e | 2790 | }, |
844a3b63 | 2791 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2792 | }; |
2793 | ||
844a3b63 PW |
2794 | /* l4_core -> dss_venc */ |
2795 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2796 | .master = &omap3xxx_l4_core_hwmod, | |
2797 | .slave = &omap3xxx_dss_venc_hwmod, | |
2798 | .clk = "dss_ick", | |
2799 | .addr = omap2_dss_venc_addrs, | |
2800 | .fw = { | |
70034d38 | 2801 | .omap2 = { |
844a3b63 PW |
2802 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2803 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2804 | .flags = OMAP_FIREWALL_L4, | |
2805 | } | |
70034d38 | 2806 | }, |
844a3b63 PW |
2807 | .flags = OCPIF_SWSUP_IDLE, |
2808 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2809 | }; |
2810 | ||
844a3b63 PW |
2811 | /* l4_wkup -> gpio1 */ |
2812 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2813 | { | |
2814 | .pa_start = 0x48310000, | |
2815 | .pa_end = 0x483101ff, | |
2816 | .flags = ADDR_TYPE_RT | |
2817 | }, | |
2818 | { } | |
70034d38 VC |
2819 | }; |
2820 | ||
844a3b63 PW |
2821 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2822 | .master = &omap3xxx_l4_wkup_hwmod, | |
2823 | .slave = &omap3xxx_gpio1_hwmod, | |
2824 | .addr = omap3xxx_gpio1_addrs, | |
2825 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2826 | }; |
2827 | ||
844a3b63 PW |
2828 | /* l4_per -> gpio2 */ |
2829 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2830 | { | |
2831 | .pa_start = 0x49050000, | |
2832 | .pa_end = 0x490501ff, | |
2833 | .flags = ADDR_TYPE_RT | |
70034d38 | 2834 | }, |
844a3b63 | 2835 | { } |
70034d38 VC |
2836 | }; |
2837 | ||
844a3b63 PW |
2838 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2839 | .master = &omap3xxx_l4_per_hwmod, | |
2840 | .slave = &omap3xxx_gpio2_hwmod, | |
2841 | .addr = omap3xxx_gpio2_addrs, | |
2842 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2843 | }; |
2844 | ||
844a3b63 PW |
2845 | /* l4_per -> gpio3 */ |
2846 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2847 | { | |
2848 | .pa_start = 0x49052000, | |
2849 | .pa_end = 0x490521ff, | |
2850 | .flags = ADDR_TYPE_RT | |
2851 | }, | |
2852 | { } | |
70034d38 VC |
2853 | }; |
2854 | ||
844a3b63 PW |
2855 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2856 | .master = &omap3xxx_l4_per_hwmod, | |
2857 | .slave = &omap3xxx_gpio3_hwmod, | |
2858 | .addr = omap3xxx_gpio3_addrs, | |
2859 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2860 | }; |
2861 | ||
5486474c PW |
2862 | /* |
2863 | * 'mmu' class | |
2864 | * The memory management unit performs virtual to physical address translation | |
2865 | * for its requestors. | |
2866 | */ | |
2867 | ||
2868 | static struct omap_hwmod_class_sysconfig mmu_sysc = { | |
2869 | .rev_offs = 0x000, | |
2870 | .sysc_offs = 0x010, | |
2871 | .syss_offs = 0x014, | |
2872 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
2873 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
2874 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
2875 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2876 | }; | |
2877 | ||
2878 | static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { | |
2879 | .name = "mmu", | |
2880 | .sysc = &mmu_sysc, | |
2881 | }; | |
2882 | ||
2883 | /* mmu isp */ | |
2884 | ||
2885 | static struct omap_mmu_dev_attr mmu_isp_dev_attr = { | |
2886 | .da_start = 0x0, | |
2887 | .da_end = 0xfffff000, | |
2888 | .nr_tlb_entries = 8, | |
2889 | }; | |
2890 | ||
2891 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod; | |
2892 | static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { | |
2893 | { .irq = 24 }, | |
2894 | { .irq = -1 } | |
2895 | }; | |
2896 | ||
2897 | static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { | |
2898 | { | |
2899 | .pa_start = 0x480bd400, | |
2900 | .pa_end = 0x480bd47f, | |
2901 | .flags = ADDR_TYPE_RT, | |
2902 | }, | |
2903 | { } | |
2904 | }; | |
2905 | ||
2906 | /* l4_core -> mmu isp */ | |
2907 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { | |
2908 | .master = &omap3xxx_l4_core_hwmod, | |
2909 | .slave = &omap3xxx_mmu_isp_hwmod, | |
2910 | .addr = omap3xxx_mmu_isp_addrs, | |
2911 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2912 | }; | |
2913 | ||
2914 | static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { | |
2915 | .name = "mmu_isp", | |
2916 | .class = &omap3xxx_mmu_hwmod_class, | |
2917 | .mpu_irqs = omap3xxx_mmu_isp_irqs, | |
2918 | .main_clk = "cam_ick", | |
2919 | .dev_attr = &mmu_isp_dev_attr, | |
2920 | .flags = HWMOD_NO_IDLEST, | |
2921 | }; | |
2922 | ||
2923 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
2924 | ||
2925 | /* mmu iva */ | |
2926 | ||
2927 | static struct omap_mmu_dev_attr mmu_iva_dev_attr = { | |
2928 | .da_start = 0x11000000, | |
2929 | .da_end = 0xfffff000, | |
2930 | .nr_tlb_entries = 32, | |
2931 | }; | |
2932 | ||
2933 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod; | |
2934 | static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { | |
2935 | { .irq = 28 }, | |
2936 | { .irq = -1 } | |
2937 | }; | |
2938 | ||
2939 | static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { | |
2940 | { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, | |
2941 | }; | |
2942 | ||
2943 | static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { | |
2944 | { | |
2945 | .pa_start = 0x5d000000, | |
2946 | .pa_end = 0x5d00007f, | |
2947 | .flags = ADDR_TYPE_RT, | |
2948 | }, | |
2949 | { } | |
2950 | }; | |
2951 | ||
2952 | /* l3_main -> iva mmu */ | |
2953 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { | |
2954 | .master = &omap3xxx_l3_main_hwmod, | |
2955 | .slave = &omap3xxx_mmu_iva_hwmod, | |
2956 | .addr = omap3xxx_mmu_iva_addrs, | |
2957 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2958 | }; | |
2959 | ||
2960 | static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { | |
2961 | .name = "mmu_iva", | |
2962 | .class = &omap3xxx_mmu_hwmod_class, | |
2963 | .mpu_irqs = omap3xxx_mmu_iva_irqs, | |
2964 | .rst_lines = omap3xxx_mmu_iva_resets, | |
2965 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), | |
2966 | .main_clk = "iva2_ck", | |
2967 | .prcm = { | |
2968 | .omap2 = { | |
2969 | .module_offs = OMAP3430_IVA2_MOD, | |
2970 | }, | |
2971 | }, | |
2972 | .dev_attr = &mmu_iva_dev_attr, | |
2973 | .flags = HWMOD_NO_IDLEST, | |
2974 | }; | |
2975 | ||
2976 | #endif | |
2977 | ||
844a3b63 PW |
2978 | /* l4_per -> gpio4 */ |
2979 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
2980 | { | |
2981 | .pa_start = 0x49054000, | |
2982 | .pa_end = 0x490541ff, | |
2983 | .flags = ADDR_TYPE_RT | |
70034d38 | 2984 | }, |
844a3b63 | 2985 | { } |
70034d38 VC |
2986 | }; |
2987 | ||
844a3b63 PW |
2988 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2989 | .master = &omap3xxx_l4_per_hwmod, | |
2990 | .slave = &omap3xxx_gpio4_hwmod, | |
2991 | .addr = omap3xxx_gpio4_addrs, | |
2992 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2993 | }; |
2994 | ||
844a3b63 PW |
2995 | /* l4_per -> gpio5 */ |
2996 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
2997 | { | |
2998 | .pa_start = 0x49056000, | |
2999 | .pa_end = 0x490561ff, | |
3000 | .flags = ADDR_TYPE_RT | |
3001 | }, | |
3002 | { } | |
01438ab6 MK |
3003 | }; |
3004 | ||
844a3b63 PW |
3005 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
3006 | .master = &omap3xxx_l4_per_hwmod, | |
3007 | .slave = &omap3xxx_gpio5_hwmod, | |
3008 | .addr = omap3xxx_gpio5_addrs, | |
3009 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3010 | }; |
3011 | ||
844a3b63 PW |
3012 | /* l4_per -> gpio6 */ |
3013 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
3014 | { | |
3015 | .pa_start = 0x49058000, | |
3016 | .pa_end = 0x490581ff, | |
3017 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3018 | }, |
844a3b63 | 3019 | { } |
01438ab6 MK |
3020 | }; |
3021 | ||
844a3b63 PW |
3022 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
3023 | .master = &omap3xxx_l4_per_hwmod, | |
3024 | .slave = &omap3xxx_gpio6_hwmod, | |
3025 | .addr = omap3xxx_gpio6_addrs, | |
3026 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3027 | }; |
3028 | ||
844a3b63 PW |
3029 | /* dma_system -> L3 */ |
3030 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
3031 | .master = &omap3xxx_dma_system_hwmod, | |
3032 | .slave = &omap3xxx_l3_main_hwmod, | |
3033 | .clk = "core_l3_ick", | |
3034 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
3035 | }; |
3036 | ||
844a3b63 PW |
3037 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
3038 | { | |
3039 | .pa_start = 0x48056000, | |
3040 | .pa_end = 0x48056fff, | |
3041 | .flags = ADDR_TYPE_RT | |
01438ab6 | 3042 | }, |
844a3b63 | 3043 | { } |
01438ab6 MK |
3044 | }; |
3045 | ||
844a3b63 PW |
3046 | /* l4_cfg -> dma_system */ |
3047 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
3048 | .master = &omap3xxx_l4_core_hwmod, | |
3049 | .slave = &omap3xxx_dma_system_hwmod, | |
3050 | .clk = "core_l4_ick", | |
3051 | .addr = omap3xxx_dma_system_addrs, | |
3052 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3053 | }; |
3054 | ||
844a3b63 PW |
3055 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
3056 | { | |
3057 | .name = "mpu", | |
3058 | .pa_start = 0x48074000, | |
3059 | .pa_end = 0x480740ff, | |
3060 | .flags = ADDR_TYPE_RT | |
3061 | }, | |
3062 | { } | |
d3442726 TG |
3063 | }; |
3064 | ||
844a3b63 PW |
3065 | /* l4_core -> mcbsp1 */ |
3066 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
3067 | .master = &omap3xxx_l4_core_hwmod, | |
3068 | .slave = &omap3xxx_mcbsp1_hwmod, | |
3069 | .clk = "mcbsp1_ick", | |
3070 | .addr = omap3xxx_mcbsp1_addrs, | |
3071 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3072 | }; |
3073 | ||
844a3b63 PW |
3074 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
3075 | { | |
3076 | .name = "mpu", | |
3077 | .pa_start = 0x49022000, | |
3078 | .pa_end = 0x490220ff, | |
3079 | .flags = ADDR_TYPE_RT | |
3080 | }, | |
3081 | { } | |
d3442726 TG |
3082 | }; |
3083 | ||
844a3b63 PW |
3084 | /* l4_per -> mcbsp2 */ |
3085 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
3086 | .master = &omap3xxx_l4_per_hwmod, | |
3087 | .slave = &omap3xxx_mcbsp2_hwmod, | |
3088 | .clk = "mcbsp2_ick", | |
3089 | .addr = omap3xxx_mcbsp2_addrs, | |
3090 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3091 | }; |
3092 | ||
844a3b63 PW |
3093 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
3094 | { | |
3095 | .name = "mpu", | |
3096 | .pa_start = 0x49024000, | |
3097 | .pa_end = 0x490240ff, | |
3098 | .flags = ADDR_TYPE_RT | |
3099 | }, | |
3100 | { } | |
d3442726 TG |
3101 | }; |
3102 | ||
844a3b63 PW |
3103 | /* l4_per -> mcbsp3 */ |
3104 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
3105 | .master = &omap3xxx_l4_per_hwmod, | |
3106 | .slave = &omap3xxx_mcbsp3_hwmod, | |
3107 | .clk = "mcbsp3_ick", | |
3108 | .addr = omap3xxx_mcbsp3_addrs, | |
3109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
3110 | }; |
3111 | ||
844a3b63 PW |
3112 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
3113 | { | |
3114 | .name = "mpu", | |
3115 | .pa_start = 0x49026000, | |
3116 | .pa_end = 0x490260ff, | |
3117 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 3118 | }, |
844a3b63 | 3119 | { } |
a52e2ab6 PW |
3120 | }; |
3121 | ||
844a3b63 PW |
3122 | /* l4_per -> mcbsp4 */ |
3123 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
3124 | .master = &omap3xxx_l4_per_hwmod, | |
3125 | .slave = &omap3xxx_mcbsp4_hwmod, | |
3126 | .clk = "mcbsp4_ick", | |
3127 | .addr = omap3xxx_mcbsp4_addrs, | |
3128 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3129 | }; |
3130 | ||
844a3b63 PW |
3131 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
3132 | { | |
3133 | .name = "mpu", | |
3134 | .pa_start = 0x48096000, | |
3135 | .pa_end = 0x480960ff, | |
3136 | .flags = ADDR_TYPE_RT | |
3137 | }, | |
3138 | { } | |
3139 | }; | |
b163605e | 3140 | |
844a3b63 PW |
3141 | /* l4_core -> mcbsp5 */ |
3142 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
3143 | .master = &omap3xxx_l4_core_hwmod, | |
3144 | .slave = &omap3xxx_mcbsp5_hwmod, | |
3145 | .clk = "mcbsp5_ick", | |
3146 | .addr = omap3xxx_mcbsp5_addrs, | |
3147 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3148 | }; |
3149 | ||
844a3b63 PW |
3150 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
3151 | { | |
3152 | .name = "sidetone", | |
3153 | .pa_start = 0x49028000, | |
3154 | .pa_end = 0x490280ff, | |
3155 | .flags = ADDR_TYPE_RT | |
3156 | }, | |
3157 | { } | |
d3442726 TG |
3158 | }; |
3159 | ||
844a3b63 PW |
3160 | /* l4_per -> mcbsp2_sidetone */ |
3161 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
3162 | .master = &omap3xxx_l4_per_hwmod, | |
3163 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
3164 | .clk = "mcbsp2_ick", | |
3165 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
3166 | .user = OCP_USER_MPU, | |
b163605e PW |
3167 | }; |
3168 | ||
844a3b63 PW |
3169 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
3170 | { | |
3171 | .name = "sidetone", | |
3172 | .pa_start = 0x4902A000, | |
3173 | .pa_end = 0x4902A0ff, | |
3174 | .flags = ADDR_TYPE_RT | |
3175 | }, | |
3176 | { } | |
a52e2ab6 PW |
3177 | }; |
3178 | ||
844a3b63 PW |
3179 | /* l4_per -> mcbsp3_sidetone */ |
3180 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
3181 | .master = &omap3xxx_l4_per_hwmod, | |
3182 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
3183 | .clk = "mcbsp3_ick", | |
3184 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
3185 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
3186 | }; |
3187 | ||
844a3b63 PW |
3188 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
3189 | { | |
3190 | .pa_start = 0x48094000, | |
3191 | .pa_end = 0x480941ff, | |
3192 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3193 | }, |
844a3b63 | 3194 | { } |
d3442726 TG |
3195 | }; |
3196 | ||
844a3b63 PW |
3197 | /* l4_core -> mailbox */ |
3198 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3199 | .master = &omap3xxx_l4_core_hwmod, | |
3200 | .slave = &omap3xxx_mailbox_hwmod, | |
3201 | .addr = omap3xxx_mailbox_addrs, | |
3202 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3203 | }; | |
b163605e | 3204 | |
844a3b63 PW |
3205 | /* l4 core -> mcspi1 interface */ |
3206 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3207 | .master = &omap3xxx_l4_core_hwmod, | |
3208 | .slave = &omap34xx_mcspi1, | |
3209 | .clk = "mcspi1_ick", | |
3210 | .addr = omap2_mcspi1_addr_space, | |
3211 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3212 | }; |
3213 | ||
844a3b63 PW |
3214 | /* l4 core -> mcspi2 interface */ |
3215 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3216 | .master = &omap3xxx_l4_core_hwmod, | |
3217 | .slave = &omap34xx_mcspi2, | |
3218 | .clk = "mcspi2_ick", | |
3219 | .addr = omap2_mcspi2_addr_space, | |
3220 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3221 | }; |
3222 | ||
844a3b63 PW |
3223 | /* l4 core -> mcspi3 interface */ |
3224 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3225 | .master = &omap3xxx_l4_core_hwmod, | |
3226 | .slave = &omap34xx_mcspi3, | |
3227 | .clk = "mcspi3_ick", | |
3228 | .addr = omap2430_mcspi3_addr_space, | |
3229 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3230 | }; |
3231 | ||
844a3b63 PW |
3232 | /* l4 core -> mcspi4 interface */ |
3233 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3234 | { | |
3235 | .pa_start = 0x480ba000, | |
3236 | .pa_end = 0x480ba0ff, | |
3237 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3238 | }, |
844a3b63 PW |
3239 | { } |
3240 | }; | |
3241 | ||
3242 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3243 | .master = &omap3xxx_l4_core_hwmod, | |
3244 | .slave = &omap34xx_mcspi4, | |
3245 | .clk = "mcspi4_ick", | |
3246 | .addr = omap34xx_mcspi4_addr_space, | |
3247 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3248 | }; |
3249 | ||
de231388 KM |
3250 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3251 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3252 | .slave = &omap3xxx_l3_main_hwmod, | |
3253 | .clk = "core_l3_ick", | |
3254 | .user = OCP_USER_MPU, | |
3255 | }; | |
3256 | ||
de231388 KM |
3257 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3258 | { | |
3259 | .name = "uhh", | |
3260 | .pa_start = 0x48064000, | |
3261 | .pa_end = 0x480643ff, | |
3262 | .flags = ADDR_TYPE_RT | |
3263 | }, | |
3264 | { | |
3265 | .name = "ohci", | |
3266 | .pa_start = 0x48064400, | |
3267 | .pa_end = 0x480647ff, | |
3268 | }, | |
3269 | { | |
3270 | .name = "ehci", | |
3271 | .pa_start = 0x48064800, | |
3272 | .pa_end = 0x48064cff, | |
3273 | }, | |
3274 | {} | |
3275 | }; | |
3276 | ||
3277 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3278 | .master = &omap3xxx_l4_core_hwmod, | |
3279 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3280 | .clk = "usbhost_ick", | |
3281 | .addr = omap3xxx_usb_host_hs_addrs, | |
3282 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3283 | }; | |
3284 | ||
de231388 KM |
3285 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3286 | { | |
3287 | .name = "tll", | |
3288 | .pa_start = 0x48062000, | |
3289 | .pa_end = 0x48062fff, | |
3290 | .flags = ADDR_TYPE_RT | |
3291 | }, | |
3292 | {} | |
3293 | }; | |
3294 | ||
3295 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3296 | .master = &omap3xxx_l4_core_hwmod, | |
3297 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3298 | .clk = "usbtll_ick", | |
3299 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3300 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3301 | }; | |
3302 | ||
45a4bb06 PW |
3303 | /* l4_core -> hdq1w interface */ |
3304 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3305 | .master = &omap3xxx_l4_core_hwmod, | |
3306 | .slave = &omap3xxx_hdq1w_hwmod, | |
3307 | .clk = "hdq_ick", | |
3308 | .addr = omap2_hdq1w_addr_space, | |
3309 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3310 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3311 | }; | |
3312 | ||
c8d82ff6 VH |
3313 | /* l4_wkup -> 32ksync_counter */ |
3314 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3315 | { | |
3316 | .pa_start = 0x48320000, | |
3317 | .pa_end = 0x4832001f, | |
3318 | .flags = ADDR_TYPE_RT | |
3319 | }, | |
3320 | { } | |
3321 | }; | |
3322 | ||
3323 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { | |
3324 | .master = &omap3xxx_l4_wkup_hwmod, | |
3325 | .slave = &omap3xxx_counter_32k_hwmod, | |
3326 | .clk = "omap_32ksync_ick", | |
3327 | .addr = omap3xxx_counter_32k_addrs, | |
3328 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3329 | }; | |
3330 | ||
31ba8808 MG |
3331 | /* am35xx has Davinci MDIO & EMAC */ |
3332 | static struct omap_hwmod_class am35xx_mdio_class = { | |
3333 | .name = "davinci_mdio", | |
3334 | }; | |
3335 | ||
3336 | static struct omap_hwmod am35xx_mdio_hwmod = { | |
3337 | .name = "davinci_mdio", | |
3338 | .class = &am35xx_mdio_class, | |
3339 | .flags = HWMOD_NO_IDLEST, | |
3340 | }; | |
3341 | ||
3342 | /* | |
3343 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3344 | * but this will probably require some additional hwmod core support, | |
3345 | * so is left as a future to-do item. | |
3346 | */ | |
3347 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | |
3348 | .master = &am35xx_mdio_hwmod, | |
3349 | .slave = &omap3xxx_l3_main_hwmod, | |
3350 | .clk = "emac_fck", | |
3351 | .user = OCP_USER_MPU, | |
3352 | }; | |
3353 | ||
3354 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | |
3355 | { | |
3356 | .pa_start = AM35XX_IPSS_MDIO_BASE, | |
3357 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | |
3358 | .flags = ADDR_TYPE_RT, | |
3359 | }, | |
3360 | { } | |
3361 | }; | |
3362 | ||
3363 | /* l4_core -> davinci mdio */ | |
3364 | /* | |
3365 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3366 | * but this will probably require some additional hwmod core support, | |
3367 | * so is left as a future to-do item. | |
3368 | */ | |
3369 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | |
3370 | .master = &omap3xxx_l4_core_hwmod, | |
3371 | .slave = &am35xx_mdio_hwmod, | |
3372 | .clk = "emac_fck", | |
3373 | .addr = am35xx_mdio_addrs, | |
3374 | .user = OCP_USER_MPU, | |
3375 | }; | |
3376 | ||
3377 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | |
7d7e1eba TL |
3378 | { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, |
3379 | { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, | |
3380 | { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, | |
3381 | { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, | |
3382 | { .irq = -1 }, | |
31ba8808 MG |
3383 | }; |
3384 | ||
3385 | static struct omap_hwmod_class am35xx_emac_class = { | |
3386 | .name = "davinci_emac", | |
3387 | }; | |
3388 | ||
3389 | static struct omap_hwmod am35xx_emac_hwmod = { | |
3390 | .name = "davinci_emac", | |
3391 | .mpu_irqs = am35xx_emac_mpu_irqs, | |
3392 | .class = &am35xx_emac_class, | |
3393 | .flags = HWMOD_NO_IDLEST, | |
3394 | }; | |
3395 | ||
3396 | /* l3_core -> davinci emac interface */ | |
3397 | /* | |
3398 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | |
3399 | * but this will probably require some additional hwmod core support, | |
3400 | * so is left as a future to-do item. | |
3401 | */ | |
3402 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | |
3403 | .master = &am35xx_emac_hwmod, | |
3404 | .slave = &omap3xxx_l3_main_hwmod, | |
3405 | .clk = "emac_ick", | |
3406 | .user = OCP_USER_MPU, | |
3407 | }; | |
3408 | ||
3409 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | |
3410 | { | |
3411 | .pa_start = AM35XX_IPSS_EMAC_BASE, | |
3412 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | |
3413 | .flags = ADDR_TYPE_RT, | |
3414 | }, | |
3415 | { } | |
3416 | }; | |
3417 | ||
3418 | /* l4_core -> davinci emac */ | |
3419 | /* | |
3420 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | |
3421 | * but this will probably require some additional hwmod core support, | |
3422 | * so is left as a future to-do item. | |
3423 | */ | |
3424 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | |
3425 | .master = &omap3xxx_l4_core_hwmod, | |
3426 | .slave = &am35xx_emac_hwmod, | |
3427 | .clk = "emac_ick", | |
3428 | .addr = am35xx_emac_addrs, | |
3429 | .user = OCP_USER_MPU, | |
3430 | }; | |
3431 | ||
0a78c5c5 PW |
3432 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3433 | &omap3xxx_l3_main__l4_core, | |
3434 | &omap3xxx_l3_main__l4_per, | |
3435 | &omap3xxx_mpu__l3_main, | |
3436 | &omap3xxx_l4_core__l4_wkup, | |
3437 | &omap3xxx_l4_core__mmc3, | |
3438 | &omap3_l4_core__uart1, | |
3439 | &omap3_l4_core__uart2, | |
3440 | &omap3_l4_per__uart3, | |
3441 | &omap3_l4_core__i2c1, | |
3442 | &omap3_l4_core__i2c2, | |
3443 | &omap3_l4_core__i2c3, | |
3444 | &omap3xxx_l4_wkup__l4_sec, | |
3445 | &omap3xxx_l4_wkup__timer1, | |
3446 | &omap3xxx_l4_per__timer2, | |
3447 | &omap3xxx_l4_per__timer3, | |
3448 | &omap3xxx_l4_per__timer4, | |
3449 | &omap3xxx_l4_per__timer5, | |
3450 | &omap3xxx_l4_per__timer6, | |
3451 | &omap3xxx_l4_per__timer7, | |
3452 | &omap3xxx_l4_per__timer8, | |
3453 | &omap3xxx_l4_per__timer9, | |
3454 | &omap3xxx_l4_core__timer10, | |
3455 | &omap3xxx_l4_core__timer11, | |
3456 | &omap3xxx_l4_wkup__wd_timer2, | |
3457 | &omap3xxx_l4_wkup__gpio1, | |
3458 | &omap3xxx_l4_per__gpio2, | |
3459 | &omap3xxx_l4_per__gpio3, | |
3460 | &omap3xxx_l4_per__gpio4, | |
3461 | &omap3xxx_l4_per__gpio5, | |
3462 | &omap3xxx_l4_per__gpio6, | |
3463 | &omap3xxx_dma_system__l3, | |
3464 | &omap3xxx_l4_core__dma_system, | |
3465 | &omap3xxx_l4_core__mcbsp1, | |
3466 | &omap3xxx_l4_per__mcbsp2, | |
3467 | &omap3xxx_l4_per__mcbsp3, | |
3468 | &omap3xxx_l4_per__mcbsp4, | |
3469 | &omap3xxx_l4_core__mcbsp5, | |
3470 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3471 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3472 | &omap34xx_l4_core__mcspi1, | |
3473 | &omap34xx_l4_core__mcspi2, | |
3474 | &omap34xx_l4_core__mcspi3, | |
3475 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3476 | &omap3xxx_l4_wkup__counter_32k, |
d6504acd PW |
3477 | NULL, |
3478 | }; | |
3479 | ||
0a78c5c5 PW |
3480 | /* GP-only hwmod links */ |
3481 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3482 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3483 | NULL |
3484 | }; | |
3485 | ||
0a78c5c5 PW |
3486 | /* 3430ES1-only hwmod links */ |
3487 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3488 | &omap3430es1_dss__l3, | |
3489 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3490 | NULL |
3491 | }; | |
3492 | ||
0a78c5c5 PW |
3493 | /* 3430ES2+-only hwmod links */ |
3494 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3495 | &omap3xxx_dss__l3, | |
3496 | &omap3xxx_l4_core__dss, | |
3497 | &omap3xxx_usbhsotg__l3, | |
3498 | &omap3xxx_l4_core__usbhsotg, | |
3499 | &omap3xxx_usb_host_hs__l3_main_2, | |
3500 | &omap3xxx_l4_core__usb_host_hs, | |
3501 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3502 | NULL |
3503 | }; | |
870ea2b8 | 3504 | |
0a78c5c5 PW |
3505 | /* <= 3430ES3-only hwmod links */ |
3506 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3507 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3508 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3509 | NULL |
3510 | }; | |
3511 | ||
0a78c5c5 PW |
3512 | /* 3430ES3+-only hwmod links */ |
3513 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3514 | &omap3xxx_l4_core__es3plus_mmc1, | |
3515 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3516 | NULL |
3517 | }; | |
3518 | ||
0a78c5c5 PW |
3519 | /* 34xx-only hwmod links (all ES revisions) */ |
3520 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3521 | &omap3xxx_l3__iva, | |
3522 | &omap34xx_l4_core__sr1, | |
3523 | &omap34xx_l4_core__sr2, | |
3524 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3525 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3526 | &omap3xxx_sad2d__l3, |
5486474c PW |
3527 | &omap3xxx_l4_core__mmu_isp, |
3528 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3529 | &omap3xxx_l3_main__mmu_iva, | |
3530 | #endif | |
d6504acd PW |
3531 | NULL |
3532 | }; | |
273ff8c3 | 3533 | |
0a78c5c5 PW |
3534 | /* 36xx-only hwmod links (all ES revisions) */ |
3535 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3536 | &omap3xxx_l3__iva, | |
3537 | &omap36xx_l4_per__uart4, | |
3538 | &omap3xxx_dss__l3, | |
3539 | &omap3xxx_l4_core__dss, | |
3540 | &omap36xx_l4_core__sr1, | |
3541 | &omap36xx_l4_core__sr2, | |
3542 | &omap3xxx_usbhsotg__l3, | |
3543 | &omap3xxx_l4_core__usbhsotg, | |
3544 | &omap3xxx_l4_core__mailbox, | |
3545 | &omap3xxx_usb_host_hs__l3_main_2, | |
3546 | &omap3xxx_l4_core__usb_host_hs, | |
3547 | &omap3xxx_l4_core__usb_tll_hs, | |
3548 | &omap3xxx_l4_core__es3plus_mmc1, | |
3549 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3550 | &omap3xxx_l4_core__hdq1w, |
8f993a01 | 3551 | &omap3xxx_sad2d__l3, |
5486474c PW |
3552 | &omap3xxx_l4_core__mmu_isp, |
3553 | #ifdef CONFIG_OMAP_IOMMU_IVA2 | |
3554 | &omap3xxx_l3_main__mmu_iva, | |
3555 | #endif | |
d6504acd PW |
3556 | NULL |
3557 | }; | |
3558 | ||
0a78c5c5 PW |
3559 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3560 | &omap3xxx_dss__l3, | |
3561 | &omap3xxx_l4_core__dss, | |
3562 | &am35xx_usbhsotg__l3, | |
3563 | &am35xx_l4_core__usbhsotg, | |
3564 | &am35xx_l4_core__uart4, | |
3565 | &omap3xxx_usb_host_hs__l3_main_2, | |
3566 | &omap3xxx_l4_core__usb_host_hs, | |
3567 | &omap3xxx_l4_core__usb_tll_hs, | |
3568 | &omap3xxx_l4_core__es3plus_mmc1, | |
3569 | &omap3xxx_l4_core__es3plus_mmc2, | |
31ba8808 MG |
3570 | &am35xx_mdio__l3, |
3571 | &am35xx_l4_core__mdio, | |
3572 | &am35xx_emac__l3, | |
3573 | &am35xx_l4_core__emac, | |
d6504acd | 3574 | NULL |
7359154e PW |
3575 | }; |
3576 | ||
0a78c5c5 PW |
3577 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3578 | &omap3xxx_l4_core__dss_dispc, | |
3579 | &omap3xxx_l4_core__dss_dsi1, | |
3580 | &omap3xxx_l4_core__dss_rfbi, | |
3581 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3582 | NULL |
3583 | }; | |
3584 | ||
7359154e PW |
3585 | int __init omap3xxx_hwmod_init(void) |
3586 | { | |
d6504acd | 3587 | int r; |
0a78c5c5 | 3588 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3589 | unsigned int rev; |
3590 | ||
9ebfd285 KH |
3591 | omap_hwmod_init(); |
3592 | ||
0a78c5c5 PW |
3593 | /* Register hwmod links common to all OMAP3 */ |
3594 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3595 | if (r < 0) |
d6504acd PW |
3596 | return r; |
3597 | ||
0a78c5c5 | 3598 | /* Register GP-only hwmod links. */ |
91a36bdb | 3599 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3600 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3601 | if (r < 0) |
3602 | return r; | |
3603 | } | |
3604 | ||
d6504acd PW |
3605 | rev = omap_rev(); |
3606 | ||
3607 | /* | |
0a78c5c5 | 3608 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3609 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3610 | * All possible revisions should be included in this conditional. | |
3611 | */ | |
3612 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3613 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3614 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3615 | h = omap34xx_hwmod_ocp_ifs; |
68a88b98 | 3616 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3617 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3618 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3619 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3620 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3621 | } else { |
3622 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3623 | return -EINVAL; | |
3624 | }; | |
3625 | ||
0a78c5c5 | 3626 | r = omap_hwmod_register_links(h); |
ace90216 | 3627 | if (r < 0) |
d6504acd PW |
3628 | return r; |
3629 | ||
3630 | /* | |
0a78c5c5 | 3631 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3632 | * particular family of silicon (e.g., 34xx ES1.0) |
3633 | */ | |
3634 | h = NULL; | |
3635 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3636 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3637 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3638 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3639 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3640 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3641 | }; |
3642 | ||
a52e2ab6 | 3643 | if (h) { |
0a78c5c5 | 3644 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3645 | if (r < 0) |
3646 | return r; | |
3647 | } | |
3648 | ||
3649 | h = NULL; | |
3650 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3651 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3652 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3653 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3654 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3655 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3656 | }; |
3657 | ||
d6504acd | 3658 | if (h) |
0a78c5c5 | 3659 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3660 | if (r < 0) |
3661 | return r; | |
3662 | ||
3663 | /* | |
3664 | * DSS code presumes that dss_core hwmod is handled first, | |
3665 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3666 | * DSS hwmod links last to ensure that dss_core is already |
3667 | * registered. Otherwise some change things may happen, for | |
3668 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3669 | * in bootloader DISPC will be reset with outputs enabled | |
3670 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3671 | * long-term fix to this is to ensure hwmods are set up in | |
3672 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3673 | */ |
0a78c5c5 | 3674 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3675 | |
3676 | return r; | |
7359154e | 3677 | } |