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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
78183f3f | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
0a78c5c5 | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
7359154e PW |
6 | * Paul Walmsley |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * The data in this file should be completely autogeneratable from | |
13 | * the TI hardware database or other technical documentation. | |
14 | * | |
15 | * XXX these should be marked initdata for multi-OMAP kernels | |
16 | */ | |
17 | #include <plat/omap_hwmod.h> | |
18 | #include <mach/irqs.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/dma.h> | |
046465b7 | 21 | #include <plat/serial.h> |
e04d9e1e | 22 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
23 | #include <plat/l4_3xxx.h> |
24 | #include <plat/i2c.h> | |
70034d38 | 25 | #include <plat/gpio.h> |
6ab8946f | 26 | #include <plat/mmc.h> |
dc48e5fc | 27 | #include <plat/mcbsp.h> |
0f616a4e | 28 | #include <plat/mcspi.h> |
ce722d26 | 29 | #include <plat/dmtimer.h> |
7359154e | 30 | |
43b40992 PW |
31 | #include "omap_hwmod_common_data.h" |
32 | ||
cea6b942 | 33 | #include "smartreflex.h" |
7359154e | 34 | #include "prm-regbits-34xx.h" |
6b667f88 | 35 | #include "cm-regbits-34xx.h" |
ff2516fb | 36 | #include "wd_timer.h" |
273ff8c3 | 37 | #include <mach/am35xx.h> |
7359154e PW |
38 | |
39 | /* | |
40 | * OMAP3xxx hardware module integration data | |
41 | * | |
844a3b63 | 42 | * All of the data in this section should be autogeneratable from the |
7359154e PW |
43 | * TI hardware database or other technical documentation. Data that |
44 | * is driver-specific or driver-kernel integration-specific belongs | |
45 | * elsewhere. | |
46 | */ | |
47 | ||
844a3b63 PW |
48 | /* |
49 | * IP blocks | |
50 | */ | |
7359154e | 51 | |
844a3b63 | 52 | /* L3 */ |
4bb194dc | 53 | static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { |
54 | { .irq = INT_34XX_L3_DBG_IRQ }, | |
55 | { .irq = INT_34XX_L3_APP_IRQ }, | |
212738a4 | 56 | { .irq = -1 } |
4bb194dc | 57 | }; |
58 | ||
4a7cf90a | 59 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 60 | .name = "l3_main", |
43b40992 | 61 | .class = &l3_hwmod_class, |
0d619a89 | 62 | .mpu_irqs = omap3xxx_l3_main_irqs, |
2eb1875d | 63 | .flags = HWMOD_NO_IDLEST, |
7359154e PW |
64 | }; |
65 | ||
844a3b63 PW |
66 | /* L4 CORE */ |
67 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
68 | .name = "l4_core", | |
69 | .class = &l4_hwmod_class, | |
70 | .flags = HWMOD_NO_IDLEST, | |
870ea2b8 | 71 | }; |
7359154e | 72 | |
844a3b63 PW |
73 | /* L4 PER */ |
74 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
75 | .name = "l4_per", | |
76 | .class = &l4_hwmod_class, | |
77 | .flags = HWMOD_NO_IDLEST, | |
273ff8c3 | 78 | }; |
844a3b63 PW |
79 | |
80 | /* L4 WKUP */ | |
81 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
82 | .name = "l4_wkup", | |
83 | .class = &l4_hwmod_class, | |
84 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
85 | }; |
86 | ||
844a3b63 PW |
87 | /* L4 SEC */ |
88 | static struct omap_hwmod omap3xxx_l4_sec_hwmod = { | |
89 | .name = "l4_sec", | |
90 | .class = &l4_hwmod_class, | |
91 | .flags = HWMOD_NO_IDLEST, | |
4a9efb62 PW |
92 | }; |
93 | ||
844a3b63 PW |
94 | /* MPU */ |
95 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
96 | .name = "mpu", | |
97 | .class = &mpu_hwmod_class, | |
98 | .main_clk = "arm_fck", | |
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99 | }; |
100 | ||
844a3b63 | 101 | /* IVA2 (IVA2) */ |
f42c5496 PW |
102 | static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { |
103 | { .name = "logic", .rst_shift = 0 }, | |
104 | { .name = "seq0", .rst_shift = 1 }, | |
105 | { .name = "seq1", .rst_shift = 2 }, | |
106 | }; | |
107 | ||
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108 | static struct omap_hwmod omap3xxx_iva_hwmod = { |
109 | .name = "iva", | |
110 | .class = &iva_hwmod_class, | |
f42c5496 PW |
111 | .clkdm_name = "iva2_clkdm", |
112 | .rst_lines = omap3xxx_iva_resets, | |
113 | .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), | |
114 | .main_clk = "iva2_ck", | |
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115 | }; |
116 | ||
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117 | /* timer class */ |
118 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { | |
119 | .rev_offs = 0x0000, | |
120 | .sysc_offs = 0x0010, | |
121 | .syss_offs = 0x0014, | |
122 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
123 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
124 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
125 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
126 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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127 | }; |
128 | ||
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129 | static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { |
130 | .name = "timer", | |
131 | .sysc = &omap3xxx_timer_1ms_sysc, | |
132 | .rev = OMAP_TIMER_IP_VERSION_1, | |
b163605e PW |
133 | }; |
134 | ||
844a3b63 PW |
135 | static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { |
136 | .rev_offs = 0x0000, | |
137 | .sysc_offs = 0x0010, | |
138 | .syss_offs = 0x0014, | |
139 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
140 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
141 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
142 | .sysc_fields = &omap_hwmod_sysc_type1, | |
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143 | }; |
144 | ||
844a3b63 PW |
145 | static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { |
146 | .name = "timer", | |
147 | .sysc = &omap3xxx_timer_sysc, | |
148 | .rev = OMAP_TIMER_IP_VERSION_1, | |
046465b7 KH |
149 | }; |
150 | ||
844a3b63 PW |
151 | /* secure timers dev attribute */ |
152 | static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { | |
153 | .timer_capability = OMAP_TIMER_SECURE, | |
046465b7 KH |
154 | }; |
155 | ||
844a3b63 PW |
156 | /* always-on timers dev attribute */ |
157 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { | |
158 | .timer_capability = OMAP_TIMER_ALWON, | |
046465b7 KH |
159 | }; |
160 | ||
844a3b63 PW |
161 | /* pwm timers dev attribute */ |
162 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { | |
163 | .timer_capability = OMAP_TIMER_HAS_PWM, | |
046465b7 KH |
164 | }; |
165 | ||
844a3b63 PW |
166 | /* timer1 */ |
167 | static struct omap_hwmod omap3xxx_timer1_hwmod = { | |
168 | .name = "timer1", | |
169 | .mpu_irqs = omap2_timer1_mpu_irqs, | |
170 | .main_clk = "gpt1_fck", | |
171 | .prcm = { | |
172 | .omap2 = { | |
173 | .prcm_reg_id = 1, | |
174 | .module_bit = OMAP3430_EN_GPT1_SHIFT, | |
175 | .module_offs = WKUP_MOD, | |
176 | .idlest_reg_id = 1, | |
177 | .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, | |
178 | }, | |
046465b7 | 179 | }, |
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180 | .dev_attr = &capability_alwon_dev_attr, |
181 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
182 | }; |
183 | ||
844a3b63 PW |
184 | /* timer2 */ |
185 | static struct omap_hwmod omap3xxx_timer2_hwmod = { | |
186 | .name = "timer2", | |
187 | .mpu_irqs = omap2_timer2_mpu_irqs, | |
188 | .main_clk = "gpt2_fck", | |
189 | .prcm = { | |
190 | .omap2 = { | |
191 | .prcm_reg_id = 1, | |
192 | .module_bit = OMAP3430_EN_GPT2_SHIFT, | |
193 | .module_offs = OMAP3430_PER_MOD, | |
194 | .idlest_reg_id = 1, | |
195 | .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, | |
196 | }, | |
197 | }, | |
198 | .dev_attr = &capability_alwon_dev_attr, | |
199 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
046465b7 KH |
200 | }; |
201 | ||
844a3b63 PW |
202 | /* timer3 */ |
203 | static struct omap_hwmod omap3xxx_timer3_hwmod = { | |
204 | .name = "timer3", | |
205 | .mpu_irqs = omap2_timer3_mpu_irqs, | |
206 | .main_clk = "gpt3_fck", | |
207 | .prcm = { | |
208 | .omap2 = { | |
209 | .prcm_reg_id = 1, | |
210 | .module_bit = OMAP3430_EN_GPT3_SHIFT, | |
211 | .module_offs = OMAP3430_PER_MOD, | |
212 | .idlest_reg_id = 1, | |
213 | .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, | |
214 | }, | |
215 | }, | |
216 | .dev_attr = &capability_alwon_dev_attr, | |
217 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
218 | }; |
219 | ||
844a3b63 PW |
220 | /* timer4 */ |
221 | static struct omap_hwmod omap3xxx_timer4_hwmod = { | |
222 | .name = "timer4", | |
223 | .mpu_irqs = omap2_timer4_mpu_irqs, | |
224 | .main_clk = "gpt4_fck", | |
225 | .prcm = { | |
226 | .omap2 = { | |
227 | .prcm_reg_id = 1, | |
228 | .module_bit = OMAP3430_EN_GPT4_SHIFT, | |
229 | .module_offs = OMAP3430_PER_MOD, | |
230 | .idlest_reg_id = 1, | |
231 | .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, | |
232 | }, | |
233 | }, | |
234 | .dev_attr = &capability_alwon_dev_attr, | |
235 | .class = &omap3xxx_timer_hwmod_class, | |
046465b7 KH |
236 | }; |
237 | ||
844a3b63 PW |
238 | /* timer5 */ |
239 | static struct omap_hwmod omap3xxx_timer5_hwmod = { | |
240 | .name = "timer5", | |
241 | .mpu_irqs = omap2_timer5_mpu_irqs, | |
242 | .main_clk = "gpt5_fck", | |
243 | .prcm = { | |
244 | .omap2 = { | |
245 | .prcm_reg_id = 1, | |
246 | .module_bit = OMAP3430_EN_GPT5_SHIFT, | |
247 | .module_offs = OMAP3430_PER_MOD, | |
248 | .idlest_reg_id = 1, | |
249 | .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, | |
250 | }, | |
4bf90f65 | 251 | }, |
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252 | .dev_attr = &capability_alwon_dev_attr, |
253 | .class = &omap3xxx_timer_hwmod_class, | |
4bf90f65 KM |
254 | }; |
255 | ||
844a3b63 PW |
256 | /* timer6 */ |
257 | static struct omap_hwmod omap3xxx_timer6_hwmod = { | |
258 | .name = "timer6", | |
259 | .mpu_irqs = omap2_timer6_mpu_irqs, | |
260 | .main_clk = "gpt6_fck", | |
261 | .prcm = { | |
262 | .omap2 = { | |
263 | .prcm_reg_id = 1, | |
264 | .module_bit = OMAP3430_EN_GPT6_SHIFT, | |
265 | .module_offs = OMAP3430_PER_MOD, | |
266 | .idlest_reg_id = 1, | |
267 | .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, | |
268 | }, | |
269 | }, | |
270 | .dev_attr = &capability_alwon_dev_attr, | |
271 | .class = &omap3xxx_timer_hwmod_class, | |
4bf90f65 KM |
272 | }; |
273 | ||
844a3b63 PW |
274 | /* timer7 */ |
275 | static struct omap_hwmod omap3xxx_timer7_hwmod = { | |
276 | .name = "timer7", | |
277 | .mpu_irqs = omap2_timer7_mpu_irqs, | |
278 | .main_clk = "gpt7_fck", | |
279 | .prcm = { | |
4fe20e97 | 280 | .omap2 = { |
844a3b63 PW |
281 | .prcm_reg_id = 1, |
282 | .module_bit = OMAP3430_EN_GPT7_SHIFT, | |
283 | .module_offs = OMAP3430_PER_MOD, | |
284 | .idlest_reg_id = 1, | |
285 | .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, | |
286 | }, | |
4fe20e97 | 287 | }, |
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288 | .dev_attr = &capability_alwon_dev_attr, |
289 | .class = &omap3xxx_timer_hwmod_class, | |
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290 | }; |
291 | ||
844a3b63 PW |
292 | /* timer8 */ |
293 | static struct omap_hwmod omap3xxx_timer8_hwmod = { | |
294 | .name = "timer8", | |
295 | .mpu_irqs = omap2_timer8_mpu_irqs, | |
296 | .main_clk = "gpt8_fck", | |
297 | .prcm = { | |
4fe20e97 | 298 | .omap2 = { |
844a3b63 PW |
299 | .prcm_reg_id = 1, |
300 | .module_bit = OMAP3430_EN_GPT8_SHIFT, | |
301 | .module_offs = OMAP3430_PER_MOD, | |
302 | .idlest_reg_id = 1, | |
303 | .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, | |
304 | }, | |
4fe20e97 | 305 | }, |
844a3b63 PW |
306 | .dev_attr = &capability_pwm_dev_attr, |
307 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
308 | }; |
309 | ||
844a3b63 PW |
310 | /* timer9 */ |
311 | static struct omap_hwmod omap3xxx_timer9_hwmod = { | |
312 | .name = "timer9", | |
313 | .mpu_irqs = omap2_timer9_mpu_irqs, | |
314 | .main_clk = "gpt9_fck", | |
315 | .prcm = { | |
316 | .omap2 = { | |
317 | .prcm_reg_id = 1, | |
318 | .module_bit = OMAP3430_EN_GPT9_SHIFT, | |
319 | .module_offs = OMAP3430_PER_MOD, | |
320 | .idlest_reg_id = 1, | |
321 | .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, | |
322 | }, | |
4fe20e97 | 323 | }, |
844a3b63 PW |
324 | .dev_attr = &capability_pwm_dev_attr, |
325 | .class = &omap3xxx_timer_hwmod_class, | |
4fe20e97 RN |
326 | }; |
327 | ||
844a3b63 PW |
328 | /* timer10 */ |
329 | static struct omap_hwmod omap3xxx_timer10_hwmod = { | |
330 | .name = "timer10", | |
331 | .mpu_irqs = omap2_timer10_mpu_irqs, | |
332 | .main_clk = "gpt10_fck", | |
333 | .prcm = { | |
4fe20e97 | 334 | .omap2 = { |
844a3b63 PW |
335 | .prcm_reg_id = 1, |
336 | .module_bit = OMAP3430_EN_GPT10_SHIFT, | |
337 | .module_offs = CORE_MOD, | |
338 | .idlest_reg_id = 1, | |
339 | .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, | |
340 | }, | |
4fe20e97 | 341 | }, |
844a3b63 PW |
342 | .dev_attr = &capability_pwm_dev_attr, |
343 | .class = &omap3xxx_timer_1ms_hwmod_class, | |
4fe20e97 RN |
344 | }; |
345 | ||
844a3b63 PW |
346 | /* timer11 */ |
347 | static struct omap_hwmod omap3xxx_timer11_hwmod = { | |
348 | .name = "timer11", | |
349 | .mpu_irqs = omap2_timer11_mpu_irqs, | |
350 | .main_clk = "gpt11_fck", | |
351 | .prcm = { | |
352 | .omap2 = { | |
353 | .prcm_reg_id = 1, | |
354 | .module_bit = OMAP3430_EN_GPT11_SHIFT, | |
355 | .module_offs = CORE_MOD, | |
356 | .idlest_reg_id = 1, | |
357 | .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, | |
358 | }, | |
359 | }, | |
360 | .dev_attr = &capability_pwm_dev_attr, | |
361 | .class = &omap3xxx_timer_hwmod_class, | |
d62bc78a NM |
362 | }; |
363 | ||
844a3b63 PW |
364 | /* timer12 */ |
365 | static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { | |
366 | { .irq = 95, }, | |
d62bc78a NM |
367 | { .irq = -1 } |
368 | }; | |
369 | ||
844a3b63 PW |
370 | static struct omap_hwmod omap3xxx_timer12_hwmod = { |
371 | .name = "timer12", | |
372 | .mpu_irqs = omap3xxx_timer12_mpu_irqs, | |
373 | .main_clk = "gpt12_fck", | |
374 | .prcm = { | |
375 | .omap2 = { | |
376 | .prcm_reg_id = 1, | |
377 | .module_bit = OMAP3430_EN_GPT12_SHIFT, | |
378 | .module_offs = WKUP_MOD, | |
379 | .idlest_reg_id = 1, | |
380 | .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, | |
381 | }, | |
d3442726 | 382 | }, |
844a3b63 PW |
383 | .dev_attr = &capability_secure_dev_attr, |
384 | .class = &omap3xxx_timer_hwmod_class, | |
d3442726 TG |
385 | }; |
386 | ||
844a3b63 PW |
387 | /* |
388 | * 'wd_timer' class | |
389 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
390 | * overflow condition | |
391 | */ | |
392 | ||
393 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
394 | .rev_offs = 0x0000, | |
395 | .sysc_offs = 0x0010, | |
396 | .syss_offs = 0x0014, | |
397 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
398 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
399 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | | |
400 | SYSS_HAS_RESET_STATUS), | |
401 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
402 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
403 | }; |
404 | ||
844a3b63 PW |
405 | /* I2C common */ |
406 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
407 | .rev_offs = 0x00, | |
408 | .sysc_offs = 0x20, | |
409 | .syss_offs = 0x10, | |
410 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
411 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
412 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
413 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
414 | .clockact = CLOCKACT_TEST_ICLK, | |
415 | .sysc_fields = &omap_hwmod_sysc_type1, | |
d3442726 TG |
416 | }; |
417 | ||
844a3b63 PW |
418 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
419 | .name = "wd_timer", | |
420 | .sysc = &omap3xxx_wd_timer_sysc, | |
414e4128 KH |
421 | .pre_shutdown = &omap2_wd_timer_disable, |
422 | .reset = &omap2_wd_timer_reset, | |
d3442726 TG |
423 | }; |
424 | ||
844a3b63 PW |
425 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { |
426 | .name = "wd_timer2", | |
427 | .class = &omap3xxx_wd_timer_hwmod_class, | |
428 | .main_clk = "wdt2_fck", | |
429 | .prcm = { | |
430 | .omap2 = { | |
431 | .prcm_reg_id = 1, | |
432 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
433 | .module_offs = WKUP_MOD, | |
434 | .idlest_reg_id = 1, | |
435 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
436 | }, | |
437 | }, | |
438 | /* | |
439 | * XXX: Use software supervised mode, HW supervised smartidle seems to | |
440 | * block CORE power domain idle transitions. Maybe a HW bug in wdt2? | |
441 | */ | |
442 | .flags = HWMOD_SWSUP_SIDLE, | |
443 | }; | |
870ea2b8 | 444 | |
844a3b63 PW |
445 | /* UART1 */ |
446 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
447 | .name = "uart1", | |
448 | .mpu_irqs = omap2_uart1_mpu_irqs, | |
449 | .sdma_reqs = omap2_uart1_sdma_reqs, | |
450 | .main_clk = "uart1_fck", | |
451 | .prcm = { | |
452 | .omap2 = { | |
453 | .module_offs = CORE_MOD, | |
454 | .prcm_reg_id = 1, | |
455 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
456 | .idlest_reg_id = 1, | |
457 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
458 | }, | |
870ea2b8 | 459 | }, |
844a3b63 | 460 | .class = &omap2_uart_class, |
870ea2b8 HH |
461 | }; |
462 | ||
844a3b63 PW |
463 | /* UART2 */ |
464 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
465 | .name = "uart2", | |
466 | .mpu_irqs = omap2_uart2_mpu_irqs, | |
467 | .sdma_reqs = omap2_uart2_sdma_reqs, | |
468 | .main_clk = "uart2_fck", | |
469 | .prcm = { | |
470 | .omap2 = { | |
471 | .module_offs = CORE_MOD, | |
472 | .prcm_reg_id = 1, | |
473 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
474 | .idlest_reg_id = 1, | |
475 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
476 | }, | |
477 | }, | |
478 | .class = &omap2_uart_class, | |
870ea2b8 HH |
479 | }; |
480 | ||
844a3b63 PW |
481 | /* UART3 */ |
482 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
483 | .name = "uart3", | |
484 | .mpu_irqs = omap2_uart3_mpu_irqs, | |
485 | .sdma_reqs = omap2_uart3_sdma_reqs, | |
486 | .main_clk = "uart3_fck", | |
487 | .prcm = { | |
488 | .omap2 = { | |
489 | .module_offs = OMAP3430_PER_MOD, | |
490 | .prcm_reg_id = 1, | |
491 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
492 | .idlest_reg_id = 1, | |
493 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
494 | }, | |
273ff8c3 | 495 | }, |
844a3b63 | 496 | .class = &omap2_uart_class, |
273ff8c3 HH |
497 | }; |
498 | ||
844a3b63 PW |
499 | /* UART4 */ |
500 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
501 | { .irq = INT_36XX_UART4_IRQ, }, | |
502 | { .irq = -1 } | |
273ff8c3 HH |
503 | }; |
504 | ||
844a3b63 PW |
505 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { |
506 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
507 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
508 | { .dma_req = -1 } | |
7359154e PW |
509 | }; |
510 | ||
844a3b63 PW |
511 | static struct omap_hwmod omap36xx_uart4_hwmod = { |
512 | .name = "uart4", | |
513 | .mpu_irqs = uart4_mpu_irqs, | |
514 | .sdma_reqs = uart4_sdma_reqs, | |
515 | .main_clk = "uart4_fck", | |
516 | .prcm = { | |
517 | .omap2 = { | |
518 | .module_offs = OMAP3430_PER_MOD, | |
519 | .prcm_reg_id = 1, | |
520 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
521 | .idlest_reg_id = 1, | |
522 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
523 | }, | |
524 | }, | |
525 | .class = &omap2_uart_class, | |
7359154e PW |
526 | }; |
527 | ||
844a3b63 PW |
528 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
529 | { .irq = INT_35XX_UART4_IRQ, }, | |
bf765237 | 530 | { .irq = -1 } |
43085705 PW |
531 | }; |
532 | ||
844a3b63 PW |
533 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
534 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | |
535 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | |
bf765237 | 536 | { .dma_req = -1 } |
7359154e PW |
537 | }; |
538 | ||
844a3b63 PW |
539 | static struct omap_hwmod am35xx_uart4_hwmod = { |
540 | .name = "uart4", | |
541 | .mpu_irqs = am35xx_uart4_mpu_irqs, | |
542 | .sdma_reqs = am35xx_uart4_sdma_reqs, | |
543 | .main_clk = "uart4_fck", | |
544 | .prcm = { | |
545 | .omap2 = { | |
546 | .module_offs = CORE_MOD, | |
547 | .prcm_reg_id = 1, | |
bf765237 | 548 | .module_bit = AM35XX_EN_UART4_SHIFT, |
844a3b63 | 549 | .idlest_reg_id = 1, |
bf765237 | 550 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
844a3b63 PW |
551 | }, |
552 | }, | |
553 | .class = &omap2_uart_class, | |
554 | }; | |
555 | ||
556 | static struct omap_hwmod_class i2c_class = { | |
557 | .name = "i2c", | |
558 | .sysc = &i2c_sysc, | |
559 | .rev = OMAP_I2C_IP_VERSION_1, | |
560 | .reset = &omap_i2c_reset, | |
561 | }; | |
562 | ||
563 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
564 | { .name = "dispc", .dma_req = 5 }, | |
565 | { .name = "dsi1", .dma_req = 74 }, | |
566 | { .dma_req = -1 } | |
43085705 PW |
567 | }; |
568 | ||
844a3b63 PW |
569 | /* dss */ |
570 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
571 | /* | |
572 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core | |
573 | * driver does not use these clocks. | |
574 | */ | |
575 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
576 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
577 | /* required only on OMAP3430 */ | |
578 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
7359154e PW |
579 | }; |
580 | ||
844a3b63 PW |
581 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { |
582 | .name = "dss_core", | |
583 | .class = &omap2_dss_hwmod_class, | |
584 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
585 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
586 | .prcm = { | |
587 | .omap2 = { | |
588 | .prcm_reg_id = 1, | |
589 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
590 | .module_offs = OMAP3430_DSS_MOD, | |
591 | .idlest_reg_id = 1, | |
592 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
593 | }, | |
594 | }, | |
595 | .opt_clks = dss_opt_clks, | |
596 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
597 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
598 | }; | |
540064bf | 599 | |
844a3b63 PW |
600 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { |
601 | .name = "dss_core", | |
602 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
603 | .class = &omap2_dss_hwmod_class, | |
604 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
605 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
606 | .prcm = { | |
607 | .omap2 = { | |
608 | .prcm_reg_id = 1, | |
609 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
610 | .module_offs = OMAP3430_DSS_MOD, | |
611 | .idlest_reg_id = 1, | |
612 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
613 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
614 | }, | |
615 | }, | |
616 | .opt_clks = dss_opt_clks, | |
617 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
540064bf KH |
618 | }; |
619 | ||
540064bf | 620 | /* |
844a3b63 PW |
621 | * 'dispc' class |
622 | * display controller | |
540064bf KH |
623 | */ |
624 | ||
844a3b63 | 625 | static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { |
ce722d26 TG |
626 | .rev_offs = 0x0000, |
627 | .sysc_offs = 0x0010, | |
628 | .syss_offs = 0x0014, | |
844a3b63 PW |
629 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
630 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
631 | SYSC_HAS_ENAWAKEUP), | |
632 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
633 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
ce722d26 | 634 | .sysc_fields = &omap_hwmod_sysc_type1, |
6b667f88 VC |
635 | }; |
636 | ||
844a3b63 PW |
637 | static struct omap_hwmod_class omap3_dispc_hwmod_class = { |
638 | .name = "dispc", | |
639 | .sysc = &omap3_dispc_sysc, | |
6b667f88 VC |
640 | }; |
641 | ||
844a3b63 PW |
642 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { |
643 | .name = "dss_dispc", | |
644 | .class = &omap3_dispc_hwmod_class, | |
645 | .mpu_irqs = omap2_dispc_irqs, | |
646 | .main_clk = "dss1_alwon_fck", | |
647 | .prcm = { | |
648 | .omap2 = { | |
649 | .prcm_reg_id = 1, | |
650 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
651 | .module_offs = OMAP3430_DSS_MOD, | |
652 | }, | |
653 | }, | |
654 | .flags = HWMOD_NO_IDLEST, | |
655 | .dev_attr = &omap2_3_dss_dispc_dev_attr | |
6b667f88 VC |
656 | }; |
657 | ||
844a3b63 PW |
658 | /* |
659 | * 'dsi' class | |
660 | * display serial interface controller | |
661 | */ | |
4fe20e97 | 662 | |
844a3b63 PW |
663 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { |
664 | .name = "dsi", | |
c345c8b0 TKD |
665 | }; |
666 | ||
844a3b63 PW |
667 | static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { |
668 | { .irq = 25 }, | |
669 | { .irq = -1 } | |
c345c8b0 TKD |
670 | }; |
671 | ||
844a3b63 PW |
672 | /* dss_dsi1 */ |
673 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { | |
674 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
c345c8b0 TKD |
675 | }; |
676 | ||
844a3b63 PW |
677 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { |
678 | .name = "dss_dsi1", | |
679 | .class = &omap3xxx_dsi_hwmod_class, | |
680 | .mpu_irqs = omap3xxx_dsi1_irqs, | |
681 | .main_clk = "dss1_alwon_fck", | |
682 | .prcm = { | |
683 | .omap2 = { | |
684 | .prcm_reg_id = 1, | |
685 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
686 | .module_offs = OMAP3430_DSS_MOD, | |
687 | }, | |
ce722d26 | 688 | }, |
844a3b63 PW |
689 | .opt_clks = dss_dsi1_opt_clks, |
690 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | |
691 | .flags = HWMOD_NO_IDLEST, | |
6b667f88 VC |
692 | }; |
693 | ||
844a3b63 PW |
694 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
695 | { .role = "ick", .clk = "dss_ick" }, | |
ce722d26 TG |
696 | }; |
697 | ||
844a3b63 PW |
698 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { |
699 | .name = "dss_rfbi", | |
700 | .class = &omap2_rfbi_hwmod_class, | |
701 | .main_clk = "dss1_alwon_fck", | |
6b667f88 VC |
702 | .prcm = { |
703 | .omap2 = { | |
704 | .prcm_reg_id = 1, | |
844a3b63 PW |
705 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
706 | .module_offs = OMAP3430_DSS_MOD, | |
6b667f88 VC |
707 | }, |
708 | }, | |
844a3b63 PW |
709 | .opt_clks = dss_rfbi_opt_clks, |
710 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | |
711 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
712 | }; |
713 | ||
844a3b63 PW |
714 | static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { |
715 | /* required only on OMAP3430 */ | |
716 | { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, | |
046465b7 KH |
717 | }; |
718 | ||
844a3b63 PW |
719 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { |
720 | .name = "dss_venc", | |
721 | .class = &omap2_venc_hwmod_class, | |
722 | .main_clk = "dss_tv_fck", | |
046465b7 KH |
723 | .prcm = { |
724 | .omap2 = { | |
046465b7 | 725 | .prcm_reg_id = 1, |
844a3b63 PW |
726 | .module_bit = OMAP3430_EN_DSS1_SHIFT, |
727 | .module_offs = OMAP3430_DSS_MOD, | |
046465b7 KH |
728 | }, |
729 | }, | |
844a3b63 PW |
730 | .opt_clks = dss_venc_opt_clks, |
731 | .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), | |
732 | .flags = HWMOD_NO_IDLEST, | |
046465b7 KH |
733 | }; |
734 | ||
844a3b63 PW |
735 | /* I2C1 */ |
736 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
737 | .fifo_depth = 8, /* bytes */ | |
738 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
739 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
740 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
741 | }; |
742 | ||
844a3b63 PW |
743 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { |
744 | .name = "i2c1", | |
745 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
746 | .mpu_irqs = omap2_i2c1_mpu_irqs, | |
747 | .sdma_reqs = omap2_i2c1_sdma_reqs, | |
748 | .main_clk = "i2c1_fck", | |
046465b7 KH |
749 | .prcm = { |
750 | .omap2 = { | |
844a3b63 | 751 | .module_offs = CORE_MOD, |
046465b7 | 752 | .prcm_reg_id = 1, |
844a3b63 | 753 | .module_bit = OMAP3430_EN_I2C1_SHIFT, |
046465b7 | 754 | .idlest_reg_id = 1, |
844a3b63 | 755 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, |
046465b7 KH |
756 | }, |
757 | }, | |
844a3b63 PW |
758 | .class = &i2c_class, |
759 | .dev_attr = &i2c1_dev_attr, | |
046465b7 KH |
760 | }; |
761 | ||
844a3b63 PW |
762 | /* I2C2 */ |
763 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
764 | .fifo_depth = 8, /* bytes */ | |
765 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
766 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
767 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
046465b7 KH |
768 | }; |
769 | ||
844a3b63 PW |
770 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { |
771 | .name = "i2c2", | |
772 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
773 | .mpu_irqs = omap2_i2c2_mpu_irqs, | |
774 | .sdma_reqs = omap2_i2c2_sdma_reqs, | |
775 | .main_clk = "i2c2_fck", | |
046465b7 KH |
776 | .prcm = { |
777 | .omap2 = { | |
844a3b63 | 778 | .module_offs = CORE_MOD, |
046465b7 | 779 | .prcm_reg_id = 1, |
844a3b63 | 780 | .module_bit = OMAP3430_EN_I2C2_SHIFT, |
046465b7 | 781 | .idlest_reg_id = 1, |
844a3b63 | 782 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, |
046465b7 KH |
783 | }, |
784 | }, | |
844a3b63 PW |
785 | .class = &i2c_class, |
786 | .dev_attr = &i2c2_dev_attr, | |
046465b7 KH |
787 | }; |
788 | ||
844a3b63 PW |
789 | /* I2C3 */ |
790 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
791 | .fifo_depth = 64, /* bytes */ | |
792 | .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | | |
793 | OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | | |
794 | OMAP_I2C_FLAG_BUS_SHIFT_2, | |
795 | }; | |
046465b7 | 796 | |
844a3b63 PW |
797 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { |
798 | { .irq = INT_34XX_I2C3_IRQ, }, | |
799 | { .irq = -1 } | |
046465b7 KH |
800 | }; |
801 | ||
844a3b63 PW |
802 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { |
803 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
804 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
805 | { .dma_req = -1 } | |
046465b7 KH |
806 | }; |
807 | ||
844a3b63 PW |
808 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { |
809 | .name = "i2c3", | |
810 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | |
811 | .mpu_irqs = i2c3_mpu_irqs, | |
812 | .sdma_reqs = i2c3_sdma_reqs, | |
813 | .main_clk = "i2c3_fck", | |
046465b7 KH |
814 | .prcm = { |
815 | .omap2 = { | |
844a3b63 | 816 | .module_offs = CORE_MOD, |
046465b7 | 817 | .prcm_reg_id = 1, |
844a3b63 | 818 | .module_bit = OMAP3430_EN_I2C3_SHIFT, |
046465b7 | 819 | .idlest_reg_id = 1, |
844a3b63 | 820 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, |
046465b7 KH |
821 | }, |
822 | }, | |
844a3b63 PW |
823 | .class = &i2c_class, |
824 | .dev_attr = &i2c3_dev_attr, | |
4fe20e97 RN |
825 | }; |
826 | ||
844a3b63 PW |
827 | /* |
828 | * 'gpio' class | |
829 | * general purpose io module | |
830 | */ | |
4fe20e97 | 831 | |
844a3b63 PW |
832 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { |
833 | .rev_offs = 0x0000, | |
834 | .sysc_offs = 0x0010, | |
835 | .syss_offs = 0x0014, | |
836 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
837 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | | |
838 | SYSS_HAS_RESET_STATUS), | |
839 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
840 | .sysc_fields = &omap_hwmod_sysc_type1, | |
4fe20e97 RN |
841 | }; |
842 | ||
844a3b63 PW |
843 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { |
844 | .name = "gpio", | |
845 | .sysc = &omap3xxx_gpio_sysc, | |
846 | .rev = 1, | |
4fe20e97 RN |
847 | }; |
848 | ||
844a3b63 PW |
849 | /* gpio_dev_attr */ |
850 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
851 | .bank_width = 32, | |
852 | .dbck_flag = true, | |
853 | }; | |
854 | ||
855 | /* gpio1 */ | |
856 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
857 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
858 | }; | |
859 | ||
860 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
861 | .name = "gpio1", | |
862 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
863 | .mpu_irqs = omap2_gpio1_irqs, | |
864 | .main_clk = "gpio1_ick", | |
865 | .opt_clks = gpio1_opt_clks, | |
866 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
4fe20e97 RN |
867 | .prcm = { |
868 | .omap2 = { | |
4fe20e97 | 869 | .prcm_reg_id = 1, |
844a3b63 PW |
870 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, |
871 | .module_offs = WKUP_MOD, | |
4fe20e97 | 872 | .idlest_reg_id = 1, |
844a3b63 | 873 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, |
4fe20e97 RN |
874 | }, |
875 | }, | |
844a3b63 PW |
876 | .class = &omap3xxx_gpio_hwmod_class, |
877 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
878 | }; |
879 | ||
844a3b63 PW |
880 | /* gpio2 */ |
881 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
882 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
4fe20e97 RN |
883 | }; |
884 | ||
844a3b63 PW |
885 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { |
886 | .name = "gpio2", | |
887 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
888 | .mpu_irqs = omap2_gpio2_irqs, | |
889 | .main_clk = "gpio2_ick", | |
890 | .opt_clks = gpio2_opt_clks, | |
891 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
4fe20e97 RN |
892 | .prcm = { |
893 | .omap2 = { | |
4fe20e97 | 894 | .prcm_reg_id = 1, |
844a3b63 | 895 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, |
ce722d26 | 896 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 897 | .idlest_reg_id = 1, |
844a3b63 | 898 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, |
4fe20e97 RN |
899 | }, |
900 | }, | |
844a3b63 PW |
901 | .class = &omap3xxx_gpio_hwmod_class, |
902 | .dev_attr = &gpio_dev_attr, | |
4fe20e97 RN |
903 | }; |
904 | ||
844a3b63 PW |
905 | /* gpio3 */ |
906 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
907 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
4fe20e97 RN |
908 | }; |
909 | ||
844a3b63 PW |
910 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { |
911 | .name = "gpio3", | |
912 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
913 | .mpu_irqs = omap2_gpio3_irqs, | |
914 | .main_clk = "gpio3_ick", | |
915 | .opt_clks = gpio3_opt_clks, | |
916 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
4fe20e97 RN |
917 | .prcm = { |
918 | .omap2 = { | |
4fe20e97 | 919 | .prcm_reg_id = 1, |
844a3b63 | 920 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, |
ce722d26 | 921 | .module_offs = OMAP3430_PER_MOD, |
4fe20e97 | 922 | .idlest_reg_id = 1, |
844a3b63 | 923 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, |
4fe20e97 RN |
924 | }, |
925 | }, | |
844a3b63 PW |
926 | .class = &omap3xxx_gpio_hwmod_class, |
927 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
928 | }; |
929 | ||
844a3b63 PW |
930 | /* gpio4 */ |
931 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
932 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
70034d38 VC |
933 | }; |
934 | ||
844a3b63 PW |
935 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { |
936 | .name = "gpio4", | |
937 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
938 | .mpu_irqs = omap2_gpio4_irqs, | |
939 | .main_clk = "gpio4_ick", | |
940 | .opt_clks = gpio4_opt_clks, | |
941 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
ce722d26 TG |
942 | .prcm = { |
943 | .omap2 = { | |
944 | .prcm_reg_id = 1, | |
844a3b63 | 945 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, |
ce722d26 TG |
946 | .module_offs = OMAP3430_PER_MOD, |
947 | .idlest_reg_id = 1, | |
844a3b63 | 948 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, |
ce722d26 | 949 | }, |
70034d38 | 950 | }, |
844a3b63 PW |
951 | .class = &omap3xxx_gpio_hwmod_class, |
952 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
953 | }; |
954 | ||
844a3b63 PW |
955 | /* gpio5 */ |
956 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
957 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
958 | { .irq = -1 } | |
959 | }; | |
70034d38 | 960 | |
844a3b63 PW |
961 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
962 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
70034d38 VC |
963 | }; |
964 | ||
844a3b63 PW |
965 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { |
966 | .name = "gpio5", | |
967 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
968 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
969 | .main_clk = "gpio5_ick", | |
970 | .opt_clks = gpio5_opt_clks, | |
971 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
ce722d26 TG |
972 | .prcm = { |
973 | .omap2 = { | |
974 | .prcm_reg_id = 1, | |
844a3b63 PW |
975 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, |
976 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 977 | .idlest_reg_id = 1, |
844a3b63 | 978 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, |
ce722d26 | 979 | }, |
70034d38 | 980 | }, |
844a3b63 PW |
981 | .class = &omap3xxx_gpio_hwmod_class, |
982 | .dev_attr = &gpio_dev_attr, | |
70034d38 VC |
983 | }; |
984 | ||
844a3b63 PW |
985 | /* gpio6 */ |
986 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
987 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
988 | { .irq = -1 } | |
989 | }; | |
70034d38 | 990 | |
844a3b63 PW |
991 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
992 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
70034d38 VC |
993 | }; |
994 | ||
844a3b63 PW |
995 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { |
996 | .name = "gpio6", | |
997 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | |
998 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
999 | .main_clk = "gpio6_ick", | |
1000 | .opt_clks = gpio6_opt_clks, | |
1001 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
ce722d26 TG |
1002 | .prcm = { |
1003 | .omap2 = { | |
1004 | .prcm_reg_id = 1, | |
844a3b63 PW |
1005 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, |
1006 | .module_offs = OMAP3430_PER_MOD, | |
ce722d26 | 1007 | .idlest_reg_id = 1, |
844a3b63 | 1008 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, |
ce722d26 TG |
1009 | }, |
1010 | }, | |
844a3b63 PW |
1011 | .class = &omap3xxx_gpio_hwmod_class, |
1012 | .dev_attr = &gpio_dev_attr, | |
ce722d26 TG |
1013 | }; |
1014 | ||
844a3b63 PW |
1015 | /* dma attributes */ |
1016 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1017 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1018 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1019 | .lch_count = 32, | |
ce722d26 TG |
1020 | }; |
1021 | ||
844a3b63 PW |
1022 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { |
1023 | .rev_offs = 0x0000, | |
1024 | .sysc_offs = 0x002c, | |
1025 | .syss_offs = 0x0028, | |
1026 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1027 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1028 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | | |
1029 | SYSS_HAS_RESET_STATUS), | |
1030 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1031 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1032 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1033 | }; |
1034 | ||
844a3b63 PW |
1035 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { |
1036 | .name = "dma", | |
1037 | .sysc = &omap3xxx_dma_sysc, | |
70034d38 VC |
1038 | }; |
1039 | ||
844a3b63 PW |
1040 | /* dma_system */ |
1041 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1042 | .name = "dma", | |
1043 | .class = &omap3xxx_dma_hwmod_class, | |
1044 | .mpu_irqs = omap2_dma_system_irqs, | |
1045 | .main_clk = "core_l3_ick", | |
1046 | .prcm = { | |
ce722d26 | 1047 | .omap2 = { |
844a3b63 PW |
1048 | .module_offs = CORE_MOD, |
1049 | .prcm_reg_id = 1, | |
1050 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1051 | .idlest_reg_id = 1, | |
1052 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
ce722d26 TG |
1053 | }, |
1054 | }, | |
844a3b63 PW |
1055 | .dev_attr = &dma_dev_attr, |
1056 | .flags = HWMOD_NO_IDLEST, | |
70034d38 VC |
1057 | }; |
1058 | ||
844a3b63 PW |
1059 | /* |
1060 | * 'mcbsp' class | |
1061 | * multi channel buffered serial port controller | |
1062 | */ | |
1063 | ||
1064 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { | |
1065 | .sysc_offs = 0x008c, | |
1066 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | | |
1067 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), | |
1068 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1069 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1070 | .clockact = 0x2, | |
70034d38 VC |
1071 | }; |
1072 | ||
844a3b63 PW |
1073 | static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { |
1074 | .name = "mcbsp", | |
1075 | .sysc = &omap3xxx_mcbsp_sysc, | |
1076 | .rev = MCBSP_CONFIG_TYPE3, | |
70034d38 VC |
1077 | }; |
1078 | ||
844a3b63 PW |
1079 | /* mcbsp1 */ |
1080 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | |
1c2badc1 | 1081 | { .name = "common", .irq = 16 }, |
844a3b63 PW |
1082 | { .name = "tx", .irq = 59 }, |
1083 | { .name = "rx", .irq = 60 }, | |
1084 | { .irq = -1 } | |
1085 | }; | |
6b667f88 | 1086 | |
844a3b63 PW |
1087 | static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { |
1088 | .name = "mcbsp1", | |
1089 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1090 | .mpu_irqs = omap3xxx_mcbsp1_irqs, | |
1091 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, | |
1092 | .main_clk = "mcbsp1_fck", | |
1093 | .prcm = { | |
1094 | .omap2 = { | |
1095 | .prcm_reg_id = 1, | |
1096 | .module_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1097 | .module_offs = CORE_MOD, | |
1098 | .idlest_reg_id = 1, | |
1099 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | |
1100 | }, | |
1101 | }, | |
70034d38 VC |
1102 | }; |
1103 | ||
844a3b63 PW |
1104 | /* mcbsp2 */ |
1105 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { | |
1c2badc1 | 1106 | { .name = "common", .irq = 17 }, |
844a3b63 PW |
1107 | { .name = "tx", .irq = 62 }, |
1108 | { .name = "rx", .irq = 63 }, | |
1109 | { .irq = -1 } | |
70034d38 VC |
1110 | }; |
1111 | ||
844a3b63 PW |
1112 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { |
1113 | .sidetone = "mcbsp2_sidetone", | |
70034d38 VC |
1114 | }; |
1115 | ||
844a3b63 PW |
1116 | static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { |
1117 | .name = "mcbsp2", | |
1118 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1119 | .mpu_irqs = omap3xxx_mcbsp2_irqs, | |
1120 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, | |
1121 | .main_clk = "mcbsp2_fck", | |
70034d38 VC |
1122 | .prcm = { |
1123 | .omap2 = { | |
1124 | .prcm_reg_id = 1, | |
844a3b63 PW |
1125 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1126 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1127 | .idlest_reg_id = 1, |
844a3b63 | 1128 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
70034d38 VC |
1129 | }, |
1130 | }, | |
844a3b63 | 1131 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
70034d38 VC |
1132 | }; |
1133 | ||
844a3b63 PW |
1134 | /* mcbsp3 */ |
1135 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { | |
1c2badc1 | 1136 | { .name = "common", .irq = 22 }, |
844a3b63 PW |
1137 | { .name = "tx", .irq = 89 }, |
1138 | { .name = "rx", .irq = 90 }, | |
1139 | { .irq = -1 } | |
1140 | }; | |
1141 | ||
1142 | static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { | |
1143 | .sidetone = "mcbsp3_sidetone", | |
1144 | }; | |
1145 | ||
1146 | static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |
1147 | .name = "mcbsp3", | |
1148 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1149 | .mpu_irqs = omap3xxx_mcbsp3_irqs, | |
1150 | .sdma_reqs = omap2_mcbsp3_sdma_reqs, | |
1151 | .main_clk = "mcbsp3_fck", | |
70034d38 VC |
1152 | .prcm = { |
1153 | .omap2 = { | |
1154 | .prcm_reg_id = 1, | |
844a3b63 PW |
1155 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1156 | .module_offs = OMAP3430_PER_MOD, | |
70034d38 | 1157 | .idlest_reg_id = 1, |
844a3b63 | 1158 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
70034d38 VC |
1159 | }, |
1160 | }, | |
844a3b63 | 1161 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
70034d38 VC |
1162 | }; |
1163 | ||
844a3b63 PW |
1164 | /* mcbsp4 */ |
1165 | static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { | |
1c2badc1 | 1166 | { .name = "common", .irq = 23 }, |
844a3b63 PW |
1167 | { .name = "tx", .irq = 54 }, |
1168 | { .name = "rx", .irq = 55 }, | |
1169 | { .irq = -1 } | |
1170 | }; | |
1171 | ||
1172 | static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { | |
1173 | { .name = "rx", .dma_req = 20 }, | |
1174 | { .name = "tx", .dma_req = 19 }, | |
1175 | { .dma_req = -1 } | |
1176 | }; | |
1177 | ||
1178 | static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |
1179 | .name = "mcbsp4", | |
1180 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1181 | .mpu_irqs = omap3xxx_mcbsp4_irqs, | |
1182 | .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, | |
1183 | .main_clk = "mcbsp4_fck", | |
70034d38 VC |
1184 | .prcm = { |
1185 | .omap2 = { | |
1186 | .prcm_reg_id = 1, | |
844a3b63 PW |
1187 | .module_bit = OMAP3430_EN_MCBSP4_SHIFT, |
1188 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1189 | .idlest_reg_id = 1, |
844a3b63 | 1190 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
046465b7 KH |
1191 | }, |
1192 | }, | |
046465b7 KH |
1193 | }; |
1194 | ||
844a3b63 PW |
1195 | /* mcbsp5 */ |
1196 | static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { | |
1c2badc1 | 1197 | { .name = "common", .irq = 27 }, |
844a3b63 PW |
1198 | { .name = "tx", .irq = 81 }, |
1199 | { .name = "rx", .irq = 82 }, | |
1200 | { .irq = -1 } | |
1201 | }; | |
1202 | ||
1203 | static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { | |
1204 | { .name = "rx", .dma_req = 22 }, | |
1205 | { .name = "tx", .dma_req = 21 }, | |
1206 | { .dma_req = -1 } | |
1207 | }; | |
1208 | ||
1209 | static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |
1210 | .name = "mcbsp5", | |
1211 | .class = &omap3xxx_mcbsp_hwmod_class, | |
1212 | .mpu_irqs = omap3xxx_mcbsp5_irqs, | |
1213 | .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, | |
1214 | .main_clk = "mcbsp5_fck", | |
046465b7 KH |
1215 | .prcm = { |
1216 | .omap2 = { | |
046465b7 | 1217 | .prcm_reg_id = 1, |
844a3b63 PW |
1218 | .module_bit = OMAP3430_EN_MCBSP5_SHIFT, |
1219 | .module_offs = CORE_MOD, | |
70034d38 | 1220 | .idlest_reg_id = 1, |
844a3b63 | 1221 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
70034d38 VC |
1222 | }, |
1223 | }, | |
70034d38 VC |
1224 | }; |
1225 | ||
844a3b63 PW |
1226 | /* 'mcbsp sidetone' class */ |
1227 | static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { | |
1228 | .sysc_offs = 0x0010, | |
1229 | .sysc_flags = SYSC_HAS_AUTOIDLE, | |
1230 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1231 | }; | |
046465b7 | 1232 | |
844a3b63 PW |
1233 | static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { |
1234 | .name = "mcbsp_sidetone", | |
1235 | .sysc = &omap3xxx_mcbsp_sidetone_sysc, | |
70034d38 VC |
1236 | }; |
1237 | ||
844a3b63 PW |
1238 | /* mcbsp2_sidetone */ |
1239 | static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { | |
1240 | { .name = "irq", .irq = 4 }, | |
1241 | { .irq = -1 } | |
70034d38 VC |
1242 | }; |
1243 | ||
844a3b63 PW |
1244 | static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { |
1245 | .name = "mcbsp2_sidetone", | |
1246 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1247 | .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, | |
1248 | .main_clk = "mcbsp2_fck", | |
046465b7 KH |
1249 | .prcm = { |
1250 | .omap2 = { | |
046465b7 | 1251 | .prcm_reg_id = 1, |
844a3b63 PW |
1252 | .module_bit = OMAP3430_EN_MCBSP2_SHIFT, |
1253 | .module_offs = OMAP3430_PER_MOD, | |
046465b7 | 1254 | .idlest_reg_id = 1, |
844a3b63 | 1255 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
046465b7 KH |
1256 | }, |
1257 | }, | |
4bf90f65 KM |
1258 | }; |
1259 | ||
844a3b63 PW |
1260 | /* mcbsp3_sidetone */ |
1261 | static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { | |
1262 | { .name = "irq", .irq = 5 }, | |
1263 | { .irq = -1 } | |
4bf90f65 KM |
1264 | }; |
1265 | ||
844a3b63 PW |
1266 | static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { |
1267 | .name = "mcbsp3_sidetone", | |
1268 | .class = &omap3xxx_mcbsp_sidetone_hwmod_class, | |
1269 | .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, | |
1270 | .main_clk = "mcbsp3_fck", | |
0a78c5c5 | 1271 | .prcm = { |
4bf90f65 | 1272 | .omap2 = { |
4bf90f65 | 1273 | .prcm_reg_id = 1, |
844a3b63 PW |
1274 | .module_bit = OMAP3430_EN_MCBSP3_SHIFT, |
1275 | .module_offs = OMAP3430_PER_MOD, | |
4bf90f65 | 1276 | .idlest_reg_id = 1, |
844a3b63 | 1277 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
4bf90f65 KM |
1278 | }, |
1279 | }, | |
4bf90f65 KM |
1280 | }; |
1281 | ||
844a3b63 PW |
1282 | /* SR common */ |
1283 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1284 | .clkact_shift = 20, | |
1285 | }; | |
4bf90f65 | 1286 | |
844a3b63 PW |
1287 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { |
1288 | .sysc_offs = 0x24, | |
1289 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1290 | .clockact = CLOCKACT_TEST_ICLK, | |
1291 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
4fe20e97 RN |
1292 | }; |
1293 | ||
844a3b63 PW |
1294 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { |
1295 | .name = "smartreflex", | |
1296 | .sysc = &omap34xx_sr_sysc, | |
1297 | .rev = 1, | |
e04d9e1e SG |
1298 | }; |
1299 | ||
844a3b63 PW |
1300 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { |
1301 | .sidle_shift = 24, | |
1302 | .enwkup_shift = 26, | |
1303 | }; | |
e04d9e1e | 1304 | |
844a3b63 PW |
1305 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { |
1306 | .sysc_offs = 0x38, | |
1307 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1308 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1309 | SYSC_NO_CACHE), | |
1310 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1311 | }; | |
1312 | ||
1313 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1314 | .name = "smartreflex", | |
1315 | .sysc = &omap36xx_sr_sysc, | |
1316 | .rev = 2, | |
1317 | }; | |
1318 | ||
1319 | /* SR1 */ | |
1320 | static struct omap_smartreflex_dev_attr sr1_dev_attr = { | |
1321 | .sensor_voltdm_name = "mpu_iva", | |
1322 | }; | |
1323 | ||
1324 | static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { | |
1325 | { .irq = 18 }, | |
1326 | { .irq = -1 } | |
1327 | }; | |
1328 | ||
1329 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1330 | .name = "sr1", | |
1331 | .class = &omap34xx_smartreflex_hwmod_class, | |
1332 | .main_clk = "sr1_fck", | |
1333 | .prcm = { | |
e04d9e1e | 1334 | .omap2 = { |
844a3b63 PW |
1335 | .prcm_reg_id = 1, |
1336 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1337 | .module_offs = WKUP_MOD, | |
1338 | .idlest_reg_id = 1, | |
1339 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1340 | }, | |
e04d9e1e | 1341 | }, |
844a3b63 PW |
1342 | .dev_attr = &sr1_dev_attr, |
1343 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
1344 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1345 | }; |
1346 | ||
844a3b63 PW |
1347 | static struct omap_hwmod omap36xx_sr1_hwmod = { |
1348 | .name = "sr1", | |
1349 | .class = &omap36xx_smartreflex_hwmod_class, | |
1350 | .main_clk = "sr1_fck", | |
1351 | .prcm = { | |
e04d9e1e | 1352 | .omap2 = { |
844a3b63 PW |
1353 | .prcm_reg_id = 1, |
1354 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1355 | .module_offs = WKUP_MOD, | |
1356 | .idlest_reg_id = 1, | |
1357 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1358 | }, | |
e04d9e1e | 1359 | }, |
844a3b63 PW |
1360 | .dev_attr = &sr1_dev_attr, |
1361 | .mpu_irqs = omap3_smartreflex_mpu_irqs, | |
e04d9e1e SG |
1362 | }; |
1363 | ||
844a3b63 PW |
1364 | /* SR2 */ |
1365 | static struct omap_smartreflex_dev_attr sr2_dev_attr = { | |
1366 | .sensor_voltdm_name = "core", | |
e04d9e1e SG |
1367 | }; |
1368 | ||
844a3b63 PW |
1369 | static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { |
1370 | { .irq = 19 }, | |
1371 | { .irq = -1 } | |
1372 | }; | |
1373 | ||
1374 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1375 | .name = "sr2", | |
1376 | .class = &omap34xx_smartreflex_hwmod_class, | |
1377 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1378 | .prcm = { |
1379 | .omap2 = { | |
1380 | .prcm_reg_id = 1, | |
844a3b63 PW |
1381 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1382 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1383 | .idlest_reg_id = 1, |
844a3b63 | 1384 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1385 | }, |
1386 | }, | |
844a3b63 PW |
1387 | .dev_attr = &sr2_dev_attr, |
1388 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
1389 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
e04d9e1e SG |
1390 | }; |
1391 | ||
844a3b63 PW |
1392 | static struct omap_hwmod omap36xx_sr2_hwmod = { |
1393 | .name = "sr2", | |
1394 | .class = &omap36xx_smartreflex_hwmod_class, | |
1395 | .main_clk = "sr2_fck", | |
e04d9e1e SG |
1396 | .prcm = { |
1397 | .omap2 = { | |
1398 | .prcm_reg_id = 1, | |
844a3b63 PW |
1399 | .module_bit = OMAP3430_EN_SR2_SHIFT, |
1400 | .module_offs = WKUP_MOD, | |
e04d9e1e | 1401 | .idlest_reg_id = 1, |
844a3b63 | 1402 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, |
e04d9e1e SG |
1403 | }, |
1404 | }, | |
844a3b63 PW |
1405 | .dev_attr = &sr2_dev_attr, |
1406 | .mpu_irqs = omap3_smartreflex_core_irqs, | |
e04d9e1e SG |
1407 | }; |
1408 | ||
1ac6d46e | 1409 | /* |
844a3b63 PW |
1410 | * 'mailbox' class |
1411 | * mailbox module allowing communication between the on-chip processors | |
1412 | * using a queued mailbox-interrupt mechanism. | |
1ac6d46e TV |
1413 | */ |
1414 | ||
844a3b63 PW |
1415 | static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { |
1416 | .rev_offs = 0x000, | |
1417 | .sysc_offs = 0x010, | |
1418 | .syss_offs = 0x014, | |
1419 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1420 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1421 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1ac6d46e TV |
1422 | .sysc_fields = &omap_hwmod_sysc_type1, |
1423 | }; | |
1424 | ||
844a3b63 PW |
1425 | static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { |
1426 | .name = "mailbox", | |
1427 | .sysc = &omap3xxx_mailbox_sysc, | |
1ac6d46e TV |
1428 | }; |
1429 | ||
844a3b63 PW |
1430 | static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { |
1431 | { .irq = 26 }, | |
1432 | { .irq = -1 } | |
e04d9e1e SG |
1433 | }; |
1434 | ||
844a3b63 PW |
1435 | static struct omap_hwmod omap3xxx_mailbox_hwmod = { |
1436 | .name = "mailbox", | |
1437 | .class = &omap3xxx_mailbox_hwmod_class, | |
1438 | .mpu_irqs = omap3xxx_mailbox_irqs, | |
1439 | .main_clk = "mailboxes_ick", | |
e04d9e1e SG |
1440 | .prcm = { |
1441 | .omap2 = { | |
1442 | .prcm_reg_id = 1, | |
844a3b63 PW |
1443 | .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
1444 | .module_offs = CORE_MOD, | |
1445 | .idlest_reg_id = 1, | |
1446 | .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, | |
e04d9e1e SG |
1447 | }, |
1448 | }, | |
e04d9e1e SG |
1449 | }; |
1450 | ||
1451 | /* | |
844a3b63 PW |
1452 | * 'mcspi' class |
1453 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1454 | * bus | |
e04d9e1e SG |
1455 | */ |
1456 | ||
844a3b63 PW |
1457 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { |
1458 | .rev_offs = 0x0000, | |
1459 | .sysc_offs = 0x0010, | |
1460 | .syss_offs = 0x0014, | |
1461 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1462 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1463 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1464 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1465 | .sysc_fields = &omap_hwmod_sysc_type1, | |
e04d9e1e SG |
1466 | }; |
1467 | ||
844a3b63 PW |
1468 | static struct omap_hwmod_class omap34xx_mcspi_class = { |
1469 | .name = "mcspi", | |
1470 | .sysc = &omap34xx_mcspi_sysc, | |
1471 | .rev = OMAP3_MCSPI_REV, | |
affe360d AT |
1472 | }; |
1473 | ||
844a3b63 PW |
1474 | /* mcspi1 */ |
1475 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1476 | .num_chipselect = 4, | |
e04d9e1e SG |
1477 | }; |
1478 | ||
844a3b63 PW |
1479 | static struct omap_hwmod omap34xx_mcspi1 = { |
1480 | .name = "mcspi1", | |
1481 | .mpu_irqs = omap2_mcspi1_mpu_irqs, | |
1482 | .sdma_reqs = omap2_mcspi1_sdma_reqs, | |
1483 | .main_clk = "mcspi1_fck", | |
1484 | .prcm = { | |
e04d9e1e | 1485 | .omap2 = { |
844a3b63 PW |
1486 | .module_offs = CORE_MOD, |
1487 | .prcm_reg_id = 1, | |
1488 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1489 | .idlest_reg_id = 1, | |
1490 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1491 | }, | |
e04d9e1e | 1492 | }, |
844a3b63 PW |
1493 | .class = &omap34xx_mcspi_class, |
1494 | .dev_attr = &omap_mcspi1_dev_attr, | |
e04d9e1e SG |
1495 | }; |
1496 | ||
844a3b63 PW |
1497 | /* mcspi2 */ |
1498 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
1499 | .num_chipselect = 2, | |
6c3d7e34 TV |
1500 | }; |
1501 | ||
844a3b63 PW |
1502 | static struct omap_hwmod omap34xx_mcspi2 = { |
1503 | .name = "mcspi2", | |
1504 | .mpu_irqs = omap2_mcspi2_mpu_irqs, | |
1505 | .sdma_reqs = omap2_mcspi2_sdma_reqs, | |
1506 | .main_clk = "mcspi2_fck", | |
e04d9e1e SG |
1507 | .prcm = { |
1508 | .omap2 = { | |
844a3b63 | 1509 | .module_offs = CORE_MOD, |
e04d9e1e | 1510 | .prcm_reg_id = 1, |
844a3b63 PW |
1511 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, |
1512 | .idlest_reg_id = 1, | |
1513 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
e04d9e1e SG |
1514 | }, |
1515 | }, | |
844a3b63 PW |
1516 | .class = &omap34xx_mcspi_class, |
1517 | .dev_attr = &omap_mcspi2_dev_attr, | |
e04d9e1e SG |
1518 | }; |
1519 | ||
844a3b63 PW |
1520 | /* mcspi3 */ |
1521 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
1522 | { .name = "irq", .irq = 91 }, /* 91 */ | |
1523 | { .irq = -1 } | |
1524 | }; | |
1525 | ||
1526 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
1527 | { .name = "tx0", .dma_req = 15 }, | |
1528 | { .name = "rx0", .dma_req = 16 }, | |
1529 | { .name = "tx1", .dma_req = 23 }, | |
1530 | { .name = "rx1", .dma_req = 24 }, | |
1531 | { .dma_req = -1 } | |
e04d9e1e SG |
1532 | }; |
1533 | ||
844a3b63 PW |
1534 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { |
1535 | .num_chipselect = 2, | |
6c3d7e34 TV |
1536 | }; |
1537 | ||
844a3b63 PW |
1538 | static struct omap_hwmod omap34xx_mcspi3 = { |
1539 | .name = "mcspi3", | |
1540 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
1541 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
1542 | .main_clk = "mcspi3_fck", | |
e04d9e1e SG |
1543 | .prcm = { |
1544 | .omap2 = { | |
844a3b63 | 1545 | .module_offs = CORE_MOD, |
e04d9e1e | 1546 | .prcm_reg_id = 1, |
844a3b63 PW |
1547 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, |
1548 | .idlest_reg_id = 1, | |
1549 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
e04d9e1e SG |
1550 | }, |
1551 | }, | |
844a3b63 PW |
1552 | .class = &omap34xx_mcspi_class, |
1553 | .dev_attr = &omap_mcspi3_dev_attr, | |
e04d9e1e SG |
1554 | }; |
1555 | ||
844a3b63 PW |
1556 | /* mcspi4 */ |
1557 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
1558 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
1559 | { .irq = -1 } | |
e04d9e1e SG |
1560 | }; |
1561 | ||
844a3b63 PW |
1562 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { |
1563 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
1564 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
1565 | { .dma_req = -1 } | |
6c3d7e34 TV |
1566 | }; |
1567 | ||
844a3b63 PW |
1568 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { |
1569 | .num_chipselect = 1, | |
1570 | }; | |
1571 | ||
1572 | static struct omap_hwmod omap34xx_mcspi4 = { | |
1573 | .name = "mcspi4", | |
1574 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
1575 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
1576 | .main_clk = "mcspi4_fck", | |
e04d9e1e SG |
1577 | .prcm = { |
1578 | .omap2 = { | |
844a3b63 | 1579 | .module_offs = CORE_MOD, |
e04d9e1e | 1580 | .prcm_reg_id = 1, |
844a3b63 PW |
1581 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, |
1582 | .idlest_reg_id = 1, | |
1583 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
e04d9e1e SG |
1584 | }, |
1585 | }, | |
844a3b63 PW |
1586 | .class = &omap34xx_mcspi_class, |
1587 | .dev_attr = &omap_mcspi4_dev_attr, | |
e04d9e1e SG |
1588 | }; |
1589 | ||
844a3b63 PW |
1590 | /* usbhsotg */ |
1591 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
1592 | .rev_offs = 0x0400, | |
1593 | .sysc_offs = 0x0404, | |
1594 | .syss_offs = 0x0408, | |
1595 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
1596 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1597 | SYSC_HAS_AUTOIDLE), | |
1598 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1599 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1600 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1601 | }; | |
4fe20e97 | 1602 | |
844a3b63 PW |
1603 | static struct omap_hwmod_class usbotg_class = { |
1604 | .name = "usbotg", | |
1605 | .sysc = &omap3xxx_usbhsotg_sysc, | |
4fe20e97 RN |
1606 | }; |
1607 | ||
844a3b63 PW |
1608 | /* usb_otg_hs */ |
1609 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
1610 | ||
1611 | { .name = "mc", .irq = 92 }, | |
1612 | { .name = "dma", .irq = 93 }, | |
1613 | { .irq = -1 } | |
1614 | }; | |
1615 | ||
1616 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
1617 | .name = "usb_otg_hs", | |
1618 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
1619 | .main_clk = "hsotgusb_ick", | |
4fe20e97 RN |
1620 | .prcm = { |
1621 | .omap2 = { | |
4fe20e97 | 1622 | .prcm_reg_id = 1, |
844a3b63 PW |
1623 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
1624 | .module_offs = CORE_MOD, | |
4fe20e97 | 1625 | .idlest_reg_id = 1, |
844a3b63 PW |
1626 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, |
1627 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
4fe20e97 RN |
1628 | }, |
1629 | }, | |
844a3b63 PW |
1630 | .class = &usbotg_class, |
1631 | ||
1632 | /* | |
1633 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
1634 | * broken when autoidle is enabled | |
1635 | * workaround is to disable the autoidle bit at module level. | |
1636 | */ | |
1637 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
1638 | | HWMOD_SWSUP_MSTANDBY, | |
4fe20e97 RN |
1639 | }; |
1640 | ||
844a3b63 PW |
1641 | /* usb_otg_hs */ |
1642 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
844a3b63 PW |
1643 | { .name = "mc", .irq = 71 }, |
1644 | { .irq = -1 } | |
4fe20e97 RN |
1645 | }; |
1646 | ||
844a3b63 PW |
1647 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1648 | .name = "am35xx_usbotg", | |
844a3b63 PW |
1649 | }; |
1650 | ||
1651 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
1652 | .name = "am35x_otg_hs", | |
1653 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
89ea2583 | 1654 | .main_clk = "hsotgusb_fck", |
844a3b63 | 1655 | .class = &am35xx_usbotg_class, |
89ea2583 | 1656 | .flags = HWMOD_NO_IDLEST, |
4fe20e97 RN |
1657 | }; |
1658 | ||
844a3b63 PW |
1659 | /* MMC/SD/SDIO common */ |
1660 | static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { | |
1661 | .rev_offs = 0x1fc, | |
1662 | .sysc_offs = 0x10, | |
1663 | .syss_offs = 0x14, | |
1664 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1665 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1666 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1667 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1668 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1669 | }; | |
4fe20e97 | 1670 | |
844a3b63 PW |
1671 | static struct omap_hwmod_class omap34xx_mmc_class = { |
1672 | .name = "mmc", | |
1673 | .sysc = &omap34xx_mmc_sysc, | |
4fe20e97 RN |
1674 | }; |
1675 | ||
844a3b63 PW |
1676 | /* MMC/SD/SDIO1 */ |
1677 | ||
1678 | static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { | |
1679 | { .irq = 83, }, | |
212738a4 | 1680 | { .irq = -1 } |
4fe20e97 RN |
1681 | }; |
1682 | ||
844a3b63 PW |
1683 | static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { |
1684 | { .name = "tx", .dma_req = 61, }, | |
1685 | { .name = "rx", .dma_req = 62, }, | |
bc614958 | 1686 | { .dma_req = -1 } |
4fe20e97 RN |
1687 | }; |
1688 | ||
844a3b63 PW |
1689 | static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { |
1690 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
1691 | }; | |
1692 | ||
1693 | static struct omap_mmc_dev_attr mmc1_dev_attr = { | |
1694 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, | |
1695 | }; | |
1696 | ||
1697 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1698 | static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { | |
1699 | .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | | |
1700 | OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), | |
1701 | }; | |
1702 | ||
1703 | static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { | |
1704 | .name = "mmc1", | |
1705 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1706 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1707 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1708 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1709 | .main_clk = "mmchs1_fck", | |
4fe20e97 RN |
1710 | .prcm = { |
1711 | .omap2 = { | |
1712 | .module_offs = CORE_MOD, | |
1713 | .prcm_reg_id = 1, | |
844a3b63 | 1714 | .module_bit = OMAP3430_EN_MMC1_SHIFT, |
4fe20e97 | 1715 | .idlest_reg_id = 1, |
844a3b63 | 1716 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, |
4fe20e97 RN |
1717 | }, |
1718 | }, | |
844a3b63 PW |
1719 | .dev_attr = &mmc1_pre_es3_dev_attr, |
1720 | .class = &omap34xx_mmc_class, | |
4fe20e97 RN |
1721 | }; |
1722 | ||
844a3b63 PW |
1723 | static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { |
1724 | .name = "mmc1", | |
1725 | .mpu_irqs = omap34xx_mmc1_mpu_irqs, | |
1726 | .sdma_reqs = omap34xx_mmc1_sdma_reqs, | |
1727 | .opt_clks = omap34xx_mmc1_opt_clks, | |
1728 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), | |
1729 | .main_clk = "mmchs1_fck", | |
1730 | .prcm = { | |
1731 | .omap2 = { | |
1732 | .module_offs = CORE_MOD, | |
1733 | .prcm_reg_id = 1, | |
1734 | .module_bit = OMAP3430_EN_MMC1_SHIFT, | |
1735 | .idlest_reg_id = 1, | |
1736 | .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, | |
1737 | }, | |
70034d38 | 1738 | }, |
844a3b63 PW |
1739 | .dev_attr = &mmc1_dev_attr, |
1740 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1741 | }; |
1742 | ||
844a3b63 | 1743 | /* MMC/SD/SDIO2 */ |
70034d38 | 1744 | |
844a3b63 PW |
1745 | static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { |
1746 | { .irq = INT_24XX_MMC2_IRQ, }, | |
1747 | { .irq = -1 } | |
70034d38 VC |
1748 | }; |
1749 | ||
844a3b63 PW |
1750 | static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { |
1751 | { .name = "tx", .dma_req = 47, }, | |
1752 | { .name = "rx", .dma_req = 48, }, | |
1753 | { .dma_req = -1 } | |
70034d38 VC |
1754 | }; |
1755 | ||
844a3b63 PW |
1756 | static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { |
1757 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1758 | }; |
1759 | ||
844a3b63 PW |
1760 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ |
1761 | static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { | |
1762 | .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
70034d38 VC |
1763 | }; |
1764 | ||
844a3b63 PW |
1765 | static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { |
1766 | .name = "mmc2", | |
1767 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1768 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1769 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1770 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1771 | .main_clk = "mmchs2_fck", | |
1772 | .prcm = { | |
1773 | .omap2 = { | |
1774 | .module_offs = CORE_MOD, | |
1775 | .prcm_reg_id = 1, | |
1776 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1777 | .idlest_reg_id = 1, | |
1778 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1779 | }, | |
70034d38 | 1780 | }, |
844a3b63 PW |
1781 | .dev_attr = &mmc2_pre_es3_dev_attr, |
1782 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1783 | }; |
1784 | ||
844a3b63 PW |
1785 | static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { |
1786 | .name = "mmc2", | |
1787 | .mpu_irqs = omap34xx_mmc2_mpu_irqs, | |
1788 | .sdma_reqs = omap34xx_mmc2_sdma_reqs, | |
1789 | .opt_clks = omap34xx_mmc2_opt_clks, | |
1790 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), | |
1791 | .main_clk = "mmchs2_fck", | |
1792 | .prcm = { | |
1793 | .omap2 = { | |
1794 | .module_offs = CORE_MOD, | |
1795 | .prcm_reg_id = 1, | |
1796 | .module_bit = OMAP3430_EN_MMC2_SHIFT, | |
1797 | .idlest_reg_id = 1, | |
1798 | .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, | |
1799 | }, | |
1800 | }, | |
1801 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1802 | }; |
1803 | ||
844a3b63 PW |
1804 | /* MMC/SD/SDIO3 */ |
1805 | ||
1806 | static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { | |
1807 | { .irq = 94, }, | |
1808 | { .irq = -1 } | |
70034d38 VC |
1809 | }; |
1810 | ||
844a3b63 PW |
1811 | static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { |
1812 | { .name = "tx", .dma_req = 77, }, | |
1813 | { .name = "rx", .dma_req = 78, }, | |
1814 | { .dma_req = -1 } | |
70034d38 VC |
1815 | }; |
1816 | ||
844a3b63 PW |
1817 | static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { |
1818 | { .role = "dbck", .clk = "omap_32k_fck", }, | |
70034d38 VC |
1819 | }; |
1820 | ||
844a3b63 PW |
1821 | static struct omap_hwmod omap3xxx_mmc3_hwmod = { |
1822 | .name = "mmc3", | |
1823 | .mpu_irqs = omap34xx_mmc3_mpu_irqs, | |
1824 | .sdma_reqs = omap34xx_mmc3_sdma_reqs, | |
1825 | .opt_clks = omap34xx_mmc3_opt_clks, | |
1826 | .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), | |
1827 | .main_clk = "mmchs3_fck", | |
1828 | .prcm = { | |
1829 | .omap2 = { | |
1830 | .prcm_reg_id = 1, | |
1831 | .module_bit = OMAP3430_EN_MMC3_SHIFT, | |
1832 | .idlest_reg_id = 1, | |
1833 | .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, | |
1834 | }, | |
1835 | }, | |
1836 | .class = &omap34xx_mmc_class, | |
70034d38 VC |
1837 | }; |
1838 | ||
1839 | /* | |
844a3b63 PW |
1840 | * 'usb_host_hs' class |
1841 | * high-speed multi-port usb host controller | |
70034d38 VC |
1842 | */ |
1843 | ||
844a3b63 | 1844 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { |
70034d38 VC |
1845 | .rev_offs = 0x0000, |
1846 | .sysc_offs = 0x0010, | |
1847 | .syss_offs = 0x0014, | |
844a3b63 PW |
1848 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
1849 | SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1850 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1851 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1852 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1853 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1854 | }; |
1855 | ||
844a3b63 PW |
1856 | static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { |
1857 | .name = "usb_host_hs", | |
1858 | .sysc = &omap3xxx_usb_host_hs_sysc, | |
70034d38 VC |
1859 | }; |
1860 | ||
844a3b63 PW |
1861 | static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { |
1862 | { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, | |
70034d38 VC |
1863 | }; |
1864 | ||
844a3b63 PW |
1865 | static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { |
1866 | { .name = "ohci-irq", .irq = 76 }, | |
1867 | { .name = "ehci-irq", .irq = 77 }, | |
1868 | { .irq = -1 } | |
70034d38 VC |
1869 | }; |
1870 | ||
844a3b63 PW |
1871 | static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { |
1872 | .name = "usb_host_hs", | |
1873 | .class = &omap3xxx_usb_host_hs_hwmod_class, | |
1874 | .clkdm_name = "l3_init_clkdm", | |
1875 | .mpu_irqs = omap3xxx_usb_host_hs_irqs, | |
1876 | .main_clk = "usbhost_48m_fck", | |
1877 | .prcm = { | |
70034d38 | 1878 | .omap2 = { |
844a3b63 | 1879 | .module_offs = OMAP3430ES2_USBHOST_MOD, |
70034d38 | 1880 | .prcm_reg_id = 1, |
844a3b63 | 1881 | .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
70034d38 | 1882 | .idlest_reg_id = 1, |
844a3b63 PW |
1883 | .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, |
1884 | .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, | |
70034d38 VC |
1885 | }, |
1886 | }, | |
844a3b63 PW |
1887 | .opt_clks = omap3xxx_usb_host_hs_opt_clks, |
1888 | .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), | |
70034d38 | 1889 | |
844a3b63 PW |
1890 | /* |
1891 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock | |
1892 | * id: i660 | |
1893 | * | |
1894 | * Description: | |
1895 | * In the following configuration : | |
1896 | * - USBHOST module is set to smart-idle mode | |
1897 | * - PRCM asserts idle_req to the USBHOST module ( This typically | |
1898 | * happens when the system is going to a low power mode : all ports | |
1899 | * have been suspended, the master part of the USBHOST module has | |
1900 | * entered the standby state, and SW has cut the functional clocks) | |
1901 | * - an USBHOST interrupt occurs before the module is able to answer | |
1902 | * idle_ack, typically a remote wakeup IRQ. | |
1903 | * Then the USB HOST module will enter a deadlock situation where it | |
1904 | * is no more accessible nor functional. | |
1905 | * | |
1906 | * Workaround: | |
1907 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE | |
1908 | */ | |
1909 | ||
1910 | /* | |
1911 | * Errata: USB host EHCI may stall when entering smart-standby mode | |
1912 | * Id: i571 | |
1913 | * | |
1914 | * Description: | |
1915 | * When the USBHOST module is set to smart-standby mode, and when it is | |
1916 | * ready to enter the standby state (i.e. all ports are suspended and | |
1917 | * all attached devices are in suspend mode), then it can wrongly assert | |
1918 | * the Mstandby signal too early while there are still some residual OCP | |
1919 | * transactions ongoing. If this condition occurs, the internal state | |
1920 | * machine may go to an undefined state and the USB link may be stuck | |
1921 | * upon the next resume. | |
1922 | * | |
1923 | * Workaround: | |
1924 | * Don't use smart standby; use only force standby, | |
1925 | * hence HWMOD_SWSUP_MSTANDBY | |
1926 | */ | |
1927 | ||
1928 | /* | |
1929 | * During system boot; If the hwmod framework resets the module | |
1930 | * the module will have smart idle settings; which can lead to deadlock | |
1931 | * (above Errata Id:i660); so, dont reset the module during boot; | |
1932 | * Use HWMOD_INIT_NO_RESET. | |
1933 | */ | |
70034d38 | 1934 | |
844a3b63 PW |
1935 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
1936 | HWMOD_INIT_NO_RESET, | |
70034d38 VC |
1937 | }; |
1938 | ||
844a3b63 PW |
1939 | /* |
1940 | * 'usb_tll_hs' class | |
1941 | * usb_tll_hs module is the adapter on the usb_host_hs ports | |
1942 | */ | |
1943 | static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { | |
1944 | .rev_offs = 0x0000, | |
1945 | .sysc_offs = 0x0010, | |
1946 | .syss_offs = 0x0014, | |
1947 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1948 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1949 | SYSC_HAS_AUTOIDLE), | |
1950 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1951 | .sysc_fields = &omap_hwmod_sysc_type1, | |
70034d38 VC |
1952 | }; |
1953 | ||
844a3b63 PW |
1954 | static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { |
1955 | .name = "usb_tll_hs", | |
1956 | .sysc = &omap3xxx_usb_tll_hs_sysc, | |
70034d38 VC |
1957 | }; |
1958 | ||
844a3b63 PW |
1959 | static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { |
1960 | { .name = "tll-irq", .irq = 78 }, | |
1961 | { .irq = -1 } | |
70034d38 VC |
1962 | }; |
1963 | ||
844a3b63 PW |
1964 | static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { |
1965 | .name = "usb_tll_hs", | |
1966 | .class = &omap3xxx_usb_tll_hs_hwmod_class, | |
1967 | .clkdm_name = "l3_init_clkdm", | |
1968 | .mpu_irqs = omap3xxx_usb_tll_hs_irqs, | |
1969 | .main_clk = "usbtll_fck", | |
1970 | .prcm = { | |
70034d38 | 1971 | .omap2 = { |
844a3b63 PW |
1972 | .module_offs = CORE_MOD, |
1973 | .prcm_reg_id = 3, | |
1974 | .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1975 | .idlest_reg_id = 3, | |
1976 | .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, | |
70034d38 VC |
1977 | }, |
1978 | }, | |
70034d38 VC |
1979 | }; |
1980 | ||
45a4bb06 PW |
1981 | static struct omap_hwmod omap3xxx_hdq1w_hwmod = { |
1982 | .name = "hdq1w", | |
1983 | .mpu_irqs = omap2_hdq1w_mpu_irqs, | |
1984 | .main_clk = "hdq_fck", | |
1985 | .prcm = { | |
1986 | .omap2 = { | |
1987 | .module_offs = CORE_MOD, | |
1988 | .prcm_reg_id = 1, | |
1989 | .module_bit = OMAP3430_EN_HDQ_SHIFT, | |
1990 | .idlest_reg_id = 1, | |
1991 | .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, | |
1992 | }, | |
1993 | }, | |
1994 | .class = &omap2_hdq1w_class, | |
1995 | }; | |
1996 | ||
c8d82ff6 VH |
1997 | /* |
1998 | * '32K sync counter' class | |
1999 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock | |
2000 | */ | |
2001 | static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { | |
2002 | .rev_offs = 0x0000, | |
2003 | .sysc_offs = 0x0004, | |
2004 | .sysc_flags = SYSC_HAS_SIDLEMODE, | |
2005 | .idlemodes = (SIDLE_FORCE | SIDLE_NO), | |
2006 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2007 | }; | |
2008 | ||
2009 | static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { | |
2010 | .name = "counter", | |
2011 | .sysc = &omap3xxx_counter_sysc, | |
2012 | }; | |
2013 | ||
2014 | static struct omap_hwmod omap3xxx_counter_32k_hwmod = { | |
2015 | .name = "counter_32k", | |
2016 | .class = &omap3xxx_counter_hwmod_class, | |
2017 | .clkdm_name = "wkup_clkdm", | |
2018 | .flags = HWMOD_SWSUP_SIDLE, | |
2019 | .main_clk = "wkup_32k_fck", | |
2020 | .prcm = { | |
2021 | .omap2 = { | |
2022 | .module_offs = WKUP_MOD, | |
2023 | .prcm_reg_id = 1, | |
2024 | .module_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2025 | .idlest_reg_id = 1, | |
2026 | .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, | |
2027 | }, | |
2028 | }, | |
2029 | }; | |
2030 | ||
844a3b63 PW |
2031 | /* |
2032 | * interfaces | |
2033 | */ | |
2034 | ||
2035 | /* L3 -> L4_CORE interface */ | |
2036 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { | |
2037 | .master = &omap3xxx_l3_main_hwmod, | |
2038 | .slave = &omap3xxx_l4_core_hwmod, | |
2039 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2040 | }; |
2041 | ||
844a3b63 PW |
2042 | /* L3 -> L4_PER interface */ |
2043 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { | |
2044 | .master = &omap3xxx_l3_main_hwmod, | |
2045 | .slave = &omap3xxx_l4_per_hwmod, | |
2046 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2047 | }; |
2048 | ||
844a3b63 PW |
2049 | static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { |
2050 | { | |
2051 | .pa_start = 0x68000000, | |
2052 | .pa_end = 0x6800ffff, | |
2053 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2054 | }, |
844a3b63 | 2055 | { } |
70034d38 VC |
2056 | }; |
2057 | ||
844a3b63 PW |
2058 | /* MPU -> L3 interface */ |
2059 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { | |
2060 | .master = &omap3xxx_mpu_hwmod, | |
2061 | .slave = &omap3xxx_l3_main_hwmod, | |
2062 | .addr = omap3xxx_l3_main_addrs, | |
2063 | .user = OCP_USER_MPU, | |
70034d38 VC |
2064 | }; |
2065 | ||
844a3b63 PW |
2066 | /* DSS -> l3 */ |
2067 | static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { | |
2068 | .master = &omap3430es1_dss_core_hwmod, | |
2069 | .slave = &omap3xxx_l3_main_hwmod, | |
2070 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2071 | }; |
2072 | ||
844a3b63 PW |
2073 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { |
2074 | .master = &omap3xxx_dss_core_hwmod, | |
2075 | .slave = &omap3xxx_l3_main_hwmod, | |
2076 | .fw = { | |
70034d38 | 2077 | .omap2 = { |
844a3b63 PW |
2078 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, |
2079 | .flags = OMAP_FIREWALL_L3, | |
2080 | } | |
70034d38 | 2081 | }, |
844a3b63 | 2082 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2083 | }; |
2084 | ||
844a3b63 PW |
2085 | /* l3_core -> usbhsotg interface */ |
2086 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
2087 | .master = &omap3xxx_usbhsotg_hwmod, | |
01438ab6 MK |
2088 | .slave = &omap3xxx_l3_main_hwmod, |
2089 | .clk = "core_l3_ick", | |
844a3b63 | 2090 | .user = OCP_USER_MPU, |
01438ab6 MK |
2091 | }; |
2092 | ||
844a3b63 PW |
2093 | /* l3_core -> am35xx_usbhsotg interface */ |
2094 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
2095 | .master = &am35xx_usbhsotg_hwmod, | |
2096 | .slave = &omap3xxx_l3_main_hwmod, | |
89ea2583 | 2097 | .clk = "hsotgusb_ick", |
844a3b63 | 2098 | .user = OCP_USER_MPU, |
01438ab6 | 2099 | }; |
89ea2583 | 2100 | |
844a3b63 PW |
2101 | /* L4_CORE -> L4_WKUP interface */ |
2102 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
2103 | .master = &omap3xxx_l4_core_hwmod, | |
2104 | .slave = &omap3xxx_l4_wkup_hwmod, | |
2105 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2106 | }; |
2107 | ||
844a3b63 PW |
2108 | /* L4 CORE -> MMC1 interface */ |
2109 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { | |
01438ab6 | 2110 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2111 | .slave = &omap3xxx_pre_es3_mmc1_hwmod, |
2112 | .clk = "mmchs1_ick", | |
2113 | .addr = omap2430_mmc1_addr_space, | |
01438ab6 | 2114 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
844a3b63 | 2115 | .flags = OMAP_FIREWALL_L4 |
01438ab6 MK |
2116 | }; |
2117 | ||
844a3b63 PW |
2118 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { |
2119 | .master = &omap3xxx_l4_core_hwmod, | |
2120 | .slave = &omap3xxx_es3plus_mmc1_hwmod, | |
2121 | .clk = "mmchs1_ick", | |
2122 | .addr = omap2430_mmc1_addr_space, | |
2123 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2124 | .flags = OMAP_FIREWALL_L4 | |
01438ab6 MK |
2125 | }; |
2126 | ||
844a3b63 PW |
2127 | /* L4 CORE -> MMC2 interface */ |
2128 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { | |
2129 | .master = &omap3xxx_l4_core_hwmod, | |
2130 | .slave = &omap3xxx_pre_es3_mmc2_hwmod, | |
2131 | .clk = "mmchs2_ick", | |
2132 | .addr = omap2430_mmc2_addr_space, | |
2133 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2134 | .flags = OMAP_FIREWALL_L4 | |
2135 | }; | |
70034d38 | 2136 | |
844a3b63 PW |
2137 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { |
2138 | .master = &omap3xxx_l4_core_hwmod, | |
2139 | .slave = &omap3xxx_es3plus_mmc2_hwmod, | |
2140 | .clk = "mmchs2_ick", | |
2141 | .addr = omap2430_mmc2_addr_space, | |
2142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2143 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2144 | }; |
2145 | ||
844a3b63 PW |
2146 | /* L4 CORE -> MMC3 interface */ |
2147 | static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { | |
2148 | { | |
2149 | .pa_start = 0x480ad000, | |
2150 | .pa_end = 0x480ad1ff, | |
2151 | .flags = ADDR_TYPE_RT, | |
2152 | }, | |
2153 | { } | |
70034d38 VC |
2154 | }; |
2155 | ||
844a3b63 PW |
2156 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { |
2157 | .master = &omap3xxx_l4_core_hwmod, | |
2158 | .slave = &omap3xxx_mmc3_hwmod, | |
2159 | .clk = "mmchs3_ick", | |
2160 | .addr = omap3xxx_mmc3_addr_space, | |
2161 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2162 | .flags = OMAP_FIREWALL_L4 | |
70034d38 VC |
2163 | }; |
2164 | ||
844a3b63 PW |
2165 | /* L4 CORE -> UART1 interface */ |
2166 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
dc48e5fc | 2167 | { |
844a3b63 PW |
2168 | .pa_start = OMAP3_UART1_BASE, |
2169 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
2170 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2171 | }, |
78183f3f | 2172 | { } |
70034d38 VC |
2173 | }; |
2174 | ||
844a3b63 | 2175 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { |
dc48e5fc | 2176 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2177 | .slave = &omap3xxx_uart1_hwmod, |
2178 | .clk = "uart1_ick", | |
2179 | .addr = omap3xxx_uart1_addr_space, | |
dc48e5fc | 2180 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2181 | }; |
2182 | ||
844a3b63 PW |
2183 | /* L4 CORE -> UART2 interface */ |
2184 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
2185 | { | |
2186 | .pa_start = OMAP3_UART2_BASE, | |
2187 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
2188 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2189 | }, |
844a3b63 | 2190 | { } |
70034d38 VC |
2191 | }; |
2192 | ||
844a3b63 PW |
2193 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { |
2194 | .master = &omap3xxx_l4_core_hwmod, | |
2195 | .slave = &omap3xxx_uart2_hwmod, | |
2196 | .clk = "uart2_ick", | |
2197 | .addr = omap3xxx_uart2_addr_space, | |
2198 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2199 | }; |
2200 | ||
844a3b63 PW |
2201 | /* L4 PER -> UART3 interface */ |
2202 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
dc48e5fc | 2203 | { |
844a3b63 PW |
2204 | .pa_start = OMAP3_UART3_BASE, |
2205 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
2206 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2207 | }, |
78183f3f | 2208 | { } |
70034d38 VC |
2209 | }; |
2210 | ||
844a3b63 | 2211 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { |
dc48e5fc | 2212 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2213 | .slave = &omap3xxx_uart3_hwmod, |
2214 | .clk = "uart3_ick", | |
2215 | .addr = omap3xxx_uart3_addr_space, | |
dc48e5fc | 2216 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2217 | }; |
2218 | ||
844a3b63 PW |
2219 | /* L4 PER -> UART4 interface */ |
2220 | static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { | |
2221 | { | |
2222 | .pa_start = OMAP3_UART4_BASE, | |
2223 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
2224 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
70034d38 | 2225 | }, |
844a3b63 | 2226 | { } |
70034d38 VC |
2227 | }; |
2228 | ||
844a3b63 PW |
2229 | static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { |
2230 | .master = &omap3xxx_l4_per_hwmod, | |
2231 | .slave = &omap36xx_uart4_hwmod, | |
2232 | .clk = "uart4_ick", | |
2233 | .addr = omap36xx_uart4_addr_space, | |
2234 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2235 | }; |
2236 | ||
844a3b63 PW |
2237 | /* AM35xx: L4 CORE -> UART4 interface */ |
2238 | static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |
dc48e5fc | 2239 | { |
844a3b63 PW |
2240 | .pa_start = OMAP3_UART4_AM35XX_BASE, |
2241 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | |
2242 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
dc48e5fc | 2243 | }, |
bf765237 | 2244 | { } |
70034d38 VC |
2245 | }; |
2246 | ||
844a3b63 PW |
2247 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
2248 | .master = &omap3xxx_l4_core_hwmod, | |
2249 | .slave = &am35xx_uart4_hwmod, | |
2250 | .clk = "uart4_ick", | |
2251 | .addr = am35xx_uart4_addr_space, | |
dc48e5fc C |
2252 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2253 | }; | |
2254 | ||
844a3b63 PW |
2255 | /* L4 CORE -> I2C1 interface */ |
2256 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
2257 | .master = &omap3xxx_l4_core_hwmod, | |
2258 | .slave = &omap3xxx_i2c1_hwmod, | |
2259 | .clk = "i2c1_ick", | |
2260 | .addr = omap2_i2c1_addr_space, | |
2261 | .fw = { | |
2262 | .omap2 = { | |
2263 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
2264 | .l4_prot_group = 7, | |
2265 | .flags = OMAP_FIREWALL_L4, | |
2266 | } | |
2267 | }, | |
2268 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
8b1906f1 KVA |
2269 | }; |
2270 | ||
844a3b63 PW |
2271 | /* L4 CORE -> I2C2 interface */ |
2272 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
2273 | .master = &omap3xxx_l4_core_hwmod, | |
2274 | .slave = &omap3xxx_i2c2_hwmod, | |
2275 | .clk = "i2c2_ick", | |
2276 | .addr = omap2_i2c2_addr_space, | |
2277 | .fw = { | |
70034d38 | 2278 | .omap2 = { |
844a3b63 PW |
2279 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, |
2280 | .l4_prot_group = 7, | |
2281 | .flags = OMAP_FIREWALL_L4, | |
2282 | } | |
70034d38 | 2283 | }, |
844a3b63 | 2284 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
70034d38 VC |
2285 | }; |
2286 | ||
844a3b63 PW |
2287 | /* L4 CORE -> I2C3 interface */ |
2288 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
2289 | { | |
2290 | .pa_start = 0x48060000, | |
2291 | .pa_end = 0x48060000 + SZ_128 - 1, | |
2292 | .flags = ADDR_TYPE_RT, | |
2293 | }, | |
2294 | { } | |
70034d38 VC |
2295 | }; |
2296 | ||
844a3b63 PW |
2297 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { |
2298 | .master = &omap3xxx_l4_core_hwmod, | |
2299 | .slave = &omap3xxx_i2c3_hwmod, | |
2300 | .clk = "i2c3_ick", | |
2301 | .addr = omap3xxx_i2c3_addr_space, | |
2302 | .fw = { | |
2303 | .omap2 = { | |
2304 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
2305 | .l4_prot_group = 7, | |
2306 | .flags = OMAP_FIREWALL_L4, | |
2307 | } | |
2308 | }, | |
2309 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2310 | }; |
2311 | ||
844a3b63 PW |
2312 | /* L4 CORE -> SR1 interface */ |
2313 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
dc48e5fc | 2314 | { |
844a3b63 PW |
2315 | .pa_start = OMAP34XX_SR1_BASE, |
2316 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
2317 | .flags = ADDR_TYPE_RT, | |
dc48e5fc | 2318 | }, |
78183f3f | 2319 | { } |
70034d38 VC |
2320 | }; |
2321 | ||
844a3b63 PW |
2322 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { |
2323 | .master = &omap3xxx_l4_core_hwmod, | |
2324 | .slave = &omap34xx_sr1_hwmod, | |
2325 | .clk = "sr_l4_ick", | |
2326 | .addr = omap3_sr1_addr_space, | |
2327 | .user = OCP_USER_MPU, | |
70034d38 VC |
2328 | }; |
2329 | ||
844a3b63 PW |
2330 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { |
2331 | .master = &omap3xxx_l4_core_hwmod, | |
2332 | .slave = &omap36xx_sr1_hwmod, | |
2333 | .clk = "sr_l4_ick", | |
2334 | .addr = omap3_sr1_addr_space, | |
2335 | .user = OCP_USER_MPU, | |
2336 | }; | |
2337 | ||
2338 | /* L4 CORE -> SR1 interface */ | |
2339 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
2340 | { | |
2341 | .pa_start = OMAP34XX_SR2_BASE, | |
2342 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
2343 | .flags = ADDR_TYPE_RT, | |
70034d38 | 2344 | }, |
844a3b63 | 2345 | { } |
70034d38 VC |
2346 | }; |
2347 | ||
844a3b63 PW |
2348 | static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { |
2349 | .master = &omap3xxx_l4_core_hwmod, | |
2350 | .slave = &omap34xx_sr2_hwmod, | |
2351 | .clk = "sr_l4_ick", | |
2352 | .addr = omap3_sr2_addr_space, | |
2353 | .user = OCP_USER_MPU, | |
70034d38 VC |
2354 | }; |
2355 | ||
844a3b63 PW |
2356 | static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { |
2357 | .master = &omap3xxx_l4_core_hwmod, | |
2358 | .slave = &omap36xx_sr2_hwmod, | |
2359 | .clk = "sr_l4_ick", | |
2360 | .addr = omap3_sr2_addr_space, | |
2361 | .user = OCP_USER_MPU, | |
70034d38 VC |
2362 | }; |
2363 | ||
844a3b63 | 2364 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { |
dc48e5fc | 2365 | { |
844a3b63 PW |
2366 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, |
2367 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
dc48e5fc C |
2368 | .flags = ADDR_TYPE_RT |
2369 | }, | |
78183f3f | 2370 | { } |
70034d38 VC |
2371 | }; |
2372 | ||
844a3b63 PW |
2373 | /* l4_core -> usbhsotg */ |
2374 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
dc48e5fc | 2375 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2376 | .slave = &omap3xxx_usbhsotg_hwmod, |
2377 | .clk = "l4_ick", | |
2378 | .addr = omap3xxx_usbhsotg_addrs, | |
2379 | .user = OCP_USER_MPU, | |
dc48e5fc C |
2380 | }; |
2381 | ||
844a3b63 PW |
2382 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
2383 | { | |
2384 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
2385 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
2386 | .flags = ADDR_TYPE_RT | |
70034d38 | 2387 | }, |
844a3b63 | 2388 | { } |
70034d38 VC |
2389 | }; |
2390 | ||
844a3b63 PW |
2391 | /* l4_core -> usbhsotg */ |
2392 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
2393 | .master = &omap3xxx_l4_core_hwmod, | |
2394 | .slave = &am35xx_usbhsotg_hwmod, | |
89ea2583 | 2395 | .clk = "hsotgusb_ick", |
844a3b63 PW |
2396 | .addr = am35xx_usbhsotg_addrs, |
2397 | .user = OCP_USER_MPU, | |
01438ab6 MK |
2398 | }; |
2399 | ||
844a3b63 PW |
2400 | /* L4_WKUP -> L4_SEC interface */ |
2401 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { | |
2402 | .master = &omap3xxx_l4_wkup_hwmod, | |
2403 | .slave = &omap3xxx_l4_sec_hwmod, | |
2404 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2405 | }; |
2406 | ||
844a3b63 PW |
2407 | /* IVA2 <- L3 interface */ |
2408 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
2409 | .master = &omap3xxx_l3_main_hwmod, | |
2410 | .slave = &omap3xxx_iva_hwmod, | |
064931ab | 2411 | .clk = "core_l3_ick", |
844a3b63 | 2412 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
01438ab6 MK |
2413 | }; |
2414 | ||
844a3b63 | 2415 | static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { |
dc48e5fc | 2416 | { |
844a3b63 PW |
2417 | .pa_start = 0x48318000, |
2418 | .pa_end = 0x48318000 + SZ_1K - 1, | |
dc48e5fc C |
2419 | .flags = ADDR_TYPE_RT |
2420 | }, | |
78183f3f | 2421 | { } |
01438ab6 MK |
2422 | }; |
2423 | ||
844a3b63 PW |
2424 | /* l4_wkup -> timer1 */ |
2425 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { | |
2426 | .master = &omap3xxx_l4_wkup_hwmod, | |
2427 | .slave = &omap3xxx_timer1_hwmod, | |
2428 | .clk = "gpt1_ick", | |
2429 | .addr = omap3xxx_timer1_addrs, | |
2430 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2431 | }; |
2432 | ||
844a3b63 PW |
2433 | static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { |
2434 | { | |
2435 | .pa_start = 0x49032000, | |
2436 | .pa_end = 0x49032000 + SZ_1K - 1, | |
2437 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2438 | }, |
844a3b63 | 2439 | { } |
01438ab6 MK |
2440 | }; |
2441 | ||
844a3b63 PW |
2442 | /* l4_per -> timer2 */ |
2443 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { | |
2444 | .master = &omap3xxx_l4_per_hwmod, | |
2445 | .slave = &omap3xxx_timer2_hwmod, | |
2446 | .clk = "gpt2_ick", | |
2447 | .addr = omap3xxx_timer2_addrs, | |
2448 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2449 | }; |
2450 | ||
844a3b63 | 2451 | static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { |
dc48e5fc | 2452 | { |
844a3b63 PW |
2453 | .pa_start = 0x49034000, |
2454 | .pa_end = 0x49034000 + SZ_1K - 1, | |
dc48e5fc C |
2455 | .flags = ADDR_TYPE_RT |
2456 | }, | |
78183f3f | 2457 | { } |
01438ab6 MK |
2458 | }; |
2459 | ||
844a3b63 PW |
2460 | /* l4_per -> timer3 */ |
2461 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { | |
dc48e5fc | 2462 | .master = &omap3xxx_l4_per_hwmod, |
844a3b63 PW |
2463 | .slave = &omap3xxx_timer3_hwmod, |
2464 | .clk = "gpt3_ick", | |
2465 | .addr = omap3xxx_timer3_addrs, | |
2466 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2467 | }; |
2468 | ||
844a3b63 PW |
2469 | static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { |
2470 | { | |
2471 | .pa_start = 0x49036000, | |
2472 | .pa_end = 0x49036000 + SZ_1K - 1, | |
2473 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2474 | }, |
844a3b63 | 2475 | { } |
01438ab6 MK |
2476 | }; |
2477 | ||
844a3b63 PW |
2478 | /* l4_per -> timer4 */ |
2479 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { | |
2480 | .master = &omap3xxx_l4_per_hwmod, | |
2481 | .slave = &omap3xxx_timer4_hwmod, | |
2482 | .clk = "gpt4_ick", | |
2483 | .addr = omap3xxx_timer4_addrs, | |
2484 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2485 | }; |
2486 | ||
844a3b63 PW |
2487 | static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { |
2488 | { | |
2489 | .pa_start = 0x49038000, | |
2490 | .pa_end = 0x49038000 + SZ_1K - 1, | |
2491 | .flags = ADDR_TYPE_RT | |
2492 | }, | |
2493 | { } | |
d3442726 TG |
2494 | }; |
2495 | ||
844a3b63 PW |
2496 | /* l4_per -> timer5 */ |
2497 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { | |
2498 | .master = &omap3xxx_l4_per_hwmod, | |
2499 | .slave = &omap3xxx_timer5_hwmod, | |
2500 | .clk = "gpt5_ick", | |
2501 | .addr = omap3xxx_timer5_addrs, | |
2502 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2503 | }; |
2504 | ||
844a3b63 PW |
2505 | static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { |
2506 | { | |
2507 | .pa_start = 0x4903A000, | |
2508 | .pa_end = 0x4903A000 + SZ_1K - 1, | |
2509 | .flags = ADDR_TYPE_RT | |
2510 | }, | |
2511 | { } | |
cea6b942 SG |
2512 | }; |
2513 | ||
844a3b63 PW |
2514 | /* l4_per -> timer6 */ |
2515 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { | |
2516 | .master = &omap3xxx_l4_per_hwmod, | |
2517 | .slave = &omap3xxx_timer6_hwmod, | |
2518 | .clk = "gpt6_ick", | |
2519 | .addr = omap3xxx_timer6_addrs, | |
2520 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2521 | }; |
2522 | ||
844a3b63 PW |
2523 | static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { |
2524 | { | |
2525 | .pa_start = 0x4903C000, | |
2526 | .pa_end = 0x4903C000 + SZ_1K - 1, | |
2527 | .flags = ADDR_TYPE_RT | |
d3442726 | 2528 | }, |
844a3b63 | 2529 | { } |
d3442726 TG |
2530 | }; |
2531 | ||
844a3b63 PW |
2532 | /* l4_per -> timer7 */ |
2533 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { | |
2534 | .master = &omap3xxx_l4_per_hwmod, | |
2535 | .slave = &omap3xxx_timer7_hwmod, | |
2536 | .clk = "gpt7_ick", | |
2537 | .addr = omap3xxx_timer7_addrs, | |
2538 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
cea6b942 SG |
2539 | }; |
2540 | ||
844a3b63 PW |
2541 | static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { |
2542 | { | |
2543 | .pa_start = 0x4903E000, | |
2544 | .pa_end = 0x4903E000 + SZ_1K - 1, | |
2545 | .flags = ADDR_TYPE_RT | |
d3442726 | 2546 | }, |
844a3b63 | 2547 | { } |
d3442726 TG |
2548 | }; |
2549 | ||
844a3b63 PW |
2550 | /* l4_per -> timer8 */ |
2551 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { | |
2552 | .master = &omap3xxx_l4_per_hwmod, | |
2553 | .slave = &omap3xxx_timer8_hwmod, | |
2554 | .clk = "gpt8_ick", | |
2555 | .addr = omap3xxx_timer8_addrs, | |
2556 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2557 | }; |
2558 | ||
844a3b63 PW |
2559 | static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { |
2560 | { | |
2561 | .pa_start = 0x49040000, | |
2562 | .pa_end = 0x49040000 + SZ_1K - 1, | |
2563 | .flags = ADDR_TYPE_RT | |
2564 | }, | |
2565 | { } | |
2566 | }; | |
0f9dfdd3 | 2567 | |
844a3b63 PW |
2568 | /* l4_per -> timer9 */ |
2569 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { | |
2570 | .master = &omap3xxx_l4_per_hwmod, | |
2571 | .slave = &omap3xxx_timer9_hwmod, | |
2572 | .clk = "gpt9_ick", | |
2573 | .addr = omap3xxx_timer9_addrs, | |
2574 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2575 | }; |
2576 | ||
844a3b63 PW |
2577 | /* l4_core -> timer10 */ |
2578 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { | |
2579 | .master = &omap3xxx_l4_core_hwmod, | |
2580 | .slave = &omap3xxx_timer10_hwmod, | |
2581 | .clk = "gpt10_ick", | |
2582 | .addr = omap2_timer10_addrs, | |
2583 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2584 | }; |
2585 | ||
844a3b63 PW |
2586 | /* l4_core -> timer11 */ |
2587 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { | |
2588 | .master = &omap3xxx_l4_core_hwmod, | |
2589 | .slave = &omap3xxx_timer11_hwmod, | |
2590 | .clk = "gpt11_ick", | |
2591 | .addr = omap2_timer11_addrs, | |
2592 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f9dfdd3 FC |
2593 | }; |
2594 | ||
844a3b63 | 2595 | static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { |
0f9dfdd3 | 2596 | { |
844a3b63 PW |
2597 | .pa_start = 0x48304000, |
2598 | .pa_end = 0x48304000 + SZ_1K - 1, | |
2599 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2600 | }, |
78183f3f | 2601 | { } |
0f9dfdd3 FC |
2602 | }; |
2603 | ||
844a3b63 PW |
2604 | /* l4_core -> timer12 */ |
2605 | static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { | |
2606 | .master = &omap3xxx_l4_sec_hwmod, | |
2607 | .slave = &omap3xxx_timer12_hwmod, | |
2608 | .clk = "gpt12_ick", | |
2609 | .addr = omap3xxx_timer12_addrs, | |
0f9dfdd3 FC |
2610 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2611 | }; | |
2612 | ||
844a3b63 PW |
2613 | /* l4_wkup -> wd_timer2 */ |
2614 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
2615 | { | |
2616 | .pa_start = 0x48314000, | |
2617 | .pa_end = 0x4831407f, | |
2618 | .flags = ADDR_TYPE_RT | |
0f9dfdd3 | 2619 | }, |
844a3b63 | 2620 | { } |
0f9dfdd3 FC |
2621 | }; |
2622 | ||
844a3b63 PW |
2623 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { |
2624 | .master = &omap3xxx_l4_wkup_hwmod, | |
2625 | .slave = &omap3xxx_wd_timer2_hwmod, | |
2626 | .clk = "wdt2_ick", | |
2627 | .addr = omap3xxx_wd_timer2_addrs, | |
2628 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
2629 | }; | |
2630 | ||
2631 | /* l4_core -> dss */ | |
2632 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
0f616a4e | 2633 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2634 | .slave = &omap3430es1_dss_core_hwmod, |
2635 | .clk = "dss_ick", | |
2636 | .addr = omap2_dss_addrs, | |
2637 | .fw = { | |
2638 | .omap2 = { | |
2639 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
2640 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2641 | .flags = OMAP_FIREWALL_L4, | |
2642 | } | |
2643 | }, | |
0f616a4e C |
2644 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2645 | }; | |
2646 | ||
844a3b63 | 2647 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { |
0f616a4e | 2648 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2649 | .slave = &omap3xxx_dss_core_hwmod, |
2650 | .clk = "dss_ick", | |
2651 | .addr = omap2_dss_addrs, | |
2652 | .fw = { | |
2653 | .omap2 = { | |
2654 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
2655 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2656 | .flags = OMAP_FIREWALL_L4, | |
2657 | } | |
2658 | }, | |
0f616a4e C |
2659 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2660 | }; | |
2661 | ||
844a3b63 PW |
2662 | /* l4_core -> dss_dispc */ |
2663 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
0f616a4e | 2664 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2665 | .slave = &omap3xxx_dss_dispc_hwmod, |
2666 | .clk = "dss_ick", | |
2667 | .addr = omap2_dss_dispc_addrs, | |
2668 | .fw = { | |
2669 | .omap2 = { | |
2670 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
2671 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2672 | .flags = OMAP_FIREWALL_L4, | |
2673 | } | |
2674 | }, | |
0f616a4e C |
2675 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2676 | }; | |
2677 | ||
844a3b63 | 2678 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { |
0f616a4e | 2679 | { |
844a3b63 PW |
2680 | .pa_start = 0x4804FC00, |
2681 | .pa_end = 0x4804FFFF, | |
2682 | .flags = ADDR_TYPE_RT | |
0f616a4e | 2683 | }, |
78183f3f | 2684 | { } |
0f616a4e C |
2685 | }; |
2686 | ||
844a3b63 PW |
2687 | /* l4_core -> dss_dsi1 */ |
2688 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
0f616a4e | 2689 | .master = &omap3xxx_l4_core_hwmod, |
844a3b63 PW |
2690 | .slave = &omap3xxx_dss_dsi1_hwmod, |
2691 | .clk = "dss_ick", | |
2692 | .addr = omap3xxx_dss_dsi1_addrs, | |
2693 | .fw = { | |
2694 | .omap2 = { | |
2695 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
2696 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2697 | .flags = OMAP_FIREWALL_L4, | |
2698 | } | |
2699 | }, | |
0f616a4e C |
2700 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2701 | }; | |
2702 | ||
844a3b63 PW |
2703 | /* l4_core -> dss_rfbi */ |
2704 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
2705 | .master = &omap3xxx_l4_core_hwmod, | |
2706 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
2707 | .clk = "dss_ick", | |
2708 | .addr = omap2_dss_rfbi_addrs, | |
2709 | .fw = { | |
0f616a4e | 2710 | .omap2 = { |
844a3b63 PW |
2711 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, |
2712 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
2713 | .flags = OMAP_FIREWALL_L4, | |
2714 | } | |
0f616a4e | 2715 | }, |
844a3b63 | 2716 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
0f616a4e C |
2717 | }; |
2718 | ||
844a3b63 PW |
2719 | /* l4_core -> dss_venc */ |
2720 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
2721 | .master = &omap3xxx_l4_core_hwmod, | |
2722 | .slave = &omap3xxx_dss_venc_hwmod, | |
2723 | .clk = "dss_ick", | |
2724 | .addr = omap2_dss_venc_addrs, | |
2725 | .fw = { | |
70034d38 | 2726 | .omap2 = { |
844a3b63 PW |
2727 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, |
2728 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
2729 | .flags = OMAP_FIREWALL_L4, | |
2730 | } | |
70034d38 | 2731 | }, |
844a3b63 PW |
2732 | .flags = OCPIF_SWSUP_IDLE, |
2733 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2734 | }; |
2735 | ||
844a3b63 PW |
2736 | /* l4_wkup -> gpio1 */ |
2737 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
2738 | { | |
2739 | .pa_start = 0x48310000, | |
2740 | .pa_end = 0x483101ff, | |
2741 | .flags = ADDR_TYPE_RT | |
2742 | }, | |
2743 | { } | |
70034d38 VC |
2744 | }; |
2745 | ||
844a3b63 PW |
2746 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { |
2747 | .master = &omap3xxx_l4_wkup_hwmod, | |
2748 | .slave = &omap3xxx_gpio1_hwmod, | |
2749 | .addr = omap3xxx_gpio1_addrs, | |
2750 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2751 | }; |
2752 | ||
844a3b63 PW |
2753 | /* l4_per -> gpio2 */ |
2754 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
2755 | { | |
2756 | .pa_start = 0x49050000, | |
2757 | .pa_end = 0x490501ff, | |
2758 | .flags = ADDR_TYPE_RT | |
70034d38 | 2759 | }, |
844a3b63 | 2760 | { } |
70034d38 VC |
2761 | }; |
2762 | ||
844a3b63 PW |
2763 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { |
2764 | .master = &omap3xxx_l4_per_hwmod, | |
2765 | .slave = &omap3xxx_gpio2_hwmod, | |
2766 | .addr = omap3xxx_gpio2_addrs, | |
2767 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
70034d38 VC |
2768 | }; |
2769 | ||
844a3b63 PW |
2770 | /* l4_per -> gpio3 */ |
2771 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
2772 | { | |
2773 | .pa_start = 0x49052000, | |
2774 | .pa_end = 0x490521ff, | |
2775 | .flags = ADDR_TYPE_RT | |
2776 | }, | |
2777 | { } | |
70034d38 VC |
2778 | }; |
2779 | ||
844a3b63 PW |
2780 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { |
2781 | .master = &omap3xxx_l4_per_hwmod, | |
2782 | .slave = &omap3xxx_gpio3_hwmod, | |
2783 | .addr = omap3xxx_gpio3_addrs, | |
2784 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
0f616a4e C |
2785 | }; |
2786 | ||
844a3b63 PW |
2787 | /* l4_per -> gpio4 */ |
2788 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
2789 | { | |
2790 | .pa_start = 0x49054000, | |
2791 | .pa_end = 0x490541ff, | |
2792 | .flags = ADDR_TYPE_RT | |
70034d38 | 2793 | }, |
844a3b63 | 2794 | { } |
70034d38 VC |
2795 | }; |
2796 | ||
844a3b63 PW |
2797 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { |
2798 | .master = &omap3xxx_l4_per_hwmod, | |
2799 | .slave = &omap3xxx_gpio4_hwmod, | |
2800 | .addr = omap3xxx_gpio4_addrs, | |
2801 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2802 | }; |
2803 | ||
844a3b63 PW |
2804 | /* l4_per -> gpio5 */ |
2805 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
2806 | { | |
2807 | .pa_start = 0x49056000, | |
2808 | .pa_end = 0x490561ff, | |
2809 | .flags = ADDR_TYPE_RT | |
2810 | }, | |
2811 | { } | |
01438ab6 MK |
2812 | }; |
2813 | ||
844a3b63 PW |
2814 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { |
2815 | .master = &omap3xxx_l4_per_hwmod, | |
2816 | .slave = &omap3xxx_gpio5_hwmod, | |
2817 | .addr = omap3xxx_gpio5_addrs, | |
2818 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2819 | }; |
2820 | ||
844a3b63 PW |
2821 | /* l4_per -> gpio6 */ |
2822 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
2823 | { | |
2824 | .pa_start = 0x49058000, | |
2825 | .pa_end = 0x490581ff, | |
2826 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2827 | }, |
844a3b63 | 2828 | { } |
01438ab6 MK |
2829 | }; |
2830 | ||
844a3b63 PW |
2831 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { |
2832 | .master = &omap3xxx_l4_per_hwmod, | |
2833 | .slave = &omap3xxx_gpio6_hwmod, | |
2834 | .addr = omap3xxx_gpio6_addrs, | |
2835 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2836 | }; |
2837 | ||
844a3b63 PW |
2838 | /* dma_system -> L3 */ |
2839 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
2840 | .master = &omap3xxx_dma_system_hwmod, | |
2841 | .slave = &omap3xxx_l3_main_hwmod, | |
2842 | .clk = "core_l3_ick", | |
2843 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
01438ab6 MK |
2844 | }; |
2845 | ||
844a3b63 PW |
2846 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { |
2847 | { | |
2848 | .pa_start = 0x48056000, | |
2849 | .pa_end = 0x48056fff, | |
2850 | .flags = ADDR_TYPE_RT | |
01438ab6 | 2851 | }, |
844a3b63 | 2852 | { } |
01438ab6 MK |
2853 | }; |
2854 | ||
844a3b63 PW |
2855 | /* l4_cfg -> dma_system */ |
2856 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
2857 | .master = &omap3xxx_l4_core_hwmod, | |
2858 | .slave = &omap3xxx_dma_system_hwmod, | |
2859 | .clk = "core_l4_ick", | |
2860 | .addr = omap3xxx_dma_system_addrs, | |
2861 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2862 | }; |
2863 | ||
844a3b63 PW |
2864 | static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { |
2865 | { | |
2866 | .name = "mpu", | |
2867 | .pa_start = 0x48074000, | |
2868 | .pa_end = 0x480740ff, | |
2869 | .flags = ADDR_TYPE_RT | |
2870 | }, | |
2871 | { } | |
d3442726 TG |
2872 | }; |
2873 | ||
844a3b63 PW |
2874 | /* l4_core -> mcbsp1 */ |
2875 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { | |
2876 | .master = &omap3xxx_l4_core_hwmod, | |
2877 | .slave = &omap3xxx_mcbsp1_hwmod, | |
2878 | .clk = "mcbsp1_ick", | |
2879 | .addr = omap3xxx_mcbsp1_addrs, | |
2880 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2881 | }; |
2882 | ||
844a3b63 PW |
2883 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { |
2884 | { | |
2885 | .name = "mpu", | |
2886 | .pa_start = 0x49022000, | |
2887 | .pa_end = 0x490220ff, | |
2888 | .flags = ADDR_TYPE_RT | |
2889 | }, | |
2890 | { } | |
d3442726 TG |
2891 | }; |
2892 | ||
844a3b63 PW |
2893 | /* l4_per -> mcbsp2 */ |
2894 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { | |
2895 | .master = &omap3xxx_l4_per_hwmod, | |
2896 | .slave = &omap3xxx_mcbsp2_hwmod, | |
2897 | .clk = "mcbsp2_ick", | |
2898 | .addr = omap3xxx_mcbsp2_addrs, | |
2899 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2900 | }; |
2901 | ||
844a3b63 PW |
2902 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { |
2903 | { | |
2904 | .name = "mpu", | |
2905 | .pa_start = 0x49024000, | |
2906 | .pa_end = 0x490240ff, | |
2907 | .flags = ADDR_TYPE_RT | |
2908 | }, | |
2909 | { } | |
d3442726 TG |
2910 | }; |
2911 | ||
844a3b63 PW |
2912 | /* l4_per -> mcbsp3 */ |
2913 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { | |
2914 | .master = &omap3xxx_l4_per_hwmod, | |
2915 | .slave = &omap3xxx_mcbsp3_hwmod, | |
2916 | .clk = "mcbsp3_ick", | |
2917 | .addr = omap3xxx_mcbsp3_addrs, | |
2918 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
a52e2ab6 PW |
2919 | }; |
2920 | ||
844a3b63 PW |
2921 | static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { |
2922 | { | |
2923 | .name = "mpu", | |
2924 | .pa_start = 0x49026000, | |
2925 | .pa_end = 0x490260ff, | |
2926 | .flags = ADDR_TYPE_RT | |
a52e2ab6 | 2927 | }, |
844a3b63 | 2928 | { } |
a52e2ab6 PW |
2929 | }; |
2930 | ||
844a3b63 PW |
2931 | /* l4_per -> mcbsp4 */ |
2932 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { | |
2933 | .master = &omap3xxx_l4_per_hwmod, | |
2934 | .slave = &omap3xxx_mcbsp4_hwmod, | |
2935 | .clk = "mcbsp4_ick", | |
2936 | .addr = omap3xxx_mcbsp4_addrs, | |
2937 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2938 | }; |
2939 | ||
844a3b63 PW |
2940 | static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { |
2941 | { | |
2942 | .name = "mpu", | |
2943 | .pa_start = 0x48096000, | |
2944 | .pa_end = 0x480960ff, | |
2945 | .flags = ADDR_TYPE_RT | |
2946 | }, | |
2947 | { } | |
2948 | }; | |
b163605e | 2949 | |
844a3b63 PW |
2950 | /* l4_core -> mcbsp5 */ |
2951 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { | |
2952 | .master = &omap3xxx_l4_core_hwmod, | |
2953 | .slave = &omap3xxx_mcbsp5_hwmod, | |
2954 | .clk = "mcbsp5_ick", | |
2955 | .addr = omap3xxx_mcbsp5_addrs, | |
2956 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
2957 | }; |
2958 | ||
844a3b63 PW |
2959 | static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { |
2960 | { | |
2961 | .name = "sidetone", | |
2962 | .pa_start = 0x49028000, | |
2963 | .pa_end = 0x490280ff, | |
2964 | .flags = ADDR_TYPE_RT | |
2965 | }, | |
2966 | { } | |
d3442726 TG |
2967 | }; |
2968 | ||
844a3b63 PW |
2969 | /* l4_per -> mcbsp2_sidetone */ |
2970 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { | |
2971 | .master = &omap3xxx_l4_per_hwmod, | |
2972 | .slave = &omap3xxx_mcbsp2_sidetone_hwmod, | |
2973 | .clk = "mcbsp2_ick", | |
2974 | .addr = omap3xxx_mcbsp2_sidetone_addrs, | |
2975 | .user = OCP_USER_MPU, | |
b163605e PW |
2976 | }; |
2977 | ||
844a3b63 PW |
2978 | static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { |
2979 | { | |
2980 | .name = "sidetone", | |
2981 | .pa_start = 0x4902A000, | |
2982 | .pa_end = 0x4902A0ff, | |
2983 | .flags = ADDR_TYPE_RT | |
2984 | }, | |
2985 | { } | |
a52e2ab6 PW |
2986 | }; |
2987 | ||
844a3b63 PW |
2988 | /* l4_per -> mcbsp3_sidetone */ |
2989 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { | |
2990 | .master = &omap3xxx_l4_per_hwmod, | |
2991 | .slave = &omap3xxx_mcbsp3_sidetone_hwmod, | |
2992 | .clk = "mcbsp3_ick", | |
2993 | .addr = omap3xxx_mcbsp3_sidetone_addrs, | |
2994 | .user = OCP_USER_MPU, | |
a52e2ab6 PW |
2995 | }; |
2996 | ||
844a3b63 PW |
2997 | static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { |
2998 | { | |
2999 | .pa_start = 0x48094000, | |
3000 | .pa_end = 0x480941ff, | |
3001 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3002 | }, |
844a3b63 | 3003 | { } |
d3442726 TG |
3004 | }; |
3005 | ||
844a3b63 PW |
3006 | /* l4_core -> mailbox */ |
3007 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { | |
3008 | .master = &omap3xxx_l4_core_hwmod, | |
3009 | .slave = &omap3xxx_mailbox_hwmod, | |
3010 | .addr = omap3xxx_mailbox_addrs, | |
3011 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3012 | }; | |
b163605e | 3013 | |
844a3b63 PW |
3014 | /* l4 core -> mcspi1 interface */ |
3015 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
3016 | .master = &omap3xxx_l4_core_hwmod, | |
3017 | .slave = &omap34xx_mcspi1, | |
3018 | .clk = "mcspi1_ick", | |
3019 | .addr = omap2_mcspi1_addr_space, | |
3020 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3021 | }; |
3022 | ||
844a3b63 PW |
3023 | /* l4 core -> mcspi2 interface */ |
3024 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
3025 | .master = &omap3xxx_l4_core_hwmod, | |
3026 | .slave = &omap34xx_mcspi2, | |
3027 | .clk = "mcspi2_ick", | |
3028 | .addr = omap2_mcspi2_addr_space, | |
3029 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3030 | }; |
3031 | ||
844a3b63 PW |
3032 | /* l4 core -> mcspi3 interface */ |
3033 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
3034 | .master = &omap3xxx_l4_core_hwmod, | |
3035 | .slave = &omap34xx_mcspi3, | |
3036 | .clk = "mcspi3_ick", | |
3037 | .addr = omap2430_mcspi3_addr_space, | |
3038 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
b163605e PW |
3039 | }; |
3040 | ||
844a3b63 PW |
3041 | /* l4 core -> mcspi4 interface */ |
3042 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
3043 | { | |
3044 | .pa_start = 0x480ba000, | |
3045 | .pa_end = 0x480ba0ff, | |
3046 | .flags = ADDR_TYPE_RT, | |
d3442726 | 3047 | }, |
844a3b63 PW |
3048 | { } |
3049 | }; | |
3050 | ||
3051 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
3052 | .master = &omap3xxx_l4_core_hwmod, | |
3053 | .slave = &omap34xx_mcspi4, | |
3054 | .clk = "mcspi4_ick", | |
3055 | .addr = omap34xx_mcspi4_addr_space, | |
3056 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
d3442726 TG |
3057 | }; |
3058 | ||
de231388 KM |
3059 | static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { |
3060 | .master = &omap3xxx_usb_host_hs_hwmod, | |
3061 | .slave = &omap3xxx_l3_main_hwmod, | |
3062 | .clk = "core_l3_ick", | |
3063 | .user = OCP_USER_MPU, | |
3064 | }; | |
3065 | ||
de231388 KM |
3066 | static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { |
3067 | { | |
3068 | .name = "uhh", | |
3069 | .pa_start = 0x48064000, | |
3070 | .pa_end = 0x480643ff, | |
3071 | .flags = ADDR_TYPE_RT | |
3072 | }, | |
3073 | { | |
3074 | .name = "ohci", | |
3075 | .pa_start = 0x48064400, | |
3076 | .pa_end = 0x480647ff, | |
3077 | }, | |
3078 | { | |
3079 | .name = "ehci", | |
3080 | .pa_start = 0x48064800, | |
3081 | .pa_end = 0x48064cff, | |
3082 | }, | |
3083 | {} | |
3084 | }; | |
3085 | ||
3086 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { | |
3087 | .master = &omap3xxx_l4_core_hwmod, | |
3088 | .slave = &omap3xxx_usb_host_hs_hwmod, | |
3089 | .clk = "usbhost_ick", | |
3090 | .addr = omap3xxx_usb_host_hs_addrs, | |
3091 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3092 | }; | |
3093 | ||
de231388 KM |
3094 | static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { |
3095 | { | |
3096 | .name = "tll", | |
3097 | .pa_start = 0x48062000, | |
3098 | .pa_end = 0x48062fff, | |
3099 | .flags = ADDR_TYPE_RT | |
3100 | }, | |
3101 | {} | |
3102 | }; | |
3103 | ||
3104 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { | |
3105 | .master = &omap3xxx_l4_core_hwmod, | |
3106 | .slave = &omap3xxx_usb_tll_hs_hwmod, | |
3107 | .clk = "usbtll_ick", | |
3108 | .addr = omap3xxx_usb_tll_hs_addrs, | |
3109 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3110 | }; | |
3111 | ||
45a4bb06 PW |
3112 | /* l4_core -> hdq1w interface */ |
3113 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { | |
3114 | .master = &omap3xxx_l4_core_hwmod, | |
3115 | .slave = &omap3xxx_hdq1w_hwmod, | |
3116 | .clk = "hdq_ick", | |
3117 | .addr = omap2_hdq1w_addr_space, | |
3118 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3119 | .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, | |
3120 | }; | |
3121 | ||
c8d82ff6 VH |
3122 | /* l4_wkup -> 32ksync_counter */ |
3123 | static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { | |
3124 | { | |
3125 | .pa_start = 0x48320000, | |
3126 | .pa_end = 0x4832001f, | |
3127 | .flags = ADDR_TYPE_RT | |
3128 | }, | |
3129 | { } | |
3130 | }; | |
3131 | ||
3132 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { | |
3133 | .master = &omap3xxx_l4_wkup_hwmod, | |
3134 | .slave = &omap3xxx_counter_32k_hwmod, | |
3135 | .clk = "omap_32ksync_ick", | |
3136 | .addr = omap3xxx_counter_32k_addrs, | |
3137 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
3138 | }; | |
3139 | ||
0a78c5c5 PW |
3140 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3141 | &omap3xxx_l3_main__l4_core, | |
3142 | &omap3xxx_l3_main__l4_per, | |
3143 | &omap3xxx_mpu__l3_main, | |
3144 | &omap3xxx_l4_core__l4_wkup, | |
3145 | &omap3xxx_l4_core__mmc3, | |
3146 | &omap3_l4_core__uart1, | |
3147 | &omap3_l4_core__uart2, | |
3148 | &omap3_l4_per__uart3, | |
3149 | &omap3_l4_core__i2c1, | |
3150 | &omap3_l4_core__i2c2, | |
3151 | &omap3_l4_core__i2c3, | |
3152 | &omap3xxx_l4_wkup__l4_sec, | |
3153 | &omap3xxx_l4_wkup__timer1, | |
3154 | &omap3xxx_l4_per__timer2, | |
3155 | &omap3xxx_l4_per__timer3, | |
3156 | &omap3xxx_l4_per__timer4, | |
3157 | &omap3xxx_l4_per__timer5, | |
3158 | &omap3xxx_l4_per__timer6, | |
3159 | &omap3xxx_l4_per__timer7, | |
3160 | &omap3xxx_l4_per__timer8, | |
3161 | &omap3xxx_l4_per__timer9, | |
3162 | &omap3xxx_l4_core__timer10, | |
3163 | &omap3xxx_l4_core__timer11, | |
3164 | &omap3xxx_l4_wkup__wd_timer2, | |
3165 | &omap3xxx_l4_wkup__gpio1, | |
3166 | &omap3xxx_l4_per__gpio2, | |
3167 | &omap3xxx_l4_per__gpio3, | |
3168 | &omap3xxx_l4_per__gpio4, | |
3169 | &omap3xxx_l4_per__gpio5, | |
3170 | &omap3xxx_l4_per__gpio6, | |
3171 | &omap3xxx_dma_system__l3, | |
3172 | &omap3xxx_l4_core__dma_system, | |
3173 | &omap3xxx_l4_core__mcbsp1, | |
3174 | &omap3xxx_l4_per__mcbsp2, | |
3175 | &omap3xxx_l4_per__mcbsp3, | |
3176 | &omap3xxx_l4_per__mcbsp4, | |
3177 | &omap3xxx_l4_core__mcbsp5, | |
3178 | &omap3xxx_l4_per__mcbsp2_sidetone, | |
3179 | &omap3xxx_l4_per__mcbsp3_sidetone, | |
3180 | &omap34xx_l4_core__mcspi1, | |
3181 | &omap34xx_l4_core__mcspi2, | |
3182 | &omap34xx_l4_core__mcspi3, | |
3183 | &omap34xx_l4_core__mcspi4, | |
c8d82ff6 | 3184 | &omap3xxx_l4_wkup__counter_32k, |
d6504acd PW |
3185 | NULL, |
3186 | }; | |
3187 | ||
0a78c5c5 PW |
3188 | /* GP-only hwmod links */ |
3189 | static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = { | |
3190 | &omap3xxx_l4_sec__timer12, | |
91a36bdb AK |
3191 | NULL |
3192 | }; | |
3193 | ||
0a78c5c5 PW |
3194 | /* 3430ES1-only hwmod links */ |
3195 | static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { | |
3196 | &omap3430es1_dss__l3, | |
3197 | &omap3430es1_l4_core__dss, | |
d6504acd PW |
3198 | NULL |
3199 | }; | |
3200 | ||
0a78c5c5 PW |
3201 | /* 3430ES2+-only hwmod links */ |
3202 | static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { | |
3203 | &omap3xxx_dss__l3, | |
3204 | &omap3xxx_l4_core__dss, | |
3205 | &omap3xxx_usbhsotg__l3, | |
3206 | &omap3xxx_l4_core__usbhsotg, | |
3207 | &omap3xxx_usb_host_hs__l3_main_2, | |
3208 | &omap3xxx_l4_core__usb_host_hs, | |
3209 | &omap3xxx_l4_core__usb_tll_hs, | |
d6504acd PW |
3210 | NULL |
3211 | }; | |
870ea2b8 | 3212 | |
0a78c5c5 PW |
3213 | /* <= 3430ES3-only hwmod links */ |
3214 | static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { | |
3215 | &omap3xxx_l4_core__pre_es3_mmc1, | |
3216 | &omap3xxx_l4_core__pre_es3_mmc2, | |
a52e2ab6 PW |
3217 | NULL |
3218 | }; | |
3219 | ||
0a78c5c5 PW |
3220 | /* 3430ES3+-only hwmod links */ |
3221 | static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { | |
3222 | &omap3xxx_l4_core__es3plus_mmc1, | |
3223 | &omap3xxx_l4_core__es3plus_mmc2, | |
a52e2ab6 PW |
3224 | NULL |
3225 | }; | |
3226 | ||
0a78c5c5 PW |
3227 | /* 34xx-only hwmod links (all ES revisions) */ |
3228 | static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { | |
3229 | &omap3xxx_l3__iva, | |
3230 | &omap34xx_l4_core__sr1, | |
3231 | &omap34xx_l4_core__sr2, | |
3232 | &omap3xxx_l4_core__mailbox, | |
45a4bb06 | 3233 | &omap3xxx_l4_core__hdq1w, |
d6504acd PW |
3234 | NULL |
3235 | }; | |
273ff8c3 | 3236 | |
0a78c5c5 PW |
3237 | /* 36xx-only hwmod links (all ES revisions) */ |
3238 | static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { | |
3239 | &omap3xxx_l3__iva, | |
3240 | &omap36xx_l4_per__uart4, | |
3241 | &omap3xxx_dss__l3, | |
3242 | &omap3xxx_l4_core__dss, | |
3243 | &omap36xx_l4_core__sr1, | |
3244 | &omap36xx_l4_core__sr2, | |
3245 | &omap3xxx_usbhsotg__l3, | |
3246 | &omap3xxx_l4_core__usbhsotg, | |
3247 | &omap3xxx_l4_core__mailbox, | |
3248 | &omap3xxx_usb_host_hs__l3_main_2, | |
3249 | &omap3xxx_l4_core__usb_host_hs, | |
3250 | &omap3xxx_l4_core__usb_tll_hs, | |
3251 | &omap3xxx_l4_core__es3plus_mmc1, | |
3252 | &omap3xxx_l4_core__es3plus_mmc2, | |
45a4bb06 | 3253 | &omap3xxx_l4_core__hdq1w, |
d6504acd PW |
3254 | NULL |
3255 | }; | |
3256 | ||
0a78c5c5 PW |
3257 | static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { |
3258 | &omap3xxx_dss__l3, | |
3259 | &omap3xxx_l4_core__dss, | |
3260 | &am35xx_usbhsotg__l3, | |
3261 | &am35xx_l4_core__usbhsotg, | |
3262 | &am35xx_l4_core__uart4, | |
3263 | &omap3xxx_usb_host_hs__l3_main_2, | |
3264 | &omap3xxx_l4_core__usb_host_hs, | |
3265 | &omap3xxx_l4_core__usb_tll_hs, | |
3266 | &omap3xxx_l4_core__es3plus_mmc1, | |
3267 | &omap3xxx_l4_core__es3plus_mmc2, | |
d6504acd | 3268 | NULL |
7359154e PW |
3269 | }; |
3270 | ||
0a78c5c5 PW |
3271 | static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { |
3272 | &omap3xxx_l4_core__dss_dispc, | |
3273 | &omap3xxx_l4_core__dss_dsi1, | |
3274 | &omap3xxx_l4_core__dss_rfbi, | |
3275 | &omap3xxx_l4_core__dss_venc, | |
1d2f56c8 IY |
3276 | NULL |
3277 | }; | |
3278 | ||
7359154e PW |
3279 | int __init omap3xxx_hwmod_init(void) |
3280 | { | |
d6504acd | 3281 | int r; |
0a78c5c5 | 3282 | struct omap_hwmod_ocp_if **h = NULL; |
d6504acd PW |
3283 | unsigned int rev; |
3284 | ||
0a78c5c5 PW |
3285 | /* Register hwmod links common to all OMAP3 */ |
3286 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | |
ace90216 | 3287 | if (r < 0) |
d6504acd PW |
3288 | return r; |
3289 | ||
0a78c5c5 | 3290 | /* Register GP-only hwmod links. */ |
91a36bdb | 3291 | if (omap_type() == OMAP2_DEVICE_TYPE_GP) { |
0a78c5c5 | 3292 | r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs); |
91a36bdb AK |
3293 | if (r < 0) |
3294 | return r; | |
3295 | } | |
3296 | ||
d6504acd PW |
3297 | rev = omap_rev(); |
3298 | ||
3299 | /* | |
0a78c5c5 | 3300 | * Register hwmod links common to individual OMAP3 families, all |
d6504acd PW |
3301 | * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) |
3302 | * All possible revisions should be included in this conditional. | |
3303 | */ | |
3304 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3305 | rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || | |
3306 | rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3307 | h = omap34xx_hwmod_ocp_ifs; |
68a88b98 | 3308 | } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
0a78c5c5 | 3309 | h = am35xx_hwmod_ocp_ifs; |
d6504acd PW |
3310 | } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || |
3311 | rev == OMAP3630_REV_ES1_2) { | |
0a78c5c5 | 3312 | h = omap36xx_hwmod_ocp_ifs; |
d6504acd PW |
3313 | } else { |
3314 | WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); | |
3315 | return -EINVAL; | |
3316 | }; | |
3317 | ||
0a78c5c5 | 3318 | r = omap_hwmod_register_links(h); |
ace90216 | 3319 | if (r < 0) |
d6504acd PW |
3320 | return r; |
3321 | ||
3322 | /* | |
0a78c5c5 | 3323 | * Register hwmod links specific to certain ES levels of a |
d6504acd PW |
3324 | * particular family of silicon (e.g., 34xx ES1.0) |
3325 | */ | |
3326 | h = NULL; | |
3327 | if (rev == OMAP3430_REV_ES1_0) { | |
0a78c5c5 | 3328 | h = omap3430es1_hwmod_ocp_ifs; |
d6504acd PW |
3329 | } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || |
3330 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || | |
3331 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3332 | h = omap3430es2plus_hwmod_ocp_ifs; |
d6504acd PW |
3333 | }; |
3334 | ||
a52e2ab6 | 3335 | if (h) { |
0a78c5c5 | 3336 | r = omap_hwmod_register_links(h); |
a52e2ab6 PW |
3337 | if (r < 0) |
3338 | return r; | |
3339 | } | |
3340 | ||
3341 | h = NULL; | |
3342 | if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || | |
3343 | rev == OMAP3430_REV_ES2_1) { | |
0a78c5c5 | 3344 | h = omap3430_pre_es3_hwmod_ocp_ifs; |
a52e2ab6 PW |
3345 | } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || |
3346 | rev == OMAP3430_REV_ES3_1_2) { | |
0a78c5c5 | 3347 | h = omap3430_es3plus_hwmod_ocp_ifs; |
a52e2ab6 PW |
3348 | }; |
3349 | ||
d6504acd | 3350 | if (h) |
0a78c5c5 | 3351 | r = omap_hwmod_register_links(h); |
1d2f56c8 IY |
3352 | if (r < 0) |
3353 | return r; | |
3354 | ||
3355 | /* | |
3356 | * DSS code presumes that dss_core hwmod is handled first, | |
3357 | * _before_ any other DSS related hwmods so register common | |
0a78c5c5 PW |
3358 | * DSS hwmod links last to ensure that dss_core is already |
3359 | * registered. Otherwise some change things may happen, for | |
3360 | * ex. if dispc is handled before dss_core and DSS is enabled | |
3361 | * in bootloader DISPC will be reset with outputs enabled | |
3362 | * which sometimes leads to unrecoverable L3 error. XXX The | |
3363 | * long-term fix to this is to ensure hwmods are set up in | |
3364 | * dependency order in the hwmod core code. | |
1d2f56c8 | 3365 | */ |
0a78c5c5 | 3366 | r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); |
d6504acd PW |
3367 | |
3368 | return r; | |
7359154e | 3369 | } |